drivers/i2c/busses/i2c-imx.c

   1 /*
   2  *      Copyright (C) 2002 Motorola GSG-China
   3  *
   4  *      This program is free software; you can redistribute it and/or
   5  *      modify it under the terms of the GNU General Public License
   6  *      as published by the Free Software Foundation; either version 2
   7  *      of the License, or (at your option) any later version.
   8  *
   9  *      This program is distributed in the hope that it will be useful,
  10  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *      GNU General Public License for more details.
  13  *
  14  * Author:
  15  *      Darius Augulis, Teltonika Inc.
  16  *
  17  * Desc.:
  18  *      Implementation of I2C Adapter/Algorithm Driver
  19  *      for I2C Bus integrated in Freescale i.MX/MXC processors
  20  *
  21  *      Derived from Motorola GSG China I2C example driver
  22  *
  23  *      Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
  24  *      Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
  25  *      Copyright (C) 2007 RightHand Technologies, Inc.
  26  *      Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  27  *
  28  *      Copyright 2013 Freescale Semiconductor, Inc.
  29  *
  30  */
  31
  32 /** Includes *******************************************************************
  33 *******************************************************************************/
  34
  35 #include <linux/init.h>
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/err.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/delay.h>
  42 #include <linux/i2c.h>
  43 #include <linux/io.h>
  44 #include <linux/sched.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/clk.h>
  47 #include <linux/slab.h>
  48 #include <linux/of.h>
  49 #include <linux/of_device.h>
  50 #include <linux/platform_data/i2c-imx.h>
  51
  52 /** Defines ********************************************************************
  53 *******************************************************************************/
  54
  55 /* This will be the driver name the kernel reports */
  56 #define DRIVER_NAME "imx-i2c"
  57
  58 /* Default value */
  59 #define IMX_I2C_BIT_RATE        100000  /* 100kHz */
  60
  61 /* IMX I2C registers:
  62  * the I2C register offset is different between SoCs,
  63  * to provid support for all these chips, split the
  64  * register offset into a fixed base address and a
  65  * variable shift value, then the full register offset
  66  * will be calculated by
  67  * reg_off = ( reg_base_addr << reg_shift)
  68  */
  69 #define IMX_I2C_IADR    0x00    /* i2c slave address */
  70 #define IMX_I2C_IFDR    0x01    /* i2c frequency divider */
  71 #define IMX_I2C_I2CR    0x02    /* i2c control */
  72 #define IMX_I2C_I2SR    0x03    /* i2c status */
  73 #define IMX_I2C_I2DR    0x04    /* i2c transfer data */
  74
  75 #define IMX_I2C_REGSHIFT        2
  76 #define VF610_I2C_REGSHIFT      0
  77
  78 /* Bits of IMX I2C registers */
  79 #define I2SR_RXAK       0x01
  80 #define I2SR_IIF        0x02
  81 #define I2SR_SRW        0x04
  82 #define I2SR_IAL        0x10
  83 #define I2SR_IBB        0x20
  84 #define I2SR_IAAS       0x40
  85 #define I2SR_ICF        0x80
  86 #define I2CR_RSTA       0x04
  87 #define I2CR_TXAK       0x08
  88 #define I2CR_MTX        0x10
  89 #define I2CR_MSTA       0x20
  90 #define I2CR_IIEN       0x40
  91 #define I2CR_IEN        0x80
  92
  93 /* register bits different operating codes definition:
  94  * 1) I2SR: Interrupt flags clear operation differ between SoCs:
  95  * - write zero to clear(w0c) INT flag on i.MX,
  96  * - but write one to clear(w1c) INT flag on Vybrid.
  97  * 2) I2CR: I2C module enable operation also differ between SoCs:
  98  * - set I2CR_IEN bit enable the module on i.MX,
  99  * - but clear I2CR_IEN bit enable the module on Vybrid.
 100  */
 101 #define I2SR_CLR_OPCODE_W0C     0x0
 102 #define I2SR_CLR_OPCODE_W1C     (I2SR_IAL | I2SR_IIF)
 103 #define I2CR_IEN_OPCODE_0       0x0
 104 #define I2CR_IEN_OPCODE_1       I2CR_IEN
 105
 106 /** Variables ******************************************************************
 107 *******************************************************************************/
 108
 109 /*
 110  * sorted list of clock divider, register value pairs
 111  * taken from table 26-5, p.26-9, Freescale i.MX
 112  * Integrated Portable System Processor Reference Manual
 113  * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
 114  *
 115  * Duplicated divider values removed from list
 116  */
 117 struct imx_i2c_clk_pair {
 118         u16     div;
 119         u16     val;
 120 };
 121
 122 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
 123         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
 124         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
 125         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
 126         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
 127         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
 128         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
 129         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
 130         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
 131         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 132         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 133         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 134         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 135         { 3072, 0x1E }, { 3840, 0x1F }
 136 };
 137
 138 /* Vybrid VF610 clock divider, register value pairs */
 139 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
 140         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
 141         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
 142         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
 143         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
 144         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
 145         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
 146         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
 147         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
 148         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
 149         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
 150         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
 151         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
 152         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
 153         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
 154         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
 155 };
 156
 157 enum imx_i2c_type {
 158         IMX1_I2C,
 159         IMX21_I2C,
 160         VF610_I2C,
 161 };
 162
 163 struct imx_i2c_hwdata {
 164         enum imx_i2c_type       devtype;
 165         unsigned                regshift;
 166         struct imx_i2c_clk_pair *clk_div;
 167         unsigned                ndivs;
 168         unsigned                i2sr_clr_opcode;
 169         unsigned                i2cr_ien_opcode;
 170 };
 171
 172 struct imx_i2c_struct {
 173         struct i2c_adapter      adapter;
 174         struct clk              *clk;
 175         void __iomem            *base;
 176         wait_queue_head_t       queue;
 177         unsigned long           i2csr;
 178         unsigned int            disable_delay;
 179         int                     stopped;
 180         unsigned int            ifdr; /* IMX_I2C_IFDR */
 181         unsigned int            cur_clk;
 182         unsigned int            bitrate;
 183         const struct imx_i2c_hwdata     *hwdata;
 184 };
 185
 186 static const struct imx_i2c_hwdata imx1_i2c_hwdata  = {
 187         .devtype                = IMX1_I2C,
 188         .regshift               = IMX_I2C_REGSHIFT,
 189         .clk_div                = imx_i2c_clk_div,
 190         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 191         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 192         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 193
 194 };
 195
 196 static const struct imx_i2c_hwdata imx21_i2c_hwdata  = {
 197         .devtype                = IMX21_I2C,
 198         .regshift               = IMX_I2C_REGSHIFT,
 199         .clk_div                = imx_i2c_clk_div,
 200         .ndivs                  = ARRAY_SIZE(imx_i2c_clk_div),
 201         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W0C,
 202         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_1,
 203
 204 };
 205
 206 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
 207         .devtype                = VF610_I2C,
 208         .regshift               = VF610_I2C_REGSHIFT,
 209         .clk_div                = vf610_i2c_clk_div,
 210         .ndivs                  = ARRAY_SIZE(vf610_i2c_clk_div),
 211         .i2sr_clr_opcode        = I2SR_CLR_OPCODE_W1C,
 212         .i2cr_ien_opcode        = I2CR_IEN_OPCODE_0,
 213
 214 };
 215
 216 static struct platform_device_id imx_i2c_devtype[] = {
 217         {
 218                 .name = "imx1-i2c",
 219                 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
 220         }, {
 221                 .name = "imx21-i2c",
 222                 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
 223         }, {
 224                 /* sentinel */
 225         }
 226 };
 227 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
 228
 229 static const struct of_device_id i2c_imx_dt_ids[] = {
 230         { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
 231         { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
 232         { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
 233         { /* sentinel */ }
 234 };
 235 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
 236
 237 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
 238 {
 239         return i2c_imx->hwdata->devtype == IMX1_I2C;
 240 }
 241
 242 static inline void imx_i2c_write_reg(unsigned int val,
 243                 struct imx_i2c_struct *i2c_imx, unsigned int reg)
 244 {
 245         writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 246 }
 247
 248 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
 249                 unsigned int reg)
 250 {
 251         return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
 252 }
 253
 254 /** Functions for IMX I2C adapter driver ***************************************
 255 *******************************************************************************/
 256
 257 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
 258 {
 259         unsigned long orig_jiffies = jiffies;
 260         unsigned int temp;
 261
 262         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 263
 264         while (1) {
 265                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 266
 267                 /* check for arbitration lost */
 268                 if (temp & I2SR_IAL) {
 269                         temp &= ~I2SR_IAL;
 270                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 271                         return -EAGAIN;
 272                 }
 273
 274                 if (for_busy && (temp & I2SR_IBB))
 275                         break;
 276                 if (!for_busy && !(temp & I2SR_IBB))
 277                         break;
 278                 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
 279                         dev_dbg(&i2c_imx->adapter.dev,
 280                                 "<%s> I2C bus is busy\n", __func__);
 281                         return -ETIMEDOUT;
 282                 }
 283                 schedule();
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
 290 {
 291         wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
 292
 293         if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
 294                 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
 295                 return -ETIMEDOUT;
 296         }
 297         dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
 298         i2c_imx->i2csr = 0;
 299         return 0;
 300 }
 301
 302 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
 303 {
 304         if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
 305                 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
 306                 return -EIO;  /* No ACK */
 307         }
 308
 309         dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
 310         return 0;
 311 }
 312
 313 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
 314 {
 315         struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
 316         unsigned int i2c_clk_rate;
 317         unsigned int div;
 318         int i;
 319
 320         /* Divider value calculation */
 321         i2c_clk_rate = clk_get_rate(i2c_imx->clk);
 322         if (i2c_imx->cur_clk == i2c_clk_rate)
 323                 return;
 324         else
 325                 i2c_imx->cur_clk = i2c_clk_rate;
 326
 327         div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
 328         if (div < i2c_clk_div[0].div)
 329                 i = 0;
 330         else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
 331                 i = i2c_imx->hwdata->ndivs - 1;
 332         else
 333                 for (i = 0; i2c_clk_div[i].div < div; i++);
 334
 335         /* Store divider value */
 336         i2c_imx->ifdr = i2c_clk_div[i].val;
 337
 338         /*
 339          * There dummy delay is calculated.
 340          * It should be about one I2C clock period long.
 341          * This delay is used in I2C bus disable function
 342          * to fix chip hardware bug.
 343          */
 344         i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
 345                 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
 346
 347 #ifdef CONFIG_I2C_DEBUG_BUS
 348         dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
 349                 i2c_clk_rate, div);
 350         dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
 351                 i2c_clk_div[i].val, i2c_clk_div[i].div);
 352 #endif
 353 }
 354
 355 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
 356 {
 357         unsigned int temp = 0;
 358         int result;
 359
 360         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 361
 362         i2c_imx_set_clk(i2c_imx);
 363
 364         result = clk_prepare_enable(i2c_imx->clk);
 365         if (result)
 366                 return result;
 367         imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
 368         /* Enable I2C controller */
 369         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 370         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
 371
 372         /* Wait controller to be stable */
 373         udelay(50);
 374
 375         /* Start I2C transaction */
 376         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 377         temp |= I2CR_MSTA;
 378         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 379         result = i2c_imx_bus_busy(i2c_imx, 1);
 380         if (result)
 381                 return result;
 382         i2c_imx->stopped = 0;
 383
 384         temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
 385         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 386         return result;
 387 }
 388
 389 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
 390 {
 391         unsigned int temp = 0;
 392
 393         if (!i2c_imx->stopped) {
 394                 /* Stop I2C transaction */
 395                 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 396                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 397                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 398                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 399         }
 400         if (is_imx1_i2c(i2c_imx)) {
 401                 /*
 402                  * This delay caused by an i.MXL hardware bug.
 403                  * If no (or too short) delay, no "STOP" bit will be generated.
 404                  */
 405                 udelay(i2c_imx->disable_delay);
 406         }
 407
 408         if (!i2c_imx->stopped) {
 409                 i2c_imx_bus_busy(i2c_imx, 0);
 410                 i2c_imx->stopped = 1;
 411         }
 412
 413         /* Disable I2C controller */
 414         temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 415         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 416         clk_disable_unprepare(i2c_imx->clk);
 417 }
 418
 419 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
 420 {
 421         struct imx_i2c_struct *i2c_imx = dev_id;
 422         unsigned int temp;
 423
 424         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 425         if (temp & I2SR_IIF) {
 426                 /* save status register */
 427                 i2c_imx->i2csr = temp;
 428                 temp &= ~I2SR_IIF;
 429                 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
 430                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
 431                 wake_up(&i2c_imx->queue);
 432                 return IRQ_HANDLED;
 433         }
 434
 435         return IRQ_NONE;
 436 }
 437
 438 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
 439 {
 440         int i, result;
 441
 442         dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
 443                 __func__, msgs->addr << 1);
 444
 445         /* write slave address */
 446         imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
 447         result = i2c_imx_trx_complete(i2c_imx);
 448         if (result)
 449                 return result;
 450         result = i2c_imx_acked(i2c_imx);
 451         if (result)
 452                 return result;
 453         dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
 454
 455         /* write data */
 456         for (i = 0; i < msgs->len; i++) {
 457                 dev_dbg(&i2c_imx->adapter.dev,
 458                         "<%s> write byte: B%d=0x%X\n",
 459                         __func__, i, msgs->buf[i]);
 460                 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
 461                 result = i2c_imx_trx_complete(i2c_imx);
 462                 if (result)
 463                         return result;
 464                 result = i2c_imx_acked(i2c_imx);
 465                 if (result)
 466                         return result;
 467         }
 468         return 0;
 469 }
 470
 471 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
 472 {
 473         int i, result;
 474         unsigned int temp;
 475         int block_data = msgs->flags & I2C_M_RECV_LEN;
 476
 477         dev_dbg(&i2c_imx->adapter.dev,
 478                 "<%s> write slave address: addr=0x%x\n",
 479                 __func__, (msgs->addr << 1) | 0x01);
 480
 481         /* write slave address */
 482         imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
 483         result = i2c_imx_trx_complete(i2c_imx);
 484         if (result)
 485                 return result;
 486         result = i2c_imx_acked(i2c_imx);
 487         if (result)
 488                 return result;
 489
 490         dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
 491
 492         /* setup bus to read data */
 493         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 494         temp &= ~I2CR_MTX;
 495
 496         /*
 497          * Reset the I2CR_TXAK flag initially for SMBus block read since the
 498          * length is unknown
 499          */
 500         if ((msgs->len - 1) || block_data)
 501                 temp &= ~I2CR_TXAK;
 502         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 503         imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
 504
 505         dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
 506
 507         /* read data */
 508         for (i = 0; i < msgs->len; i++) {
 509                 u8 len = 0;
 510                 result = i2c_imx_trx_complete(i2c_imx);
 511                 if (result)
 512                         return result;
 513                 /*
 514                  * First byte is the length of remaining packet
 515                  * in the SMBus block data read. Add it to
 516                  * msgs->len.
 517                  */
 518                 if ((!i) && block_data) {
 519                         len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 520                         if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
 521                                 return -EPROTO;
 522                         dev_dbg(&i2c_imx->adapter.dev,
 523                                 "<%s> read length: 0x%X\n",
 524                                 __func__, len);
 525                         msgs->len += len;
 526                 }
 527                 if (i == (msgs->len - 1)) {
 528                         if (is_lastmsg) {
 529                                 /*
 530                                  * It must generate STOP before read I2DR to prevent
 531                                  * controller from generating another clock cycle
 532                                  */
 533                                 dev_dbg(&i2c_imx->adapter.dev,
 534                                         "<%s> clear MSTA\n", __func__);
 535                                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 536                                 temp &= ~(I2CR_MSTA | I2CR_MTX);
 537                                 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 538                                 i2c_imx_bus_busy(i2c_imx, 0);
 539                                 i2c_imx->stopped = 1;
 540                         } else {
 541                                 /*
 542                                  * For i2c master receiver repeat restart operation like:
 543                                  * read -> repeat MSTA -> read/write
 544                                  * The controller must set MTX before read the last byte in
 545                                  * the first read operation, otherwise the first read cost
 546                                  * one extra clock cycle.
 547                                  */
 548                                 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
 549                                 temp |= I2CR_MTX;
 550                                 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
 551                         }
 552                 } else if (i == (msgs->len - 2)) {
 553                         dev_dbg(&i2c_imx->adapter.dev,
 554                                 "<%s> set TXAK\n", __func__);
 555                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 556                         temp |= I2CR_TXAK;
 557                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 558                 }
 559                 if ((!i) && block_data)
 560                         msgs->buf[0] = len;
 561                 else
 562                         msgs->buf[i] =  imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
 563                 dev_dbg(&i2c_imx->adapter.dev,
 564                         "<%s> read byte: B%d=0x%X\n",
 565                         __func__, i, msgs->buf[i]);
 566         }
 567         return 0;
 568 }
 569
 570 static int i2c_imx_xfer(struct i2c_adapter *adapter,
 571                                                 struct i2c_msg *msgs, int num)
 572 {
 573         unsigned int i, temp;
 574         int result;
 575         bool is_lastmsg = false;
 576         struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
 577
 578         dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
 579
 580         /* Start I2C transfer */
 581         result = i2c_imx_start(i2c_imx);
 582         if (result)
 583                 goto fail0;
 584
 585         /* read/write data */
 586         for (i = 0; i < num; i++) {
 587                 if (i == num - 1)
 588                         is_lastmsg = true;
 589
 590                 if (i) {
 591                         dev_dbg(&i2c_imx->adapter.dev,
 592                                 "<%s> repeated start\n", __func__);
 593                         temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 594                         temp |= I2CR_RSTA;
 595                         imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
 596                         result =  i2c_imx_bus_busy(i2c_imx, 1);
 597                         if (result)
 598                                 goto fail0;
 599                 }
 600                 dev_dbg(&i2c_imx->adapter.dev,
 601                         "<%s> transfer message: %d\n", __func__, i);
 602                 /* write/read data */
 603 #ifdef CONFIG_I2C_DEBUG_BUS
 604                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
 605                 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
 606                         "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
 607                         (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
 608                         (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
 609                         (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
 610                 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
 611                 dev_dbg(&i2c_imx->adapter.dev,
 612                         "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
 613                         "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
 614                         (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
 615                         (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
 616                         (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
 617                         (temp & I2SR_RXAK ? 1 : 0));
 618 #endif
 619                 if (msgs[i].flags & I2C_M_RD)
 620                         result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
 621                 else
 622                         result = i2c_imx_write(i2c_imx, &msgs[i]);
 623                 if (result)
 624                         goto fail0;
 625         }
 626
 627 fail0:
 628         /* Stop I2C transfer */
 629         i2c_imx_stop(i2c_imx);
 630
 631         dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
 632                 (result < 0) ? "error" : "success msg",
 633                         (result < 0) ? result : num);
 634         return (result < 0) ? result : num;
 635 }
 636
 637 static u32 i2c_imx_func(struct i2c_adapter *adapter)
 638 {
 639         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
 640                 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
 641 }
 642
 643 static struct i2c_algorithm i2c_imx_algo = {
 644         .master_xfer    = i2c_imx_xfer,
 645         .functionality  = i2c_imx_func,
 646 };
 647
 648 static int i2c_imx_probe(struct platform_device *pdev)
 649 {
 650         const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
 651                                                            &pdev->dev);
 652         struct imx_i2c_struct *i2c_imx;
 653         struct resource *res;
 654         struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
 655         void __iomem *base;
 656         int irq, ret;
 657
 658         dev_dbg(&pdev->dev, "<%s>\n", __func__);
 659
 660         irq = platform_get_irq(pdev, 0);
 661         if (irq < 0) {
 662                 dev_err(&pdev->dev, "can't get irq number\n");
 663                 return irq;
 664         }
 665
 666         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 667         base = devm_ioremap_resource(&pdev->dev, res);
 668         if (IS_ERR(base))
 669                 return PTR_ERR(base);
 670
 671         i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct),
 672                                 GFP_KERNEL);
 673         if (!i2c_imx)
 674                 return -ENOMEM;
 675
 676         if (of_id)
 677                 i2c_imx->hwdata = of_id->data;
 678         else
 679                 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
 680                                 platform_get_device_id(pdev)->driver_data;
 681
 682         /* Setup i2c_imx driver structure */
 683         strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
 684         i2c_imx->adapter.owner          = THIS_MODULE;
 685         i2c_imx->adapter.algo           = &i2c_imx_algo;
 686         i2c_imx->adapter.dev.parent     = &pdev->dev;
 687         i2c_imx->adapter.nr             = pdev->id;
 688         i2c_imx->adapter.dev.of_node    = pdev->dev.of_node;
 689         i2c_imx->base                   = base;
 690
 691         /* Get I2C clock */
 692         i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
 693         if (IS_ERR(i2c_imx->clk)) {
 694                 dev_err(&pdev->dev, "can't get I2C clock\n");
 695                 return PTR_ERR(i2c_imx->clk);
 696         }
 697
 698         ret = clk_prepare_enable(i2c_imx->clk);
 699         if (ret) {
 700                 dev_err(&pdev->dev, "can't enable I2C clock\n");
 701                 return ret;
 702         }
 703         /* Request IRQ */
 704         ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
 705                                 pdev->name, i2c_imx);
 706         if (ret) {
 707                 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
 708                 goto clk_disable;
 709         }
 710
 711         /* Init queue */
 712         init_waitqueue_head(&i2c_imx->queue);
 713
 714         /* Set up adapter data */
 715         i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
 716
 717         /* Set up clock divider */
 718         i2c_imx->bitrate = IMX_I2C_BIT_RATE;
 719         ret = of_property_read_u32(pdev->dev.of_node,
 720                                    "clock-frequency", &i2c_imx->bitrate);
 721         if (ret < 0 && pdata && pdata->bitrate)
 722                 i2c_imx->bitrate = pdata->bitrate;
 723
 724         /* Set up chip registers to defaults */
 725         imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
 726                         i2c_imx, IMX_I2C_I2CR);
 727         imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
 728
 729         /* Add I2C adapter */
 730         ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
 731         if (ret < 0) {
 732                 dev_err(&pdev->dev, "registration failed\n");
 733                 goto clk_disable;
 734         }
 735
 736         /* Set up platform driver data */
 737         platform_set_drvdata(pdev, i2c_imx);
 738         clk_disable_unprepare(i2c_imx->clk);
 739
 740         dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
 741         dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
 742         dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
 743                 i2c_imx->adapter.name);
 744         dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
 745
 746         return 0;   /* Return OK */
 747
 748 clk_disable:
 749         clk_disable_unprepare(i2c_imx->clk);
 750         return ret;
 751 }
 752
 753 static int i2c_imx_remove(struct platform_device *pdev)
 754 {
 755         struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
 756
 757         /* remove adapter */
 758         dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
 759         i2c_del_adapter(&i2c_imx->adapter);
 760
 761         /* setup chip registers to defaults */
 762         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
 763         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
 764         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
 765         imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
 766
 767         return 0;
 768 }
 769
 770 static struct platform_driver i2c_imx_driver = {
 771         .probe = i2c_imx_probe,
 772         .remove = i2c_imx_remove,
 773         .driver = {
 774                 .name   = DRIVER_NAME,
 775                 .owner  = THIS_MODULE,
 776                 .of_match_table = i2c_imx_dt_ids,
 777         },
 778         .id_table       = imx_i2c_devtype,
 779 };
 780
 781 static int __init i2c_adap_imx_init(void)
 782 {
 783         return platform_driver_register(&i2c_imx_driver);
 784 }
 785 subsys_initcall(i2c_adap_imx_init);
 786
 787 static void __exit i2c_adap_imx_exit(void)
 788 {
 789         platform_driver_unregister(&i2c_imx_driver);
 790 }
 791 module_exit(i2c_adap_imx_exit);
 792
 793 MODULE_LICENSE("GPL");
 794 MODULE_AUTHOR("Darius Augulis");
 795 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
 796 MODULE_ALIAS("platform:" DRIVER_NAME);