drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly separated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/time.h>
  27 #include <linux/sched.h>
  28 #include <linux/delay.h>
  29 #include <linux/errno.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/i2c-pxa.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_i2c.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/err.h>
  37 #include <linux/clk.h>
  38 #include <linux/slab.h>
  39 #include <linux/io.h>
  40 #include <linux/i2c/pxa-i2c.h>
  41
  42 #include <asm/irq.h>
  43
  44 #ifndef CONFIG_HAVE_CLK
  45 #define clk_get(dev, id)        NULL
  46 #define clk_put(clk)            do { } while (0)
  47 #define clk_disable(clk)        do { } while (0)
  48 #define clk_enable(clk)         do { } while (0)
  49 #endif
  50
  51 struct pxa_reg_layout {
  52         u32 ibmr;
  53         u32 idbr;
  54         u32 icr;
  55         u32 isr;
  56         u32 isar;
  57 };
  58
  59 enum pxa_i2c_types {
  60         REGS_PXA2XX,
  61         REGS_PXA3XX,
  62         REGS_CE4100,
  63 };
  64
  65 /*
  66  * I2C registers definitions
  67  */
  68 static struct pxa_reg_layout pxa_reg_layout[] = {
  69         [REGS_PXA2XX] = {
  70                 .ibmr = 0x00,
  71                 .idbr = 0x08,
  72                 .icr =  0x10,
  73                 .isr =  0x18,
  74                 .isar = 0x20,
  75         },
  76         [REGS_PXA3XX] = {
  77                 .ibmr = 0x00,
  78                 .idbr = 0x04,
  79                 .icr =  0x08,
  80                 .isr =  0x0c,
  81                 .isar = 0x10,
  82         },
  83         [REGS_CE4100] = {
  84                 .ibmr = 0x14,
  85                 .idbr = 0x0c,
  86                 .icr =  0x00,
  87                 .isr =  0x04,
  88                 /* no isar register */
  89         },
  90 };
  91
  92 static const struct platform_device_id i2c_pxa_id_table[] = {
  93         { "pxa2xx-i2c",         REGS_PXA2XX },
  94         { "pxa3xx-pwri2c",      REGS_PXA3XX },
  95         { "ce4100-i2c",         REGS_CE4100 },
  96         { },
  97 };
  98 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
  99
 100 /*
 101  * I2C bit definitions
 102  */
 103
 104 #define ICR_START       (1 << 0)           /* start bit */
 105 #define ICR_STOP        (1 << 1)           /* stop bit */
 106 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
 107 #define ICR_TB          (1 << 3)           /* transfer byte bit */
 108 #define ICR_MA          (1 << 4)           /* master abort */
 109 #define ICR_SCLE        (1 << 5)           /* master clock enable */
 110 #define ICR_IUE         (1 << 6)           /* unit enable */
 111 #define ICR_GCD         (1 << 7)           /* general call disable */
 112 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
 113 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
 114 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
 115 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
 116 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
 117 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
 118 #define ICR_UR          (1 << 14)          /* unit reset */
 119 #define ICR_FM          (1 << 15)          /* fast mode */
 120
 121 #define ISR_RWM         (1 << 0)           /* read/write mode */
 122 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
 123 #define ISR_UB          (1 << 2)           /* unit busy */
 124 #define ISR_IBB         (1 << 3)           /* bus busy */
 125 #define ISR_SSD         (1 << 4)           /* slave stop detected */
 126 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
 127 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
 128 #define ISR_IRF         (1 << 7)           /* rx buffer full */
 129 #define ISR_GCAD        (1 << 8)           /* general call address detected */
 130 #define ISR_SAD         (1 << 9)           /* slave address detected */
 131 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
 132
 133 struct pxa_i2c {
 134         spinlock_t              lock;
 135         wait_queue_head_t       wait;
 136         struct i2c_msg          *msg;
 137         unsigned int            msg_num;
 138         unsigned int            msg_idx;
 139         unsigned int            msg_ptr;
 140         unsigned int            slave_addr;
 141
 142         struct i2c_adapter      adap;
 143         struct clk              *clk;
 144 #ifdef CONFIG_I2C_PXA_SLAVE
 145         struct i2c_slave_client *slave;
 146 #endif
 147
 148         unsigned int            irqlogidx;
 149         u32                     isrlog[32];
 150         u32                     icrlog[32];
 151
 152         void __iomem            *reg_base;
 153         void __iomem            *reg_ibmr;
 154         void __iomem            *reg_idbr;
 155         void __iomem            *reg_icr;
 156         void __iomem            *reg_isr;
 157         void __iomem            *reg_isar;
 158
 159         unsigned long           iobase;
 160         unsigned long           iosize;
 161
 162         int                     irq;
 163         unsigned int            use_pio :1;
 164         unsigned int            fast_mode :1;
 165 };
 166
 167 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
 168 #define _IDBR(i2c)      ((i2c)->reg_idbr)
 169 #define _ICR(i2c)       ((i2c)->reg_icr)
 170 #define _ISR(i2c)       ((i2c)->reg_isr)
 171 #define _ISAR(i2c)      ((i2c)->reg_isar)
 172
 173 /*
 174  * I2C Slave mode address
 175  */
 176 #define I2C_PXA_SLAVE_ADDR      0x1
 177
 178 #ifdef DEBUG
 179
 180 struct bits {
 181         u32     mask;
 182         const char *set;
 183         const char *unset;
 184 };
 185 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 186
 187 static inline void
 188 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 189 {
 190         printk("%s %08x: ", prefix, val);
 191         while (num--) {
 192                 const char *str = val & bits->mask ? bits->set : bits->unset;
 193                 if (str)
 194                         printk("%s ", str);
 195                 bits++;
 196         }
 197 }
 198
 199 static const struct bits isr_bits[] = {
 200         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 201         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 202         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 203         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 204         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 205         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 206         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 207         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 208         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 209         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 210         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 211 };
 212
 213 static void decode_ISR(unsigned int val)
 214 {
 215         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 216         printk("\n");
 217 }
 218
 219 static const struct bits icr_bits[] = {
 220         PXA_BIT(ICR_START,  "START",    NULL),
 221         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 222         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 223         PXA_BIT(ICR_TB,     "TB",       NULL),
 224         PXA_BIT(ICR_MA,     "MA",       NULL),
 225         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 226         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 227         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 228         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 229         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 230         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 231         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 232         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 233         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 234         PXA_BIT(ICR_UR,     "UR",               "ur"),
 235 };
 236
 237 #ifdef CONFIG_I2C_PXA_SLAVE
 238 static void decode_ICR(unsigned int val)
 239 {
 240         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 241         printk("\n");
 242 }
 243 #endif
 244
 245 static unsigned int i2c_debug = DEBUG;
 246
 247 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 248 {
 249         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 250                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 251 }
 252
 253 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 254
 255 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 256 {
 257         unsigned int i;
 258         printk(KERN_ERR "i2c: error: %s\n", why);
 259         printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 260                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 261         printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
 262                readl(_ICR(i2c)), readl(_ISR(i2c)));
 263         printk(KERN_DEBUG "i2c: log: ");
 264         for (i = 0; i < i2c->irqlogidx; i++)
 265                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 266         printk("\n");
 267 }
 268
 269 #else /* ifdef DEBUG */
 270
 271 #define i2c_debug       0
 272
 273 #define show_state(i2c) do { } while (0)
 274 #define decode_ISR(val) do { } while (0)
 275 #define decode_ICR(val) do { } while (0)
 276 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 277
 278 #endif /* ifdef DEBUG / else */
 279
 280 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 281 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 282
 283 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 284 {
 285         return !(readl(_ICR(i2c)) & ICR_SCLE);
 286 }
 287
 288 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 289 {
 290         int i = 250;
 291
 292         if (i2c_pxa_is_slavemode(i2c)) {
 293                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 294                 return;
 295         }
 296
 297         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 298                 unsigned long icr = readl(_ICR(i2c));
 299
 300                 icr &= ~ICR_START;
 301                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 302
 303                 writel(icr, _ICR(i2c));
 304
 305                 show_state(i2c);
 306
 307                 mdelay(1);
 308                 i --;
 309         }
 310
 311         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 312                _ICR(i2c));
 313 }
 314
 315 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 316 {
 317         int timeout = DEF_TIMEOUT;
 318
 319         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 320                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 321                         timeout += 4;
 322
 323                 msleep(2);
 324                 show_state(i2c);
 325         }
 326
 327         if (timeout < 0)
 328                 show_state(i2c);
 329
 330         return timeout < 0 ? I2C_RETRY : 0;
 331 }
 332
 333 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 334 {
 335         unsigned long timeout = jiffies + HZ*4;
 336
 337         while (time_before(jiffies, timeout)) {
 338                 if (i2c_debug > 1)
 339                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 340                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 341
 342                 if (readl(_ISR(i2c)) & ISR_SAD) {
 343                         if (i2c_debug > 0)
 344                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 345                         goto out;
 346                 }
 347
 348                 /* wait for unit and bus being not busy, and we also do a
 349                  * quick check of the i2c lines themselves to ensure they've
 350                  * gone high...
 351                  */
 352                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 353                         if (i2c_debug > 0)
 354                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 355                         return 1;
 356                 }
 357
 358                 msleep(1);
 359         }
 360
 361         if (i2c_debug > 0)
 362                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 363  out:
 364         return 0;
 365 }
 366
 367 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 368 {
 369         if (i2c_debug)
 370                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 371
 372         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 373                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 374                 if (!i2c_pxa_wait_master(i2c)) {
 375                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 376                         return I2C_RETRY;
 377                 }
 378         }
 379
 380         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 381         return 0;
 382 }
 383
 384 #ifdef CONFIG_I2C_PXA_SLAVE
 385 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 386 {
 387         unsigned long timeout = jiffies + HZ*1;
 388
 389         /* wait for stop */
 390
 391         show_state(i2c);
 392
 393         while (time_before(jiffies, timeout)) {
 394                 if (i2c_debug > 1)
 395                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 396                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 397
 398                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 399                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 400                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 401                         if (i2c_debug > 1)
 402                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 403                         return 1;
 404                 }
 405
 406                 msleep(1);
 407         }
 408
 409         if (i2c_debug > 0)
 410                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 411         return 0;
 412 }
 413
 414 /*
 415  * clear the hold on the bus, and take of anything else
 416  * that has been configured
 417  */
 418 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 419 {
 420         show_state(i2c);
 421
 422         if (errcode < 0) {
 423                 udelay(100);   /* simple delay */
 424         } else {
 425                 /* we need to wait for the stop condition to end */
 426
 427                 /* if we where in stop, then clear... */
 428                 if (readl(_ICR(i2c)) & ICR_STOP) {
 429                         udelay(100);
 430                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 431                 }
 432
 433                 if (!i2c_pxa_wait_slave(i2c)) {
 434                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 435                                 __func__);
 436                         return;
 437                 }
 438         }
 439
 440         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 441         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 442
 443         if (i2c_debug) {
 444                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 445                 decode_ICR(readl(_ICR(i2c)));
 446         }
 447 }
 448 #else
 449 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 450 #endif
 451
 452 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 453 {
 454         pr_debug("Resetting I2C Controller Unit\n");
 455
 456         /* abort any transfer currently under way */
 457         i2c_pxa_abort(i2c);
 458
 459         /* reset according to 9.8 */
 460         writel(ICR_UR, _ICR(i2c));
 461         writel(I2C_ISR_INIT, _ISR(i2c));
 462         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 463
 464         if (i2c->reg_isar)
 465                 writel(i2c->slave_addr, _ISAR(i2c));
 466
 467         /* set control register values */
 468         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 469
 470 #ifdef CONFIG_I2C_PXA_SLAVE
 471         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 472         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 473 #endif
 474
 475         i2c_pxa_set_slave(i2c, 0);
 476
 477         /* enable unit */
 478         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 479         udelay(100);
 480 }
 481
 482
 483 #ifdef CONFIG_I2C_PXA_SLAVE
 484 /*
 485  * PXA I2C Slave mode
 486  */
 487
 488 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 489 {
 490         if (isr & ISR_BED) {
 491                 /* what should we do here? */
 492         } else {
 493                 int ret = 0;
 494
 495                 if (i2c->slave != NULL)
 496                         ret = i2c->slave->read(i2c->slave->data);
 497
 498                 writel(ret, _IDBR(i2c));
 499                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 500         }
 501 }
 502
 503 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 504 {
 505         unsigned int byte = readl(_IDBR(i2c));
 506
 507         if (i2c->slave != NULL)
 508                 i2c->slave->write(i2c->slave->data, byte);
 509
 510         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 511 }
 512
 513 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 514 {
 515         int timeout;
 516
 517         if (i2c_debug > 0)
 518                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 519                        (isr & ISR_RWM) ? 'r' : 't');
 520
 521         if (i2c->slave != NULL)
 522                 i2c->slave->event(i2c->slave->data,
 523                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 524
 525         /*
 526          * slave could interrupt in the middle of us generating a
 527          * start condition... if this happens, we'd better back off
 528          * and stop holding the poor thing up
 529          */
 530         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 531         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 532
 533         timeout = 0x10000;
 534
 535         while (1) {
 536                 if ((readl(_IBMR(i2c)) & 2) == 2)
 537                         break;
 538
 539                 timeout--;
 540
 541                 if (timeout <= 0) {
 542                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 543                         break;
 544                 }
 545         }
 546
 547         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 548 }
 549
 550 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 551 {
 552         if (i2c_debug > 2)
 553                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 554
 555         if (i2c->slave != NULL)
 556                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 557
 558         if (i2c_debug > 2)
 559                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 560
 561         /*
 562          * If we have a master-mode message waiting,
 563          * kick it off now that the slave has completed.
 564          */
 565         if (i2c->msg)
 566                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 567 }
 568 #else
 569 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 570 {
 571         if (isr & ISR_BED) {
 572                 /* what should we do here? */
 573         } else {
 574                 writel(0, _IDBR(i2c));
 575                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 576         }
 577 }
 578
 579 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 580 {
 581         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 582 }
 583
 584 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 585 {
 586         int timeout;
 587
 588         /*
 589          * slave could interrupt in the middle of us generating a
 590          * start condition... if this happens, we'd better back off
 591          * and stop holding the poor thing up
 592          */
 593         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 594         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 595
 596         timeout = 0x10000;
 597
 598         while (1) {
 599                 if ((readl(_IBMR(i2c)) & 2) == 2)
 600                         break;
 601
 602                 timeout--;
 603
 604                 if (timeout <= 0) {
 605                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 606                         break;
 607                 }
 608         }
 609
 610         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 611 }
 612
 613 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 614 {
 615         if (i2c->msg)
 616                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 617 }
 618 #endif
 619
 620 /*
 621  * PXA I2C Master mode
 622  */
 623
 624 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 625 {
 626         unsigned int addr = (msg->addr & 0x7f) << 1;
 627
 628         if (msg->flags & I2C_M_RD)
 629                 addr |= 1;
 630
 631         return addr;
 632 }
 633
 634 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 635 {
 636         u32 icr;
 637
 638         /*
 639          * Step 1: target slave address into IDBR
 640          */
 641         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 642
 643         /*
 644          * Step 2: initiate the write.
 645          */
 646         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 647         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 648 }
 649
 650 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 651 {
 652         u32 icr;
 653
 654         /*
 655          * Clear the STOP and ACK flags
 656          */
 657         icr = readl(_ICR(i2c));
 658         icr &= ~(ICR_STOP | ICR_ACKNAK);
 659         writel(icr, _ICR(i2c));
 660 }
 661
 662 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 663 {
 664         /* make timeout the same as for interrupt based functions */
 665         long timeout = 2 * DEF_TIMEOUT;
 666
 667         /*
 668          * Wait for the bus to become free.
 669          */
 670         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 671                 udelay(1000);
 672                 show_state(i2c);
 673         }
 674
 675         if (timeout < 0) {
 676                 show_state(i2c);
 677                 dev_err(&i2c->adap.dev,
 678                         "i2c_pxa: timeout waiting for bus free\n");
 679                 return I2C_RETRY;
 680         }
 681
 682         /*
 683          * Set master mode.
 684          */
 685         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 686
 687         return 0;
 688 }
 689
 690 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 691                                struct i2c_msg *msg, int num)
 692 {
 693         unsigned long timeout = 500000; /* 5 seconds */
 694         int ret = 0;
 695
 696         ret = i2c_pxa_pio_set_master(i2c);
 697         if (ret)
 698                 goto out;
 699
 700         i2c->msg = msg;
 701         i2c->msg_num = num;
 702         i2c->msg_idx = 0;
 703         i2c->msg_ptr = 0;
 704         i2c->irqlogidx = 0;
 705
 706         i2c_pxa_start_message(i2c);
 707
 708         while (i2c->msg_num > 0 && --timeout) {
 709                 i2c_pxa_handler(0, i2c);
 710                 udelay(10);
 711         }
 712
 713         i2c_pxa_stop_message(i2c);
 714
 715         /*
 716          * We place the return code in i2c->msg_idx.
 717          */
 718         ret = i2c->msg_idx;
 719
 720 out:
 721         if (timeout == 0)
 722                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 723
 724         return ret;
 725 }
 726
 727 /*
 728  * We are protected by the adapter bus mutex.
 729  */
 730 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 731 {
 732         long timeout;
 733         int ret;
 734
 735         /*
 736          * Wait for the bus to become free.
 737          */
 738         ret = i2c_pxa_wait_bus_not_busy(i2c);
 739         if (ret) {
 740                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 741                 goto out;
 742         }
 743
 744         /*
 745          * Set master mode.
 746          */
 747         ret = i2c_pxa_set_master(i2c);
 748         if (ret) {
 749                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 750                 goto out;
 751         }
 752
 753         spin_lock_irq(&i2c->lock);
 754
 755         i2c->msg = msg;
 756         i2c->msg_num = num;
 757         i2c->msg_idx = 0;
 758         i2c->msg_ptr = 0;
 759         i2c->irqlogidx = 0;
 760
 761         i2c_pxa_start_message(i2c);
 762
 763         spin_unlock_irq(&i2c->lock);
 764
 765         /*
 766          * The rest of the processing occurs in the interrupt handler.
 767          */
 768         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 769         i2c_pxa_stop_message(i2c);
 770
 771         /*
 772          * We place the return code in i2c->msg_idx.
 773          */
 774         ret = i2c->msg_idx;
 775
 776         if (!timeout && i2c->msg_num) {
 777                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 778                 ret = I2C_RETRY;
 779         }
 780
 781  out:
 782         return ret;
 783 }
 784
 785 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 786                             struct i2c_msg msgs[], int num)
 787 {
 788         struct pxa_i2c *i2c = adap->algo_data;
 789         int ret, i;
 790
 791         /* If the I2C controller is disabled we need to reset it
 792           (probably due to a suspend/resume destroying state). We do
 793           this here as we can then avoid worrying about resuming the
 794           controller before its users. */
 795         if (!(readl(_ICR(i2c)) & ICR_IUE))
 796                 i2c_pxa_reset(i2c);
 797
 798         for (i = adap->retries; i >= 0; i--) {
 799                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 800                 if (ret != I2C_RETRY)
 801                         goto out;
 802
 803                 if (i2c_debug)
 804                         dev_dbg(&adap->dev, "Retrying transmission\n");
 805                 udelay(100);
 806         }
 807         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 808         ret = -EREMOTEIO;
 809  out:
 810         i2c_pxa_set_slave(i2c, ret);
 811         return ret;
 812 }
 813
 814 /*
 815  * i2c_pxa_master_complete - complete the message and wake up.
 816  */
 817 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 818 {
 819         i2c->msg_ptr = 0;
 820         i2c->msg = NULL;
 821         i2c->msg_idx ++;
 822         i2c->msg_num = 0;
 823         if (ret)
 824                 i2c->msg_idx = ret;
 825         if (!i2c->use_pio)
 826                 wake_up(&i2c->wait);
 827 }
 828
 829 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 830 {
 831         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 832
 833  again:
 834         /*
 835          * If ISR_ALD is set, we lost arbitration.
 836          */
 837         if (isr & ISR_ALD) {
 838                 /*
 839                  * Do we need to do anything here?  The PXA docs
 840                  * are vague about what happens.
 841                  */
 842                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 843
 844                 /*
 845                  * We ignore this error.  We seem to see spurious ALDs
 846                  * for seemingly no reason.  If we handle them as I think
 847                  * they should, we end up causing an I2C error, which
 848                  * is painful for some systems.
 849                  */
 850                 return; /* ignore */
 851         }
 852
 853         if (isr & ISR_BED) {
 854                 int ret = BUS_ERROR;
 855
 856                 /*
 857                  * I2C bus error - either the device NAK'd us, or
 858                  * something more serious happened.  If we were NAK'd
 859                  * on the initial address phase, we can retry.
 860                  */
 861                 if (isr & ISR_ACKNAK) {
 862                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 863                                 ret = I2C_RETRY;
 864                         else
 865                                 ret = XFER_NAKED;
 866                 }
 867                 i2c_pxa_master_complete(i2c, ret);
 868         } else if (isr & ISR_RWM) {
 869                 /*
 870                  * Read mode.  We have just sent the address byte, and
 871                  * now we must initiate the transfer.
 872                  */
 873                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 874                     i2c->msg_idx == i2c->msg_num - 1)
 875                         icr |= ICR_STOP | ICR_ACKNAK;
 876
 877                 icr |= ICR_ALDIE | ICR_TB;
 878         } else if (i2c->msg_ptr < i2c->msg->len) {
 879                 /*
 880                  * Write mode.  Write the next data byte.
 881                  */
 882                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 883
 884                 icr |= ICR_ALDIE | ICR_TB;
 885
 886                 /*
 887                  * If this is the last byte of the last message, send
 888                  * a STOP.
 889                  */
 890                 if (i2c->msg_ptr == i2c->msg->len &&
 891                     i2c->msg_idx == i2c->msg_num - 1)
 892                         icr |= ICR_STOP;
 893         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 894                 /*
 895                  * Next segment of the message.
 896                  */
 897                 i2c->msg_ptr = 0;
 898                 i2c->msg_idx ++;
 899                 i2c->msg++;
 900
 901                 /*
 902                  * If we aren't doing a repeated start and address,
 903                  * go back and try to send the next byte.  Note that
 904                  * we do not support switching the R/W direction here.
 905                  */
 906                 if (i2c->msg->flags & I2C_M_NOSTART)
 907                         goto again;
 908
 909                 /*
 910                  * Write the next address.
 911                  */
 912                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 913
 914                 /*
 915                  * And trigger a repeated start, and send the byte.
 916                  */
 917                 icr &= ~ICR_ALDIE;
 918                 icr |= ICR_START | ICR_TB;
 919         } else {
 920                 if (i2c->msg->len == 0) {
 921                         /*
 922                          * Device probes have a message length of zero
 923                          * and need the bus to be reset before it can
 924                          * be used again.
 925                          */
 926                         i2c_pxa_reset(i2c);
 927                 }
 928                 i2c_pxa_master_complete(i2c, 0);
 929         }
 930
 931         i2c->icrlog[i2c->irqlogidx-1] = icr;
 932
 933         writel(icr, _ICR(i2c));
 934         show_state(i2c);
 935 }
 936
 937 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 938 {
 939         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 940
 941         /*
 942          * Read the byte.
 943          */
 944         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 945
 946         if (i2c->msg_ptr < i2c->msg->len) {
 947                 /*
 948                  * If this is the last byte of the last
 949                  * message, send a STOP.
 950                  */
 951                 if (i2c->msg_ptr == i2c->msg->len - 1)
 952                         icr |= ICR_STOP | ICR_ACKNAK;
 953
 954                 icr |= ICR_ALDIE | ICR_TB;
 955         } else {
 956                 i2c_pxa_master_complete(i2c, 0);
 957         }
 958
 959         i2c->icrlog[i2c->irqlogidx-1] = icr;
 960
 961         writel(icr, _ICR(i2c));
 962 }
 963
 964 #define VALID_INT_SOURCE        (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
 965                                 ISR_SAD | ISR_BED)
 966 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 967 {
 968         struct pxa_i2c *i2c = dev_id;
 969         u32 isr = readl(_ISR(i2c));
 970
 971         if (!(isr & VALID_INT_SOURCE))
 972                 return IRQ_NONE;
 973
 974         if (i2c_debug > 2 && 0) {
 975                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 976                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
 977                 decode_ISR(isr);
 978         }
 979
 980         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 981                 i2c->isrlog[i2c->irqlogidx++] = isr;
 982
 983         show_state(i2c);
 984
 985         /*
 986          * Always clear all pending IRQs.
 987          */
 988         writel(isr & VALID_INT_SOURCE, _ISR(i2c));
 989
 990         if (isr & ISR_SAD)
 991                 i2c_pxa_slave_start(i2c, isr);
 992         if (isr & ISR_SSD)
 993                 i2c_pxa_slave_stop(i2c);
 994
 995         if (i2c_pxa_is_slavemode(i2c)) {
 996                 if (isr & ISR_ITE)
 997                         i2c_pxa_slave_txempty(i2c, isr);
 998                 if (isr & ISR_IRF)
 999                         i2c_pxa_slave_rxfull(i2c, isr);
1000         } else if (i2c->msg) {
1001                 if (isr & ISR_ITE)
1002                         i2c_pxa_irq_txempty(i2c, isr);
1003                 if (isr & ISR_IRF)
1004                         i2c_pxa_irq_rxfull(i2c, isr);
1005         } else {
1006                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1007         }
1008
1009         return IRQ_HANDLED;
1010 }
1011
1012
1013 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1014 {
1015         struct pxa_i2c *i2c = adap->algo_data;
1016         int ret, i;
1017
1018         for (i = adap->retries; i >= 0; i--) {
1019                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1020                 if (ret != I2C_RETRY)
1021                         goto out;
1022
1023                 if (i2c_debug)
1024                         dev_dbg(&adap->dev, "Retrying transmission\n");
1025                 udelay(100);
1026         }
1027         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1028         ret = -EREMOTEIO;
1029  out:
1030         i2c_pxa_set_slave(i2c, ret);
1031         return ret;
1032 }
1033
1034 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1035 {
1036         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1037 }
1038
1039 static const struct i2c_algorithm i2c_pxa_algorithm = {
1040         .master_xfer    = i2c_pxa_xfer,
1041         .functionality  = i2c_pxa_functionality,
1042 };
1043
1044 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1045         .master_xfer    = i2c_pxa_pio_xfer,
1046         .functionality  = i2c_pxa_functionality,
1047 };
1048
1049 static struct of_device_id i2c_pxa_dt_ids[] = {
1050         { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1051         { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1052         { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX },
1053         {}
1054 };
1055 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1056
1057 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1058                             enum pxa_i2c_types *i2c_types)
1059 {
1060         struct device_node *np = pdev->dev.of_node;
1061         const struct of_device_id *of_id =
1062                         of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1063         int ret;
1064
1065         if (!of_id)
1066                 return 1;
1067         ret = of_alias_get_id(np, "i2c");
1068         if (ret < 0) {
1069                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1070                 return ret;
1071         }
1072         pdev->id = ret;
1073         if (of_get_property(np, "mrvl,i2c-polling", NULL))
1074                 i2c->use_pio = 1;
1075         if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1076                 i2c->fast_mode = 1;
1077         *i2c_types = (u32)(of_id->data);
1078         return 0;
1079 }
1080
1081 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1082                                struct pxa_i2c *i2c,
1083                                enum pxa_i2c_types *i2c_types)
1084 {
1085         struct i2c_pxa_platform_data *plat = pdev->dev.platform_data;
1086         const struct platform_device_id *id = platform_get_device_id(pdev);
1087
1088         *i2c_types = id->driver_data;
1089         if (plat) {
1090                 i2c->use_pio = plat->use_pio;
1091                 i2c->fast_mode = plat->fast_mode;
1092         }
1093         return 0;
1094 }
1095
1096 static int i2c_pxa_probe(struct platform_device *dev)
1097 {
1098         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1099         enum pxa_i2c_types i2c_type;
1100         struct pxa_i2c *i2c;
1101         struct resource *res = NULL;
1102         int ret, irq;
1103
1104         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1105         if (!i2c) {
1106                 ret = -ENOMEM;
1107                 goto emalloc;
1108         }
1109
1110         ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1111         if (ret > 0)
1112                 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1113         if (ret < 0)
1114                 goto eclk;
1115
1116         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1117         irq = platform_get_irq(dev, 0);
1118         if (res == NULL || irq < 0) {
1119                 ret = -ENODEV;
1120                 goto eclk;
1121         }
1122
1123         if (!request_mem_region(res->start, resource_size(res), res->name)) {
1124                 ret = -ENOMEM;
1125                 goto eclk;
1126         }
1127
1128         i2c->adap.owner   = THIS_MODULE;
1129         i2c->adap.retries = 5;
1130
1131         spin_lock_init(&i2c->lock);
1132         init_waitqueue_head(&i2c->wait);
1133
1134         i2c->adap.nr = dev->id;
1135         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1136                  i2c->adap.nr);
1137
1138         i2c->clk = clk_get(&dev->dev, NULL);
1139         if (IS_ERR(i2c->clk)) {
1140                 ret = PTR_ERR(i2c->clk);
1141                 goto eclk;
1142         }
1143
1144         i2c->reg_base = ioremap(res->start, resource_size(res));
1145         if (!i2c->reg_base) {
1146                 ret = -EIO;
1147                 goto eremap;
1148         }
1149
1150         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1151         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1152         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1153         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1154         if (i2c_type != REGS_CE4100)
1155                 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1156
1157         i2c->iobase = res->start;
1158         i2c->iosize = resource_size(res);
1159
1160         i2c->irq = irq;
1161
1162         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1163
1164         if (plat) {
1165 #ifdef CONFIG_I2C_PXA_SLAVE
1166                 i2c->slave_addr = plat->slave_addr;
1167                 i2c->slave = plat->slave;
1168 #endif
1169                 i2c->adap.class = plat->class;
1170         }
1171
1172         clk_enable(i2c->clk);
1173
1174         if (i2c->use_pio) {
1175                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1176         } else {
1177                 i2c->adap.algo = &i2c_pxa_algorithm;
1178                 ret = request_irq(irq, i2c_pxa_handler, IRQF_SHARED,
1179                                   i2c->adap.name, i2c);
1180                 if (ret)
1181                         goto ereqirq;
1182         }
1183
1184         i2c_pxa_reset(i2c);
1185
1186         i2c->adap.algo_data = i2c;
1187         i2c->adap.dev.parent = &dev->dev;
1188 #ifdef CONFIG_OF
1189         i2c->adap.dev.of_node = dev->dev.of_node;
1190 #endif
1191
1192         ret = i2c_add_numbered_adapter(&i2c->adap);
1193         if (ret < 0) {
1194                 printk(KERN_INFO "I2C: Failed to add bus\n");
1195                 goto eadapt;
1196         }
1197         of_i2c_register_devices(&i2c->adap);
1198
1199         platform_set_drvdata(dev, i2c);
1200
1201 #ifdef CONFIG_I2C_PXA_SLAVE
1202         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1203                dev_name(&i2c->adap.dev), i2c->slave_addr);
1204 #else
1205         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1206                dev_name(&i2c->adap.dev));
1207 #endif
1208         return 0;
1209
1210 eadapt:
1211         if (!i2c->use_pio)
1212                 free_irq(irq, i2c);
1213 ereqirq:
1214         clk_disable(i2c->clk);
1215         iounmap(i2c->reg_base);
1216 eremap:
1217         clk_put(i2c->clk);
1218 eclk:
1219         kfree(i2c);
1220 emalloc:
1221         release_mem_region(res->start, resource_size(res));
1222         return ret;
1223 }
1224
1225 static int __exit i2c_pxa_remove(struct platform_device *dev)
1226 {
1227         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1228
1229         platform_set_drvdata(dev, NULL);
1230
1231         i2c_del_adapter(&i2c->adap);
1232         if (!i2c->use_pio)
1233                 free_irq(i2c->irq, i2c);
1234
1235         clk_disable(i2c->clk);
1236         clk_put(i2c->clk);
1237
1238         iounmap(i2c->reg_base);
1239         release_mem_region(i2c->iobase, i2c->iosize);
1240         kfree(i2c);
1241
1242         return 0;
1243 }
1244
1245 #ifdef CONFIG_PM
1246 static int i2c_pxa_suspend_noirq(struct device *dev)
1247 {
1248         struct platform_device *pdev = to_platform_device(dev);
1249         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1250
1251         clk_disable(i2c->clk);
1252
1253         return 0;
1254 }
1255
1256 static int i2c_pxa_resume_noirq(struct device *dev)
1257 {
1258         struct platform_device *pdev = to_platform_device(dev);
1259         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1260
1261         clk_enable(i2c->clk);
1262         i2c_pxa_reset(i2c);
1263
1264         return 0;
1265 }
1266
1267 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1268         .suspend_noirq = i2c_pxa_suspend_noirq,
1269         .resume_noirq = i2c_pxa_resume_noirq,
1270 };
1271
1272 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1273 #else
1274 #define I2C_PXA_DEV_PM_OPS NULL
1275 #endif
1276
1277 static struct platform_driver i2c_pxa_driver = {
1278         .probe          = i2c_pxa_probe,
1279         .remove         = __exit_p(i2c_pxa_remove),
1280         .driver         = {
1281                 .name   = "pxa2xx-i2c",
1282                 .owner  = THIS_MODULE,
1283                 .pm     = I2C_PXA_DEV_PM_OPS,
1284                 .of_match_table = i2c_pxa_dt_ids,
1285         },
1286         .id_table       = i2c_pxa_id_table,
1287 };
1288
1289 static int __init i2c_adap_pxa_init(void)
1290 {
1291         return platform_driver_register(&i2c_pxa_driver);
1292 }
1293
1294 static void __exit i2c_adap_pxa_exit(void)
1295 {
1296         platform_driver_unregister(&i2c_pxa_driver);
1297 }
1298
1299 MODULE_LICENSE("GPL");
1300 MODULE_ALIAS("platform:pxa2xx-i2c");
1301
1302 subsys_initcall(i2c_adap_pxa_init);
1303 module_exit(i2c_adap_pxa_exit);