2 * SuperH Mobile I2C Controller
4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2008 Magnus Damm
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/dmaengine.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/err.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/i2c-sh_mobile.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/slab.h>
38 /* Transmit operation: */
41 /* BUS: S A8 ACK P(*) */
48 /* BUS: S A8 ACK D8(1) ACK P(*) */
49 /* IRQ: DTE WAIT WAIT */
55 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
56 /* IRQ: DTE WAIT WAIT WAIT */
59 /* ICDR: A8 D8(1) D8(2) */
61 /* 3 bytes or more, +---------+ gets repeated */
64 /* Receive operation: */
66 /* 0 byte receive - not supported since slave may hold SDA low */
68 /* 1 byte receive [TX] | [RX] */
69 /* BUS: S A8 ACK | D8(1) ACK P(*) */
70 /* IRQ: DTE WAIT | WAIT DTE */
71 /* ICIC: -DTE | +DTE */
72 /* ICCR: 0x94 0x81 | 0xc0 */
73 /* ICDR: A8 | D8(1) */
75 /* 2 byte receive [TX]| [RX] */
76 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
77 /* IRQ: DTE WAIT | WAIT WAIT DTE */
78 /* ICIC: -DTE | +DTE */
79 /* ICCR: 0x94 0x81 | 0xc0 */
80 /* ICDR: A8 | D8(1) D8(2) */
82 /* 3 byte receive [TX] | [RX] (*) */
83 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
84 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
85 /* ICIC: -DTE | +DTE */
86 /* ICCR: 0x94 0x81 | 0xc0 */
87 /* ICDR: A8 | D8(1) D8(2) D8(3) */
89 /* 4 bytes or more, this part is repeated +---------+ */
92 /* Interrupt order and BUSY flag */
94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
95 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
97 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
99 /* WAIT IRQ ________________________________/ \___________ */
100 /* TACK IRQ ____________________________________/ \_______ */
101 /* DTE IRQ __________________________________________/ \_ */
102 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
103 /* _______________________________________________ */
106 /* (*) The STOP condition is only sent by the master at the end of the last */
107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
108 /* only cleared after the STOP condition, so, between messages we have to */
109 /* poll for the DTE bit. */
112 enum sh_mobile_i2c_op {
124 struct sh_mobile_i2c_data {
127 struct i2c_adapter adap;
128 unsigned long bus_speed;
129 unsigned int clks_per_count;
137 wait_queue_head_t wait;
143 struct dma_chan *dma_tx;
144 struct dma_chan *dma_rx;
145 struct scatterlist sg;
146 enum dma_data_direction dma_direction;
149 struct sh_mobile_dt_config {
153 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
155 #define STANDARD_MODE 100000
156 #define FAST_MODE 400000
158 /* Register offsets */
167 #define ICCR_ICE 0x80
168 #define ICCR_RACK 0x40
169 #define ICCR_TRS 0x10
170 #define ICCR_BBSY 0x04
171 #define ICCR_SCP 0x01
173 #define ICSR_SCLM 0x80
174 #define ICSR_SDAM 0x40
176 #define ICSR_BUSY 0x10
178 #define ICSR_TACK 0x04
179 #define ICSR_WAIT 0x02
180 #define ICSR_DTE 0x01
182 #define ICIC_ICCLB8 0x80
183 #define ICIC_ICCHB8 0x40
184 #define ICIC_TDMAE 0x20
185 #define ICIC_RDMAE 0x10
186 #define ICIC_ALE 0x08
187 #define ICIC_TACKE 0x04
188 #define ICIC_WAITE 0x02
189 #define ICIC_DTEE 0x01
191 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
196 iowrite8(data, pd->reg + offs);
199 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
201 return ioread8(pd->reg + offs);
204 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
205 unsigned char set, unsigned char clr)
207 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
210 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
213 * Conditional expression:
214 * ICCL >= COUNT_CLK * (tLOW + tf)
216 * SH-Mobile IIC hardware starts counting the LOW period of
217 * the SCL signal (tLOW) as soon as it pulls the SCL line.
218 * In order to meet the tLOW timing spec, we need to take into
219 * account the fall time of SCL signal (tf). Default tf value
220 * should be 0.3 us, for safety.
222 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
225 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
228 * Conditional expression:
229 * ICCH >= COUNT_CLK * (tHIGH + tf)
231 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
232 * and can ignore it. SH-Mobile IIC controller starts counting
233 * the HIGH period of the SCL signal (tHIGH) after the SCL input
234 * voltage increases at VIH.
236 * Afterward it turned out calculating ICCH using only tHIGH spec
237 * will result in violation of the tHD;STA timing spec. We need
238 * to take into account the fall time of SDA signal (tf) at START
239 * condition, in order to meet both tHIGH and tHD;STA specs.
241 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
244 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
246 unsigned long i2c_clk_khz;
250 /* Get clock rate after clock is enabled */
251 clk_prepare_enable(pd->clk);
252 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
253 clk_disable_unprepare(pd->clk);
254 i2c_clk_khz /= pd->clks_per_count;
256 if (pd->bus_speed == STANDARD_MODE) {
257 tLOW = 47; /* tLOW = 4.7 us */
258 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
259 tf = 3; /* tf = 0.3 us */
260 } else if (pd->bus_speed == FAST_MODE) {
261 tLOW = 13; /* tLOW = 1.3 us */
262 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
263 tf = 3; /* tf = 0.3 us */
265 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
270 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
271 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
273 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
274 if (pd->iccl > max_val || pd->icch > max_val) {
275 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
280 /* one more bit of ICCL in ICIC */
281 if (pd->iccl & 0x100)
282 pd->icic |= ICIC_ICCLB8;
284 pd->icic &= ~ICIC_ICCLB8;
286 /* one more bit of ICCH in ICIC */
287 if (pd->icch & 0x100)
288 pd->icic |= ICIC_ICCHB8;
290 pd->icic &= ~ICIC_ICCHB8;
292 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
296 static void activate_ch(struct sh_mobile_i2c_data *pd)
298 /* Wake up device and enable clock */
299 pm_runtime_get_sync(pd->dev);
300 clk_prepare_enable(pd->clk);
302 /* Enable channel and configure rx ack */
303 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
305 /* Mask all interrupts */
309 iic_wr(pd, ICCL, pd->iccl & 0xff);
310 iic_wr(pd, ICCH, pd->icch & 0xff);
313 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
315 /* Clear/disable interrupts */
319 /* Disable channel */
320 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
322 /* Disable clock and mark device as idle */
323 clk_disable_unprepare(pd->clk);
324 pm_runtime_put_sync(pd->dev);
327 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
328 enum sh_mobile_i2c_op op, unsigned char data)
330 unsigned char ret = 0;
333 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
335 spin_lock_irqsave(&pd->lock, flags);
338 case OP_START: /* issue start and trigger DTE interrupt */
339 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
341 case OP_TX_FIRST: /* disable DTE interrupt and write data */
342 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
343 iic_wr(pd, ICDR, data);
345 case OP_TX: /* write data */
346 iic_wr(pd, ICDR, data);
348 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
349 iic_wr(pd, ICDR, data);
351 case OP_TX_STOP: /* issue a stop */
352 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
353 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
355 case OP_TX_TO_RX: /* select read mode */
356 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
358 case OP_RX: /* just read data */
359 ret = iic_rd(pd, ICDR);
361 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
363 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
364 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
366 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
368 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
369 ret = iic_rd(pd, ICDR);
370 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
374 spin_unlock_irqrestore(&pd->lock, flags);
376 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
380 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
382 return pd->pos == -1;
385 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
387 return pd->pos == pd->msg->len - 1;
390 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
395 *buf = (pd->msg->addr & 0x7f) << 1;
396 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
399 *buf = pd->msg->buf[pd->pos];
403 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
407 if (pd->pos == pd->msg->len) {
408 /* Send stop if we haven't yet (DMA case) */
409 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY))
410 i2c_op(pd, OP_TX_STOP, 0);
414 sh_mobile_i2c_get_data(pd, &data);
416 if (sh_mobile_i2c_is_last_byte(pd))
417 i2c_op(pd, OP_TX_STOP_DATA, data);
418 else if (sh_mobile_i2c_is_first_byte(pd))
419 i2c_op(pd, OP_TX_FIRST, data);
421 i2c_op(pd, OP_TX, data);
427 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
434 sh_mobile_i2c_get_data(pd, &data);
436 if (sh_mobile_i2c_is_first_byte(pd))
437 i2c_op(pd, OP_TX_FIRST, data);
439 i2c_op(pd, OP_TX, data);
444 i2c_op(pd, OP_TX_TO_RX, 0);
448 real_pos = pd->pos - 2;
450 if (pd->pos == pd->msg->len) {
452 i2c_op(pd, OP_RX_STOP, 0);
455 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
457 data = i2c_op(pd, OP_RX, 0);
460 pd->msg->buf[real_pos] = data;
464 return pd->pos == (pd->msg->len + 2);
467 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
469 struct platform_device *dev = dev_id;
470 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
474 sr = iic_rd(pd, ICSR);
475 pd->sr |= sr; /* remember state */
477 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
478 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
479 pd->pos, pd->msg->len);
481 /* Kick off TxDMA after preface was done */
482 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
483 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
484 else if (sr & (ICSR_AL | ICSR_TACK))
485 /* don't interrupt transaction - continue to issue stop */
486 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
487 else if (pd->msg->flags & I2C_M_RD)
488 wakeup = sh_mobile_i2c_isr_rx(pd);
490 wakeup = sh_mobile_i2c_isr_tx(pd);
492 /* Kick off RxDMA after preface was done */
493 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
494 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
496 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
497 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
504 /* defeat write posting to avoid spurious WAIT interrupts */
510 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
512 if (pd->dma_direction == DMA_NONE)
514 else if (pd->dma_direction == DMA_FROM_DEVICE)
515 dmaengine_terminate_all(pd->dma_rx);
516 else if (pd->dma_direction == DMA_TO_DEVICE)
517 dmaengine_terminate_all(pd->dma_tx);
519 dma_unmap_single(pd->dev, sg_dma_address(&pd->sg),
520 pd->msg->len, pd->dma_direction);
522 pd->dma_direction = DMA_NONE;
525 static void sh_mobile_i2c_dma_callback(void *data)
527 struct sh_mobile_i2c_data *pd = data;
529 dma_unmap_single(pd->dev, sg_dma_address(&pd->sg),
530 pd->msg->len, pd->dma_direction);
532 pd->dma_direction = DMA_NONE;
533 pd->pos = pd->msg->len;
535 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
538 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
540 bool read = pd->msg->flags & I2C_M_RD;
541 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
542 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
543 struct dma_async_tx_descriptor *txdesc;
550 dma_addr = dma_map_single(pd->dev, pd->msg->buf, pd->msg->len, dir);
551 if (dma_mapping_error(pd->dev, dma_addr)) {
552 dev_dbg(pd->dev, "dma map failed, using PIO\n");
556 sg_dma_len(&pd->sg) = pd->msg->len;
557 sg_dma_address(&pd->sg) = dma_addr;
559 pd->dma_direction = dir;
561 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
562 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
563 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
565 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
566 sh_mobile_i2c_cleanup_dma(pd);
570 txdesc->callback = sh_mobile_i2c_dma_callback;
571 txdesc->callback_param = pd;
573 cookie = dmaengine_submit(txdesc);
574 if (dma_submit_error(cookie)) {
575 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
576 sh_mobile_i2c_cleanup_dma(pd);
580 dma_async_issue_pending(chan);
583 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
586 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
587 dev_err(pd->dev, "Unsupported zero length i2c read\n");
592 /* Initialize channel registers */
593 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
595 /* Enable channel and configure rx ack */
596 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
599 iic_wr(pd, ICCL, pd->iccl & 0xff);
600 iic_wr(pd, ICCH, pd->icch & 0xff);
607 if (pd->msg->len > 8)
608 sh_mobile_i2c_xfer_dma(pd);
610 /* Enable all interrupts to begin with */
611 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
615 static int poll_dte(struct sh_mobile_i2c_data *pd)
619 for (i = 1000; i; i--) {
620 u_int8_t val = iic_rd(pd, ICSR);
631 return i ? 0 : -ETIMEDOUT;
634 static int poll_busy(struct sh_mobile_i2c_data *pd)
638 for (i = 1000; i; i--) {
639 u_int8_t val = iic_rd(pd, ICSR);
641 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
643 /* the interrupt handler may wake us up before the
644 * transfer is finished, so poll the hardware
647 if (!(val & ICSR_BUSY)) {
648 /* handle missing acknowledge and arbitration lost */
660 return i ? 0 : -ETIMEDOUT;
663 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
664 struct i2c_msg *msgs,
667 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
674 /* Process all messages */
675 for (i = 0; i < num; i++) {
676 bool do_start = pd->send_stop || !i;
678 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
680 err = start_ch(pd, msg, do_start);
685 i2c_op(pd, OP_START, 0);
687 /* The interrupt handler takes care of the rest... */
688 k = wait_event_timeout(pd->wait,
689 pd->sr & (ICSR_TACK | SW_DONE),
692 dev_err(pd->dev, "Transfer request timed out\n");
693 if (pd->dma_direction != DMA_NONE)
694 sh_mobile_i2c_cleanup_dma(pd);
715 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
717 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
720 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
721 .functionality = sh_mobile_i2c_func,
722 .master_xfer = sh_mobile_i2c_xfer,
725 static const struct sh_mobile_dt_config default_dt_config = {
729 static const struct sh_mobile_dt_config fast_clock_dt_config = {
733 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
734 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
735 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
736 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
737 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
738 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
739 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
740 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
741 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
744 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
746 static int sh_mobile_i2c_request_dma_chan(struct device *dev, enum dma_transfer_direction dir,
747 dma_addr_t port_addr, struct dma_chan **chan_ptr)
750 struct dma_chan *chan;
751 struct dma_slave_config cfg;
752 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
756 dma_cap_set(DMA_SLAVE, mask);
759 chan = dma_request_slave_channel_reason(dev, chan_name);
762 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
766 memset(&cfg, 0, sizeof(cfg));
768 if (dir == DMA_MEM_TO_DEV) {
769 cfg.dst_addr = port_addr;
770 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
772 cfg.src_addr = port_addr;
773 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
776 ret = dmaengine_slave_config(chan, &cfg);
778 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
779 dma_release_channel(chan);
785 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
789 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
792 dma_release_channel(pd->dma_tx);
797 dma_release_channel(pd->dma_rx);
802 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev)
804 struct resource *res;
808 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
809 for (n = res->start; n <= res->end; n++) {
810 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
811 0, dev_name(&dev->dev), dev);
813 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
820 return k > 0 ? 0 : -ENOENT;
823 static int sh_mobile_i2c_probe(struct platform_device *dev)
825 struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
826 struct sh_mobile_i2c_data *pd;
827 struct i2c_adapter *adap;
828 struct resource *res;
832 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
836 pd->clk = devm_clk_get(&dev->dev, NULL);
837 if (IS_ERR(pd->clk)) {
838 dev_err(&dev->dev, "cannot get clock\n");
839 return PTR_ERR(pd->clk);
842 ret = sh_mobile_i2c_hook_irqs(dev);
847 platform_set_drvdata(dev, pd);
849 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
851 pd->reg = devm_ioremap_resource(&dev->dev, res);
853 return PTR_ERR(pd->reg);
855 /* Use platform data bus speed or STANDARD_MODE */
856 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
857 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
859 pd->clks_per_count = 1;
861 if (dev->dev.of_node) {
862 const struct of_device_id *match;
864 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
866 const struct sh_mobile_dt_config *config;
868 config = match->data;
869 pd->clks_per_count = config->clks_per_count;
872 if (pdata && pdata->bus_speed)
873 pd->bus_speed = pdata->bus_speed;
874 if (pdata && pdata->clks_per_count)
875 pd->clks_per_count = pdata->clks_per_count;
878 /* The IIC blocks on SH-Mobile ARM processors
879 * come with two new bits in ICIC.
881 if (resource_size(res) > 0x17)
882 pd->flags |= IIC_FLAG_HAS_ICIC67;
884 ret = sh_mobile_i2c_init(pd);
889 sg_init_table(&pd->sg, 1);
890 pd->dma_direction = DMA_NONE;
891 ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
892 res->start + ICDR, &pd->dma_rx);
893 if (ret == -EPROBE_DEFER)
896 ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
897 res->start + ICDR, &pd->dma_tx);
898 if (ret == -EPROBE_DEFER) {
899 sh_mobile_i2c_release_dma(pd);
903 /* Enable Runtime PM for this device.
905 * Also tell the Runtime PM core to ignore children
906 * for this device since it is valid for us to suspend
907 * this I2C master driver even though the slave devices
908 * on the I2C bus may not be suspended.
910 * The state of the I2C hardware bus is unaffected by
911 * the Runtime PM state.
913 pm_suspend_ignore_children(&dev->dev, true);
914 pm_runtime_enable(&dev->dev);
916 /* setup the private data */
918 i2c_set_adapdata(adap, pd);
920 adap->owner = THIS_MODULE;
921 adap->algo = &sh_mobile_i2c_algorithm;
922 adap->dev.parent = &dev->dev;
925 adap->dev.of_node = dev->dev.of_node;
927 strlcpy(adap->name, dev->name, sizeof(adap->name));
929 spin_lock_init(&pd->lock);
930 init_waitqueue_head(&pd->wait);
932 ret = i2c_add_numbered_adapter(adap);
934 sh_mobile_i2c_release_dma(pd);
935 dev_err(&dev->dev, "cannot add numbered adapter\n");
939 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz, DMA=%c\n",
940 adap->nr, pd->bus_speed, (pd->dma_rx || pd->dma_tx) ? 'y' : 'n');
945 static int sh_mobile_i2c_remove(struct platform_device *dev)
947 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
949 i2c_del_adapter(&pd->adap);
950 sh_mobile_i2c_release_dma(pd);
951 pm_runtime_disable(&dev->dev);
955 static int sh_mobile_i2c_runtime_nop(struct device *dev)
957 /* Runtime PM callback shared between ->runtime_suspend()
958 * and ->runtime_resume(). Simply returns success.
960 * This driver re-initializes all registers after
961 * pm_runtime_get_sync() anyway so there is no need
962 * to save and restore registers here.
967 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
968 .runtime_suspend = sh_mobile_i2c_runtime_nop,
969 .runtime_resume = sh_mobile_i2c_runtime_nop,
972 static struct platform_driver sh_mobile_i2c_driver = {
974 .name = "i2c-sh_mobile",
975 .owner = THIS_MODULE,
976 .pm = &sh_mobile_i2c_dev_pm_ops,
977 .of_match_table = sh_mobile_i2c_dt_ids,
979 .probe = sh_mobile_i2c_probe,
980 .remove = sh_mobile_i2c_remove,
983 static int __init sh_mobile_i2c_adap_init(void)
985 return platform_driver_register(&sh_mobile_i2c_driver);
987 subsys_initcall(sh_mobile_i2c_adap_init);
989 static void __exit sh_mobile_i2c_adap_exit(void)
991 platform_driver_unregister(&sh_mobile_i2c_driver);
993 module_exit(sh_mobile_i2c_adap_exit);
995 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
996 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
997 MODULE_LICENSE("GPL v2");
998 MODULE_ALIAS("platform:i2c-sh_mobile");