drivers/i2c/busses/i2c-sh_mobile.c

   1 /*
   2  * SuperH Mobile I2C Controller
   3  *
   4  * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
   5  *
   6  * Copyright (C) 2008 Magnus Damm
   7  *
   8  * Portions of the code based on out-of-tree driver i2c-sh7343.c
   9  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/delay.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/err.h>
  26 #include <linux/i2c.h>
  27 #include <linux/i2c/i2c-sh_mobile.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/of_device.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/pm_runtime.h>
  36 #include <linux/slab.h>
  37
  38 /* Transmit operation:                                                      */
  39 /*                                                                          */
  40 /* 0 byte transmit                                                          */
  41 /* BUS:     S     A8     ACK   P(*)                                         */
  42 /* IRQ:       DTE   WAIT                                                    */
  43 /* ICIC:                                                                    */
  44 /* ICCR: 0x94 0x90                                                          */
  45 /* ICDR:      A8                                                            */
  46 /*                                                                          */
  47 /* 1 byte transmit                                                          */
  48 /* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  49 /* IRQ:       DTE   WAIT         WAIT                                       */
  50 /* ICIC:      -DTE                                                          */
  51 /* ICCR: 0x94       0x90                                                    */
  52 /* ICDR:      A8    D8(1)                                                   */
  53 /*                                                                          */
  54 /* 2 byte transmit                                                          */
  55 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  56 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  57 /* ICIC:      -DTE                                                          */
  58 /* ICCR: 0x94                    0x90                                       */
  59 /* ICDR:      A8    D8(1)        D8(2)                                      */
  60 /*                                                                          */
  61 /* 3 bytes or more, +---------+ gets repeated                               */
  62 /*                                                                          */
  63 /*                                                                          */
  64 /* Receive operation:                                                       */
  65 /*                                                                          */
  66 /* 0 byte receive - not supported since slave may hold SDA low              */
  67 /*                                                                          */
  68 /* 1 byte receive       [TX] | [RX]                                         */
  69 /* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  70 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  71 /* ICIC:      -DTE           |   +DTE                                       */
  72 /* ICCR: 0x94       0x81     |   0xc0                                       */
  73 /* ICDR:      A8             |            D8(1)                             */
  74 /*                                                                          */
  75 /* 2 byte receive        [TX]| [RX]                                         */
  76 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  77 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  78 /* ICIC:      -DTE           |                 +DTE                         */
  79 /* ICCR: 0x94       0x81     |                 0xc0                         */
  80 /* ICDR:      A8             |                 D8(1)    D8(2)               */
  81 /*                                                                          */
  82 /* 3 byte receive       [TX] | [RX]                                     (*) */
  83 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  84 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  85 /* ICIC:      -DTE           |                              +DTE            */
  86 /* ICCR: 0x94       0x81     |                              0xc0            */
  87 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  88 /*                                                                          */
  89 /* 4 bytes or more, this part is repeated    +---------+                    */
  90 /*                                                                          */
  91 /*                                                                          */
  92 /* Interrupt order and BUSY flag                                            */
  93 /*     ___                                                 _                */
  94 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  95 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  96 /*                                                                          */
  97 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  98 /*                                           ___                            */
  99 /* WAIT IRQ ________________________________/   \___________                */
 100 /* TACK IRQ ____________________________________/   \_______                */
 101 /* DTE  IRQ __________________________________________/   \_                */
 102 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
 103 /*         _______________________________________________                  */
 104 /* BUSY __/                                               \_                */
 105 /*                                                                          */
 106 /* (*) The STOP condition is only sent by the master at the end of the last */
 107 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
 108 /* only cleared after the STOP condition, so, between messages we have to   */
 109 /* poll for the DTE bit.                                                    */
 110 /*                                                                          */
 111
 112 enum sh_mobile_i2c_op {
 113         OP_START = 0,
 114         OP_TX_FIRST,
 115         OP_TX,
 116         OP_TX_STOP,
 117         OP_TX_STOP_DATA,
 118         OP_TX_TO_RX,
 119         OP_RX,
 120         OP_RX_STOP,
 121         OP_RX_STOP_DATA,
 122 };
 123
 124 struct sh_mobile_i2c_data {
 125         struct device *dev;
 126         void __iomem *reg;
 127         struct i2c_adapter adap;
 128         unsigned long bus_speed;
 129         unsigned int clks_per_count;
 130         struct clk *clk;
 131         u_int8_t icic;
 132         u_int8_t flags;
 133         u_int16_t iccl;
 134         u_int16_t icch;
 135
 136         spinlock_t lock;
 137         wait_queue_head_t wait;
 138         struct i2c_msg *msg;
 139         int pos;
 140         int sr;
 141         bool send_stop;
 142
 143         struct dma_chan *dma_tx;
 144         struct dma_chan *dma_rx;
 145         struct scatterlist sg;
 146         enum dma_data_direction dma_direction;
 147 };
 148
 149 struct sh_mobile_dt_config {
 150         int clks_per_count;
 151 };
 152
 153 #define IIC_FLAG_HAS_ICIC67     (1 << 0)
 154
 155 #define STANDARD_MODE           100000
 156 #define FAST_MODE               400000
 157
 158 /* Register offsets */
 159 #define ICDR                    0x00
 160 #define ICCR                    0x04
 161 #define ICSR                    0x08
 162 #define ICIC                    0x0c
 163 #define ICCL                    0x10
 164 #define ICCH                    0x14
 165
 166 /* Register bits */
 167 #define ICCR_ICE                0x80
 168 #define ICCR_RACK               0x40
 169 #define ICCR_TRS                0x10
 170 #define ICCR_BBSY               0x04
 171 #define ICCR_SCP                0x01
 172
 173 #define ICSR_SCLM               0x80
 174 #define ICSR_SDAM               0x40
 175 #define SW_DONE                 0x20
 176 #define ICSR_BUSY               0x10
 177 #define ICSR_AL                 0x08
 178 #define ICSR_TACK               0x04
 179 #define ICSR_WAIT               0x02
 180 #define ICSR_DTE                0x01
 181
 182 #define ICIC_ICCLB8             0x80
 183 #define ICIC_ICCHB8             0x40
 184 #define ICIC_TDMAE              0x20
 185 #define ICIC_RDMAE              0x10
 186 #define ICIC_ALE                0x08
 187 #define ICIC_TACKE              0x04
 188 #define ICIC_WAITE              0x02
 189 #define ICIC_DTEE               0x01
 190
 191 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 192 {
 193         if (offs == ICIC)
 194                 data |= pd->icic;
 195
 196         iowrite8(data, pd->reg + offs);
 197 }
 198
 199 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 200 {
 201         return ioread8(pd->reg + offs);
 202 }
 203
 204 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 205                         unsigned char set, unsigned char clr)
 206 {
 207         iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 208 }
 209
 210 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 211 {
 212         /*
 213          * Conditional expression:
 214          *   ICCL >= COUNT_CLK * (tLOW + tf)
 215          *
 216          * SH-Mobile IIC hardware starts counting the LOW period of
 217          * the SCL signal (tLOW) as soon as it pulls the SCL line.
 218          * In order to meet the tLOW timing spec, we need to take into
 219          * account the fall time of SCL signal (tf).  Default tf value
 220          * should be 0.3 us, for safety.
 221          */
 222         return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 223 }
 224
 225 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 226 {
 227         /*
 228          * Conditional expression:
 229          *   ICCH >= COUNT_CLK * (tHIGH + tf)
 230          *
 231          * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 232          * and can ignore it.  SH-Mobile IIC controller starts counting
 233          * the HIGH period of the SCL signal (tHIGH) after the SCL input
 234          * voltage increases at VIH.
 235          *
 236          * Afterward it turned out calculating ICCH using only tHIGH spec
 237          * will result in violation of the tHD;STA timing spec.  We need
 238          * to take into account the fall time of SDA signal (tf) at START
 239          * condition, in order to meet both tHIGH and tHD;STA specs.
 240          */
 241         return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 242 }
 243
 244 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 245 {
 246         unsigned long i2c_clk_khz;
 247         u32 tHIGH, tLOW, tf;
 248         uint16_t max_val;
 249
 250         /* Get clock rate after clock is enabled */
 251         clk_prepare_enable(pd->clk);
 252         i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
 253         clk_disable_unprepare(pd->clk);
 254         i2c_clk_khz /= pd->clks_per_count;
 255
 256         if (pd->bus_speed == STANDARD_MODE) {
 257                 tLOW    = 47;   /* tLOW = 4.7 us */
 258                 tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 259                 tf      = 3;    /* tf = 0.3 us */
 260         } else if (pd->bus_speed == FAST_MODE) {
 261                 tLOW    = 13;   /* tLOW = 1.3 us */
 262                 tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 263                 tf      = 3;    /* tf = 0.3 us */
 264         } else {
 265                 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 266                         pd->bus_speed);
 267                 return -EINVAL;
 268         }
 269
 270         pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 271         pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 272
 273         max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 274         if (pd->iccl > max_val || pd->icch > max_val) {
 275                 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 276                         pd->iccl, pd->icch);
 277                 return -EINVAL;
 278         }
 279
 280         /* one more bit of ICCL in ICIC */
 281         if (pd->iccl & 0x100)
 282                 pd->icic |= ICIC_ICCLB8;
 283         else
 284                 pd->icic &= ~ICIC_ICCLB8;
 285
 286         /* one more bit of ICCH in ICIC */
 287         if (pd->icch & 0x100)
 288                 pd->icic |= ICIC_ICCHB8;
 289         else
 290                 pd->icic &= ~ICIC_ICCHB8;
 291
 292         dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 293         return 0;
 294 }
 295
 296 static void activate_ch(struct sh_mobile_i2c_data *pd)
 297 {
 298         /* Wake up device and enable clock */
 299         pm_runtime_get_sync(pd->dev);
 300         clk_prepare_enable(pd->clk);
 301
 302         /* Enable channel and configure rx ack */
 303         iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 304
 305         /* Mask all interrupts */
 306         iic_wr(pd, ICIC, 0);
 307
 308         /* Set the clock */
 309         iic_wr(pd, ICCL, pd->iccl & 0xff);
 310         iic_wr(pd, ICCH, pd->icch & 0xff);
 311 }
 312
 313 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 314 {
 315         /* Clear/disable interrupts */
 316         iic_wr(pd, ICSR, 0);
 317         iic_wr(pd, ICIC, 0);
 318
 319         /* Disable channel */
 320         iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 321
 322         /* Disable clock and mark device as idle */
 323         clk_disable_unprepare(pd->clk);
 324         pm_runtime_put_sync(pd->dev);
 325 }
 326
 327 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 328                             enum sh_mobile_i2c_op op, unsigned char data)
 329 {
 330         unsigned char ret = 0;
 331         unsigned long flags;
 332
 333         dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 334
 335         spin_lock_irqsave(&pd->lock, flags);
 336
 337         switch (op) {
 338         case OP_START: /* issue start and trigger DTE interrupt */
 339                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 340                 break;
 341         case OP_TX_FIRST: /* disable DTE interrupt and write data */
 342                 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 343                 iic_wr(pd, ICDR, data);
 344                 break;
 345         case OP_TX: /* write data */
 346                 iic_wr(pd, ICDR, data);
 347                 break;
 348         case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
 349                 iic_wr(pd, ICDR, data);
 350                 /* fallthrough */
 351         case OP_TX_STOP: /* issue a stop */
 352                 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 353                                                : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 354                 break;
 355         case OP_TX_TO_RX: /* select read mode */
 356                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 357                 break;
 358         case OP_RX: /* just read data */
 359                 ret = iic_rd(pd, ICDR);
 360                 break;
 361         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 362                 iic_wr(pd, ICIC,
 363                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 364                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 365                 break;
 366         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 367                 iic_wr(pd, ICIC,
 368                        ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 369                 ret = iic_rd(pd, ICDR);
 370                 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 371                 break;
 372         }
 373
 374         spin_unlock_irqrestore(&pd->lock, flags);
 375
 376         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 377         return ret;
 378 }
 379
 380 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 381 {
 382         return pd->pos == -1;
 383 }
 384
 385 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
 386 {
 387         return pd->pos == pd->msg->len - 1;
 388 }
 389
 390 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 391                                    unsigned char *buf)
 392 {
 393         switch (pd->pos) {
 394         case -1:
 395                 *buf = (pd->msg->addr & 0x7f) << 1;
 396                 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
 397                 break;
 398         default:
 399                 *buf = pd->msg->buf[pd->pos];
 400         }
 401 }
 402
 403 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 404 {
 405         unsigned char data;
 406
 407         if (pd->pos == pd->msg->len) {
 408                 /* Send stop if we haven't yet (DMA case) */
 409                 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY))
 410                         i2c_op(pd, OP_TX_STOP, 0);
 411                 return 1;
 412         }
 413
 414         sh_mobile_i2c_get_data(pd, &data);
 415
 416         if (sh_mobile_i2c_is_last_byte(pd))
 417                 i2c_op(pd, OP_TX_STOP_DATA, data);
 418         else if (sh_mobile_i2c_is_first_byte(pd))
 419                 i2c_op(pd, OP_TX_FIRST, data);
 420         else
 421                 i2c_op(pd, OP_TX, data);
 422
 423         pd->pos++;
 424         return 0;
 425 }
 426
 427 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 428 {
 429         unsigned char data;
 430         int real_pos;
 431
 432         do {
 433                 if (pd->pos <= -1) {
 434                         sh_mobile_i2c_get_data(pd, &data);
 435
 436                         if (sh_mobile_i2c_is_first_byte(pd))
 437                                 i2c_op(pd, OP_TX_FIRST, data);
 438                         else
 439                                 i2c_op(pd, OP_TX, data);
 440                         break;
 441                 }
 442
 443                 if (pd->pos == 0) {
 444                         i2c_op(pd, OP_TX_TO_RX, 0);
 445                         break;
 446                 }
 447
 448                 real_pos = pd->pos - 2;
 449
 450                 if (pd->pos == pd->msg->len) {
 451                         if (real_pos < 0) {
 452                                 i2c_op(pd, OP_RX_STOP, 0);
 453                                 break;
 454                         }
 455                         data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 456                 } else
 457                         data = i2c_op(pd, OP_RX, 0);
 458
 459                 if (real_pos >= 0)
 460                         pd->msg->buf[real_pos] = data;
 461         } while (0);
 462
 463         pd->pos++;
 464         return pd->pos == (pd->msg->len + 2);
 465 }
 466
 467 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 468 {
 469         struct sh_mobile_i2c_data *pd = dev_id;
 470         unsigned char sr;
 471         int wakeup = 0;
 472
 473         sr = iic_rd(pd, ICSR);
 474         pd->sr |= sr; /* remember state */
 475
 476         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 477                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 478                pd->pos, pd->msg->len);
 479
 480         /* Kick off TxDMA after preface was done */
 481         if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 482                 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 483         else if (sr & (ICSR_AL | ICSR_TACK))
 484                 /* don't interrupt transaction - continue to issue stop */
 485                 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 486         else if (pd->msg->flags & I2C_M_RD)
 487                 wakeup = sh_mobile_i2c_isr_rx(pd);
 488         else
 489                 wakeup = sh_mobile_i2c_isr_tx(pd);
 490
 491         /* Kick off RxDMA after preface was done */
 492         if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 493                 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 494
 495         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 496                 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 497
 498         if (wakeup) {
 499                 pd->sr |= SW_DONE;
 500                 wake_up(&pd->wait);
 501         }
 502
 503         /* defeat write posting to avoid spurious WAIT interrupts */
 504         iic_rd(pd, ICSR);
 505
 506         return IRQ_HANDLED;
 507 }
 508
 509 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 510 {
 511         struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 512                                 ? pd->dma_rx : pd->dma_tx;
 513
 514         dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 515                          pd->msg->len, pd->dma_direction);
 516
 517         pd->dma_direction = DMA_NONE;
 518 }
 519
 520 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 521 {
 522         if (pd->dma_direction == DMA_NONE)
 523                 return;
 524         else if (pd->dma_direction == DMA_FROM_DEVICE)
 525                 dmaengine_terminate_all(pd->dma_rx);
 526         else if (pd->dma_direction == DMA_TO_DEVICE)
 527                 dmaengine_terminate_all(pd->dma_tx);
 528
 529         sh_mobile_i2c_dma_unmap(pd);
 530 }
 531
 532 static void sh_mobile_i2c_dma_callback(void *data)
 533 {
 534         struct sh_mobile_i2c_data *pd = data;
 535
 536         sh_mobile_i2c_dma_unmap(pd);
 537         pd->pos = pd->msg->len;
 538
 539         iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 540 }
 541
 542 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 543 {
 544         bool read = pd->msg->flags & I2C_M_RD;
 545         enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 546         struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 547         struct dma_async_tx_descriptor *txdesc;
 548         dma_addr_t dma_addr;
 549         dma_cookie_t cookie;
 550
 551         if (IS_ERR(chan))
 552                 return;
 553
 554         dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
 555         if (dma_mapping_error(pd->dev, dma_addr)) {
 556                 dev_dbg(pd->dev, "dma map failed, using PIO\n");
 557                 return;
 558         }
 559
 560         sg_dma_len(&pd->sg) = pd->msg->len;
 561         sg_dma_address(&pd->sg) = dma_addr;
 562
 563         pd->dma_direction = dir;
 564
 565         txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 566                                          read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 567                                          DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 568         if (!txdesc) {
 569                 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 570                 sh_mobile_i2c_cleanup_dma(pd);
 571                 return;
 572         }
 573
 574         txdesc->callback = sh_mobile_i2c_dma_callback;
 575         txdesc->callback_param = pd;
 576
 577         cookie = dmaengine_submit(txdesc);
 578         if (dma_submit_error(cookie)) {
 579                 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 580                 sh_mobile_i2c_cleanup_dma(pd);
 581                 return;
 582         }
 583
 584         dma_async_issue_pending(chan);
 585 }
 586
 587 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 588                     bool do_init)
 589 {
 590         if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
 591                 dev_err(pd->dev, "Unsupported zero length i2c read\n");
 592                 return -EOPNOTSUPP;
 593         }
 594
 595         if (do_init) {
 596                 /* Initialize channel registers */
 597                 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 598
 599                 /* Enable channel and configure rx ack */
 600                 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 601
 602                 /* Set the clock */
 603                 iic_wr(pd, ICCL, pd->iccl & 0xff);
 604                 iic_wr(pd, ICCH, pd->icch & 0xff);
 605         }
 606
 607         pd->msg = usr_msg;
 608         pd->pos = -1;
 609         pd->sr = 0;
 610
 611         if (pd->msg->len > 8)
 612                 sh_mobile_i2c_xfer_dma(pd);
 613
 614         /* Enable all interrupts to begin with */
 615         iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 616         return 0;
 617 }
 618
 619 static int poll_dte(struct sh_mobile_i2c_data *pd)
 620 {
 621         int i;
 622
 623         for (i = 1000; i; i--) {
 624                 u_int8_t val = iic_rd(pd, ICSR);
 625
 626                 if (val & ICSR_DTE)
 627                         break;
 628
 629                 if (val & ICSR_TACK)
 630                         return -ENXIO;
 631
 632                 udelay(10);
 633         }
 634
 635         return i ? 0 : -ETIMEDOUT;
 636 }
 637
 638 static int poll_busy(struct sh_mobile_i2c_data *pd)
 639 {
 640         int i;
 641
 642         for (i = 1000; i; i--) {
 643                 u_int8_t val = iic_rd(pd, ICSR);
 644
 645                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 646
 647                 /* the interrupt handler may wake us up before the
 648                  * transfer is finished, so poll the hardware
 649                  * until we're done.
 650                  */
 651                 if (!(val & ICSR_BUSY)) {
 652                         /* handle missing acknowledge and arbitration lost */
 653                         val |= pd->sr;
 654                         if (val & ICSR_TACK)
 655                                 return -ENXIO;
 656                         if (val & ICSR_AL)
 657                                 return -EAGAIN;
 658                         break;
 659                 }
 660
 661                 udelay(10);
 662         }
 663
 664         return i ? 0 : -ETIMEDOUT;
 665 }
 666
 667 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 668                               struct i2c_msg *msgs,
 669                               int num)
 670 {
 671         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 672         struct i2c_msg  *msg;
 673         int err = 0;
 674         int i, k;
 675
 676         activate_ch(pd);
 677
 678         /* Process all messages */
 679         for (i = 0; i < num; i++) {
 680                 bool do_start = pd->send_stop || !i;
 681                 msg = &msgs[i];
 682                 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 683
 684                 err = start_ch(pd, msg, do_start);
 685                 if (err)
 686                         break;
 687
 688                 if (do_start)
 689                         i2c_op(pd, OP_START, 0);
 690
 691                 /* The interrupt handler takes care of the rest... */
 692                 k = wait_event_timeout(pd->wait,
 693                                        pd->sr & (ICSR_TACK | SW_DONE),
 694                                        5 * HZ);
 695                 if (!k) {
 696                         dev_err(pd->dev, "Transfer request timed out\n");
 697                         if (pd->dma_direction != DMA_NONE)
 698                                 sh_mobile_i2c_cleanup_dma(pd);
 699
 700                         err = -ETIMEDOUT;
 701                         break;
 702                 }
 703
 704                 if (pd->send_stop)
 705                         err = poll_busy(pd);
 706                 else
 707                         err = poll_dte(pd);
 708                 if (err < 0)
 709                         break;
 710         }
 711
 712         deactivate_ch(pd);
 713
 714         if (!err)
 715                 err = num;
 716         return err;
 717 }
 718
 719 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 720 {
 721         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 722 }
 723
 724 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
 725         .functionality  = sh_mobile_i2c_func,
 726         .master_xfer    = sh_mobile_i2c_xfer,
 727 };
 728
 729 static const struct sh_mobile_dt_config default_dt_config = {
 730         .clks_per_count = 1,
 731 };
 732
 733 static const struct sh_mobile_dt_config fast_clock_dt_config = {
 734         .clks_per_count = 2,
 735 };
 736
 737 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 738         { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 739         { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 740         { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
 741         { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
 742         { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
 743         { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
 744         { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
 745         { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 746         {},
 747 };
 748 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 749
 750 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 751                                 enum dma_transfer_direction dir, dma_addr_t port_addr)
 752 {
 753         struct dma_chan *chan;
 754         struct dma_slave_config cfg;
 755         char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 756         int ret;
 757
 758         chan = dma_request_slave_channel_reason(dev, chan_name);
 759         if (IS_ERR(chan)) {
 760                 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
 761                 return chan;
 762         }
 763
 764         memset(&cfg, 0, sizeof(cfg));
 765         cfg.direction = dir;
 766         if (dir == DMA_MEM_TO_DEV) {
 767                 cfg.dst_addr = port_addr;
 768                 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 769         } else {
 770                 cfg.src_addr = port_addr;
 771                 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 772         }
 773
 774         ret = dmaengine_slave_config(chan, &cfg);
 775         if (ret) {
 776                 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 777                 dma_release_channel(chan);
 778                 return ERR_PTR(ret);
 779         }
 780
 781         dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 782         return chan;
 783 }
 784
 785 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 786 {
 787         if (!IS_ERR(pd->dma_tx)) {
 788                 dma_release_channel(pd->dma_tx);
 789                 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 790         }
 791
 792         if (!IS_ERR(pd->dma_rx)) {
 793                 dma_release_channel(pd->dma_rx);
 794                 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 795         }
 796 }
 797
 798 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 799 {
 800         struct resource *res;
 801         resource_size_t n;
 802         int k = 0, ret;
 803
 804         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 805                 for (n = res->start; n <= res->end; n++) {
 806                         ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 807                                           0, dev_name(&dev->dev), pd);
 808                         if (ret) {
 809                                 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 810                                 return ret;
 811                         }
 812                 }
 813                 k++;
 814         }
 815
 816         return k > 0 ? 0 : -ENOENT;
 817 }
 818
 819 static int sh_mobile_i2c_probe(struct platform_device *dev)
 820 {
 821         struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
 822         struct sh_mobile_i2c_data *pd;
 823         struct i2c_adapter *adap;
 824         struct resource *res;
 825         int ret;
 826         u32 bus_speed;
 827
 828         pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 829         if (!pd)
 830                 return -ENOMEM;
 831
 832         pd->clk = devm_clk_get(&dev->dev, NULL);
 833         if (IS_ERR(pd->clk)) {
 834                 dev_err(&dev->dev, "cannot get clock\n");
 835                 return PTR_ERR(pd->clk);
 836         }
 837
 838         ret = sh_mobile_i2c_hook_irqs(dev, pd);
 839         if (ret)
 840                 return ret;
 841
 842         pd->dev = &dev->dev;
 843         platform_set_drvdata(dev, pd);
 844
 845         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 846
 847         pd->reg = devm_ioremap_resource(&dev->dev, res);
 848         if (IS_ERR(pd->reg))
 849                 return PTR_ERR(pd->reg);
 850
 851         /* Use platform data bus speed or STANDARD_MODE */
 852         ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 853         pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
 854
 855         pd->clks_per_count = 1;
 856
 857         if (dev->dev.of_node) {
 858                 const struct of_device_id *match;
 859
 860                 match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
 861                 if (match) {
 862                         const struct sh_mobile_dt_config *config;
 863
 864                         config = match->data;
 865                         pd->clks_per_count = config->clks_per_count;
 866                 }
 867         } else {
 868                 if (pdata && pdata->bus_speed)
 869                         pd->bus_speed = pdata->bus_speed;
 870                 if (pdata && pdata->clks_per_count)
 871                         pd->clks_per_count = pdata->clks_per_count;
 872         }
 873
 874         /* The IIC blocks on SH-Mobile ARM processors
 875          * come with two new bits in ICIC.
 876          */
 877         if (resource_size(res) > 0x17)
 878                 pd->flags |= IIC_FLAG_HAS_ICIC67;
 879
 880         ret = sh_mobile_i2c_init(pd);
 881         if (ret)
 882                 return ret;
 883
 884         /* Init DMA */
 885         sg_init_table(&pd->sg, 1);
 886         pd->dma_direction = DMA_NONE;
 887         pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 888                                                     res->start + ICDR);
 889         ret = PTR_ERR(pd->dma_rx);
 890         if (ret == -EPROBE_DEFER)
 891                 return ret;
 892
 893         pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 894                                                     res->start + ICDR);
 895         ret = PTR_ERR(pd->dma_tx);
 896         if (ret == -EPROBE_DEFER) {
 897                 sh_mobile_i2c_release_dma(pd);
 898                 return ret;
 899         }
 900
 901         /* Enable Runtime PM for this device.
 902          *
 903          * Also tell the Runtime PM core to ignore children
 904          * for this device since it is valid for us to suspend
 905          * this I2C master driver even though the slave devices
 906          * on the I2C bus may not be suspended.
 907          *
 908          * The state of the I2C hardware bus is unaffected by
 909          * the Runtime PM state.
 910          */
 911         pm_suspend_ignore_children(&dev->dev, true);
 912         pm_runtime_enable(&dev->dev);
 913
 914         /* setup the private data */
 915         adap = &pd->adap;
 916         i2c_set_adapdata(adap, pd);
 917
 918         adap->owner = THIS_MODULE;
 919         adap->algo = &sh_mobile_i2c_algorithm;
 920         adap->dev.parent = &dev->dev;
 921         adap->retries = 5;
 922         adap->nr = dev->id;
 923         adap->dev.of_node = dev->dev.of_node;
 924
 925         strlcpy(adap->name, dev->name, sizeof(adap->name));
 926
 927         spin_lock_init(&pd->lock);
 928         init_waitqueue_head(&pd->wait);
 929
 930         ret = i2c_add_numbered_adapter(adap);
 931         if (ret < 0) {
 932                 sh_mobile_i2c_release_dma(pd);
 933                 dev_err(&dev->dev, "cannot add numbered adapter\n");
 934                 return ret;
 935         }
 936
 937         dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz, DMA=%c\n",
 938                  adap->nr, pd->bus_speed, (pd->dma_rx || pd->dma_tx) ? 'y' : 'n');
 939
 940         return 0;
 941 }
 942
 943 static int sh_mobile_i2c_remove(struct platform_device *dev)
 944 {
 945         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 946
 947         i2c_del_adapter(&pd->adap);
 948         sh_mobile_i2c_release_dma(pd);
 949         pm_runtime_disable(&dev->dev);
 950         return 0;
 951 }
 952
 953 static int sh_mobile_i2c_runtime_nop(struct device *dev)
 954 {
 955         /* Runtime PM callback shared between ->runtime_suspend()
 956          * and ->runtime_resume(). Simply returns success.
 957          *
 958          * This driver re-initializes all registers after
 959          * pm_runtime_get_sync() anyway so there is no need
 960          * to save and restore registers here.
 961          */
 962         return 0;
 963 }
 964
 965 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
 966         .runtime_suspend = sh_mobile_i2c_runtime_nop,
 967         .runtime_resume = sh_mobile_i2c_runtime_nop,
 968 };
 969
 970 static struct platform_driver sh_mobile_i2c_driver = {
 971         .driver         = {
 972                 .name           = "i2c-sh_mobile",
 973                 .pm             = &sh_mobile_i2c_dev_pm_ops,
 974                 .of_match_table = sh_mobile_i2c_dt_ids,
 975         },
 976         .probe          = sh_mobile_i2c_probe,
 977         .remove         = sh_mobile_i2c_remove,
 978 };
 979
 980 static int __init sh_mobile_i2c_adap_init(void)
 981 {
 982         return platform_driver_register(&sh_mobile_i2c_driver);
 983 }
 984 subsys_initcall(sh_mobile_i2c_adap_init);
 985
 986 static void __exit sh_mobile_i2c_adap_exit(void)
 987 {
 988         platform_driver_unregister(&sh_mobile_i2c_driver);
 989 }
 990 module_exit(sh_mobile_i2c_adap_exit);
 991
 992 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
 993 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
 994 MODULE_LICENSE("GPL v2");
 995 MODULE_ALIAS("platform:i2c-sh_mobile");