2 * drivers/i2c/busses/i2c-tegra.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Colin Cross <ccross@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/i2c-tegra.h>
29 #include <linux/of_i2c.h>
30 #include <linux/of_device.h>
31 #include <linux/module.h>
32 #include <linux/clk/tegra.h>
34 #include <asm/unaligned.h>
36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
37 #define BYTES_PER_FIFO_WORD 4
39 #define I2C_CNFG 0x000
40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
41 #define I2C_CNFG_PACKET_MODE_EN (1<<10)
42 #define I2C_CNFG_NEW_MASTER_FSM (1<<11)
43 #define I2C_STATUS 0x01C
44 #define I2C_SL_CNFG 0x020
45 #define I2C_SL_CNFG_NACK (1<<1)
46 #define I2C_SL_CNFG_NEWSL (1<<2)
47 #define I2C_SL_ADDR1 0x02c
48 #define I2C_SL_ADDR2 0x030
49 #define I2C_TX_FIFO 0x050
50 #define I2C_RX_FIFO 0x054
51 #define I2C_PACKET_TRANSFER_STATUS 0x058
52 #define I2C_FIFO_CONTROL 0x05c
53 #define I2C_FIFO_CONTROL_TX_FLUSH (1<<1)
54 #define I2C_FIFO_CONTROL_RX_FLUSH (1<<0)
55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT 5
56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT 2
57 #define I2C_FIFO_STATUS 0x060
58 #define I2C_FIFO_STATUS_TX_MASK 0xF0
59 #define I2C_FIFO_STATUS_TX_SHIFT 4
60 #define I2C_FIFO_STATUS_RX_MASK 0x0F
61 #define I2C_FIFO_STATUS_RX_SHIFT 0
62 #define I2C_INT_MASK 0x064
63 #define I2C_INT_STATUS 0x068
64 #define I2C_INT_PACKET_XFER_COMPLETE (1<<7)
65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE (1<<6)
66 #define I2C_INT_TX_FIFO_OVERFLOW (1<<5)
67 #define I2C_INT_RX_FIFO_UNDERFLOW (1<<4)
68 #define I2C_INT_NO_ACK (1<<3)
69 #define I2C_INT_ARBITRATION_LOST (1<<2)
70 #define I2C_INT_TX_FIFO_DATA_REQ (1<<1)
71 #define I2C_INT_RX_FIFO_DATA_REQ (1<<0)
72 #define I2C_CLK_DIVISOR 0x06c
73 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16
74 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE 8
76 #define DVC_CTRL_REG1 0x000
77 #define DVC_CTRL_REG1_INTR_EN (1<<10)
78 #define DVC_CTRL_REG2 0x004
79 #define DVC_CTRL_REG3 0x008
80 #define DVC_CTRL_REG3_SW_PROG (1<<26)
81 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN (1<<30)
82 #define DVC_STATUS 0x00c
83 #define DVC_STATUS_I2C_DONE_INTR (1<<30)
85 #define I2C_ERR_NONE 0x00
86 #define I2C_ERR_NO_ACK 0x01
87 #define I2C_ERR_ARBITRATION_LOST 0x02
88 #define I2C_ERR_UNKNOWN_INTERRUPT 0x04
90 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
91 #define PACKET_HEADER0_PACKET_ID_SHIFT 16
92 #define PACKET_HEADER0_CONT_ID_SHIFT 12
93 #define PACKET_HEADER0_PROTOCOL_I2C (1<<4)
95 #define I2C_HEADER_HIGHSPEED_MODE (1<<22)
96 #define I2C_HEADER_CONT_ON_NAK (1<<21)
97 #define I2C_HEADER_SEND_START_BYTE (1<<20)
98 #define I2C_HEADER_READ (1<<19)
99 #define I2C_HEADER_10BIT_ADDR (1<<18)
100 #define I2C_HEADER_IE_ENABLE (1<<17)
101 #define I2C_HEADER_REPEAT_START (1<<16)
102 #define I2C_HEADER_CONTINUE_XFER (1<<15)
103 #define I2C_HEADER_MASTER_ADDR_SHIFT 12
104 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
106 * msg_end_type: The bus control which need to be send at end of transfer.
107 * @MSG_END_STOP: Send stop pulse at end of transfer.
108 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
109 * @MSG_END_CONTINUE: The following on message is coming and so do not send
110 * stop or repeat start.
114 MSG_END_REPEAT_START,
119 * struct tegra_i2c_hw_feature : Different HW support on Tegra
120 * @has_continue_xfer_support: Continue transfer supports.
121 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
122 * complete interrupt per packet basis.
123 * @has_single_clk_source: The i2c controller has single clock source. Tegra30
124 * and earlier Socs has two clock sources i.e. div-clk and
126 * @clk_divisor_hs_mode: Clock divisor in HS mode.
127 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
128 * applicable if there is no fast clock source i.e. single clock
132 struct tegra_i2c_hw_feature {
133 bool has_continue_xfer_support;
134 bool has_per_pkt_xfer_complete_irq;
135 bool has_single_clk_source;
136 int clk_divisor_hs_mode;
137 int clk_divisor_std_fast_mode;
141 * struct tegra_i2c_dev - per device i2c context
142 * @dev: device reference for power management
143 * @hw: Tegra i2c hw feature.
144 * @adapter: core i2c layer adapter information
145 * @div_clk: clock reference for div clock of i2c controller.
146 * @fast_clk: clock reference for fast clock of i2c controller.
147 * @base: ioremapped registers cookie
148 * @cont_id: i2c controller id, used for for packet header
149 * @irq: irq number of transfer complete interrupt
150 * @is_dvc: identifies the DVC i2c controller, has a different register layout
151 * @msg_complete: transfer completion notifier
152 * @msg_err: error code for completed message
153 * @msg_buf: pointer to current message data
154 * @msg_buf_remaining: size of unsent data in the message buffer
155 * @msg_read: identifies read transfers
156 * @bus_clk_rate: current i2c bus clock rate
157 * @is_suspended: prevents i2c controller accesses after suspend is called
159 struct tegra_i2c_dev {
161 const struct tegra_i2c_hw_feature *hw;
162 struct i2c_adapter adapter;
164 struct clk *fast_clk;
170 struct completion msg_complete;
173 size_t msg_buf_remaining;
175 unsigned long bus_clk_rate;
179 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
181 writel(val, i2c_dev->base + reg);
184 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
186 return readl(i2c_dev->base + reg);
190 * i2c_writel and i2c_readl will offset the register if necessary to talk
191 * to the I2C block inside the DVC block
193 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
197 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
201 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
204 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
206 /* Read back register to make sure that register writes completed */
207 if (reg != I2C_TX_FIFO)
208 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
211 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
213 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
216 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
217 unsigned long reg, int len)
219 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
222 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
223 unsigned long reg, int len)
225 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
228 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
230 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
232 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
235 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
237 u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
239 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
242 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
244 unsigned long timeout = jiffies + HZ;
245 u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
246 val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
247 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
249 while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
250 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
251 if (time_after(jiffies, timeout)) {
252 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
260 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
264 u8 *buf = i2c_dev->msg_buf;
265 size_t buf_remaining = i2c_dev->msg_buf_remaining;
266 int words_to_transfer;
268 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
269 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
270 I2C_FIFO_STATUS_RX_SHIFT;
272 /* Rounds down to not include partial word at the end of buf */
273 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
274 if (words_to_transfer > rx_fifo_avail)
275 words_to_transfer = rx_fifo_avail;
277 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
279 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
280 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
281 rx_fifo_avail -= words_to_transfer;
284 * If there is a partial word at the end of buf, handle it manually to
285 * prevent overwriting past the end of buf
287 if (rx_fifo_avail > 0 && buf_remaining > 0) {
288 BUG_ON(buf_remaining > 3);
289 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
290 memcpy(buf, &val, buf_remaining);
295 BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
296 i2c_dev->msg_buf_remaining = buf_remaining;
297 i2c_dev->msg_buf = buf;
301 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
305 u8 *buf = i2c_dev->msg_buf;
306 size_t buf_remaining = i2c_dev->msg_buf_remaining;
307 int words_to_transfer;
309 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
310 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
311 I2C_FIFO_STATUS_TX_SHIFT;
313 /* Rounds down to not include partial word at the end of buf */
314 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
316 /* It's very common to have < 4 bytes, so optimize that case. */
317 if (words_to_transfer) {
318 if (words_to_transfer > tx_fifo_avail)
319 words_to_transfer = tx_fifo_avail;
322 * Update state before writing to FIFO. If this casues us
323 * to finish writing all bytes (AKA buf_remaining goes to 0) we
324 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
325 * not maskable). We need to make sure that the isr sees
326 * buf_remaining as 0 and doesn't call us back re-entrantly.
328 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
329 tx_fifo_avail -= words_to_transfer;
330 i2c_dev->msg_buf_remaining = buf_remaining;
331 i2c_dev->msg_buf = buf +
332 words_to_transfer * BYTES_PER_FIFO_WORD;
335 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
337 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
341 * If there is a partial word at the end of buf, handle it manually to
342 * prevent reading past the end of buf, which could cross a page
343 * boundary and fault.
345 if (tx_fifo_avail > 0 && buf_remaining > 0) {
346 BUG_ON(buf_remaining > 3);
347 memcpy(&val, buf, buf_remaining);
349 /* Again update before writing to FIFO to make sure isr sees. */
350 i2c_dev->msg_buf_remaining = 0;
351 i2c_dev->msg_buf = NULL;
354 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
361 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
362 * block. This block is identical to the rest of the I2C blocks, except that
363 * it only supports master mode, it has registers moved around, and it needs
364 * some extra init to get it into I2C mode. The register moves are handled
365 * by i2c_readl and i2c_writel
367 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
370 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
371 val |= DVC_CTRL_REG3_SW_PROG;
372 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
373 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
375 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
376 val |= DVC_CTRL_REG1_INTR_EN;
377 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
380 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
383 if (!i2c_dev->hw->has_single_clk_source) {
384 ret = clk_prepare_enable(i2c_dev->fast_clk);
386 dev_err(i2c_dev->dev,
387 "Enabling fast clk failed, err %d\n", ret);
391 ret = clk_prepare_enable(i2c_dev->div_clk);
393 dev_err(i2c_dev->dev,
394 "Enabling div clk failed, err %d\n", ret);
395 clk_disable_unprepare(i2c_dev->fast_clk);
400 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
402 clk_disable_unprepare(i2c_dev->div_clk);
403 if (!i2c_dev->hw->has_single_clk_source)
404 clk_disable_unprepare(i2c_dev->fast_clk);
407 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
411 int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
414 err = tegra_i2c_clock_enable(i2c_dev);
416 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
420 tegra_periph_reset_assert(i2c_dev->div_clk);
422 tegra_periph_reset_deassert(i2c_dev->div_clk);
425 tegra_dvc_init(i2c_dev);
427 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
428 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
429 i2c_writel(i2c_dev, val, I2C_CNFG);
430 i2c_writel(i2c_dev, 0, I2C_INT_MASK);
432 clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
433 clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier);
435 /* Make sure clock divisor programmed correctly */
436 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
437 clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
438 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
439 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
441 if (!i2c_dev->is_dvc) {
442 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
443 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
444 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
445 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
446 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
450 val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
451 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
452 i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
454 if (tegra_i2c_flush_fifos(i2c_dev))
457 tegra_i2c_clock_disable(i2c_dev);
459 if (i2c_dev->irq_disabled) {
460 i2c_dev->irq_disabled = 0;
461 enable_irq(i2c_dev->irq);
467 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
470 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
471 struct tegra_i2c_dev *i2c_dev = dev_id;
473 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
476 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
477 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
478 i2c_readl(i2c_dev, I2C_STATUS),
479 i2c_readl(i2c_dev, I2C_CNFG));
480 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
482 if (!i2c_dev->irq_disabled) {
483 disable_irq_nosync(i2c_dev->irq);
484 i2c_dev->irq_disabled = 1;
489 if (unlikely(status & status_err)) {
490 if (status & I2C_INT_NO_ACK)
491 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
492 if (status & I2C_INT_ARBITRATION_LOST)
493 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
497 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
498 if (i2c_dev->msg_buf_remaining)
499 tegra_i2c_empty_rx_fifo(i2c_dev);
504 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
505 if (i2c_dev->msg_buf_remaining)
506 tegra_i2c_fill_tx_fifo(i2c_dev);
508 tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
511 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
513 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
515 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
516 BUG_ON(i2c_dev->msg_buf_remaining);
517 complete(&i2c_dev->msg_complete);
521 /* An error occurred, mask all interrupts */
522 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
523 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
524 I2C_INT_RX_FIFO_DATA_REQ);
525 i2c_writel(i2c_dev, status, I2C_INT_STATUS);
527 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
529 complete(&i2c_dev->msg_complete);
533 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
534 struct i2c_msg *msg, enum msg_end_type end_state)
540 tegra_i2c_flush_fifos(i2c_dev);
545 i2c_dev->msg_buf = msg->buf;
546 i2c_dev->msg_buf_remaining = msg->len;
547 i2c_dev->msg_err = I2C_ERR_NONE;
548 i2c_dev->msg_read = (msg->flags & I2C_M_RD);
549 INIT_COMPLETION(i2c_dev->msg_complete);
551 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
552 PACKET_HEADER0_PROTOCOL_I2C |
553 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
554 (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
555 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
557 packet_header = msg->len - 1;
558 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
560 packet_header = I2C_HEADER_IE_ENABLE;
561 if (end_state == MSG_END_CONTINUE)
562 packet_header |= I2C_HEADER_CONTINUE_XFER;
563 else if (end_state == MSG_END_REPEAT_START)
564 packet_header |= I2C_HEADER_REPEAT_START;
565 if (msg->flags & I2C_M_TEN) {
566 packet_header |= msg->addr;
567 packet_header |= I2C_HEADER_10BIT_ADDR;
569 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
571 if (msg->flags & I2C_M_IGNORE_NAK)
572 packet_header |= I2C_HEADER_CONT_ON_NAK;
573 if (msg->flags & I2C_M_RD)
574 packet_header |= I2C_HEADER_READ;
575 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
577 if (!(msg->flags & I2C_M_RD))
578 tegra_i2c_fill_tx_fifo(i2c_dev);
580 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
581 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
582 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
583 if (msg->flags & I2C_M_RD)
584 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
585 else if (i2c_dev->msg_buf_remaining)
586 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
587 tegra_i2c_unmask_irq(i2c_dev, int_mask);
588 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
589 i2c_readl(i2c_dev, I2C_INT_MASK));
591 ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
592 tegra_i2c_mask_irq(i2c_dev, int_mask);
595 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
597 tegra_i2c_init(i2c_dev);
601 dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
602 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
604 if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
608 * NACK interrupt is generated before the I2C controller generates the
609 * STOP condition on the bus. So wait for 2 clock periods before resetting
610 * the controller so that STOP condition has been delivered properly.
612 if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
613 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
615 tegra_i2c_init(i2c_dev);
616 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
617 if (msg->flags & I2C_M_IGNORE_NAK)
625 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
628 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
632 if (i2c_dev->is_suspended)
635 ret = tegra_i2c_clock_enable(i2c_dev);
637 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
641 for (i = 0; i < num; i++) {
642 enum msg_end_type end_type = MSG_END_STOP;
644 if (msgs[i + 1].flags & I2C_M_NOSTART)
645 end_type = MSG_END_CONTINUE;
647 end_type = MSG_END_REPEAT_START;
649 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
653 tegra_i2c_clock_disable(i2c_dev);
657 static u32 tegra_i2c_func(struct i2c_adapter *adap)
659 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
660 u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
661 I2C_FUNC_PROTOCOL_MANGLING;
663 if (i2c_dev->hw->has_continue_xfer_support)
664 ret |= I2C_FUNC_NOSTART;
668 static const struct i2c_algorithm tegra_i2c_algo = {
669 .master_xfer = tegra_i2c_xfer,
670 .functionality = tegra_i2c_func,
673 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
674 .has_continue_xfer_support = false,
675 .has_per_pkt_xfer_complete_irq = false,
676 .has_single_clk_source = false,
677 .clk_divisor_hs_mode = 3,
678 .clk_divisor_std_fast_mode = 0,
681 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
682 .has_continue_xfer_support = true,
683 .has_per_pkt_xfer_complete_irq = false,
684 .has_single_clk_source = false,
685 .clk_divisor_hs_mode = 3,
686 .clk_divisor_std_fast_mode = 0,
689 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
690 .has_continue_xfer_support = true,
691 .has_per_pkt_xfer_complete_irq = true,
692 .has_single_clk_source = true,
693 .clk_divisor_hs_mode = 1,
694 .clk_divisor_std_fast_mode = 0x19,
697 #if defined(CONFIG_OF)
698 /* Match table for of_platform binding */
699 static const struct of_device_id tegra_i2c_of_match[] = {
700 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
701 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
702 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
703 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
706 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
709 static int tegra_i2c_probe(struct platform_device *pdev)
711 struct tegra_i2c_dev *i2c_dev;
712 struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
713 struct resource *res;
715 struct clk *fast_clk;
716 const unsigned int *prop;
721 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
723 dev_err(&pdev->dev, "no mem resource\n");
727 base = devm_ioremap_resource(&pdev->dev, res);
729 return PTR_ERR(base);
731 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
733 dev_err(&pdev->dev, "no irq resource\n");
738 div_clk = devm_clk_get(&pdev->dev, "div-clk");
739 if (IS_ERR(div_clk)) {
740 dev_err(&pdev->dev, "missing controller clock");
741 return PTR_ERR(div_clk);
744 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
746 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
750 i2c_dev->base = base;
751 i2c_dev->div_clk = div_clk;
752 i2c_dev->adapter.algo = &tegra_i2c_algo;
754 i2c_dev->cont_id = pdev->id;
755 i2c_dev->dev = &pdev->dev;
757 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
759 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
761 } else if (i2c_dev->dev->of_node) { /* if there is a device tree node ... */
762 prop = of_get_property(i2c_dev->dev->of_node,
763 "clock-frequency", NULL);
765 i2c_dev->bus_clk_rate = be32_to_cpup(prop);
768 i2c_dev->hw = &tegra20_i2c_hw;
770 if (pdev->dev.of_node) {
771 const struct of_device_id *match;
772 match = of_match_device(of_match_ptr(tegra_i2c_of_match),
774 i2c_dev->hw = match->data;
775 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
776 "nvidia,tegra20-i2c-dvc");
777 } else if (pdev->id == 3) {
780 init_completion(&i2c_dev->msg_complete);
782 if (!i2c_dev->hw->has_single_clk_source) {
783 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
784 if (IS_ERR(fast_clk)) {
785 dev_err(&pdev->dev, "missing fast clock");
786 return PTR_ERR(fast_clk);
788 i2c_dev->fast_clk = fast_clk;
791 platform_set_drvdata(pdev, i2c_dev);
793 ret = tegra_i2c_init(i2c_dev);
795 dev_err(&pdev->dev, "Failed to initialize i2c controller");
799 ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
800 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
802 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
806 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
807 i2c_dev->adapter.owner = THIS_MODULE;
808 i2c_dev->adapter.class = I2C_CLASS_HWMON;
809 strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
810 sizeof(i2c_dev->adapter.name));
811 i2c_dev->adapter.algo = &tegra_i2c_algo;
812 i2c_dev->adapter.dev.parent = &pdev->dev;
813 i2c_dev->adapter.nr = pdev->id;
814 i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
816 ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
818 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
822 of_i2c_register_devices(&i2c_dev->adapter);
827 static int tegra_i2c_remove(struct platform_device *pdev)
829 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
830 i2c_del_adapter(&i2c_dev->adapter);
834 #ifdef CONFIG_PM_SLEEP
835 static int tegra_i2c_suspend(struct device *dev)
837 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
839 i2c_lock_adapter(&i2c_dev->adapter);
840 i2c_dev->is_suspended = true;
841 i2c_unlock_adapter(&i2c_dev->adapter);
846 static int tegra_i2c_resume(struct device *dev)
848 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
851 i2c_lock_adapter(&i2c_dev->adapter);
853 ret = tegra_i2c_init(i2c_dev);
856 i2c_unlock_adapter(&i2c_dev->adapter);
860 i2c_dev->is_suspended = false;
862 i2c_unlock_adapter(&i2c_dev->adapter);
867 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
868 #define TEGRA_I2C_PM (&tegra_i2c_pm)
870 #define TEGRA_I2C_PM NULL
873 static struct platform_driver tegra_i2c_driver = {
874 .probe = tegra_i2c_probe,
875 .remove = tegra_i2c_remove,
878 .owner = THIS_MODULE,
879 .of_match_table = of_match_ptr(tegra_i2c_of_match),
884 static int __init tegra_i2c_init_driver(void)
886 return platform_driver_register(&tegra_i2c_driver);
889 static void __exit tegra_i2c_exit_driver(void)
891 platform_driver_unregister(&tegra_i2c_driver);
894 subsys_initcall(tegra_i2c_init_driver);
895 module_exit(tegra_i2c_exit_driver);
897 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
898 MODULE_AUTHOR("Colin Cross");
899 MODULE_LICENSE("GPL v2");