5 * VIA IDE driver for Linux. Supported southbridges:
7 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
8 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
11 * Copyright (c) 2000-2002 Vojtech Pavlik
13 * Based on the work of:
19 * Obsolete device documentation publically available from via.com.tw
20 * Current device documentation available under NDA only
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms of the GNU General Public License version 2 as published by
26 * the Free Software Foundation.
29 #include <linux/config.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/ioport.h>
33 #include <linux/blkdev.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
39 #ifdef CONFIG_PPC_MULTIPLATFORM
40 #include <asm/processor.h>
43 #include "ide-timing.h"
45 #define DISPLAY_VIA_TIMINGS
47 #define VIA_IDE_ENABLE 0x40
48 #define VIA_IDE_CONFIG 0x41
49 #define VIA_FIFO_CONFIG 0x43
50 #define VIA_MISC_1 0x44
51 #define VIA_MISC_2 0x45
52 #define VIA_MISC_3 0x46
53 #define VIA_DRIVE_TIMING 0x48
54 #define VIA_8BIT_TIMING 0x4e
55 #define VIA_ADDRESS_SETUP 0x4c
56 #define VIA_UDMA_TIMING 0x50
58 #define VIA_UDMA 0x007
59 #define VIA_UDMA_NONE 0x000
60 #define VIA_UDMA_33 0x001
61 #define VIA_UDMA_66 0x002
62 #define VIA_UDMA_100 0x003
63 #define VIA_UDMA_133 0x004
64 #define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
65 #define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
66 #define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
67 #define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
68 #define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
69 #define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
72 * VIA SouthBridge chips.
75 static struct via_isa_bridge {
81 } via_isa_bridges[] = {
82 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
83 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
84 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
85 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
86 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
87 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
88 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
89 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
90 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
91 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
92 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
93 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
94 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
95 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
96 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
97 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
98 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
99 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
103 static struct via_isa_bridge *via_config;
104 static unsigned int via_80w;
105 static unsigned int via_clock;
106 static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
109 * via_set_speed - write timing registers
112 * @timing: IDE timing data to use
114 * via_set_speed writes timing values to the chipset registers
117 static void via_set_speed(struct pci_dev *dev, u8 dn, struct ide_timing *timing)
121 if (~via_config->flags & VIA_BAD_AST) {
122 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
123 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
124 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
127 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
128 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
130 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
131 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
133 switch (via_config->flags & VIA_UDMA) {
134 case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
135 case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
136 case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
137 case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
141 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
145 * via_set_drive - configure transfer mode
146 * @drive: Drive to set up
147 * @speed: desired speed
149 * via_set_drive() computes timing values configures the drive and
150 * the chipset to a desired transfer mode. It also can be called
154 static int via_set_drive(ide_drive_t *drive, u8 speed)
156 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
157 struct ide_timing t, p;
160 if (speed != XFER_PIO_SLOW)
161 ide_config_drive_speed(drive, speed);
163 T = 1000000000 / via_clock;
165 switch (via_config->flags & VIA_UDMA) {
166 case VIA_UDMA_33: UT = T; break;
167 case VIA_UDMA_66: UT = T/2; break;
168 case VIA_UDMA_100: UT = T/3; break;
169 case VIA_UDMA_133: UT = T/4; break;
173 ide_timing_compute(drive, speed, &t, T, UT);
176 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
177 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
180 via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
182 if (!drive->init_speed)
183 drive->init_speed = speed;
184 drive->current_speed = speed;
190 * via82cxxx_tune_drive - PIO setup
191 * @drive: drive to set up
192 * @pio: mode to use (255 for 'best possible')
194 * A callback from the upper layers for PIO-only tuning.
197 static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
201 ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
205 via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
209 * via82cxxx_ide_dma_check - set up for DMA if possible
210 * @drive: IDE drive to set up
212 * Set up the drive for the highest supported speed considering the
213 * driver, controller and cable
216 static int via82cxxx_ide_dma_check (ide_drive_t *drive)
218 u16 w80 = HWIF(drive)->udma_four;
220 u16 speed = ide_find_best_mode(drive,
221 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
222 (via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
223 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
224 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
225 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
227 via_set_drive(drive, speed);
229 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
230 return HWIF(drive)->ide_dma_on(drive);
231 return HWIF(drive)->ide_dma_off_quietly(drive);
235 * init_chipset_via82cxxx - initialization handler
237 * @name: Name of interface
239 * The initialization callback. Here we determine the IDE chip type
240 * and initialize its drive independent registers.
243 static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
245 struct pci_dev *isa = NULL;
251 * Find the ISA bridge to see how good the IDE is.
254 for (via_config = via_isa_bridges; via_config->id; via_config++)
255 if ((isa = pci_find_device(PCI_VENDOR_ID_VIA +
256 !!(via_config->flags & VIA_BAD_ID),
257 via_config->id, NULL))) {
259 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
260 if (t >= via_config->rev_min &&
261 t <= via_config->rev_max)
265 if (!via_config->id) {
266 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
271 * Check 80-wire cable presence and setup Clk66.
274 switch (via_config->flags & VIA_UDMA) {
278 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
279 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
280 for (i = 24; i >= 0; i -= 8)
281 if (((u >> (i & 16)) & 8) &&
283 (((u >> i) & 7) < 2)) {
288 via_80w |= (1 << (1 - (i >> 4)));
293 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
294 for (i = 24; i >= 0; i -= 8)
295 if (((u >> i) & 0x10) ||
296 (((u >> i) & 0x20) &&
297 (((u >> i) & 7) < 4))) {
298 /* BIOS 80-wire bit or
299 * UDMA w/ < 60ns/cycle
301 via_80w |= (1 << (1 - (i >> 4)));
306 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
307 for (i = 24; i >= 0; i -= 8)
308 if (((u >> i) & 0x10) ||
309 (((u >> i) & 0x20) &&
310 (((u >> i) & 7) < 6))) {
311 /* BIOS 80-wire bit or
312 * UDMA w/ < 60ns/cycle
314 via_80w |= (1 << (1 - (i >> 4)));
321 if (via_config->flags & VIA_BAD_CLK66) {
322 /* Would cause trouble on 596a and 686 */
323 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
324 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
328 * Check whether interfaces are enabled.
331 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
334 * Set up FIFO sizes and thresholds.
337 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
339 /* Disable PREQ# till DDACK# */
340 if (via_config->flags & VIA_BAD_PREQ) {
341 /* Would crash on 586b rev 41 */
345 /* Fix FIFO split between channels */
346 if (via_config->flags & VIA_SET_FIFO) {
349 case 2: t |= 0x00; break; /* 16 on primary */
350 case 1: t |= 0x60; break; /* 16 on secondary */
351 case 3: t |= 0x20; break; /* 8 pri 8 sec */
355 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
358 * Determine system bus clock.
361 via_clock = system_bus_clock() * 1000;
364 case 33000: via_clock = 33333; break;
365 case 37000: via_clock = 37500; break;
366 case 41000: via_clock = 41666; break;
369 if (via_clock < 20000 || via_clock > 50000) {
370 printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
371 "impossible (%d), using 33 MHz instead.\n", via_clock);
372 printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
373 "to assume 80-wire cable.\n");
378 * Print the boot message.
381 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
382 printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
383 "controller on pci%s\n",
385 via_dma[via_config->flags & VIA_UDMA],
391 static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
397 hwif->tuneproc = &via82cxxx_tune_drive;
398 hwif->speedproc = &via_set_drive;
401 #if defined(CONFIG_PPC_MULTIPLATFORM) && defined(CONFIG_PPC32)
402 if(_machine == _MACH_chrp && _chrp_type == _CHRP_Pegasos) {
403 hwif->irq = hwif->channel ? 15 : 14;
407 for (i = 0; i < 2; i++) {
408 hwif->drives[i].io_32bit = 1;
409 hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
410 hwif->drives[i].autotune = 1;
411 hwif->drives[i].dn = hwif->channel * 2 + i;
418 hwif->ultra_mask = 0x7f;
419 hwif->mwdma_mask = 0x07;
420 hwif->swdma_mask = 0x07;
422 if (!hwif->udma_four)
423 hwif->udma_four = (via_80w >> hwif->channel) & 1;
424 hwif->ide_dma_check = &via82cxxx_ide_dma_check;
427 hwif->drives[0].autodma = hwif->autodma;
428 hwif->drives[1].autodma = hwif->autodma;
431 static ide_pci_device_t via82cxxx_chipset __devinitdata = {
433 .init_chipset = init_chipset_via82cxxx,
434 .init_hwif = init_hwif_via82cxxx,
436 .autodma = NOAUTODMA,
437 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
438 .bootable = ON_BOARD,
441 static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
443 return ide_setup_pci_device(dev, &via82cxxx_chipset);
446 static struct pci_device_id via_pci_tbl[] = {
447 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
448 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
451 MODULE_DEVICE_TABLE(pci, via_pci_tbl);
453 static struct pci_driver driver = {
455 .id_table = via_pci_tbl,
456 .probe = via_init_one,
459 static int via_ide_init(void)
461 return ide_pci_register_driver(&driver);
464 module_init(via_ide_init);
466 MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
467 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
468 MODULE_LICENSE("GPL");