2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
4 * Firmware Infiniband Interface code for POWER
6 * Authors: Christoph Raisch <raisch@de.ibm.com>
7 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
8 * Joachim Fenkes <fenkes@de.ibm.com>
9 * Gerd Bayer <gerd.bayer@de.ibm.com>
10 * Waleri Fomin <fomin@de.ibm.com>
12 * Copyright (c) 2005 IBM Corporation
14 * All rights reserved.
16 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
24 * Redistributions of source code must retain the above copyright notice, this
25 * list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright notice,
28 * this list of conditions and the following disclaimer in the documentation
29 * and/or other materials
30 * provided with the distribution.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
35 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
36 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
37 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
38 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
40 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
41 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGE.
45 #include <asm/hvcall.h>
46 #include "ehca_tools.h"
50 #include "ipz_pt_fn.h"
52 #define H_ALL_RES_QP_ENHANCED_OPS EHCA_BMASK_IBM(9, 11)
53 #define H_ALL_RES_QP_PTE_PIN EHCA_BMASK_IBM(12, 12)
54 #define H_ALL_RES_QP_SERVICE_TYPE EHCA_BMASK_IBM(13, 15)
55 #define H_ALL_RES_QP_LL_RQ_CQE_POSTING EHCA_BMASK_IBM(18, 18)
56 #define H_ALL_RES_QP_LL_SQ_CQE_POSTING EHCA_BMASK_IBM(19, 21)
57 #define H_ALL_RES_QP_SIGNALING_TYPE EHCA_BMASK_IBM(22, 23)
58 #define H_ALL_RES_QP_UD_AV_LKEY_CTRL EHCA_BMASK_IBM(31, 31)
59 #define H_ALL_RES_QP_RESOURCE_TYPE EHCA_BMASK_IBM(56, 63)
61 #define H_ALL_RES_QP_MAX_OUTST_SEND_WR EHCA_BMASK_IBM(0, 15)
62 #define H_ALL_RES_QP_MAX_OUTST_RECV_WR EHCA_BMASK_IBM(16, 31)
63 #define H_ALL_RES_QP_MAX_SEND_SGE EHCA_BMASK_IBM(32, 39)
64 #define H_ALL_RES_QP_MAX_RECV_SGE EHCA_BMASK_IBM(40, 47)
66 #define H_ALL_RES_QP_UD_AV_LKEY EHCA_BMASK_IBM(32, 63)
67 #define H_ALL_RES_QP_SRQ_QP_TOKEN EHCA_BMASK_IBM(0, 31)
68 #define H_ALL_RES_QP_SRQ_QP_HANDLE EHCA_BMASK_IBM(0, 64)
69 #define H_ALL_RES_QP_SRQ_LIMIT EHCA_BMASK_IBM(48, 63)
70 #define H_ALL_RES_QP_SRQ_QPN EHCA_BMASK_IBM(40, 63)
72 #define H_ALL_RES_QP_ACT_OUTST_SEND_WR EHCA_BMASK_IBM(16, 31)
73 #define H_ALL_RES_QP_ACT_OUTST_RECV_WR EHCA_BMASK_IBM(48, 63)
74 #define H_ALL_RES_QP_ACT_SEND_SGE EHCA_BMASK_IBM(8, 15)
75 #define H_ALL_RES_QP_ACT_RECV_SGE EHCA_BMASK_IBM(24, 31)
77 #define H_ALL_RES_QP_SQUEUE_SIZE_PAGES EHCA_BMASK_IBM(0, 31)
78 #define H_ALL_RES_QP_RQUEUE_SIZE_PAGES EHCA_BMASK_IBM(32, 63)
80 #define H_MP_INIT_TYPE EHCA_BMASK_IBM(44, 47)
81 #define H_MP_SHUTDOWN EHCA_BMASK_IBM(48, 48)
82 #define H_MP_RESET_QKEY_CTR EHCA_BMASK_IBM(49, 49)
84 static u32 get_longbusy_msecs(int longbusy_rc)
86 switch (longbusy_rc) {
87 case H_LONG_BUSY_ORDER_1_MSEC:
89 case H_LONG_BUSY_ORDER_10_MSEC:
91 case H_LONG_BUSY_ORDER_100_MSEC:
93 case H_LONG_BUSY_ORDER_1_SEC:
95 case H_LONG_BUSY_ORDER_10_SEC:
97 case H_LONG_BUSY_ORDER_100_SEC:
104 static long ehca_plpar_hcall_norets(unsigned long opcode,
116 ehca_gen_dbg("opcode=%lx arg1=%lx arg2=%lx arg3=%lx arg4=%lx "
117 "arg5=%lx arg6=%lx arg7=%lx",
118 opcode, arg1, arg2, arg3, arg4, arg5, arg6, arg7);
120 for (i = 0; i < 5; i++) {
121 ret = plpar_hcall_norets(opcode, arg1, arg2, arg3, arg4,
124 if (H_IS_LONG_BUSY(ret)) {
125 sleep_msecs = get_longbusy_msecs(ret);
126 msleep_interruptible(sleep_msecs);
131 ehca_gen_err("opcode=%lx ret=%lx"
132 " arg1=%lx arg2=%lx arg3=%lx arg4=%lx"
133 " arg5=%lx arg6=%lx arg7=%lx ",
135 arg1, arg2, arg3, arg4, arg5,
138 ehca_gen_dbg("opcode=%lx ret=%lx", opcode, ret);
146 static long ehca_plpar_hcall9(unsigned long opcode,
147 unsigned long *outs, /* array of 9 outputs */
159 int i, sleep_msecs, lock_is_set = 0;
160 unsigned long flags = 0;
162 ehca_gen_dbg("opcode=%lx arg1=%lx arg2=%lx arg3=%lx arg4=%lx "
163 "arg5=%lx arg6=%lx arg7=%lx arg8=%lx arg9=%lx",
164 opcode, arg1, arg2, arg3, arg4, arg5, arg6, arg7,
167 for (i = 0; i < 5; i++) {
168 if ((opcode == H_ALLOC_RESOURCE) && (arg2 == 5)) {
169 spin_lock_irqsave(&hcall_lock, flags);
173 ret = plpar_hcall9(opcode, outs,
174 arg1, arg2, arg3, arg4, arg5,
175 arg6, arg7, arg8, arg9);
178 spin_unlock_irqrestore(&hcall_lock, flags);
180 if (H_IS_LONG_BUSY(ret)) {
181 sleep_msecs = get_longbusy_msecs(ret);
182 msleep_interruptible(sleep_msecs);
187 ehca_gen_err("opcode=%lx ret=%lx"
188 " arg1=%lx arg2=%lx arg3=%lx arg4=%lx"
189 " arg5=%lx arg6=%lx arg7=%lx arg8=%lx"
191 " out1=%lx out2=%lx out3=%lx out4=%lx"
192 " out5=%lx out6=%lx out7=%lx out8=%lx"
195 arg1, arg2, arg3, arg4, arg5,
196 arg6, arg7, arg8, arg9,
197 outs[0], outs[1], outs[2], outs[3],
198 outs[4], outs[5], outs[6], outs[7],
201 ehca_gen_dbg("opcode=%lx ret=%lx out1=%lx out2=%lx out3=%lx "
202 "out4=%lx out5=%lx out6=%lx out7=%lx out8=%lx "
204 opcode, ret, outs[0], outs[1], outs[2], outs[3],
205 outs[4], outs[5], outs[6], outs[7], outs[8]);
212 u64 hipz_h_alloc_resource_eq(const struct ipz_adapter_handle adapter_handle,
213 struct ehca_pfeq *pfeq,
214 const u32 neq_control,
215 const u32 number_of_entries,
216 struct ipz_eq_handle *eq_handle,
217 u32 *act_nr_of_entries,
222 u64 outs[PLPAR_HCALL9_BUFSIZE];
223 u64 allocate_controls;
226 allocate_controls = 3ULL;
228 /* ISN is associated */
229 if (neq_control != 1)
230 allocate_controls = (1ULL << (63 - 7)) | allocate_controls;
231 else /* notification event queue */
232 allocate_controls = (1ULL << 63) | allocate_controls;
234 ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs,
235 adapter_handle.handle, /* r4 */
236 allocate_controls, /* r5 */
237 number_of_entries, /* r6 */
239 eq_handle->handle = outs[0];
240 *act_nr_of_entries = (u32)outs[3];
241 *act_pages = (u32)outs[4];
242 *eq_ist = (u32)outs[5];
244 if (ret == H_NOT_ENOUGH_RESOURCES)
245 ehca_gen_err("Not enough resource - ret=%lx ", ret);
250 u64 hipz_h_reset_event(const struct ipz_adapter_handle adapter_handle,
251 struct ipz_eq_handle eq_handle,
252 const u64 event_mask)
254 return ehca_plpar_hcall_norets(H_RESET_EVENTS,
255 adapter_handle.handle, /* r4 */
256 eq_handle.handle, /* r5 */
261 u64 hipz_h_alloc_resource_cq(const struct ipz_adapter_handle adapter_handle,
263 struct ehca_alloc_cq_parms *param)
266 u64 outs[PLPAR_HCALL9_BUFSIZE];
268 ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs,
269 adapter_handle.handle, /* r4 */
271 param->eq_handle.handle, /* r6 */
273 param->nr_cqe, /* r8 */
275 cq->ipz_cq_handle.handle = outs[0];
276 param->act_nr_of_entries = (u32)outs[3];
277 param->act_pages = (u32)outs[4];
279 if (ret == H_SUCCESS)
280 hcp_galpas_ctor(&cq->galpas, outs[5], outs[6]);
282 if (ret == H_NOT_ENOUGH_RESOURCES)
283 ehca_gen_err("Not enough resources. ret=%lx", ret);
288 u64 hipz_h_alloc_resource_qp(const struct ipz_adapter_handle adapter_handle,
289 struct ehca_alloc_qp_parms *parms)
292 u64 allocate_controls, max_r10_reg, r11, r12;
293 u64 outs[PLPAR_HCALL9_BUFSIZE];
296 EHCA_BMASK_SET(H_ALL_RES_QP_ENHANCED_OPS, parms->ext_type)
297 | EHCA_BMASK_SET(H_ALL_RES_QP_PTE_PIN, 0)
298 | EHCA_BMASK_SET(H_ALL_RES_QP_SERVICE_TYPE, parms->servicetype)
299 | EHCA_BMASK_SET(H_ALL_RES_QP_SIGNALING_TYPE, parms->sigtype)
300 | EHCA_BMASK_SET(H_ALL_RES_QP_LL_RQ_CQE_POSTING,
301 !!(parms->ll_comp_flags & LLQP_RECV_COMP))
302 | EHCA_BMASK_SET(H_ALL_RES_QP_LL_SQ_CQE_POSTING,
303 !!(parms->ll_comp_flags & LLQP_SEND_COMP))
304 | EHCA_BMASK_SET(H_ALL_RES_QP_UD_AV_LKEY_CTRL,
305 parms->ud_av_l_key_ctl)
306 | EHCA_BMASK_SET(H_ALL_RES_QP_RESOURCE_TYPE, 1);
309 EHCA_BMASK_SET(H_ALL_RES_QP_MAX_OUTST_SEND_WR,
310 parms->max_send_wr + 1)
311 | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_OUTST_RECV_WR,
312 parms->max_recv_wr + 1)
313 | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_SEND_SGE,
315 | EHCA_BMASK_SET(H_ALL_RES_QP_MAX_RECV_SGE,
316 parms->max_recv_sge);
318 r11 = EHCA_BMASK_SET(H_ALL_RES_QP_SRQ_QP_TOKEN, parms->srq_token);
320 if (parms->ext_type == EQPT_SRQ)
321 r12 = EHCA_BMASK_SET(H_ALL_RES_QP_SRQ_LIMIT, parms->srq_limit);
323 r12 = EHCA_BMASK_SET(H_ALL_RES_QP_SRQ_QPN, parms->srq_qpn);
325 ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs,
326 adapter_handle.handle, /* r4 */
327 allocate_controls, /* r5 */
328 parms->send_cq_handle.handle,
329 parms->recv_cq_handle.handle,
330 parms->eq_handle.handle,
331 ((u64)parms->token << 32) | parms->pd.value,
332 max_r10_reg, r11, r12);
334 parms->qp_handle.handle = outs[0];
335 parms->real_qp_num = (u32)outs[1];
336 parms->act_nr_send_wqes =
337 (u16)EHCA_BMASK_GET(H_ALL_RES_QP_ACT_OUTST_SEND_WR, outs[2]);
338 parms->act_nr_recv_wqes =
339 (u16)EHCA_BMASK_GET(H_ALL_RES_QP_ACT_OUTST_RECV_WR, outs[2]);
340 parms->act_nr_send_sges =
341 (u8)EHCA_BMASK_GET(H_ALL_RES_QP_ACT_SEND_SGE, outs[3]);
342 parms->act_nr_recv_sges =
343 (u8)EHCA_BMASK_GET(H_ALL_RES_QP_ACT_RECV_SGE, outs[3]);
345 (u32)EHCA_BMASK_GET(H_ALL_RES_QP_SQUEUE_SIZE_PAGES, outs[4]);
347 (u32)EHCA_BMASK_GET(H_ALL_RES_QP_RQUEUE_SIZE_PAGES, outs[4]);
349 if (ret == H_SUCCESS)
350 hcp_galpas_ctor(&parms->galpas, outs[6], outs[6]);
352 if (ret == H_NOT_ENOUGH_RESOURCES)
353 ehca_gen_err("Not enough resources. ret=%lx", ret);
358 u64 hipz_h_query_port(const struct ipz_adapter_handle adapter_handle,
360 struct hipz_query_port *query_port_response_block)
363 u64 r_cb = virt_to_abs(query_port_response_block);
365 if (r_cb & (EHCA_PAGESIZE-1)) {
366 ehca_gen_err("response block not page aligned");
370 ret = ehca_plpar_hcall_norets(H_QUERY_PORT,
371 adapter_handle.handle, /* r4 */
376 if (ehca_debug_level)
377 ehca_dmp(query_port_response_block, 64, "response_block");
382 u64 hipz_h_modify_port(const struct ipz_adapter_handle adapter_handle,
383 const u8 port_id, const u32 port_cap,
384 const u8 init_type, const int modify_mask)
386 u64 port_attributes = port_cap;
388 if (modify_mask & IB_PORT_SHUTDOWN)
389 port_attributes |= EHCA_BMASK_SET(H_MP_SHUTDOWN, 1);
390 if (modify_mask & IB_PORT_INIT_TYPE)
391 port_attributes |= EHCA_BMASK_SET(H_MP_INIT_TYPE, init_type);
392 if (modify_mask & IB_PORT_RESET_QKEY_CNTR)
393 port_attributes |= EHCA_BMASK_SET(H_MP_RESET_QKEY_CTR, 1);
395 return ehca_plpar_hcall_norets(H_MODIFY_PORT,
396 adapter_handle.handle, /* r4 */
398 port_attributes, /* r6 */
402 u64 hipz_h_query_hca(const struct ipz_adapter_handle adapter_handle,
403 struct hipz_query_hca *query_hca_rblock)
405 u64 r_cb = virt_to_abs(query_hca_rblock);
407 if (r_cb & (EHCA_PAGESIZE-1)) {
408 ehca_gen_err("response_block=%p not page aligned",
413 return ehca_plpar_hcall_norets(H_QUERY_HCA,
414 adapter_handle.handle, /* r4 */
419 u64 hipz_h_register_rpage(const struct ipz_adapter_handle adapter_handle,
422 const u64 resource_handle,
423 const u64 logical_address_of_page,
426 return ehca_plpar_hcall_norets(H_REGISTER_RPAGES,
427 adapter_handle.handle, /* r4 */
428 queue_type | pagesize << 8, /* r5 */
429 resource_handle, /* r6 */
430 logical_address_of_page, /* r7 */
435 u64 hipz_h_register_rpage_eq(const struct ipz_adapter_handle adapter_handle,
436 const struct ipz_eq_handle eq_handle,
437 struct ehca_pfeq *pfeq,
440 const u64 logical_address_of_page,
444 ehca_gen_err("Ppage counter=%lx", count);
447 return hipz_h_register_rpage(adapter_handle,
451 logical_address_of_page, count);
454 u64 hipz_h_query_int_state(const struct ipz_adapter_handle adapter_handle,
458 ret = ehca_plpar_hcall_norets(H_QUERY_INT_STATE,
459 adapter_handle.handle, /* r4 */
463 if (ret != H_SUCCESS && ret != H_BUSY)
464 ehca_gen_err("Could not query interrupt state.");
469 u64 hipz_h_register_rpage_cq(const struct ipz_adapter_handle adapter_handle,
470 const struct ipz_cq_handle cq_handle,
471 struct ehca_pfcq *pfcq,
474 const u64 logical_address_of_page,
476 const struct h_galpa gal)
479 ehca_gen_err("Page counter=%lx", count);
483 return hipz_h_register_rpage(adapter_handle, pagesize, queue_type,
484 cq_handle.handle, logical_address_of_page,
488 u64 hipz_h_register_rpage_qp(const struct ipz_adapter_handle adapter_handle,
489 const struct ipz_qp_handle qp_handle,
490 struct ehca_pfqp *pfqp,
493 const u64 logical_address_of_page,
495 const struct h_galpa galpa)
498 ehca_gen_err("Page counter=%lx", count);
502 return hipz_h_register_rpage(adapter_handle,pagesize,queue_type,
503 qp_handle.handle,logical_address_of_page,
507 u64 hipz_h_disable_and_get_wqe(const struct ipz_adapter_handle adapter_handle,
508 const struct ipz_qp_handle qp_handle,
509 struct ehca_pfqp *pfqp,
510 void **log_addr_next_sq_wqe2processed,
511 void **log_addr_next_rq_wqe2processed,
512 int dis_and_get_function_code)
515 u64 outs[PLPAR_HCALL9_BUFSIZE];
517 ret = ehca_plpar_hcall9(H_DISABLE_AND_GETC, outs,
518 adapter_handle.handle, /* r4 */
519 dis_and_get_function_code, /* r5 */
520 qp_handle.handle, /* r6 */
522 if (log_addr_next_sq_wqe2processed)
523 *log_addr_next_sq_wqe2processed = (void*)outs[0];
524 if (log_addr_next_rq_wqe2processed)
525 *log_addr_next_rq_wqe2processed = (void*)outs[1];
530 u64 hipz_h_modify_qp(const struct ipz_adapter_handle adapter_handle,
531 const struct ipz_qp_handle qp_handle,
532 struct ehca_pfqp *pfqp,
533 const u64 update_mask,
534 struct hcp_modify_qp_control_block *mqpcb,
538 u64 outs[PLPAR_HCALL9_BUFSIZE];
539 ret = ehca_plpar_hcall9(H_MODIFY_QP, outs,
540 adapter_handle.handle, /* r4 */
541 qp_handle.handle, /* r5 */
542 update_mask, /* r6 */
543 virt_to_abs(mqpcb), /* r7 */
546 if (ret == H_NOT_ENOUGH_RESOURCES)
547 ehca_gen_err("Insufficient resources ret=%lx", ret);
552 u64 hipz_h_query_qp(const struct ipz_adapter_handle adapter_handle,
553 const struct ipz_qp_handle qp_handle,
554 struct ehca_pfqp *pfqp,
555 struct hcp_modify_qp_control_block *qqpcb,
558 return ehca_plpar_hcall_norets(H_QUERY_QP,
559 adapter_handle.handle, /* r4 */
560 qp_handle.handle, /* r5 */
561 virt_to_abs(qqpcb), /* r6 */
565 u64 hipz_h_destroy_qp(const struct ipz_adapter_handle adapter_handle,
569 u64 outs[PLPAR_HCALL9_BUFSIZE];
571 ret = hcp_galpas_dtor(&qp->galpas);
573 ehca_gen_err("Could not destruct qp->galpas");
576 ret = ehca_plpar_hcall9(H_DISABLE_AND_GETC, outs,
577 adapter_handle.handle, /* r4 */
580 qp->ipz_qp_handle.handle, /* r6 */
582 if (ret == H_HARDWARE)
583 ehca_gen_err("HCA not operational. ret=%lx", ret);
585 ret = ehca_plpar_hcall_norets(H_FREE_RESOURCE,
586 adapter_handle.handle, /* r4 */
587 qp->ipz_qp_handle.handle, /* r5 */
590 if (ret == H_RESOURCE)
591 ehca_gen_err("Resource still in use. ret=%lx", ret);
596 u64 hipz_h_define_aqp0(const struct ipz_adapter_handle adapter_handle,
597 const struct ipz_qp_handle qp_handle,
601 return ehca_plpar_hcall_norets(H_DEFINE_AQP0,
602 adapter_handle.handle, /* r4 */
603 qp_handle.handle, /* r5 */
608 u64 hipz_h_define_aqp1(const struct ipz_adapter_handle adapter_handle,
609 const struct ipz_qp_handle qp_handle,
611 u32 port, u32 * pma_qp_nr,
615 u64 outs[PLPAR_HCALL9_BUFSIZE];
617 ret = ehca_plpar_hcall9(H_DEFINE_AQP1, outs,
618 adapter_handle.handle, /* r4 */
619 qp_handle.handle, /* r5 */
622 *pma_qp_nr = (u32)outs[0];
623 *bma_qp_nr = (u32)outs[1];
625 if (ret == H_ALIAS_EXIST)
626 ehca_gen_err("AQP1 already exists. ret=%lx", ret);
631 u64 hipz_h_attach_mcqp(const struct ipz_adapter_handle adapter_handle,
632 const struct ipz_qp_handle qp_handle,
635 u64 subnet_prefix, u64 interface_id)
639 ret = ehca_plpar_hcall_norets(H_ATTACH_MCQP,
640 adapter_handle.handle, /* r4 */
641 qp_handle.handle, /* r5 */
643 interface_id, /* r7 */
644 subnet_prefix, /* r8 */
647 if (ret == H_NOT_ENOUGH_RESOURCES)
648 ehca_gen_err("Not enough resources. ret=%lx", ret);
653 u64 hipz_h_detach_mcqp(const struct ipz_adapter_handle adapter_handle,
654 const struct ipz_qp_handle qp_handle,
657 u64 subnet_prefix, u64 interface_id)
659 return ehca_plpar_hcall_norets(H_DETACH_MCQP,
660 adapter_handle.handle, /* r4 */
661 qp_handle.handle, /* r5 */
663 interface_id, /* r7 */
664 subnet_prefix, /* r8 */
668 u64 hipz_h_destroy_cq(const struct ipz_adapter_handle adapter_handle,
674 ret = hcp_galpas_dtor(&cq->galpas);
676 ehca_gen_err("Could not destruct cp->galpas");
680 ret = ehca_plpar_hcall_norets(H_FREE_RESOURCE,
681 adapter_handle.handle, /* r4 */
682 cq->ipz_cq_handle.handle, /* r5 */
683 force_flag != 0 ? 1L : 0L, /* r6 */
686 if (ret == H_RESOURCE)
687 ehca_gen_err("H_FREE_RESOURCE failed ret=%lx ", ret);
692 u64 hipz_h_destroy_eq(const struct ipz_adapter_handle adapter_handle,
697 ret = hcp_galpas_dtor(&eq->galpas);
699 ehca_gen_err("Could not destruct eq->galpas");
703 ret = ehca_plpar_hcall_norets(H_FREE_RESOURCE,
704 adapter_handle.handle, /* r4 */
705 eq->ipz_eq_handle.handle, /* r5 */
708 if (ret == H_RESOURCE)
709 ehca_gen_err("Resource in use. ret=%lx ", ret);
714 u64 hipz_h_alloc_resource_mr(const struct ipz_adapter_handle adapter_handle,
715 const struct ehca_mr *mr,
718 const u32 access_ctrl,
719 const struct ipz_pd pd,
720 struct ehca_mr_hipzout_parms *outparms)
723 u64 outs[PLPAR_HCALL9_BUFSIZE];
725 ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs,
726 adapter_handle.handle, /* r4 */
730 (((u64)access_ctrl) << 32ULL), /* r8 */
733 outparms->handle.handle = outs[0];
734 outparms->lkey = (u32)outs[2];
735 outparms->rkey = (u32)outs[3];
740 u64 hipz_h_register_rpage_mr(const struct ipz_adapter_handle adapter_handle,
741 const struct ehca_mr *mr,
744 const u64 logical_address_of_page,
749 if ((count > 1) && (logical_address_of_page & (EHCA_PAGESIZE-1))) {
750 ehca_gen_err("logical_address_of_page not on a 4k boundary "
751 "adapter_handle=%lx mr=%p mr_handle=%lx "
752 "pagesize=%x queue_type=%x "
753 "logical_address_of_page=%lx count=%lx",
754 adapter_handle.handle, mr,
755 mr->ipz_mr_handle.handle, pagesize, queue_type,
756 logical_address_of_page, count);
759 ret = hipz_h_register_rpage(adapter_handle, pagesize,
761 mr->ipz_mr_handle.handle,
762 logical_address_of_page, count);
766 u64 hipz_h_query_mr(const struct ipz_adapter_handle adapter_handle,
767 const struct ehca_mr *mr,
768 struct ehca_mr_hipzout_parms *outparms)
771 u64 outs[PLPAR_HCALL9_BUFSIZE];
773 ret = ehca_plpar_hcall9(H_QUERY_MR, outs,
774 adapter_handle.handle, /* r4 */
775 mr->ipz_mr_handle.handle, /* r5 */
776 0, 0, 0, 0, 0, 0, 0);
777 outparms->len = outs[0];
778 outparms->vaddr = outs[1];
779 outparms->acl = outs[4] >> 32;
780 outparms->lkey = (u32)(outs[5] >> 32);
781 outparms->rkey = (u32)(outs[5] & (0xffffffff));
786 u64 hipz_h_free_resource_mr(const struct ipz_adapter_handle adapter_handle,
787 const struct ehca_mr *mr)
789 return ehca_plpar_hcall_norets(H_FREE_RESOURCE,
790 adapter_handle.handle, /* r4 */
791 mr->ipz_mr_handle.handle, /* r5 */
795 u64 hipz_h_reregister_pmr(const struct ipz_adapter_handle adapter_handle,
796 const struct ehca_mr *mr,
799 const u32 access_ctrl,
800 const struct ipz_pd pd,
801 const u64 mr_addr_cb,
802 struct ehca_mr_hipzout_parms *outparms)
805 u64 outs[PLPAR_HCALL9_BUFSIZE];
807 ret = ehca_plpar_hcall9(H_REREGISTER_PMR, outs,
808 adapter_handle.handle, /* r4 */
809 mr->ipz_mr_handle.handle, /* r5 */
813 ((((u64)access_ctrl) << 32ULL) | pd.value),
816 outparms->vaddr = outs[1];
817 outparms->lkey = (u32)outs[2];
818 outparms->rkey = (u32)outs[3];
823 u64 hipz_h_register_smr(const struct ipz_adapter_handle adapter_handle,
824 const struct ehca_mr *mr,
825 const struct ehca_mr *orig_mr,
827 const u32 access_ctrl,
828 const struct ipz_pd pd,
829 struct ehca_mr_hipzout_parms *outparms)
832 u64 outs[PLPAR_HCALL9_BUFSIZE];
834 ret = ehca_plpar_hcall9(H_REGISTER_SMR, outs,
835 adapter_handle.handle, /* r4 */
836 orig_mr->ipz_mr_handle.handle, /* r5 */
838 (((u64)access_ctrl) << 32ULL), /* r7 */
841 outparms->handle.handle = outs[0];
842 outparms->lkey = (u32)outs[2];
843 outparms->rkey = (u32)outs[3];
848 u64 hipz_h_alloc_resource_mw(const struct ipz_adapter_handle adapter_handle,
849 const struct ehca_mw *mw,
850 const struct ipz_pd pd,
851 struct ehca_mw_hipzout_parms *outparms)
854 u64 outs[PLPAR_HCALL9_BUFSIZE];
856 ret = ehca_plpar_hcall9(H_ALLOC_RESOURCE, outs,
857 adapter_handle.handle, /* r4 */
861 outparms->handle.handle = outs[0];
862 outparms->rkey = (u32)outs[3];
867 u64 hipz_h_query_mw(const struct ipz_adapter_handle adapter_handle,
868 const struct ehca_mw *mw,
869 struct ehca_mw_hipzout_parms *outparms)
872 u64 outs[PLPAR_HCALL9_BUFSIZE];
874 ret = ehca_plpar_hcall9(H_QUERY_MW, outs,
875 adapter_handle.handle, /* r4 */
876 mw->ipz_mw_handle.handle, /* r5 */
877 0, 0, 0, 0, 0, 0, 0);
878 outparms->rkey = (u32)outs[3];
883 u64 hipz_h_free_resource_mw(const struct ipz_adapter_handle adapter_handle,
884 const struct ehca_mw *mw)
886 return ehca_plpar_hcall_norets(H_FREE_RESOURCE,
887 adapter_handle.handle, /* r4 */
888 mw->ipz_mw_handle.handle, /* r5 */
892 u64 hipz_h_error_data(const struct ipz_adapter_handle adapter_handle,
893 const u64 ressource_handle,
895 unsigned long *byte_count)
897 u64 r_cb = virt_to_abs(rblock);
899 if (r_cb & (EHCA_PAGESIZE-1)) {
900 ehca_gen_err("rblock not page aligned.");
904 return ehca_plpar_hcall_norets(H_ERROR_DATA,
905 adapter_handle.handle,