2 * Copyright(c) 2015, 2016 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
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30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/firmware.h>
49 #include <linux/mutex.h>
50 #include <linux/module.h>
51 #include <linux/delay.h>
52 #include <linux/crc32.h>
58 * Make it easy to toggle firmware file name and if it gets loaded by
59 * editing the following. This may be something we do while in development
60 * but not necessarily something a user would ever need to use.
62 #define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin"
63 #define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw"
64 #define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw"
65 #define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw"
66 #define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw"
67 #define DEFAULT_PLATFORM_CONFIG_NAME "hfi1_platform.dat"
68 #define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw"
69 #define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw"
70 #define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw"
71 #define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw"
73 static uint fw_8051_load = 1;
74 static uint fw_fabric_serdes_load = 1;
75 static uint fw_pcie_serdes_load = 1;
76 static uint fw_sbus_load = 1;
79 * Access required in platform.c
80 * Maintains state of whether the platform config was fetched via the
83 uint platform_config_load;
85 /* Firmware file names get set in hfi1_firmware_init() based on the above */
86 static char *fw_8051_name;
87 static char *fw_fabric_serdes_name;
88 static char *fw_sbus_name;
89 static char *fw_pcie_serdes_name;
90 static char *platform_config_name;
92 #define SBUS_MAX_POLL_COUNT 100
93 #define SBUS_COUNTER(reg, name) \
94 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \
95 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK)
98 * Firmware security header.
106 u32 date; /* BCD yyyymmdd */
107 u32 size; /* in DWORDs */
108 u32 key_size; /* in DWORDs */
109 u32 modulus_size; /* in DWORDs */
110 u32 exponent_size; /* in DWORDs */
114 /* expected field values */
115 #define CSS_MODULE_TYPE 0x00000006
116 #define CSS_HEADER_LEN 0x000000a1
117 #define CSS_HEADER_VERSION 0x00010000
118 #define CSS_MODULE_VENDOR 0x00008086
122 #define EXPONENT_SIZE 4
124 /* the file itself */
125 struct firmware_file {
126 struct css_header css_header;
127 u8 modulus[KEY_SIZE];
128 u8 exponent[EXPONENT_SIZE];
129 u8 signature[KEY_SIZE];
133 struct augmented_firmware_file {
134 struct css_header css_header;
135 u8 modulus[KEY_SIZE];
136 u8 exponent[EXPONENT_SIZE];
137 u8 signature[KEY_SIZE];
143 /* augmented file size difference */
144 #define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \
145 sizeof(struct firmware_file))
147 struct firmware_details {
148 /* Linux core piece */
149 const struct firmware *fw;
151 struct css_header *css_header;
152 u8 *firmware_ptr; /* pointer to binary data */
153 u32 firmware_len; /* length in bytes */
154 u8 *modulus; /* pointer to the modulus */
155 u8 *exponent; /* pointer to the exponent */
156 u8 *signature; /* pointer to the signature */
157 u8 *r2; /* pointer to r2 */
158 u8 *mu; /* pointer to mu */
159 struct augmented_firmware_file dummy_header;
163 * The mutex protects fw_state, fw_err, and all of the firmware_details
166 static DEFINE_MUTEX(fw_mutex);
174 static enum fw_state fw_state = FW_EMPTY;
176 static struct firmware_details fw_8051;
177 static struct firmware_details fw_fabric;
178 static struct firmware_details fw_pcie;
179 static struct firmware_details fw_sbus;
180 static const struct firmware *platform_config;
182 /* flags for turn_off_spicos() */
183 #define SPICO_SBUS 0x1
184 #define SPICO_FABRIC 0x2
185 #define ENABLE_SPICO_SMASK 0x1
187 /* security block commands */
188 #define RSA_CMD_INIT 0x1
189 #define RSA_CMD_START 0x2
191 /* security block status */
192 #define RSA_STATUS_IDLE 0x0
193 #define RSA_STATUS_ACTIVE 0x1
194 #define RSA_STATUS_DONE 0x2
195 #define RSA_STATUS_FAILED 0x3
197 /* RSA engine timeout, in ms */
198 #define RSA_ENGINE_TIMEOUT 100 /* ms */
200 /* hardware mutex timeout, in ms */
201 #define HM_TIMEOUT 10 /* ms */
203 /* 8051 memory access timeout, in us */
204 #define DC8051_ACCESS_TIMEOUT 100 /* us */
206 /* the number of fabric SerDes on the SBus */
207 #define NUM_FABRIC_SERDES 4
209 /* SBus fabric SerDes addresses, one set per HFI */
210 static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = {
211 { 0x01, 0x02, 0x03, 0x04 },
212 { 0x28, 0x29, 0x2a, 0x2b }
215 /* SBus PCIe SerDes addresses, one set per HFI */
216 static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = {
217 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16,
218 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 },
219 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
220 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d }
223 /* SBus PCIe PCS addresses, one set per HFI */
224 const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = {
225 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17,
226 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 },
227 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
228 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e }
231 /* SBus fabric SerDes broadcast addresses, one per HFI */
232 static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 };
233 static const u8 all_fabric_serdes_broadcast = 0xe1;
235 /* SBus PCIe SerDes broadcast addresses, one per HFI */
236 const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 };
237 static const u8 all_pcie_serdes_broadcast = 0xe0;
240 static void dispose_one_firmware(struct firmware_details *fdet);
241 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
242 struct firmware_details *fdet);
245 * Read a single 64-bit value from 8051 data memory.
248 * o caller to have already set up data read, no auto increment
249 * o caller to turn off read enable when finished
251 * The address argument is a byte offset. Bits 0:2 in the address are
252 * ignored - i.e. the hardware will always do aligned 8-byte reads as if
253 * the lower bits are zero.
255 * Return 0 on success, -ENXIO on a read error (timeout).
257 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result)
262 /* start the read at the given address */
263 reg = ((addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
264 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
265 | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK;
266 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
268 /* wait until ACCESS_COMPLETED is set */
270 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
271 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
274 if (count > DC8051_ACCESS_TIMEOUT) {
275 dd_dev_err(dd, "timeout reading 8051 data\n");
281 /* gather the data */
282 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA);
288 * Read 8051 data starting at addr, for len bytes. Will read in 8-byte chunks.
289 * Return 0 on success, -errno on error.
291 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result)
297 spin_lock_irqsave(&dd->dc8051_memlock, flags);
299 /* data read set-up, no auto-increment */
300 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
302 for (done = 0; done < len; addr += 8, done += 8, result++) {
303 ret = __read_8051_data(dd, addr, result);
308 /* turn off read enable */
309 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
311 spin_unlock_irqrestore(&dd->dc8051_memlock, flags);
317 * Write data or code to the 8051 code or data RAM.
319 static int write_8051(struct hfi1_devdata *dd, int code, u32 start,
320 const u8 *data, u32 len)
326 /* check alignment */
327 aligned = ((unsigned long)data & 0x7) == 0;
330 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull)
331 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK;
332 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
334 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
335 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
336 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK;
337 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
340 for (offset = 0; offset < len; offset += 8) {
341 int bytes = len - offset;
345 memcpy(®, &data[offset], bytes);
346 } else if (aligned) {
347 reg = *(u64 *)&data[offset];
349 memcpy(®, &data[offset], 8);
351 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
353 /* wait until ACCESS_COMPLETED is set */
355 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
356 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
359 if (count > DC8051_ACCESS_TIMEOUT) {
360 dd_dev_err(dd, "timeout writing 8051 data\n");
367 /* turn off write access, auto increment (also sets to data access) */
368 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
369 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
374 /* return 0 if values match, non-zero and complain otherwise */
375 static int invalid_header(struct hfi1_devdata *dd, const char *what,
376 u32 actual, u32 expected)
378 if (actual == expected)
382 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
383 what, expected, actual);
388 * Verify that the static fields in the CSS header match.
390 static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css)
392 /* verify CSS header fields (most sizes are in DW, so add /4) */
393 if (invalid_header(dd, "module_type", css->module_type,
395 invalid_header(dd, "header_len", css->header_len,
396 (sizeof(struct firmware_file) / 4)) ||
397 invalid_header(dd, "header_version", css->header_version,
398 CSS_HEADER_VERSION) ||
399 invalid_header(dd, "module_vendor", css->module_vendor,
400 CSS_MODULE_VENDOR) ||
401 invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) ||
402 invalid_header(dd, "modulus_size", css->modulus_size,
404 invalid_header(dd, "exponent_size", css->exponent_size,
405 EXPONENT_SIZE / 4)) {
412 * Make sure there are at least some bytes after the prefix.
414 static int payload_check(struct hfi1_devdata *dd, const char *name,
415 long file_size, long prefix_size)
417 /* make sure we have some payload */
418 if (prefix_size >= file_size) {
420 "firmware \"%s\", size %ld, must be larger than %ld bytes\n",
421 name, file_size, prefix_size);
429 * Request the firmware from the system. Extract the pieces and fill in
430 * fdet. If successful, the caller will need to call dispose_one_firmware().
431 * Returns 0 on success, -ERRNO on error.
433 static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
434 struct firmware_details *fdet)
436 struct css_header *css;
439 memset(fdet, 0, sizeof(*fdet));
441 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev);
443 dd_dev_warn(dd, "cannot find firmware \"%s\", err %d\n",
448 /* verify the firmware */
449 if (fdet->fw->size < sizeof(struct css_header)) {
450 dd_dev_err(dd, "firmware \"%s\" is too small\n", name);
454 css = (struct css_header *)fdet->fw->data;
456 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name);
457 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size);
458 hfi1_cdbg(FIRMWARE, "CSS structure:");
459 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type);
460 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)",
461 css->header_len, 4 * css->header_len);
462 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version);
463 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id);
464 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor);
465 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date);
466 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)",
467 css->size, 4 * css->size);
468 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)",
469 css->key_size, 4 * css->key_size);
470 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)",
471 css->modulus_size, 4 * css->modulus_size);
472 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)",
473 css->exponent_size, 4 * css->exponent_size);
474 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes",
475 fdet->fw->size - sizeof(struct firmware_file));
478 * If the file does not have a valid CSS header, fail.
479 * Otherwise, check the CSS size field for an expected size.
480 * The augmented file has r2 and mu inserted after the header
481 * was generated, so there will be a known difference between
482 * the CSS header size and the actual file size. Use this
483 * difference to identify an augmented file.
485 * Note: css->size is in DWORDs, multiply by 4 to get bytes.
487 ret = verify_css_header(dd, css);
489 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name);
490 } else if ((css->size * 4) == fdet->fw->size) {
491 /* non-augmented firmware file */
492 struct firmware_file *ff = (struct firmware_file *)
495 /* make sure there are bytes in the payload */
496 ret = payload_check(dd, name, fdet->fw->size,
497 sizeof(struct firmware_file));
499 fdet->css_header = css;
500 fdet->modulus = ff->modulus;
501 fdet->exponent = ff->exponent;
502 fdet->signature = ff->signature;
503 fdet->r2 = fdet->dummy_header.r2; /* use dummy space */
504 fdet->mu = fdet->dummy_header.mu; /* use dummy space */
505 fdet->firmware_ptr = ff->firmware;
506 fdet->firmware_len = fdet->fw->size -
507 sizeof(struct firmware_file);
509 * Header does not include r2 and mu - generate here.
512 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n");
515 } else if ((css->size * 4) + AUGMENT_SIZE == fdet->fw->size) {
516 /* augmented firmware file */
517 struct augmented_firmware_file *aff =
518 (struct augmented_firmware_file *)fdet->fw->data;
520 /* make sure there are bytes in the payload */
521 ret = payload_check(dd, name, fdet->fw->size,
522 sizeof(struct augmented_firmware_file));
524 fdet->css_header = css;
525 fdet->modulus = aff->modulus;
526 fdet->exponent = aff->exponent;
527 fdet->signature = aff->signature;
530 fdet->firmware_ptr = aff->firmware;
531 fdet->firmware_len = fdet->fw->size -
532 sizeof(struct augmented_firmware_file);
535 /* css->size check failed */
537 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
539 (fdet->fw->size - AUGMENT_SIZE) / 4,
546 /* if returning an error, clean up after ourselves */
548 dispose_one_firmware(fdet);
552 static void dispose_one_firmware(struct firmware_details *fdet)
554 release_firmware(fdet->fw);
555 /* erase all previous information */
556 memset(fdet, 0, sizeof(*fdet));
560 * Obtain the 4 firmwares from the OS. All must be obtained at once or not
561 * at all. If called with the firmware state in FW_TRY, use alternate names.
562 * On exit, this routine will have set the firmware state to one of FW_TRY,
563 * FW_FINAL, or FW_ERR.
565 * Must be holding fw_mutex.
567 static void __obtain_firmware(struct hfi1_devdata *dd)
571 if (fw_state == FW_FINAL) /* nothing more to obtain */
573 if (fw_state == FW_ERR) /* already in error */
576 /* fw_state is FW_EMPTY or FW_TRY */
578 if (fw_state == FW_TRY) {
580 * We tried the original and it failed. Move to the
583 dd_dev_warn(dd, "using alternate firmware names\n");
585 * Let others run. Some systems, when missing firmware, does
586 * something that holds for 30 seconds. If we do that twice
587 * in a row it triggers task blocked warning.
591 dispose_one_firmware(&fw_8051);
592 if (fw_fabric_serdes_load)
593 dispose_one_firmware(&fw_fabric);
595 dispose_one_firmware(&fw_sbus);
596 if (fw_pcie_serdes_load)
597 dispose_one_firmware(&fw_pcie);
598 fw_8051_name = ALT_FW_8051_NAME_ASIC;
599 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME;
600 fw_sbus_name = ALT_FW_SBUS_NAME;
601 fw_pcie_serdes_name = ALT_FW_PCIE_NAME;
605 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus);
610 if (fw_pcie_serdes_load) {
611 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie);
616 if (fw_fabric_serdes_load) {
617 err = obtain_one_firmware(dd, fw_fabric_serdes_name,
624 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051);
631 /* oops, had problems obtaining a firmware */
632 if (fw_state == FW_EMPTY && dd->icode == ICODE_RTL_SILICON) {
633 /* retry with alternate (RTL only) */
637 dd_dev_err(dd, "unable to obtain working firmware\n");
642 if (fw_state == FW_EMPTY &&
643 dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
644 fw_state = FW_TRY; /* may retry later */
646 fw_state = FW_FINAL; /* cannot try again */
651 * Called by all HFIs when loading their firmware - i.e. device probe time.
652 * The first one will do the actual firmware load. Use a mutex to resolve
653 * any possible race condition.
655 * The call to this routine cannot be moved to driver load because the kernel
656 * call request_firmware() requires a device which is only available after
657 * the first device probe.
659 static int obtain_firmware(struct hfi1_devdata *dd)
661 unsigned long timeout;
664 mutex_lock(&fw_mutex);
666 /* 40s delay due to long delay on missing firmware on some systems */
667 timeout = jiffies + msecs_to_jiffies(40000);
668 while (fw_state == FW_TRY) {
670 * Another device is trying the firmware. Wait until it
671 * decides what works (or not).
673 if (time_after(jiffies, timeout)) {
674 /* waited too long */
675 dd_dev_err(dd, "Timeout waiting for firmware try");
680 mutex_unlock(&fw_mutex);
681 msleep(20); /* arbitrary delay */
682 mutex_lock(&fw_mutex);
684 /* not in FW_TRY state */
686 if (fw_state == FW_FINAL) {
687 if (platform_config) {
688 dd->platform_config.data = platform_config->data;
689 dd->platform_config.size = platform_config->size;
691 goto done; /* already acquired */
692 } else if (fw_state == FW_ERR) {
693 goto done; /* already tried and failed */
695 /* fw_state is FW_EMPTY */
697 /* set fw_state to FW_TRY, FW_FINAL, or FW_ERR, and fw_err */
698 __obtain_firmware(dd);
700 if (platform_config_load) {
701 platform_config = NULL;
702 err = request_firmware(&platform_config, platform_config_name,
705 platform_config = NULL;
708 dd->platform_config.data = platform_config->data;
709 dd->platform_config.size = platform_config->size;
713 mutex_unlock(&fw_mutex);
719 * Called when the driver unloads. The timing is asymmetric with its
720 * counterpart, obtain_firmware(). If called at device remove time,
721 * then it is conceivable that another device could probe while the
722 * firmware is being disposed. The mutexes can be moved to do that
723 * safely, but then the firmware would be requested from the OS multiple
726 * No mutex is needed as the driver is unloading and there cannot be any
729 void dispose_firmware(void)
731 dispose_one_firmware(&fw_8051);
732 dispose_one_firmware(&fw_fabric);
733 dispose_one_firmware(&fw_pcie);
734 dispose_one_firmware(&fw_sbus);
736 release_firmware(platform_config);
737 platform_config = NULL;
739 /* retain the error state, otherwise revert to empty */
740 if (fw_state != FW_ERR)
745 * Called with the result of a firmware download.
747 * Return 1 to retry loading the firmware, 0 to stop.
749 static int retry_firmware(struct hfi1_devdata *dd, int load_result)
753 mutex_lock(&fw_mutex);
755 if (load_result == 0) {
757 * The load succeeded, so expect all others to do the same.
758 * Do not retry again.
760 if (fw_state == FW_TRY)
762 retry = 0; /* do NOT retry */
763 } else if (fw_state == FW_TRY) {
764 /* load failed, obtain alternate firmware */
765 __obtain_firmware(dd);
766 retry = (fw_state == FW_FINAL);
768 /* else in FW_FINAL or FW_ERR, no retry in either case */
772 mutex_unlock(&fw_mutex);
777 * Write a block of data to a given array CSR. All calls will be in
778 * multiples of 8 bytes.
780 static void write_rsa_data(struct hfi1_devdata *dd, int what,
781 const u8 *data, int nbytes)
783 int qw_size = nbytes / 8;
786 if (((unsigned long)data & 0x7) == 0) {
788 u64 *ptr = (u64 *)data;
790 for (i = 0; i < qw_size; i++, ptr++)
791 write_csr(dd, what + (8 * i), *ptr);
794 for (i = 0; i < qw_size; i++, data += 8) {
797 memcpy(&value, data, 8);
798 write_csr(dd, what + (8 * i), value);
804 * Write a block of data to a given CSR as a stream of writes. All calls will
805 * be in multiples of 8 bytes.
807 static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what,
808 const u8 *data, int nbytes)
810 u64 *ptr = (u64 *)data;
811 int qw_size = nbytes / 8;
813 for (; qw_size > 0; qw_size--, ptr++)
814 write_csr(dd, what, *ptr);
818 * Download the signature and start the RSA mechanism. Wait for
819 * RSA_ENGINE_TIMEOUT before giving up.
821 static int run_rsa(struct hfi1_devdata *dd, const char *who,
824 unsigned long timeout;
829 /* write the signature */
830 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE);
833 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
836 * Make sure the engine is idle and insert a delay between the two
837 * writes to MISC_CFG_RSA_CMD.
839 status = (read_csr(dd, MISC_CFG_FW_CTRL)
840 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
841 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
842 if (status != RSA_STATUS_IDLE) {
843 dd_dev_err(dd, "%s security engine not idle - giving up\n",
849 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
852 * Look for the result.
854 * The RSA engine is hooked up to two MISC errors. The driver
855 * masks these errors as they do not respond to the standard
856 * error "clear down" mechanism. Look for these errors here and
857 * clear them when possible. This routine will exit with the
858 * errors of the current run still set.
860 * MISC_FW_AUTH_FAILED_ERR
861 * Firmware authorization failed. This can be cleared by
862 * re-initializing the RSA engine, then clearing the status bit.
863 * Do not re-init the RSA angine immediately after a successful
864 * run - this will reset the current authorization.
866 * MISC_KEY_MISMATCH_ERR
867 * Key does not match. The only way to clear this is to load
868 * a matching key then clear the status bit. If this error
869 * is raised, it will persist outside of this routine until a
870 * matching key is loaded.
872 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies;
874 status = (read_csr(dd, MISC_CFG_FW_CTRL)
875 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
876 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
878 if (status == RSA_STATUS_IDLE) {
879 /* should not happen */
880 dd_dev_err(dd, "%s firmware security bad idle state\n",
884 } else if (status == RSA_STATUS_DONE) {
885 /* finished successfully */
887 } else if (status == RSA_STATUS_FAILED) {
888 /* finished unsuccessfully */
892 /* else still active */
894 if (time_after(jiffies, timeout)) {
896 * Timed out while active. We can't reset the engine
897 * if it is stuck active, but run through the
898 * error code to see what error bits are set.
900 dd_dev_err(dd, "%s firmware security time out\n", who);
909 * Arrive here on success or failure. Clear all RSA engine
910 * errors. All current errors will stick - the RSA logic is keeping
911 * error high. All previous errors will clear - the RSA logic
912 * is not keeping the error high.
914 write_csr(dd, MISC_ERR_CLEAR,
915 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK |
916 MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
918 * All that is left are the current errors. Print warnings on
919 * authorization failure details, if any. Firmware authorization
920 * can be retried, so these are only warnings.
922 reg = read_csr(dd, MISC_ERR_STATUS);
924 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK)
925 dd_dev_warn(dd, "%s firmware authorization failed\n",
927 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK)
928 dd_dev_warn(dd, "%s firmware key mismatch\n", who);
934 static void load_security_variables(struct hfi1_devdata *dd,
935 struct firmware_details *fdet)
937 /* Security variables a. Write the modulus */
938 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE);
939 /* Security variables b. Write the r2 */
940 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE);
941 /* Security variables c. Write the mu */
942 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE);
943 /* Security variables d. Write the header */
944 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD,
945 (u8 *)fdet->css_header,
946 sizeof(struct css_header));
949 /* return the 8051 firmware state */
950 static inline u32 get_firmware_state(struct hfi1_devdata *dd)
952 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
954 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT)
955 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK;
959 * Wait until the firmware is up and ready to take host requests.
960 * Return 0 on success, -ETIMEDOUT on timeout.
962 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout)
964 unsigned long timeout;
966 /* in the simulator, the fake 8051 is always ready */
967 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
970 timeout = msecs_to_jiffies(mstimeout) + jiffies;
972 if (get_firmware_state(dd) == 0xa0) /* ready */
974 if (time_after(jiffies, timeout)) /* timed out */
976 usleep_range(1950, 2050); /* sleep 2ms-ish */
981 * Load the 8051 firmware.
983 static int load_8051_firmware(struct hfi1_devdata *dd,
984 struct firmware_details *fdet)
992 * Load DC 8051 firmware
995 * DC reset step 1: Reset DC8051
997 reg = DC_DC8051_CFG_RST_M8051W_SMASK
998 | DC_DC8051_CFG_RST_CRAM_SMASK
999 | DC_DC8051_CFG_RST_DRAM_SMASK
1000 | DC_DC8051_CFG_RST_IRAM_SMASK
1001 | DC_DC8051_CFG_RST_SFR_SMASK;
1002 write_csr(dd, DC_DC8051_CFG_RST, reg);
1005 * DC reset step 2 (optional): Load 8051 data memory with link
1010 * DC reset step 3: Load DC8051 firmware
1012 /* release all but the core reset */
1013 reg = DC_DC8051_CFG_RST_M8051W_SMASK;
1014 write_csr(dd, DC_DC8051_CFG_RST, reg);
1016 /* Firmware load step 1 */
1017 load_security_variables(dd, fdet);
1020 * Firmware load step 2. Clear MISC_CFG_FW_CTRL.FW_8051_LOADED
1022 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1024 /* Firmware load steps 3-5 */
1025 ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr,
1026 fdet->firmware_len);
1031 * DC reset step 4. Host starts the DC8051 firmware
1034 * Firmware load step 6. Set MISC_CFG_FW_CTRL.FW_8051_LOADED
1036 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
1038 /* Firmware load steps 7-10 */
1039 ret = run_rsa(dd, "8051", fdet->signature);
1043 /* clear all reset bits, releasing the 8051 */
1044 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
1047 * DC reset step 5. Wait for firmware to be ready to accept host
1050 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
1051 if (ret) { /* timed out */
1052 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n",
1053 get_firmware_state(dd));
1057 read_misc_status(dd, &ver_a, &ver_b);
1058 dd_dev_info(dd, "8051 firmware version %d.%d\n",
1059 (int)ver_b, (int)ver_a);
1060 dd->dc8051_ver = dc8051_ver(ver_b, ver_a);
1066 * Write the SBus request register
1068 * No need for masking - the arguments are sized exactly.
1070 void sbus_request(struct hfi1_devdata *dd,
1071 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1073 write_csr(dd, ASIC_CFG_SBUS_REQUEST,
1074 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) |
1075 ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) |
1076 ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) |
1077 ((u64)receiver_addr <<
1078 ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
1082 * Turn off the SBus and fabric serdes spicos.
1084 * + Must be called with Sbus fast mode turned on.
1085 * + Must be called after fabric serdes broadcast is set up.
1086 * + Must be called before the 8051 is loaded - assumes 8051 is not loaded
1087 * when using MISC_CFG_FW_CTRL.
1089 static void turn_off_spicos(struct hfi1_devdata *dd, int flags)
1091 /* only needed on A0 */
1095 dd_dev_info(dd, "Turning off spicos:%s%s\n",
1096 flags & SPICO_SBUS ? " SBus" : "",
1097 flags & SPICO_FABRIC ? " fabric" : "");
1099 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
1100 /* disable SBus spico */
1101 if (flags & SPICO_SBUS)
1102 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
1103 WRITE_SBUS_RECEIVER, 0x00000040);
1105 /* disable the fabric serdes spicos */
1106 if (flags & SPICO_FABRIC)
1107 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id],
1108 0x07, WRITE_SBUS_RECEIVER, 0x00000000);
1109 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1113 * Reset all of the fabric serdes for this HFI in preparation to take the
1116 * To do a reset, we need to write to to the serdes registers. Unfortunately,
1117 * the fabric serdes download to the other HFI on the ASIC will have turned
1118 * off the firmware validation on this HFI. This means we can't write to the
1119 * registers to reset the serdes. Work around this by performing a complete
1120 * re-download and validation of the fabric serdes firmware. This, as a
1121 * by-product, will reset the serdes. NOTE: the re-download requires that
1122 * the 8051 be in the Offline state. I.e. not actively trying to use the
1123 * serdes. This routine is called at the point where the link is Offline and
1124 * is getting ready to go to Polling.
1126 void fabric_serdes_reset(struct hfi1_devdata *dd)
1130 if (!fw_fabric_serdes_load)
1133 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1136 "Cannot acquire SBus resource to reset fabric SerDes - perhaps you should reboot\n");
1139 set_sbus_fast_mode(dd);
1142 /* A0 serdes do not work with a re-download */
1143 u8 ra = fabric_serdes_broadcast[dd->hfi1_id];
1145 /* place SerDes in reset and disable SPICO */
1146 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1147 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1149 /* remove SerDes reset */
1150 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1151 /* turn SPICO enable on */
1152 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1154 turn_off_spicos(dd, SPICO_FABRIC);
1156 * No need for firmware retry - what to download has already
1158 * No need to pay attention to the load return - the only
1159 * failure is a validation failure, which has already been
1160 * checked by the initial download.
1162 (void)load_fabric_serdes_firmware(dd, &fw_fabric);
1165 clear_sbus_fast_mode(dd);
1166 release_chip_resource(dd, CR_SBUS);
1169 /* Access to the SBus in this routine should probably be serialized */
1170 int sbus_request_slow(struct hfi1_devdata *dd,
1171 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1175 /* make sure fast mode is clear */
1176 clear_sbus_fast_mode(dd);
1178 sbus_request(dd, receiver_addr, data_addr, command, data_in);
1179 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1180 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK);
1181 /* Wait for both DONE and RCV_DATA_VALID to go high */
1182 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1183 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1184 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) {
1185 if (count++ >= SBUS_MAX_POLL_COUNT) {
1186 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1188 * If the loop has timed out, we are OK if DONE bit
1189 * is set and RCV_DATA_VALID and EXECUTE counters
1190 * are the same. If not, we cannot proceed.
1192 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1193 (SBUS_COUNTER(counts, RCV_DATA_VALID) ==
1194 SBUS_COUNTER(counts, EXECUTE)))
1199 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1202 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1203 /* Wait for DONE to clear after EXECUTE is cleared */
1204 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1205 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) {
1206 if (count++ >= SBUS_MAX_POLL_COUNT)
1209 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1214 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
1215 struct firmware_details *fdet)
1218 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; /* receiver addr */
1220 dd_dev_info(dd, "Downloading fabric firmware\n");
1222 /* step 1: load security variables */
1223 load_security_variables(dd, fdet);
1224 /* step 2: place SerDes in reset and disable SPICO */
1225 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1226 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1228 /* step 3: remove SerDes reset */
1229 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1230 /* step 4: assert IMEM override */
1231 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000);
1232 /* step 5: download SerDes machine code */
1233 for (i = 0; i < fdet->firmware_len; i += 4) {
1234 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER,
1235 *(u32 *)&fdet->firmware_ptr[i]);
1237 /* step 6: IMEM override off */
1238 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000);
1239 /* step 7: turn ECC on */
1240 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000);
1242 /* steps 8-11: run the RSA engine */
1243 err = run_rsa(dd, "fabric serdes", fdet->signature);
1247 /* step 12: turn SPICO enable on */
1248 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1249 /* step 13: enable core hardware interrupts */
1250 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000);
1255 static int load_sbus_firmware(struct hfi1_devdata *dd,
1256 struct firmware_details *fdet)
1259 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1261 dd_dev_info(dd, "Downloading SBus firmware\n");
1263 /* step 1: load security variables */
1264 load_security_variables(dd, fdet);
1265 /* step 2: place SPICO into reset and enable off */
1266 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0);
1267 /* step 3: remove reset, enable off, IMEM_CNTRL_EN on */
1268 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240);
1269 /* step 4: set starting IMEM address for burst download */
1270 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000);
1271 /* step 5: download the SBus Master machine code */
1272 for (i = 0; i < fdet->firmware_len; i += 4) {
1273 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER,
1274 *(u32 *)&fdet->firmware_ptr[i]);
1276 /* step 6: set IMEM_CNTL_EN off */
1277 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040);
1278 /* step 7: turn ECC on */
1279 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000);
1281 /* steps 8-11: run the RSA engine */
1282 err = run_rsa(dd, "SBus", fdet->signature);
1286 /* step 12: set SPICO_ENABLE on */
1287 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1292 static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
1293 struct firmware_details *fdet)
1296 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1298 dd_dev_info(dd, "Downloading PCIe firmware\n");
1300 /* step 1: load security variables */
1301 load_security_variables(dd, fdet);
1302 /* step 2: assert single step (halts the SBus Master spico) */
1303 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001);
1304 /* step 3: enable XDMEM access */
1305 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40);
1306 /* step 4: load firmware into SBus Master XDMEM */
1308 * NOTE: the dmem address, write_en, and wdata are all pre-packed,
1309 * we only need to pick up the bytes and write them
1311 for (i = 0; i < fdet->firmware_len; i += 4) {
1312 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
1313 *(u32 *)&fdet->firmware_ptr[i]);
1315 /* step 5: disable XDMEM access */
1316 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1317 /* step 6: allow SBus Spico to run */
1318 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000);
1321 * steps 7-11: run RSA, if it succeeds, firmware is available to
1324 return run_rsa(dd, "PCIe serdes", fdet->signature);
1328 * Set the given broadcast values on the given list of devices.
1330 static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2,
1331 const u8 *addrs, int count)
1333 while (--count >= 0) {
1335 * Set BROADCAST_GROUP_1 and BROADCAST_GROUP_2, leave
1336 * defaults for everything else. Do not read-modify-write,
1337 * per instruction from the manufacturer.
1341 * ----- ---------------------------------
1342 * 0 IGNORE_BROADCAST (default 0)
1343 * 11:4 BROADCAST_GROUP_1 (default 0xff)
1344 * 23:16 BROADCAST_GROUP_2 (default 0xff)
1346 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER,
1347 (u32)bg1 << 4 | (u32)bg2 << 16);
1351 int acquire_hw_mutex(struct hfi1_devdata *dd)
1353 unsigned long timeout;
1355 u8 mask = 1 << dd->hfi1_id;
1359 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies;
1361 write_csr(dd, ASIC_CFG_MUTEX, mask);
1362 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1364 return 0; /* success */
1365 if (time_after(jiffies, timeout))
1366 break; /* timed out */
1372 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
1373 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
1376 /* break mutex and retry */
1377 write_csr(dd, ASIC_CFG_MUTEX, 0);
1385 void release_hw_mutex(struct hfi1_devdata *dd)
1387 write_csr(dd, ASIC_CFG_MUTEX, 0);
1390 /* return the given resource bit(s) as a mask for the given HFI */
1391 static inline u64 resource_mask(u32 hfi1_id, u32 resource)
1393 return ((u64)resource) << (hfi1_id ? CR_DYN_SHIFT : 0);
1396 static void fail_mutex_acquire_message(struct hfi1_devdata *dd,
1400 "%s: hardware mutex stuck - suggest rebooting the machine\n",
1405 * Acquire access to a chip resource.
1407 * Return 0 on success, -EBUSY if resource busy, -EIO if mutex acquire failed.
1409 static int __acquire_chip_resource(struct hfi1_devdata *dd, u32 resource)
1411 u64 scratch0, all_bits, my_bit;
1414 if (resource & CR_DYN_MASK) {
1415 /* a dynamic resource is in use if either HFI has set the bit */
1416 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0 &&
1417 (resource & (CR_I2C1 | CR_I2C2))) {
1418 /* discrete devices must serialize across both chains */
1419 all_bits = resource_mask(0, CR_I2C1 | CR_I2C2) |
1420 resource_mask(1, CR_I2C1 | CR_I2C2);
1422 all_bits = resource_mask(0, resource) |
1423 resource_mask(1, resource);
1425 my_bit = resource_mask(dd->hfi1_id, resource);
1427 /* non-dynamic resources are not split between HFIs */
1428 all_bits = resource;
1432 /* lock against other callers within the driver wanting a resource */
1433 mutex_lock(&dd->asic_data->asic_resource_mutex);
1435 ret = acquire_hw_mutex(dd);
1437 fail_mutex_acquire_message(dd, __func__);
1442 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1443 if (scratch0 & all_bits) {
1446 write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit);
1447 /* force write to be visible to other HFI on another OS */
1448 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1451 release_hw_mutex(dd);
1454 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1459 * Acquire access to a chip resource, wait up to mswait milliseconds for
1460 * the resource to become available.
1462 * Return 0 on success, -EBUSY if busy (even after wait), -EIO if mutex
1465 int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait)
1467 unsigned long timeout;
1470 timeout = jiffies + msecs_to_jiffies(mswait);
1472 ret = __acquire_chip_resource(dd, resource);
1475 /* resource is busy, check our timeout */
1476 if (time_after_eq(jiffies, timeout))
1478 usleep_range(80, 120); /* arbitrary delay */
1483 * Release access to a chip resource
1485 void release_chip_resource(struct hfi1_devdata *dd, u32 resource)
1489 /* only dynamic resources should ever be cleared */
1490 if (!(resource & CR_DYN_MASK)) {
1491 dd_dev_err(dd, "%s: invalid resource 0x%x\n", __func__,
1495 bit = resource_mask(dd->hfi1_id, resource);
1497 /* lock against other callers within the driver wanting a resource */
1498 mutex_lock(&dd->asic_data->asic_resource_mutex);
1500 if (acquire_hw_mutex(dd)) {
1501 fail_mutex_acquire_message(dd, __func__);
1505 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1506 if ((scratch0 & bit) != 0) {
1508 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1509 /* force write to be visible to other HFI on another OS */
1510 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1512 dd_dev_warn(dd, "%s: id %d, resource 0x%x: bit not set\n",
1513 __func__, dd->hfi1_id, resource);
1516 release_hw_mutex(dd);
1519 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1523 * Return true if resource is set, false otherwise. Print a warning
1524 * if not set and a function is supplied.
1526 bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
1531 if (resource & CR_DYN_MASK)
1532 bit = resource_mask(dd->hfi1_id, resource);
1536 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1537 if ((scratch0 & bit) == 0) {
1540 "%s: id %d, resource 0x%x, not acquired!\n",
1541 func, dd->hfi1_id, resource);
1547 static void clear_chip_resources(struct hfi1_devdata *dd, const char *func)
1551 /* lock against other callers within the driver wanting a resource */
1552 mutex_lock(&dd->asic_data->asic_resource_mutex);
1554 if (acquire_hw_mutex(dd)) {
1555 fail_mutex_acquire_message(dd, func);
1559 /* clear all dynamic access bits for this HFI */
1560 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1561 scratch0 &= ~resource_mask(dd->hfi1_id, CR_DYN_MASK);
1562 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1563 /* force write to be visible to other HFI on another OS */
1564 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1566 release_hw_mutex(dd);
1569 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1572 void init_chip_resources(struct hfi1_devdata *dd)
1574 /* clear any holds left by us */
1575 clear_chip_resources(dd, __func__);
1578 void finish_chip_resources(struct hfi1_devdata *dd)
1580 /* clear any holds left by us */
1581 clear_chip_resources(dd, __func__);
1584 void set_sbus_fast_mode(struct hfi1_devdata *dd)
1586 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1587 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
1590 void clear_sbus_fast_mode(struct hfi1_devdata *dd)
1594 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1595 while (SBUS_COUNTER(reg, EXECUTE) !=
1596 SBUS_COUNTER(reg, RCV_DATA_VALID)) {
1597 if (count++ >= SBUS_MAX_POLL_COUNT)
1600 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1602 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1605 int load_firmware(struct hfi1_devdata *dd)
1609 if (fw_fabric_serdes_load) {
1610 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1614 set_sbus_fast_mode(dd);
1616 set_serdes_broadcast(dd, all_fabric_serdes_broadcast,
1617 fabric_serdes_broadcast[dd->hfi1_id],
1618 fabric_serdes_addrs[dd->hfi1_id],
1620 turn_off_spicos(dd, SPICO_FABRIC);
1622 ret = load_fabric_serdes_firmware(dd, &fw_fabric);
1623 } while (retry_firmware(dd, ret));
1625 clear_sbus_fast_mode(dd);
1626 release_chip_resource(dd, CR_SBUS);
1633 ret = load_8051_firmware(dd, &fw_8051);
1634 } while (retry_firmware(dd, ret));
1642 int hfi1_firmware_init(struct hfi1_devdata *dd)
1644 /* only RTL can use these */
1645 if (dd->icode != ICODE_RTL_SILICON) {
1646 fw_fabric_serdes_load = 0;
1647 fw_pcie_serdes_load = 0;
1651 /* no 8051 or QSFP on simulator */
1652 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
1654 platform_config_load = 0;
1657 if (!fw_8051_name) {
1658 if (dd->icode == ICODE_RTL_SILICON)
1659 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC;
1661 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA;
1663 if (!fw_fabric_serdes_name)
1664 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME;
1666 fw_sbus_name = DEFAULT_FW_SBUS_NAME;
1667 if (!fw_pcie_serdes_name)
1668 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME;
1669 if (!platform_config_name)
1670 platform_config_name = DEFAULT_PLATFORM_CONFIG_NAME;
1672 return obtain_firmware(dd);
1676 * This function is a helper function for parse_platform_config(...) and
1677 * does not check for validity of the platform configuration cache
1678 * (because we know it is invalid as we are building up the cache).
1679 * As such, this should not be called from anywhere other than
1680 * parse_platform_config
1682 static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table)
1684 u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask;
1685 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1691 *(pcfgcache->config_tables[PLATFORM_CONFIG_SYSTEM_TABLE].table_metadata
1692 + SYSTEM_TABLE_META_VERSION);
1694 mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
1695 ver_start = meta_ver_meta & mask;
1697 meta_ver_meta >>= METADATA_TABLE_FIELD_LEN_SHIFT;
1699 mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
1700 ver_len = meta_ver_meta & mask;
1703 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1);
1707 dd, "%s:Please update platform config\n", __func__);
1713 int parse_platform_config(struct hfi1_devdata *dd)
1715 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1717 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0, file_length = 0;
1718 u32 record_idx = 0, table_type = 0, table_length_dwords = 0;
1719 int ret = -EINVAL; /* assume failure */
1721 if (!dd->platform_config.data) {
1722 dd_dev_info(dd, "%s: Missing config file\n", __func__);
1725 ptr = (u32 *)dd->platform_config.data;
1729 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) {
1730 dd_dev_info(dd, "%s: Bad config file\n", __func__);
1734 /* Field is file size in DWORDs */
1735 file_length = (*ptr) * 4;
1738 if (file_length > dd->platform_config.size) {
1739 dd_dev_info(dd, "%s:File claims to be larger than read size\n",
1742 } else if (file_length < dd->platform_config.size) {
1744 "%s:File claims to be smaller than read size, continuing\n",
1747 /* exactly equal, perfection */
1750 * In both cases where we proceed, using the self-reported file length
1751 * is the safer option
1753 while (ptr < (u32 *)(dd->platform_config.data + file_length)) {
1755 header2 = *(ptr + 1);
1756 if (header1 != ~header2) {
1757 dd_dev_info(dd, "%s: Failed validation at offset %ld\n",
1758 __func__, (ptr - (u32 *)
1759 dd->platform_config.data));
1764 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1);
1766 table_length_dwords = (*ptr >>
1767 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) &
1768 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1);
1770 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) &
1771 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1);
1773 /* Done with this set of headers */
1778 switch (table_type) {
1779 case PLATFORM_CONFIG_SYSTEM_TABLE:
1780 pcfgcache->config_tables[table_type].num_table =
1782 ret = check_meta_version(dd, ptr);
1786 case PLATFORM_CONFIG_PORT_TABLE:
1787 pcfgcache->config_tables[table_type].num_table =
1790 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1792 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1794 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1796 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1797 pcfgcache->config_tables[table_type].num_table =
1798 table_length_dwords;
1802 "%s: Unknown data table %d, offset %ld\n",
1803 __func__, table_type,
1805 dd->platform_config.data));
1806 goto bail; /* We don't trust this file now */
1808 pcfgcache->config_tables[table_type].table = ptr;
1810 /* metadata table */
1811 switch (table_type) {
1812 case PLATFORM_CONFIG_SYSTEM_TABLE:
1814 case PLATFORM_CONFIG_PORT_TABLE:
1816 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1818 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1820 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1822 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1826 "%s: Unknown meta table %d, offset %ld\n",
1827 __func__, table_type,
1829 (u32 *)dd->platform_config.data));
1830 goto bail; /* We don't trust this file now */
1832 pcfgcache->config_tables[table_type].table_metadata =
1836 /* Calculate and check table crc */
1837 crc = crc32_le(~(u32)0, (unsigned char const *)ptr,
1838 (table_length_dwords * 4));
1841 /* Jump the table */
1842 ptr += table_length_dwords;
1844 dd_dev_info(dd, "%s: Failed CRC check at offset %ld\n",
1847 dd->platform_config.data));
1850 /* Jump the CRC DWORD */
1854 pcfgcache->cache_valid = 1;
1857 memset(pcfgcache, 0, sizeof(struct platform_config_cache));
1861 static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
1862 int field, u32 *field_len_bits,
1863 u32 *field_start_bits)
1865 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1866 u32 *src_ptr = NULL;
1868 if (!pcfgcache->cache_valid)
1872 case PLATFORM_CONFIG_SYSTEM_TABLE:
1874 case PLATFORM_CONFIG_PORT_TABLE:
1876 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1878 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1880 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1882 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1883 if (field && field < platform_config_table_limits[table])
1885 pcfgcache->config_tables[table].table_metadata + field;
1888 dd_dev_info(dd, "%s: Unknown table\n", __func__);
1895 if (field_start_bits)
1896 *field_start_bits = *src_ptr &
1897 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
1900 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT)
1901 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
1906 /* This is the central interface to getting data out of the platform config
1907 * file. It depends on parse_platform_config() having populated the
1908 * platform_config_cache in hfi1_devdata, and checks the cache_valid member to
1909 * validate the sanity of the cache.
1911 * The non-obvious parameters:
1912 * @table_index: Acts as a look up key into which instance of the tables the
1913 * relevant field is fetched from.
1915 * This applies to the data tables that have multiple instances. The port table
1916 * is an exception to this rule as each HFI only has one port and thus the
1917 * relevant table can be distinguished by hfi_id.
1919 * @data: pointer to memory that will be populated with the field requested.
1920 * @len: length of memory pointed by @data in bytes.
1922 int get_platform_config_field(struct hfi1_devdata *dd,
1923 enum platform_config_table_type_encoding
1924 table_type, int table_index, int field_index,
1927 int ret = 0, wlen = 0, seek = 0;
1928 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL;
1929 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1932 memset(data, 0, len);
1936 ret = get_platform_fw_field_metadata(dd, table_type, field_index,
1942 /* Convert length to bits */
1945 /* Our metadata function checked cache_valid and field_index for us */
1946 switch (table_type) {
1947 case PLATFORM_CONFIG_SYSTEM_TABLE:
1948 src_ptr = pcfgcache->config_tables[table_type].table;
1950 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) {
1951 if (len < field_len_bits)
1954 seek = field_start_bits / 8;
1955 wlen = field_len_bits / 8;
1957 src_ptr = (u32 *)((u8 *)src_ptr + seek);
1960 * We expect the field to be byte aligned and whole byte
1961 * lengths if we are here
1963 memcpy(data, src_ptr, wlen);
1967 case PLATFORM_CONFIG_PORT_TABLE:
1968 /* Port table is 4 DWORDS */
1969 src_ptr = dd->hfi1_id ?
1970 pcfgcache->config_tables[table_type].table + 4 :
1971 pcfgcache->config_tables[table_type].table;
1973 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1975 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1977 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1979 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1980 src_ptr = pcfgcache->config_tables[table_type].table;
1983 pcfgcache->config_tables[table_type].num_table)
1984 src_ptr += table_index;
1989 dd_dev_info(dd, "%s: Unknown table\n", __func__);
1993 if (!src_ptr || len < field_len_bits)
1996 src_ptr += (field_start_bits / 32);
1997 *data = (*src_ptr >> (field_start_bits % 32)) &
1998 ((1 << field_len_bits) - 1);
2004 * Download the firmware needed for the Gen3 PCIe SerDes. An update
2005 * to the SBus firmware is needed before updating the PCIe firmware.
2007 * Note: caller must be holding the SBus resource.
2009 int load_pcie_firmware(struct hfi1_devdata *dd)
2013 /* both firmware loads below use the SBus */
2014 set_sbus_fast_mode(dd);
2017 turn_off_spicos(dd, SPICO_SBUS);
2019 ret = load_sbus_firmware(dd, &fw_sbus);
2020 } while (retry_firmware(dd, ret));
2025 if (fw_pcie_serdes_load) {
2026 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n");
2027 set_serdes_broadcast(dd, all_pcie_serdes_broadcast,
2028 pcie_serdes_broadcast[dd->hfi1_id],
2029 pcie_serdes_addrs[dd->hfi1_id],
2032 ret = load_pcie_serdes_firmware(dd, &fw_pcie);
2033 } while (retry_firmware(dd, ret));
2039 clear_sbus_fast_mode(dd);
2045 * Read the GUID from the hardware, store it in dd.
2047 void read_guid(struct hfi1_devdata *dd)
2049 /* Take the DC out of reset to get a valid GUID value */
2050 write_csr(dd, CCE_DC_CTRL, 0);
2051 (void)read_csr(dd, CCE_DC_CTRL);
2053 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
2054 dd_dev_info(dd, "GUID %llx",
2055 (unsigned long long)dd->base_guid);