drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/qp.h>
  44
  45 #include "mlx4_ib.h"
  46 #include "user.h"
  47
  48 enum {
  49         MLX4_IB_ACK_REQ_FREQ    = 8,
  50 };
  51
  52 enum {
  53         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  54         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  55         MLX4_IB_LINK_TYPE_IB            = 0,
  56         MLX4_IB_LINK_TYPE_ETH           = 1
  57 };
  58
  59 enum {
  60         /*
  61          * Largest possible UD header: send with GRH and immediate
  62          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  63          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  64          * biggest case)
  65          */
  66         MLX4_IB_UD_HEADER_SIZE          = 82,
  67         MLX4_IB_LSO_HEADER_SPARE        = 128,
  68 };
  69
  70 enum {
  71         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  72 };
  73
  74 struct mlx4_ib_sqp {
  75         struct mlx4_ib_qp       qp;
  76         int                     pkey_index;
  77         u32                     qkey;
  78         u32                     send_psn;
  79         struct ib_ud_header     ud_header;
  80         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  81 };
  82
  83 enum {
  84         MLX4_IB_MIN_SQ_STRIDE   = 6,
  85         MLX4_IB_CACHE_LINE_SIZE = 64,
  86 };
  87
  88 enum {
  89         MLX4_RAW_QP_MTU         = 7,
  90         MLX4_RAW_QP_MSGMAX      = 31,
  91 };
  92
  93 #ifndef ETH_ALEN
  94 #define ETH_ALEN        6
  95 #endif
  96 static inline u64 mlx4_mac_to_u64(u8 *addr)
  97 {
  98         u64 mac = 0;
  99         int i;
 100
 101         for (i = 0; i < ETH_ALEN; i++) {
 102                 mac <<= 8;
 103                 mac |= addr[i];
 104         }
 105         return mac;
 106 }
 107
 108 static const __be32 mlx4_ib_opcode[] = {
 109         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 110         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 111         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 112         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 113         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 114         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 115         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 116         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 117         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 118         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 119         [IB_WR_FAST_REG_MR]                     = cpu_to_be32(MLX4_OPCODE_FMR),
 120         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 121         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 122         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 123 };
 124
 125 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 126 {
 127         return container_of(mqp, struct mlx4_ib_sqp, qp);
 128 }
 129
 130 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 131 {
 132         if (!mlx4_is_master(dev->dev))
 133                 return 0;
 134
 135         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 136                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 137                 8 * MLX4_MFUNC_MAX;
 138 }
 139
 140 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 141 {
 142         int proxy_sqp = 0;
 143         int real_sqp = 0;
 144         int i;
 145         /* PPF or Native -- real SQP */
 146         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 147                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 148                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 149         if (real_sqp)
 150                 return 1;
 151         /* VF or PF -- proxy SQP */
 152         if (mlx4_is_mfunc(dev->dev)) {
 153                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 154                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 155                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 156                                 proxy_sqp = 1;
 157                                 break;
 158                         }
 159                 }
 160         }
 161         return proxy_sqp;
 162 }
 163
 164 /* used for INIT/CLOSE port logic */
 165 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 166 {
 167         int proxy_qp0 = 0;
 168         int real_qp0 = 0;
 169         int i;
 170         /* PPF or Native -- real QP0 */
 171         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 172                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 173                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 174         if (real_qp0)
 175                 return 1;
 176         /* VF or PF -- proxy QP0 */
 177         if (mlx4_is_mfunc(dev->dev)) {
 178                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 179                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 180                                 proxy_qp0 = 1;
 181                                 break;
 182                         }
 183                 }
 184         }
 185         return proxy_qp0;
 186 }
 187
 188 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 189 {
 190         return mlx4_buf_offset(&qp->buf, offset);
 191 }
 192
 193 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 196 }
 197
 198 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 199 {
 200         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 201 }
 202
 203 /*
 204  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 205  * first four bytes of every 64 byte chunk with
 206  *     0x7FFFFFF | (invalid_ownership_value << 31).
 207  *
 208  * When the max work request size is less than or equal to the WQE
 209  * basic block size, as an optimization, we can stamp all WQEs with
 210  * 0xffffffff, and skip the very first chunk of each WQE.
 211  */
 212 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 213 {
 214         __be32 *wqe;
 215         int i;
 216         int s;
 217         int ind;
 218         void *buf;
 219         __be32 stamp;
 220         struct mlx4_wqe_ctrl_seg *ctrl;
 221
 222         if (qp->sq_max_wqes_per_wr > 1) {
 223                 s = roundup(size, 1U << qp->sq.wqe_shift);
 224                 for (i = 0; i < s; i += 64) {
 225                         ind = (i >> qp->sq.wqe_shift) + n;
 226                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 227                                                        cpu_to_be32(0xffffffff);
 228                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 229                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 230                         *wqe = stamp;
 231                 }
 232         } else {
 233                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 234                 s = (ctrl->fence_size & 0x3f) << 4;
 235                 for (i = 64; i < s; i += 64) {
 236                         wqe = buf + i;
 237                         *wqe = cpu_to_be32(0xffffffff);
 238                 }
 239         }
 240 }
 241
 242 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 243 {
 244         struct mlx4_wqe_ctrl_seg *ctrl;
 245         struct mlx4_wqe_inline_seg *inl;
 246         void *wqe;
 247         int s;
 248
 249         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 250         s = sizeof(struct mlx4_wqe_ctrl_seg);
 251
 252         if (qp->ibqp.qp_type == IB_QPT_UD) {
 253                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 254                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 255                 memset(dgram, 0, sizeof *dgram);
 256                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 257                 s += sizeof(struct mlx4_wqe_datagram_seg);
 258         }
 259
 260         /* Pad the remainder of the WQE with an inline data segment. */
 261         if (size > s) {
 262                 inl = wqe + s;
 263                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 264         }
 265         ctrl->srcrb_flags = 0;
 266         ctrl->fence_size = size / 16;
 267         /*
 268          * Make sure descriptor is fully written before setting ownership bit
 269          * (because HW can start executing as soon as we do).
 270          */
 271         wmb();
 272
 273         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 274                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 275
 276         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 277 }
 278
 279 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 280 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 281 {
 282         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 283         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 284                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 285                 ind += s;
 286         }
 287         return ind;
 288 }
 289
 290 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 291 {
 292         struct ib_event event;
 293         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 294
 295         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 296                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 297
 298         if (ibqp->event_handler) {
 299                 event.device     = ibqp->device;
 300                 event.element.qp = ibqp;
 301                 switch (type) {
 302                 case MLX4_EVENT_TYPE_PATH_MIG:
 303                         event.event = IB_EVENT_PATH_MIG;
 304                         break;
 305                 case MLX4_EVENT_TYPE_COMM_EST:
 306                         event.event = IB_EVENT_COMM_EST;
 307                         break;
 308                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 309                         event.event = IB_EVENT_SQ_DRAINED;
 310                         break;
 311                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 312                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 313                         break;
 314                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 315                         event.event = IB_EVENT_QP_FATAL;
 316                         break;
 317                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 318                         event.event = IB_EVENT_PATH_MIG_ERR;
 319                         break;
 320                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 321                         event.event = IB_EVENT_QP_REQ_ERR;
 322                         break;
 323                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 324                         event.event = IB_EVENT_QP_ACCESS_ERR;
 325                         break;
 326                 default:
 327                         pr_warn("Unexpected event type %d "
 328                                "on QP %06x\n", type, qp->qpn);
 329                         return;
 330                 }
 331
 332                 ibqp->event_handler(&event, ibqp->qp_context);
 333         }
 334 }
 335
 336 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 337 {
 338         /*
 339          * UD WQEs must have a datagram segment.
 340          * RC and UC WQEs might have a remote address segment.
 341          * MLX WQEs need two extra inline data segments (for the UD
 342          * header and space for the ICRC).
 343          */
 344         switch (type) {
 345         case MLX4_IB_QPT_UD:
 346                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 347                         sizeof (struct mlx4_wqe_datagram_seg) +
 348                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 349         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 350         case MLX4_IB_QPT_PROXY_SMI:
 351         case MLX4_IB_QPT_PROXY_GSI:
 352                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 353                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 354         case MLX4_IB_QPT_TUN_SMI_OWNER:
 355         case MLX4_IB_QPT_TUN_GSI:
 356                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 357                         sizeof (struct mlx4_wqe_datagram_seg);
 358
 359         case MLX4_IB_QPT_UC:
 360                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 361                         sizeof (struct mlx4_wqe_raddr_seg);
 362         case MLX4_IB_QPT_RC:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         sizeof (struct mlx4_wqe_atomic_seg) +
 365                         sizeof (struct mlx4_wqe_raddr_seg);
 366         case MLX4_IB_QPT_SMI:
 367         case MLX4_IB_QPT_GSI:
 368                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 369                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 370                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 371                                            MLX4_INLINE_ALIGN) *
 372                               sizeof (struct mlx4_wqe_inline_seg),
 373                               sizeof (struct mlx4_wqe_data_seg)) +
 374                         ALIGN(4 +
 375                               sizeof (struct mlx4_wqe_inline_seg),
 376                               sizeof (struct mlx4_wqe_data_seg));
 377         default:
 378                 return sizeof (struct mlx4_wqe_ctrl_seg);
 379         }
 380 }
 381
 382 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 383                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 384 {
 385         /* Sanity check RQ size before proceeding */
 386         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 387             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 388                 return -EINVAL;
 389
 390         if (!has_rq) {
 391                 if (cap->max_recv_wr)
 392                         return -EINVAL;
 393
 394                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 395         } else {
 396                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 397                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 398                         return -EINVAL;
 399
 400                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 401                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 402                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 403         }
 404
 405         /* leave userspace return values as they were, so as not to break ABI */
 406         if (is_user) {
 407                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 408                 cap->max_recv_sge = qp->rq.max_gs;
 409         } else {
 410                 cap->max_recv_wr  = qp->rq.max_post =
 411                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 412                 cap->max_recv_sge = min(qp->rq.max_gs,
 413                                         min(dev->dev->caps.max_sq_sg,
 414                                             dev->dev->caps.max_rq_sg));
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 421                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 422 {
 423         int s;
 424
 425         /* Sanity check SQ size before proceeding */
 426         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 427             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 428             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 429             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 430                 return -EINVAL;
 431
 432         /*
 433          * For MLX transport we need 2 extra S/G entries:
 434          * one for the header and one for the checksum at the end
 435          */
 436         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 437              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 438             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 439                 return -EINVAL;
 440
 441         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 442                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 443                 send_wqe_overhead(type, qp->flags);
 444
 445         if (s > dev->dev->caps.max_sq_desc_sz)
 446                 return -EINVAL;
 447
 448         /*
 449          * Hermon supports shrinking WQEs, such that a single work
 450          * request can include multiple units of 1 << wqe_shift.  This
 451          * way, work requests can differ in size, and do not have to
 452          * be a power of 2 in size, saving memory and speeding up send
 453          * WR posting.  Unfortunately, if we do this then the
 454          * wqe_index field in CQEs can't be used to look up the WR ID
 455          * anymore, so we do this only if selective signaling is off.
 456          *
 457          * Further, on 32-bit platforms, we can't use vmap() to make
 458          * the QP buffer virtually contiguous.  Thus we have to use
 459          * constant-sized WRs to make sure a WR is always fully within
 460          * a single page-sized chunk.
 461          *
 462          * Finally, we use NOP work requests to pad the end of the
 463          * work queue, to avoid wrap-around in the middle of WR.  We
 464          * set NEC bit to avoid getting completions with error for
 465          * these NOP WRs, but since NEC is only supported starting
 466          * with firmware 2.2.232, we use constant-sized WRs for older
 467          * firmware.
 468          *
 469          * And, since MLX QPs only support SEND, we use constant-sized
 470          * WRs in this case.
 471          *
 472          * We look for the smallest value of wqe_shift such that the
 473          * resulting number of wqes does not exceed device
 474          * capabilities.
 475          *
 476          * We set WQE size to at least 64 bytes, this way stamping
 477          * invalidates each WQE.
 478          */
 479         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 480             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 481             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 482             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 483                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 484                 qp->sq.wqe_shift = ilog2(64);
 485         else
 486                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 487
 488         for (;;) {
 489                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 490
 491                 /*
 492                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 493                  * allow HW to prefetch.
 494                  */
 495                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 496                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 497                                                     qp->sq_max_wqes_per_wr +
 498                                                     qp->sq_spare_wqes);
 499
 500                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 501                         break;
 502
 503                 if (qp->sq_max_wqes_per_wr <= 1)
 504                         return -EINVAL;
 505
 506                 ++qp->sq.wqe_shift;
 507         }
 508
 509         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 510                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 511                          send_wqe_overhead(type, qp->flags)) /
 512                 sizeof (struct mlx4_wqe_data_seg);
 513
 514         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 515                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 516         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 517                 qp->rq.offset = 0;
 518                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 519         } else {
 520                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 521                 qp->sq.offset = 0;
 522         }
 523
 524         cap->max_send_wr  = qp->sq.max_post =
 525                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 526         cap->max_send_sge = min(qp->sq.max_gs,
 527                                 min(dev->dev->caps.max_sq_sg,
 528                                     dev->dev->caps.max_rq_sg));
 529         /* We don't support inline sends for kernel QPs (yet) */
 530         cap->max_inline_data = 0;
 531
 532         return 0;
 533 }
 534
 535 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 536                             struct mlx4_ib_qp *qp,
 537                             struct mlx4_ib_create_qp *ucmd)
 538 {
 539         /* Sanity check SQ size before proceeding */
 540         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 541             ucmd->log_sq_stride >
 542                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 543             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 544                 return -EINVAL;
 545
 546         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 547         qp->sq.wqe_shift = ucmd->log_sq_stride;
 548
 549         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 550                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 551
 552         return 0;
 553 }
 554
 555 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 556 {
 557         int i;
 558
 559         qp->sqp_proxy_rcv =
 560                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 561                         GFP_KERNEL);
 562         if (!qp->sqp_proxy_rcv)
 563                 return -ENOMEM;
 564         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 565                 qp->sqp_proxy_rcv[i].addr =
 566                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 567                                 GFP_KERNEL);
 568                 if (!qp->sqp_proxy_rcv[i].addr)
 569                         goto err;
 570                 qp->sqp_proxy_rcv[i].map =
 571                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 572                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 573                                           DMA_FROM_DEVICE);
 574         }
 575         return 0;
 576
 577 err:
 578         while (i > 0) {
 579                 --i;
 580                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 581                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 582                                     DMA_FROM_DEVICE);
 583                 kfree(qp->sqp_proxy_rcv[i].addr);
 584         }
 585         kfree(qp->sqp_proxy_rcv);
 586         qp->sqp_proxy_rcv = NULL;
 587         return -ENOMEM;
 588 }
 589
 590 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 591 {
 592         int i;
 593
 594         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 595                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 596                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 597                                     DMA_FROM_DEVICE);
 598                 kfree(qp->sqp_proxy_rcv[i].addr);
 599         }
 600         kfree(qp->sqp_proxy_rcv);
 601 }
 602
 603 static int qp_has_rq(struct ib_qp_init_attr *attr)
 604 {
 605         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 606                 return 0;
 607
 608         return !attr->srq;
 609 }
 610
 611 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 612                             struct ib_qp_init_attr *init_attr,
 613                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp)
 614 {
 615         int qpn;
 616         int err;
 617         struct mlx4_ib_sqp *sqp;
 618         struct mlx4_ib_qp *qp;
 619         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 620
 621         /* When tunneling special qps, we use a plain UD qp */
 622         if (sqpn) {
 623                 if (mlx4_is_mfunc(dev->dev) &&
 624                     (!mlx4_is_master(dev->dev) ||
 625                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 626                         if (init_attr->qp_type == IB_QPT_GSI)
 627                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 628                         else if (mlx4_is_master(dev->dev))
 629                                 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 630                         else
 631                                 qp_type = MLX4_IB_QPT_PROXY_SMI;
 632                 }
 633                 qpn = sqpn;
 634                 /* add extra sg entry for tunneling */
 635                 init_attr->cap.max_recv_sge++;
 636         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 637                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 638                         container_of(init_attr,
 639                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 640                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 641                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 642                     !mlx4_is_master(dev->dev))
 643                         return -EINVAL;
 644                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 645                         qp_type = MLX4_IB_QPT_TUN_GSI;
 646                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev))
 647                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 648                 else
 649                         qp_type = MLX4_IB_QPT_TUN_SMI;
 650                 /* we are definitely in the PPF here, since we are creating
 651                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 652                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 653                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 654                 sqpn = qpn;
 655         }
 656
 657         if (!*caller_qp) {
 658                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 659                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 660                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 661                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), GFP_KERNEL);
 662                         if (!sqp)
 663                                 return -ENOMEM;
 664                         qp = &sqp->qp;
 665                         qp->pri.vid = 0xFFFF;
 666                         qp->alt.vid = 0xFFFF;
 667                 } else {
 668                         qp = kzalloc(sizeof (struct mlx4_ib_qp), GFP_KERNEL);
 669                         if (!qp)
 670                                 return -ENOMEM;
 671                         qp->pri.vid = 0xFFFF;
 672                         qp->alt.vid = 0xFFFF;
 673                 }
 674         } else
 675                 qp = *caller_qp;
 676
 677         qp->mlx4_ib_qp_type = qp_type;
 678
 679         mutex_init(&qp->mutex);
 680         spin_lock_init(&qp->sq.lock);
 681         spin_lock_init(&qp->rq.lock);
 682         INIT_LIST_HEAD(&qp->gid_list);
 683         INIT_LIST_HEAD(&qp->steering_rules);
 684
 685         qp->state        = IB_QPS_RESET;
 686         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 687                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 688
 689         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 690         if (err)
 691                 goto err;
 692
 693         if (pd->uobject) {
 694                 struct mlx4_ib_create_qp ucmd;
 695
 696                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 697                         err = -EFAULT;
 698                         goto err;
 699                 }
 700
 701                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 702
 703                 err = set_user_sq_size(dev, qp, &ucmd);
 704                 if (err)
 705                         goto err;
 706
 707                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 708                                        qp->buf_size, 0, 0);
 709                 if (IS_ERR(qp->umem)) {
 710                         err = PTR_ERR(qp->umem);
 711                         goto err;
 712                 }
 713
 714                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 715                                     ilog2(qp->umem->page_size), &qp->mtt);
 716                 if (err)
 717                         goto err_buf;
 718
 719                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 720                 if (err)
 721                         goto err_mtt;
 722
 723                 if (qp_has_rq(init_attr)) {
 724                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 725                                                   ucmd.db_addr, &qp->db);
 726                         if (err)
 727                                 goto err_mtt;
 728                 }
 729         } else {
 730                 qp->sq_no_prefetch = 0;
 731
 732                 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 733                         qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 734
 735                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 736                         qp->flags |= MLX4_IB_QP_LSO;
 737
 738                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 739                         if (dev->steering_support ==
 740                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 741                                 qp->flags |= MLX4_IB_QP_NETIF;
 742                         else
 743                                 goto err;
 744                 }
 745
 746                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 747                 if (err)
 748                         goto err;
 749
 750                 if (qp_has_rq(init_attr)) {
 751                         err = mlx4_db_alloc(dev->dev, &qp->db, 0);
 752                         if (err)
 753                                 goto err;
 754
 755                         *qp->db.db = 0;
 756                 }
 757
 758                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
 759                         err = -ENOMEM;
 760                         goto err_db;
 761                 }
 762
 763                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 764                                     &qp->mtt);
 765                 if (err)
 766                         goto err_buf;
 767
 768                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
 769                 if (err)
 770                         goto err_mtt;
 771
 772                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 773                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
 774
 775                 if (!qp->sq.wrid || !qp->rq.wrid) {
 776                         err = -ENOMEM;
 777                         goto err_wrid;
 778                 }
 779         }
 780
 781         if (sqpn) {
 782                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 783                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 784                         if (alloc_proxy_bufs(pd->device, qp)) {
 785                                 err = -ENOMEM;
 786                                 goto err_wrid;
 787                         }
 788                 }
 789         } else {
 790                 /* Raw packet QPNs must be aligned to 8 bits. If not, the WQE
 791                  * BlueFlame setup flow wrongly causes VLAN insertion. */
 792                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 793                         err = mlx4_qp_reserve_range(dev->dev, 1, 1 << 8, &qpn);
 794                 else
 795                         if (qp->flags & MLX4_IB_QP_NETIF)
 796                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 797                         else
 798                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 799                                                             &qpn);
 800                 if (err)
 801                         goto err_proxy;
 802         }
 803
 804         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
 805         if (err)
 806                 goto err_qpn;
 807
 808         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 809                 qp->mqp.qpn |= (1 << 23);
 810
 811         /*
 812          * Hardware wants QPN written in big-endian order (after
 813          * shifting) for send doorbell.  Precompute this value to save
 814          * a little bit when posting sends.
 815          */
 816         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 817
 818         qp->mqp.event = mlx4_ib_qp_event;
 819         if (!*caller_qp)
 820                 *caller_qp = qp;
 821         return 0;
 822
 823 err_qpn:
 824         if (!sqpn) {
 825                 if (qp->flags & MLX4_IB_QP_NETIF)
 826                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 827                 else
 828                         mlx4_qp_release_range(dev->dev, qpn, 1);
 829         }
 830 err_proxy:
 831         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 832                 free_proxy_bufs(pd->device, qp);
 833 err_wrid:
 834         if (pd->uobject) {
 835                 if (qp_has_rq(init_attr))
 836                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 837         } else {
 838                 kfree(qp->sq.wrid);
 839                 kfree(qp->rq.wrid);
 840         }
 841
 842 err_mtt:
 843         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 844
 845 err_buf:
 846         if (pd->uobject)
 847                 ib_umem_release(qp->umem);
 848         else
 849                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 850
 851 err_db:
 852         if (!pd->uobject && qp_has_rq(init_attr))
 853                 mlx4_db_free(dev->dev, &qp->db);
 854
 855 err:
 856         if (!*caller_qp)
 857                 kfree(qp);
 858         return err;
 859 }
 860
 861 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 862 {
 863         switch (state) {
 864         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 865         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 866         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 867         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 868         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 869         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 870         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 871         default:                return -1;
 872         }
 873 }
 874
 875 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 876         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 877 {
 878         if (send_cq == recv_cq) {
 879                 spin_lock_irq(&send_cq->lock);
 880                 __acquire(&recv_cq->lock);
 881         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 882                 spin_lock_irq(&send_cq->lock);
 883                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 884         } else {
 885                 spin_lock_irq(&recv_cq->lock);
 886                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 887         }
 888 }
 889
 890 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 891         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 892 {
 893         if (send_cq == recv_cq) {
 894                 __release(&recv_cq->lock);
 895                 spin_unlock_irq(&send_cq->lock);
 896         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 897                 spin_unlock(&recv_cq->lock);
 898                 spin_unlock_irq(&send_cq->lock);
 899         } else {
 900                 spin_unlock(&send_cq->lock);
 901                 spin_unlock_irq(&recv_cq->lock);
 902         }
 903 }
 904
 905 static void del_gid_entries(struct mlx4_ib_qp *qp)
 906 {
 907         struct mlx4_ib_gid_entry *ge, *tmp;
 908
 909         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 910                 list_del(&ge->list);
 911                 kfree(ge);
 912         }
 913 }
 914
 915 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 916 {
 917         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 918                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 919         else
 920                 return to_mpd(qp->ibqp.pd);
 921 }
 922
 923 static void get_cqs(struct mlx4_ib_qp *qp,
 924                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 925 {
 926         switch (qp->ibqp.qp_type) {
 927         case IB_QPT_XRC_TGT:
 928                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 929                 *recv_cq = *send_cq;
 930                 break;
 931         case IB_QPT_XRC_INI:
 932                 *send_cq = to_mcq(qp->ibqp.send_cq);
 933                 *recv_cq = *send_cq;
 934                 break;
 935         default:
 936                 *send_cq = to_mcq(qp->ibqp.send_cq);
 937                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 938                 break;
 939         }
 940 }
 941
 942 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 943                               int is_user)
 944 {
 945         struct mlx4_ib_cq *send_cq, *recv_cq;
 946
 947         if (qp->state != IB_QPS_RESET) {
 948                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
 949                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
 950                         pr_warn("modify QP %06x to RESET failed.\n",
 951                                qp->mqp.qpn);
 952                 if (qp->pri.smac) {
 953                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
 954                         qp->pri.smac = 0;
 955                 }
 956                 if (qp->alt.smac) {
 957                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
 958                         qp->alt.smac = 0;
 959                 }
 960                 if (qp->pri.vid < 0x1000) {
 961                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
 962                         qp->pri.vid = 0xFFFF;
 963                         qp->pri.candidate_vid = 0xFFFF;
 964                         qp->pri.update_vid = 0;
 965                 }
 966                 if (qp->alt.vid < 0x1000) {
 967                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
 968                         qp->alt.vid = 0xFFFF;
 969                         qp->alt.candidate_vid = 0xFFFF;
 970                         qp->alt.update_vid = 0;
 971                 }
 972         }
 973
 974         get_cqs(qp, &send_cq, &recv_cq);
 975
 976         mlx4_ib_lock_cqs(send_cq, recv_cq);
 977
 978         if (!is_user) {
 979                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
 980                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
 981                 if (send_cq != recv_cq)
 982                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
 983         }
 984
 985         mlx4_qp_remove(dev->dev, &qp->mqp);
 986
 987         mlx4_ib_unlock_cqs(send_cq, recv_cq);
 988
 989         mlx4_qp_free(dev->dev, &qp->mqp);
 990
 991         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
 992                 if (qp->flags & MLX4_IB_QP_NETIF)
 993                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
 994                 else
 995                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
 996         }
 997
 998         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 999
1000         if (is_user) {
1001                 if (qp->rq.wqe_cnt)
1002                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1003                                               &qp->db);
1004                 ib_umem_release(qp->umem);
1005         } else {
1006                 kfree(qp->sq.wrid);
1007                 kfree(qp->rq.wrid);
1008                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1009                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1010                         free_proxy_bufs(&dev->ib_dev, qp);
1011                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1012                 if (qp->rq.wqe_cnt)
1013                         mlx4_db_free(dev->dev, &qp->db);
1014         }
1015
1016         del_gid_entries(qp);
1017 }
1018
1019 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1020 {
1021         /* Native or PPF */
1022         if (!mlx4_is_mfunc(dev->dev) ||
1023             (mlx4_is_master(dev->dev) &&
1024              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1025                 return  dev->dev->phys_caps.base_sqpn +
1026                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1027                         attr->port_num - 1;
1028         }
1029         /* PF or VF -- creating proxies */
1030         if (attr->qp_type == IB_QPT_SMI)
1031                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1032         else
1033                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1034 }
1035
1036 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1037                                 struct ib_qp_init_attr *init_attr,
1038                                 struct ib_udata *udata)
1039 {
1040         struct mlx4_ib_qp *qp = NULL;
1041         int err;
1042         u16 xrcdn = 0;
1043
1044         /*
1045          * We only support LSO, vendor flag1, and multicast loopback blocking,
1046          * and only for kernel UD QPs.
1047          */
1048         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1049                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1050                                         MLX4_IB_SRIOV_TUNNEL_QP |
1051                                         MLX4_IB_SRIOV_SQP |
1052                                         MLX4_IB_QP_NETIF))
1053                 return ERR_PTR(-EINVAL);
1054
1055         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1056                 if (init_attr->qp_type != IB_QPT_UD)
1057                         return ERR_PTR(-EINVAL);
1058         }
1059
1060         if (init_attr->create_flags &&
1061             (udata ||
1062              ((init_attr->create_flags & ~MLX4_IB_SRIOV_SQP) &&
1063               init_attr->qp_type != IB_QPT_UD) ||
1064              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1065               init_attr->qp_type > IB_QPT_GSI)))
1066                 return ERR_PTR(-EINVAL);
1067
1068         switch (init_attr->qp_type) {
1069         case IB_QPT_XRC_TGT:
1070                 pd = to_mxrcd(init_attr->xrcd)->pd;
1071                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1072                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1073                 /* fall through */
1074         case IB_QPT_XRC_INI:
1075                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1076                         return ERR_PTR(-ENOSYS);
1077                 init_attr->recv_cq = init_attr->send_cq;
1078                 /* fall through */
1079         case IB_QPT_RC:
1080         case IB_QPT_UC:
1081         case IB_QPT_RAW_PACKET:
1082                 qp = kzalloc(sizeof *qp, GFP_KERNEL);
1083                 if (!qp)
1084                         return ERR_PTR(-ENOMEM);
1085                 qp->pri.vid = 0xFFFF;
1086                 qp->alt.vid = 0xFFFF;
1087                 /* fall through */
1088         case IB_QPT_UD:
1089         {
1090                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1091                                        udata, 0, &qp);
1092                 if (err)
1093                         return ERR_PTR(err);
1094
1095                 qp->ibqp.qp_num = qp->mqp.qpn;
1096                 qp->xrcdn = xrcdn;
1097
1098                 break;
1099         }
1100         case IB_QPT_SMI:
1101         case IB_QPT_GSI:
1102         {
1103                 /* Userspace is not allowed to create special QPs: */
1104                 if (udata)
1105                         return ERR_PTR(-EINVAL);
1106
1107                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1108                                        get_sqp_num(to_mdev(pd->device), init_attr),
1109                                        &qp);
1110                 if (err)
1111                         return ERR_PTR(err);
1112
1113                 qp->port        = init_attr->port_num;
1114                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1115
1116                 break;
1117         }
1118         default:
1119                 /* Don't support raw QPs */
1120                 return ERR_PTR(-EINVAL);
1121         }
1122
1123         return &qp->ibqp;
1124 }
1125
1126 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1127 {
1128         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1129         struct mlx4_ib_qp *mqp = to_mqp(qp);
1130         struct mlx4_ib_pd *pd;
1131
1132         if (is_qp0(dev, mqp))
1133                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1134
1135         if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1136                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1137                 dev->qp1_proxy[mqp->port - 1] = NULL;
1138                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1139         }
1140
1141         pd = get_pd(mqp);
1142         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1143
1144         if (is_sqp(dev, mqp))
1145                 kfree(to_msqp(mqp));
1146         else
1147                 kfree(mqp);
1148
1149         return 0;
1150 }
1151
1152 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1153 {
1154         switch (type) {
1155         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1156         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1157         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1158         case MLX4_IB_QPT_XRC_INI:
1159         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1160         case MLX4_IB_QPT_SMI:
1161         case MLX4_IB_QPT_GSI:
1162         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1163
1164         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1165         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1166                                                 MLX4_QP_ST_MLX : -1);
1167         case MLX4_IB_QPT_PROXY_SMI:
1168         case MLX4_IB_QPT_TUN_SMI:
1169         case MLX4_IB_QPT_PROXY_GSI:
1170         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1171                                                 MLX4_QP_ST_UD : -1);
1172         default:                        return -1;
1173         }
1174 }
1175
1176 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1177                                    int attr_mask)
1178 {
1179         u8 dest_rd_atomic;
1180         u32 access_flags;
1181         u32 hw_access_flags = 0;
1182
1183         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1184                 dest_rd_atomic = attr->max_dest_rd_atomic;
1185         else
1186                 dest_rd_atomic = qp->resp_depth;
1187
1188         if (attr_mask & IB_QP_ACCESS_FLAGS)
1189                 access_flags = attr->qp_access_flags;
1190         else
1191                 access_flags = qp->atomic_rd_en;
1192
1193         if (!dest_rd_atomic)
1194                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1195
1196         if (access_flags & IB_ACCESS_REMOTE_READ)
1197                 hw_access_flags |= MLX4_QP_BIT_RRE;
1198         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1199                 hw_access_flags |= MLX4_QP_BIT_RAE;
1200         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1201                 hw_access_flags |= MLX4_QP_BIT_RWE;
1202
1203         return cpu_to_be32(hw_access_flags);
1204 }
1205
1206 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1207                             int attr_mask)
1208 {
1209         if (attr_mask & IB_QP_PKEY_INDEX)
1210                 sqp->pkey_index = attr->pkey_index;
1211         if (attr_mask & IB_QP_QKEY)
1212                 sqp->qkey = attr->qkey;
1213         if (attr_mask & IB_QP_SQ_PSN)
1214                 sqp->send_psn = attr->sq_psn;
1215 }
1216
1217 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1218 {
1219         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1220 }
1221
1222 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1223                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1224                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1225 {
1226         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1227                 IB_LINK_LAYER_ETHERNET;
1228         int vidx;
1229         int smac_index;
1230         int err;
1231
1232
1233         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1234         path->rlid          = cpu_to_be16(ah->dlid);
1235         if (ah->static_rate) {
1236                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1237                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1238                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1239                         --path->static_rate;
1240         } else
1241                 path->static_rate = 0;
1242
1243         if (ah->ah_flags & IB_AH_GRH) {
1244                 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
1245                         pr_err("sgid_index (%u) too large. max is %d\n",
1246                                ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1247                         return -1;
1248                 }
1249
1250                 path->grh_mylmc |= 1 << 7;
1251                 path->mgid_index = ah->grh.sgid_index;
1252                 path->hop_limit  = ah->grh.hop_limit;
1253                 path->tclass_flowlabel =
1254                         cpu_to_be32((ah->grh.traffic_class << 20) |
1255                                     (ah->grh.flow_label));
1256                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1257         }
1258
1259         if (is_eth) {
1260                 if (!(ah->ah_flags & IB_AH_GRH))
1261                         return -1;
1262
1263                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1264                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1265
1266                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1267                 if (vlan_tag < 0x1000) {
1268                         if (smac_info->vid < 0x1000) {
1269                                 /* both valid vlan ids */
1270                                 if (smac_info->vid != vlan_tag) {
1271                                         /* different VIDs.  unreg old and reg new */
1272                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1273                                         if (err)
1274                                                 return err;
1275                                         smac_info->candidate_vid = vlan_tag;
1276                                         smac_info->candidate_vlan_index = vidx;
1277                                         smac_info->candidate_vlan_port = port;
1278                                         smac_info->update_vid = 1;
1279                                         path->vlan_index = vidx;
1280                                 } else {
1281                                         path->vlan_index = smac_info->vlan_index;
1282                                 }
1283                         } else {
1284                                 /* no current vlan tag in qp */
1285                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1286                                 if (err)
1287                                         return err;
1288                                 smac_info->candidate_vid = vlan_tag;
1289                                 smac_info->candidate_vlan_index = vidx;
1290                                 smac_info->candidate_vlan_port = port;
1291                                 smac_info->update_vid = 1;
1292                                 path->vlan_index = vidx;
1293                         }
1294                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1295                         path->fl = 1 << 6;
1296                 } else {
1297                         /* have current vlan tag. unregister it at modify-qp success */
1298                         if (smac_info->vid < 0x1000) {
1299                                 smac_info->candidate_vid = 0xFFFF;
1300                                 smac_info->update_vid = 1;
1301                         }
1302                 }
1303
1304                 /* get smac_index for RoCE use.
1305                  * If no smac was yet assigned, register one.
1306                  * If one was already assigned, but the new mac differs,
1307                  * unregister the old one and register the new one.
1308                 */
1309                 if (!smac_info->smac || smac_info->smac != smac) {
1310                         /* register candidate now, unreg if needed, after success */
1311                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1312                         if (smac_index >= 0) {
1313                                 smac_info->candidate_smac_index = smac_index;
1314                                 smac_info->candidate_smac = smac;
1315                                 smac_info->candidate_smac_port = port;
1316                         } else {
1317                                 return -EINVAL;
1318                         }
1319                 } else {
1320                         smac_index = smac_info->smac_index;
1321                 }
1322
1323                 memcpy(path->dmac, ah->dmac, 6);
1324                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1325                 /* put MAC table smac index for IBoE */
1326                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1327         } else {
1328                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1329                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1330         }
1331
1332         return 0;
1333 }
1334
1335 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1336                          enum ib_qp_attr_mask qp_attr_mask,
1337                          struct mlx4_ib_qp *mqp,
1338                          struct mlx4_qp_path *path, u8 port)
1339 {
1340         return _mlx4_set_path(dev, &qp->ah_attr,
1341                               mlx4_mac_to_u64((u8 *)qp->smac),
1342                               (qp_attr_mask & IB_QP_VID) ? qp->vlan_id : 0xffff,
1343                               path, &mqp->pri, port);
1344 }
1345
1346 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1347                              const struct ib_qp_attr *qp,
1348                              enum ib_qp_attr_mask qp_attr_mask,
1349                              struct mlx4_ib_qp *mqp,
1350                              struct mlx4_qp_path *path, u8 port)
1351 {
1352         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1353                               mlx4_mac_to_u64((u8 *)qp->alt_smac),
1354                               (qp_attr_mask & IB_QP_ALT_VID) ?
1355                               qp->alt_vlan_id : 0xffff,
1356                               path, &mqp->alt, port);
1357 }
1358
1359 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1360 {
1361         struct mlx4_ib_gid_entry *ge, *tmp;
1362
1363         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1364                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1365                         ge->added = 1;
1366                         ge->port = qp->port;
1367                 }
1368         }
1369 }
1370
1371 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, u8 *smac,
1372                                     struct mlx4_qp_context *context)
1373 {
1374         struct net_device *ndev;
1375         u64 u64_mac;
1376         int smac_index;
1377
1378
1379         ndev = dev->iboe.netdevs[qp->port - 1];
1380         if (ndev) {
1381                 smac = ndev->dev_addr;
1382                 u64_mac = mlx4_mac_to_u64(smac);
1383         } else {
1384                 u64_mac = dev->dev->caps.def_mac[qp->port];
1385         }
1386
1387         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1388         if (!qp->pri.smac) {
1389                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1390                 if (smac_index >= 0) {
1391                         qp->pri.candidate_smac_index = smac_index;
1392                         qp->pri.candidate_smac = u64_mac;
1393                         qp->pri.candidate_smac_port = qp->port;
1394                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1395                 } else {
1396                         return -ENOENT;
1397                 }
1398         }
1399         return 0;
1400 }
1401
1402 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1403                                const struct ib_qp_attr *attr, int attr_mask,
1404                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1405 {
1406         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1407         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1408         struct mlx4_ib_pd *pd;
1409         struct mlx4_ib_cq *send_cq, *recv_cq;
1410         struct mlx4_qp_context *context;
1411         enum mlx4_qp_optpar optpar = 0;
1412         int sqd_event;
1413         int steer_qp = 0;
1414         int err = -EINVAL;
1415
1416         context = kzalloc(sizeof *context, GFP_KERNEL);
1417         if (!context)
1418                 return -ENOMEM;
1419
1420         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1421                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1422
1423         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1424                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1425         else {
1426                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1427                 switch (attr->path_mig_state) {
1428                 case IB_MIG_MIGRATED:
1429                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1430                         break;
1431                 case IB_MIG_REARM:
1432                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1433                         break;
1434                 case IB_MIG_ARMED:
1435                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1436                         break;
1437                 }
1438         }
1439
1440         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1441                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1442         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1443                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1444         else if (ibqp->qp_type == IB_QPT_UD) {
1445                 if (qp->flags & MLX4_IB_QP_LSO)
1446                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1447                                               ilog2(dev->dev->caps.max_gso_sz);
1448                 else
1449                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1450         } else if (attr_mask & IB_QP_PATH_MTU) {
1451                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1452                         pr_err("path MTU (%u) is invalid\n",
1453                                attr->path_mtu);
1454                         goto out;
1455                 }
1456                 context->mtu_msgmax = (attr->path_mtu << 5) |
1457                         ilog2(dev->dev->caps.max_msg_sz);
1458         }
1459
1460         if (qp->rq.wqe_cnt)
1461                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1462         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1463
1464         if (qp->sq.wqe_cnt)
1465                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1466         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1467
1468         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1469                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1470                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1471                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1472                         context->param3 |= cpu_to_be32(1 << 30);
1473         }
1474
1475         if (qp->ibqp.uobject)
1476                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1477         else
1478                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1479
1480         if (attr_mask & IB_QP_DEST_QPN)
1481                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1482
1483         if (attr_mask & IB_QP_PORT) {
1484                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1485                     !(attr_mask & IB_QP_AV)) {
1486                         mlx4_set_sched(&context->pri_path, attr->port_num);
1487                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1488                 }
1489         }
1490
1491         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1492                 if (dev->counters[qp->port - 1] != -1) {
1493                         context->pri_path.counter_index =
1494                                                 dev->counters[qp->port - 1];
1495                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1496                 } else
1497                         context->pri_path.counter_index = 0xff;
1498
1499                 if (qp->flags & MLX4_IB_QP_NETIF) {
1500                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1501                         steer_qp = 1;
1502                 }
1503         }
1504
1505         if (attr_mask & IB_QP_PKEY_INDEX) {
1506                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1507                         context->pri_path.disable_pkey_check = 0x40;
1508                 context->pri_path.pkey_index = attr->pkey_index;
1509                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1510         }
1511
1512         if (attr_mask & IB_QP_AV) {
1513                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1514                                   attr_mask & IB_QP_PORT ?
1515                                   attr->port_num : qp->port))
1516                         goto out;
1517
1518                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1519                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1520         }
1521
1522         if (attr_mask & IB_QP_TIMEOUT) {
1523                 context->pri_path.ackto |= attr->timeout << 3;
1524                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1525         }
1526
1527         if (attr_mask & IB_QP_ALT_PATH) {
1528                 if (attr->alt_port_num == 0 ||
1529                     attr->alt_port_num > dev->dev->caps.num_ports)
1530                         goto out;
1531
1532                 if (attr->alt_pkey_index >=
1533                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1534                         goto out;
1535
1536                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1537                                       &context->alt_path,
1538                                       attr->alt_port_num))
1539                         goto out;
1540
1541                 context->alt_path.pkey_index = attr->alt_pkey_index;
1542                 context->alt_path.ackto = attr->alt_timeout << 3;
1543                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1544         }
1545
1546         pd = get_pd(qp);
1547         get_cqs(qp, &send_cq, &recv_cq);
1548         context->pd       = cpu_to_be32(pd->pdn);
1549         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1550         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1551         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1552
1553         /* Set "fast registration enabled" for all kernel QPs */
1554         if (!qp->ibqp.uobject)
1555                 context->params1 |= cpu_to_be32(1 << 11);
1556
1557         if (attr_mask & IB_QP_RNR_RETRY) {
1558                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1559                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1560         }
1561
1562         if (attr_mask & IB_QP_RETRY_CNT) {
1563                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1564                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1565         }
1566
1567         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1568                 if (attr->max_rd_atomic)
1569                         context->params1 |=
1570                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1571                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1572         }
1573
1574         if (attr_mask & IB_QP_SQ_PSN)
1575                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1576
1577         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1578                 if (attr->max_dest_rd_atomic)
1579                         context->params2 |=
1580                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1581                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1582         }
1583
1584         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1585                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1586                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1587         }
1588
1589         if (ibqp->srq)
1590                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1591
1592         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1593                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1594                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1595         }
1596         if (attr_mask & IB_QP_RQ_PSN)
1597                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1598
1599         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1600         if (attr_mask & IB_QP_QKEY) {
1601                 if (qp->mlx4_ib_qp_type &
1602                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1603                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1604                 else {
1605                         if (mlx4_is_mfunc(dev->dev) &&
1606                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1607                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1608                             MLX4_RESERVED_QKEY_BASE) {
1609                                 pr_err("Cannot use reserved QKEY"
1610                                        " 0x%x (range 0xffff0000..0xffffffff"
1611                                        " is reserved)\n", attr->qkey);
1612                                 err = -EINVAL;
1613                                 goto out;
1614                         }
1615                         context->qkey = cpu_to_be32(attr->qkey);
1616                 }
1617                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1618         }
1619
1620         if (ibqp->srq)
1621                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1622
1623         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1624                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1625
1626         if (cur_state == IB_QPS_INIT &&
1627             new_state == IB_QPS_RTR  &&
1628             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1629              ibqp->qp_type == IB_QPT_UD ||
1630              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1631                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1632                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1633                     qp->mlx4_ib_qp_type &
1634                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1635                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1636                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1637                                 context->pri_path.fl = 0x80;
1638                 } else {
1639                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1640                                 context->pri_path.fl = 0x80;
1641                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1642                 }
1643                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1644                     IB_LINK_LAYER_ETHERNET) {
1645                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1646                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1647                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1648                         /* handle smac_index */
1649                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1650                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1651                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1652                                 err = handle_eth_ud_smac_index(dev, qp, (u8 *)attr->smac, context);
1653                                 if (err)
1654                                         return -EINVAL;
1655                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1656                                         dev->qp1_proxy[qp->port - 1] = qp;
1657                         }
1658                 }
1659         }
1660
1661         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
1662                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1663                                         MLX4_IB_LINK_TYPE_ETH;
1664
1665         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1666                 int is_eth = rdma_port_get_link_layer(
1667                                 &dev->ib_dev, qp->port) ==
1668                                 IB_LINK_LAYER_ETHERNET;
1669                 if (is_eth) {
1670                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1671                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1672                 }
1673         }
1674
1675
1676         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1677             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1678                 sqd_event = 1;
1679         else
1680                 sqd_event = 0;
1681
1682         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1683                 context->rlkey |= (1 << 4);
1684
1685         /*
1686          * Before passing a kernel QP to the HW, make sure that the
1687          * ownership bits of the send queue are set and the SQ
1688          * headroom is stamped so that the hardware doesn't start
1689          * processing stale work requests.
1690          */
1691         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1692                 struct mlx4_wqe_ctrl_seg *ctrl;
1693                 int i;
1694
1695                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1696                         ctrl = get_send_wqe(qp, i);
1697                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1698                         if (qp->sq_max_wqes_per_wr == 1)
1699                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1700
1701                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1702                 }
1703         }
1704
1705         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1706                              to_mlx4_state(new_state), context, optpar,
1707                              sqd_event, &qp->mqp);
1708         if (err)
1709                 goto out;
1710
1711         qp->state = new_state;
1712
1713         if (attr_mask & IB_QP_ACCESS_FLAGS)
1714                 qp->atomic_rd_en = attr->qp_access_flags;
1715         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1716                 qp->resp_depth = attr->max_dest_rd_atomic;
1717         if (attr_mask & IB_QP_PORT) {
1718                 qp->port = attr->port_num;
1719                 update_mcg_macs(dev, qp);
1720         }
1721         if (attr_mask & IB_QP_ALT_PATH)
1722                 qp->alt_port = attr->alt_port_num;
1723
1724         if (is_sqp(dev, qp))
1725                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1726
1727         /*
1728          * If we moved QP0 to RTR, bring the IB link up; if we moved
1729          * QP0 to RESET or ERROR, bring the link back down.
1730          */
1731         if (is_qp0(dev, qp)) {
1732                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1733                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1734                                 pr_warn("INIT_PORT failed for port %d\n",
1735                                        qp->port);
1736
1737                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1738                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1739                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1740         }
1741
1742         /*
1743          * If we moved a kernel QP to RESET, clean up all old CQ
1744          * entries and reinitialize the QP.
1745          */
1746         if (new_state == IB_QPS_RESET) {
1747                 if (!ibqp->uobject) {
1748                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1749                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1750                         if (send_cq != recv_cq)
1751                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1752
1753                         qp->rq.head = 0;
1754                         qp->rq.tail = 0;
1755                         qp->sq.head = 0;
1756                         qp->sq.tail = 0;
1757                         qp->sq_next_wqe = 0;
1758                         if (qp->rq.wqe_cnt)
1759                                 *qp->db.db  = 0;
1760
1761                         if (qp->flags & MLX4_IB_QP_NETIF)
1762                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1763                 }
1764                 if (qp->pri.smac) {
1765                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1766                         qp->pri.smac = 0;
1767                 }
1768                 if (qp->alt.smac) {
1769                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1770                         qp->alt.smac = 0;
1771                 }
1772                 if (qp->pri.vid < 0x1000) {
1773                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1774                         qp->pri.vid = 0xFFFF;
1775                         qp->pri.candidate_vid = 0xFFFF;
1776                         qp->pri.update_vid = 0;
1777                 }
1778
1779                 if (qp->alt.vid < 0x1000) {
1780                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1781                         qp->alt.vid = 0xFFFF;
1782                         qp->alt.candidate_vid = 0xFFFF;
1783                         qp->alt.update_vid = 0;
1784                 }
1785         }
1786 out:
1787         if (err && steer_qp)
1788                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1789         kfree(context);
1790         if (qp->pri.candidate_smac) {
1791                 if (err) {
1792                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1793                 } else {
1794                         if (qp->pri.smac)
1795                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1796                         qp->pri.smac = qp->pri.candidate_smac;
1797                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1798                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1799                 }
1800                 qp->pri.candidate_smac = 0;
1801                 qp->pri.candidate_smac_index = 0;
1802                 qp->pri.candidate_smac_port = 0;
1803         }
1804         if (qp->alt.candidate_smac) {
1805                 if (err) {
1806                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1807                 } else {
1808                         if (qp->alt.smac)
1809                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1810                         qp->alt.smac = qp->alt.candidate_smac;
1811                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1812                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1813                 }
1814                 qp->alt.candidate_smac = 0;
1815                 qp->alt.candidate_smac_index = 0;
1816                 qp->alt.candidate_smac_port = 0;
1817         }
1818
1819         if (qp->pri.update_vid) {
1820                 if (err) {
1821                         if (qp->pri.candidate_vid < 0x1000)
1822                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1823                                                      qp->pri.candidate_vid);
1824                 } else {
1825                         if (qp->pri.vid < 0x1000)
1826                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1827                                                      qp->pri.vid);
1828                         qp->pri.vid = qp->pri.candidate_vid;
1829                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1830                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1831                 }
1832                 qp->pri.candidate_vid = 0xFFFF;
1833                 qp->pri.update_vid = 0;
1834         }
1835
1836         if (qp->alt.update_vid) {
1837                 if (err) {
1838                         if (qp->alt.candidate_vid < 0x1000)
1839                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
1840                                                      qp->alt.candidate_vid);
1841                 } else {
1842                         if (qp->alt.vid < 0x1000)
1843                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
1844                                                      qp->alt.vid);
1845                         qp->alt.vid = qp->alt.candidate_vid;
1846                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
1847                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
1848                 }
1849                 qp->alt.candidate_vid = 0xFFFF;
1850                 qp->alt.update_vid = 0;
1851         }
1852
1853         return err;
1854 }
1855
1856 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1857                       int attr_mask, struct ib_udata *udata)
1858 {
1859         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1860         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1861         enum ib_qp_state cur_state, new_state;
1862         int err = -EINVAL;
1863         int ll;
1864         mutex_lock(&qp->mutex);
1865
1866         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1867         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1868
1869         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1870                 ll = IB_LINK_LAYER_UNSPECIFIED;
1871         } else {
1872                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1873                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1874         }
1875
1876         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
1877                                 attr_mask, ll)) {
1878                 pr_debug("qpn 0x%x: invalid attribute mask specified "
1879                          "for transition %d to %d. qp_type %d,"
1880                          " attr_mask 0x%x\n",
1881                          ibqp->qp_num, cur_state, new_state,
1882                          ibqp->qp_type, attr_mask);
1883                 goto out;
1884         }
1885
1886         if ((attr_mask & IB_QP_PORT) &&
1887             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
1888                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
1889                          "for transition %d to %d. qp_type %d\n",
1890                          ibqp->qp_num, attr->port_num, cur_state,
1891                          new_state, ibqp->qp_type);
1892                 goto out;
1893         }
1894
1895         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
1896             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
1897              IB_LINK_LAYER_ETHERNET))
1898                 goto out;
1899
1900         if (attr_mask & IB_QP_PKEY_INDEX) {
1901                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1902                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
1903                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
1904                                  "for transition %d to %d. qp_type %d\n",
1905                                  ibqp->qp_num, attr->pkey_index, cur_state,
1906                                  new_state, ibqp->qp_type);
1907                         goto out;
1908                 }
1909         }
1910
1911         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1912             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1913                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
1914                          "Transition %d to %d. qp_type %d\n",
1915                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
1916                          new_state, ibqp->qp_type);
1917                 goto out;
1918         }
1919
1920         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1921             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1922                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
1923                          "Transition %d to %d. qp_type %d\n",
1924                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
1925                          new_state, ibqp->qp_type);
1926                 goto out;
1927         }
1928
1929         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1930                 err = 0;
1931                 goto out;
1932         }
1933
1934         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1935
1936 out:
1937         mutex_unlock(&qp->mutex);
1938         return err;
1939 }
1940
1941 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
1942                                   struct ib_send_wr *wr,
1943                                   void *wqe, unsigned *mlx_seg_len)
1944 {
1945         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
1946         struct ib_device *ib_dev = &mdev->ib_dev;
1947         struct mlx4_wqe_mlx_seg *mlx = wqe;
1948         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1949         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1950         u16 pkey;
1951         u32 qkey;
1952         int send_size;
1953         int header_size;
1954         int spc;
1955         int i;
1956
1957         if (wr->opcode != IB_WR_SEND)
1958                 return -EINVAL;
1959
1960         send_size = 0;
1961
1962         for (i = 0; i < wr->num_sge; ++i)
1963                 send_size += wr->sg_list[i].length;
1964
1965         /* for proxy-qp0 sends, need to add in size of tunnel header */
1966         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
1967         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
1968                 send_size += sizeof (struct mlx4_ib_tunnel_header);
1969
1970         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
1971
1972         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
1973                 sqp->ud_header.lrh.service_level =
1974                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
1975                 sqp->ud_header.lrh.destination_lid =
1976                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1977                 sqp->ud_header.lrh.source_lid =
1978                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
1979         }
1980
1981         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1982
1983         /* force loopback */
1984         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
1985         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1986
1987         sqp->ud_header.lrh.virtual_lane    = 0;
1988         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1989         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
1990         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1991         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
1992                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1993         else
1994                 sqp->ud_header.bth.destination_qpn =
1995                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
1996
1997         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1998         if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
1999                 return -EINVAL;
2000         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2001         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2002
2003         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2004         sqp->ud_header.immediate_present = 0;
2005
2006         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2007
2008         /*
2009          * Inline data segments may not cross a 64 byte boundary.  If
2010          * our UD header is bigger than the space available up to the
2011          * next 64 byte boundary in the WQE, use two inline data
2012          * segments to hold the UD header.
2013          */
2014         spc = MLX4_INLINE_ALIGN -
2015               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2016         if (header_size <= spc) {
2017                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2018                 memcpy(inl + 1, sqp->header_buf, header_size);
2019                 i = 1;
2020         } else {
2021                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2022                 memcpy(inl + 1, sqp->header_buf, spc);
2023
2024                 inl = (void *) (inl + 1) + spc;
2025                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2026                 /*
2027                  * Need a barrier here to make sure all the data is
2028                  * visible before the byte_count field is set.
2029                  * Otherwise the HCA prefetcher could grab the 64-byte
2030                  * chunk with this inline segment and get a valid (!=
2031                  * 0xffffffff) byte count but stale data, and end up
2032                  * generating a packet with bad headers.
2033                  *
2034                  * The first inline segment's byte_count field doesn't
2035                  * need a barrier, because it comes after a
2036                  * control/MLX segment and therefore is at an offset
2037                  * of 16 mod 64.
2038                  */
2039                 wmb();
2040                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2041                 i = 2;
2042         }
2043
2044         *mlx_seg_len =
2045         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2046         return 0;
2047 }
2048
2049 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
2050                             void *wqe, unsigned *mlx_seg_len)
2051 {
2052         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2053         struct mlx4_wqe_mlx_seg *mlx = wqe;
2054         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2055         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2056         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2057         union ib_gid sgid;
2058         u16 pkey;
2059         int send_size;
2060         int header_size;
2061         int spc;
2062         int i;
2063         int err = 0;
2064         u16 vlan = 0xffff;
2065         bool is_eth;
2066         bool is_vlan = false;
2067         bool is_grh;
2068
2069         send_size = 0;
2070         for (i = 0; i < wr->num_sge; ++i)
2071                 send_size += wr->sg_list[i].length;
2072
2073         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2074         is_grh = mlx4_ib_ah_grh_present(ah);
2075         if (is_eth) {
2076                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2077                         /* When multi-function is enabled, the ib_core gid
2078                          * indexes don't necessarily match the hw ones, so
2079                          * we must use our own cache */
2080                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2081                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2082                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2083                         if (err)
2084                                 return err;
2085                 } else  {
2086                         err = ib_get_cached_gid(ib_dev,
2087                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2088                                                 ah->av.ib.gid_index, &sgid);
2089                         if (err)
2090                                 return err;
2091                 }
2092
2093                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2094                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2095                         is_vlan = 1;
2096                 }
2097         }
2098         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2099
2100         if (!is_eth) {
2101                 sqp->ud_header.lrh.service_level =
2102                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2103                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2104                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2105         }
2106
2107         if (is_grh) {
2108                 sqp->ud_header.grh.traffic_class =
2109                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2110                 sqp->ud_header.grh.flow_label    =
2111                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2112                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2113                 if (is_eth)
2114                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2115                 else {
2116                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2117                         /* When multi-function is enabled, the ib_core gid
2118                          * indexes don't necessarily match the hw ones, so
2119                          * we must use our own cache */
2120                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2121                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2122                                                        subnet_prefix;
2123                         sqp->ud_header.grh.source_gid.global.interface_id =
2124                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2125                                                guid_cache[ah->av.ib.gid_index];
2126                 } else
2127                         ib_get_cached_gid(ib_dev,
2128                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2129                                           ah->av.ib.gid_index,
2130                                           &sqp->ud_header.grh.source_gid);
2131                 }
2132                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2133                        ah->av.ib.dgid, 16);
2134         }
2135
2136         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2137
2138         if (!is_eth) {
2139                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2140                                           (sqp->ud_header.lrh.destination_lid ==
2141                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2142                                           (sqp->ud_header.lrh.service_level << 8));
2143                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2144                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2145                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2146         }
2147
2148         switch (wr->opcode) {
2149         case IB_WR_SEND:
2150                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2151                 sqp->ud_header.immediate_present = 0;
2152                 break;
2153         case IB_WR_SEND_WITH_IMM:
2154                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2155                 sqp->ud_header.immediate_present = 1;
2156                 sqp->ud_header.immediate_data    = wr->ex.imm_data;
2157                 break;
2158         default:
2159                 return -EINVAL;
2160         }
2161
2162         if (is_eth) {
2163                 u8 *smac;
2164                 struct in6_addr in6;
2165
2166                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2167
2168                 mlx->sched_prio = cpu_to_be16(pcp);
2169
2170                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2171                 /* FIXME: cache smac value? */
2172                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2173                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2174                 memcpy(&in6, sgid.raw, sizeof(in6));
2175
2176                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev))
2177                         smac = to_mdev(sqp->qp.ibqp.device)->
2178                                 iboe.netdevs[sqp->qp.port - 1]->dev_addr;
2179                 else    /* use the src mac of the tunnel */
2180                         smac = ah->av.eth.s_mac;
2181                 memcpy(sqp->ud_header.eth.smac_h, smac, 6);
2182                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2183                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2184                 if (!is_vlan) {
2185                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2186                 } else {
2187                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2188                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2189                 }
2190         } else {
2191                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2192                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2193                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2194         }
2195         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
2196         if (!sqp->qp.ibqp.qp_num)
2197                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2198         else
2199                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
2200         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2201         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2202         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2203         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
2204                                                sqp->qkey : wr->wr.ud.remote_qkey);
2205         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2206
2207         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2208
2209         if (0) {
2210                 pr_err("built UD header of size %d:\n", header_size);
2211                 for (i = 0; i < header_size / 4; ++i) {
2212                         if (i % 8 == 0)
2213                                 pr_err("  [%02x] ", i * 4);
2214                         pr_cont(" %08x",
2215                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2216                         if ((i + 1) % 8 == 0)
2217                                 pr_cont("\n");
2218                 }
2219                 pr_err("\n");
2220         }
2221
2222         /*
2223          * Inline data segments may not cross a 64 byte boundary.  If
2224          * our UD header is bigger than the space available up to the
2225          * next 64 byte boundary in the WQE, use two inline data
2226          * segments to hold the UD header.
2227          */
2228         spc = MLX4_INLINE_ALIGN -
2229                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2230         if (header_size <= spc) {
2231                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2232                 memcpy(inl + 1, sqp->header_buf, header_size);
2233                 i = 1;
2234         } else {
2235                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2236                 memcpy(inl + 1, sqp->header_buf, spc);
2237
2238                 inl = (void *) (inl + 1) + spc;
2239                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2240                 /*
2241                  * Need a barrier here to make sure all the data is
2242                  * visible before the byte_count field is set.
2243                  * Otherwise the HCA prefetcher could grab the 64-byte
2244                  * chunk with this inline segment and get a valid (!=
2245                  * 0xffffffff) byte count but stale data, and end up
2246                  * generating a packet with bad headers.
2247                  *
2248                  * The first inline segment's byte_count field doesn't
2249                  * need a barrier, because it comes after a
2250                  * control/MLX segment and therefore is at an offset
2251                  * of 16 mod 64.
2252                  */
2253                 wmb();
2254                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2255                 i = 2;
2256         }
2257
2258         *mlx_seg_len =
2259                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2260         return 0;
2261 }
2262
2263 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2264 {
2265         unsigned cur;
2266         struct mlx4_ib_cq *cq;
2267
2268         cur = wq->head - wq->tail;
2269         if (likely(cur + nreq < wq->max_post))
2270                 return 0;
2271
2272         cq = to_mcq(ib_cq);
2273         spin_lock(&cq->lock);
2274         cur = wq->head - wq->tail;
2275         spin_unlock(&cq->lock);
2276
2277         return cur + nreq >= wq->max_post;
2278 }
2279
2280 static __be32 convert_access(int acc)
2281 {
2282         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2283                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2284                (acc & IB_ACCESS_REMOTE_WRITE  ?
2285                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2286                (acc & IB_ACCESS_REMOTE_READ   ?
2287                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2288                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2289                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2290 }
2291
2292 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
2293 {
2294         struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
2295         int i;
2296
2297         for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2298                 mfrpl->mapped_page_list[i] =
2299                         cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
2300                                     MLX4_MTT_FLAG_PRESENT);
2301
2302         fseg->flags             = convert_access(wr->wr.fast_reg.access_flags);
2303         fseg->mem_key           = cpu_to_be32(wr->wr.fast_reg.rkey);
2304         fseg->buf_list          = cpu_to_be64(mfrpl->map);
2305         fseg->start_addr        = cpu_to_be64(wr->wr.fast_reg.iova_start);
2306         fseg->reg_len           = cpu_to_be64(wr->wr.fast_reg.length);
2307         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2308         fseg->page_size         = cpu_to_be32(wr->wr.fast_reg.page_shift);
2309         fseg->reserved[0]       = 0;
2310         fseg->reserved[1]       = 0;
2311 }
2312
2313 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg, struct ib_send_wr *wr)
2314 {
2315         bseg->flags1 =
2316                 convert_access(wr->wr.bind_mw.bind_info.mw_access_flags) &
2317                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2318                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2319                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2320         bseg->flags2 = 0;
2321         if (wr->wr.bind_mw.mw->type == IB_MW_TYPE_2)
2322                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2323         if (wr->wr.bind_mw.bind_info.mw_access_flags & IB_ZERO_BASED)
2324                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2325         bseg->new_rkey = cpu_to_be32(wr->wr.bind_mw.rkey);
2326         bseg->lkey = cpu_to_be32(wr->wr.bind_mw.bind_info.mr->lkey);
2327         bseg->addr = cpu_to_be64(wr->wr.bind_mw.bind_info.addr);
2328         bseg->length = cpu_to_be64(wr->wr.bind_mw.bind_info.length);
2329 }
2330
2331 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2332 {
2333         memset(iseg, 0, sizeof(*iseg));
2334         iseg->mem_key = cpu_to_be32(rkey);
2335 }
2336
2337 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2338                                           u64 remote_addr, u32 rkey)
2339 {
2340         rseg->raddr    = cpu_to_be64(remote_addr);
2341         rseg->rkey     = cpu_to_be32(rkey);
2342         rseg->reserved = 0;
2343 }
2344
2345 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
2346 {
2347         if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2348                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
2349                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add);
2350         } else if (wr->opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2351                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2352                 aseg->compare  = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2353         } else {
2354                 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
2355                 aseg->compare  = 0;
2356         }
2357
2358 }
2359
2360 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2361                                   struct ib_send_wr *wr)
2362 {
2363         aseg->swap_add          = cpu_to_be64(wr->wr.atomic.swap);
2364         aseg->swap_add_mask     = cpu_to_be64(wr->wr.atomic.swap_mask);
2365         aseg->compare           = cpu_to_be64(wr->wr.atomic.compare_add);
2366         aseg->compare_mask      = cpu_to_be64(wr->wr.atomic.compare_add_mask);
2367 }
2368
2369 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2370                              struct ib_send_wr *wr)
2371 {
2372         memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
2373         dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2374         dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2375         dseg->vlan = to_mah(wr->wr.ud.ah)->av.eth.vlan;
2376         memcpy(dseg->mac, to_mah(wr->wr.ud.ah)->av.eth.mac, 6);
2377 }
2378
2379 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2380                                     struct mlx4_wqe_datagram_seg *dseg,
2381                                     struct ib_send_wr *wr, enum ib_qp_type qpt)
2382 {
2383         union mlx4_ext_av *av = &to_mah(wr->wr.ud.ah)->av;
2384         struct mlx4_av sqp_av = {0};
2385         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2386
2387         /* force loopback */
2388         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2389         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2390         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2391                         cpu_to_be32(0xf0000000);
2392
2393         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2394         /* This function used only for sending on QP1 proxies */
2395         dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2396         /* Use QKEY from the QP context, which is set by master */
2397         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2398 }
2399
2400 static void build_tunnel_header(struct ib_send_wr *wr, void *wqe, unsigned *mlx_seg_len)
2401 {
2402         struct mlx4_wqe_inline_seg *inl = wqe;
2403         struct mlx4_ib_tunnel_header hdr;
2404         struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
2405         int spc;
2406         int i;
2407
2408         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2409         hdr.remote_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
2410         hdr.pkey_index = cpu_to_be16(wr->wr.ud.pkey_index);
2411         hdr.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
2412         memcpy(hdr.mac, ah->av.eth.mac, 6);
2413         hdr.vlan = ah->av.eth.vlan;
2414
2415         spc = MLX4_INLINE_ALIGN -
2416                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2417         if (sizeof (hdr) <= spc) {
2418                 memcpy(inl + 1, &hdr, sizeof (hdr));
2419                 wmb();
2420                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2421                 i = 1;
2422         } else {
2423                 memcpy(inl + 1, &hdr, spc);
2424                 wmb();
2425                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2426
2427                 inl = (void *) (inl + 1) + spc;
2428                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2429                 wmb();
2430                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2431                 i = 2;
2432         }
2433
2434         *mlx_seg_len =
2435                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2436 }
2437
2438 static void set_mlx_icrc_seg(void *dseg)
2439 {
2440         u32 *t = dseg;
2441         struct mlx4_wqe_inline_seg *iseg = dseg;
2442
2443         t[1] = 0;
2444
2445         /*
2446          * Need a barrier here before writing the byte_count field to
2447          * make sure that all the data is visible before the
2448          * byte_count field is set.  Otherwise, if the segment begins
2449          * a new cacheline, the HCA prefetcher could grab the 64-byte
2450          * chunk and get a valid (!= * 0xffffffff) byte count but
2451          * stale data, and end up sending the wrong data.
2452          */
2453         wmb();
2454
2455         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2456 }
2457
2458 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2459 {
2460         dseg->lkey       = cpu_to_be32(sg->lkey);
2461         dseg->addr       = cpu_to_be64(sg->addr);
2462
2463         /*
2464          * Need a barrier here before writing the byte_count field to
2465          * make sure that all the data is visible before the
2466          * byte_count field is set.  Otherwise, if the segment begins
2467          * a new cacheline, the HCA prefetcher could grab the 64-byte
2468          * chunk and get a valid (!= * 0xffffffff) byte count but
2469          * stale data, and end up sending the wrong data.
2470          */
2471         wmb();
2472
2473         dseg->byte_count = cpu_to_be32(sg->length);
2474 }
2475
2476 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2477 {
2478         dseg->byte_count = cpu_to_be32(sg->length);
2479         dseg->lkey       = cpu_to_be32(sg->lkey);
2480         dseg->addr       = cpu_to_be64(sg->addr);
2481 }
2482
2483 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
2484                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2485                          __be32 *lso_hdr_sz, __be32 *blh)
2486 {
2487         unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
2488
2489         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2490                 *blh = cpu_to_be32(1 << 6);
2491
2492         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2493                      wr->num_sge > qp->sq.max_gs - (halign >> 4)))
2494                 return -EINVAL;
2495
2496         memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
2497
2498         *lso_hdr_sz  = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
2499                                    wr->wr.ud.hlen);
2500         *lso_seg_len = halign;
2501         return 0;
2502 }
2503
2504 static __be32 send_ieth(struct ib_send_wr *wr)
2505 {
2506         switch (wr->opcode) {
2507         case IB_WR_SEND_WITH_IMM:
2508         case IB_WR_RDMA_WRITE_WITH_IMM:
2509                 return wr->ex.imm_data;
2510
2511         case IB_WR_SEND_WITH_INV:
2512                 return cpu_to_be32(wr->ex.invalidate_rkey);
2513
2514         default:
2515                 return 0;
2516         }
2517 }
2518
2519 static void add_zero_len_inline(void *wqe)
2520 {
2521         struct mlx4_wqe_inline_seg *inl = wqe;
2522         memset(wqe, 0, 16);
2523         inl->byte_count = cpu_to_be32(1 << 31);
2524 }
2525
2526 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2527                       struct ib_send_wr **bad_wr)
2528 {
2529         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2530         void *wqe;
2531         struct mlx4_wqe_ctrl_seg *ctrl;
2532         struct mlx4_wqe_data_seg *dseg;
2533         unsigned long flags;
2534         int nreq;
2535         int err = 0;
2536         unsigned ind;
2537         int uninitialized_var(stamp);
2538         int uninitialized_var(size);
2539         unsigned uninitialized_var(seglen);
2540         __be32 dummy;
2541         __be32 *lso_wqe;
2542         __be32 uninitialized_var(lso_hdr_sz);
2543         __be32 blh;
2544         int i;
2545
2546         spin_lock_irqsave(&qp->sq.lock, flags);
2547
2548         ind = qp->sq_next_wqe;
2549
2550         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2551                 lso_wqe = &dummy;
2552                 blh = 0;
2553
2554                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2555                         err = -ENOMEM;
2556                         *bad_wr = wr;
2557                         goto out;
2558                 }
2559
2560                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2561                         err = -EINVAL;
2562                         *bad_wr = wr;
2563                         goto out;
2564                 }
2565
2566                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2567                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2568
2569                 ctrl->srcrb_flags =
2570                         (wr->send_flags & IB_SEND_SIGNALED ?
2571                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2572                         (wr->send_flags & IB_SEND_SOLICITED ?
2573                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2574                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2575                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2576                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2577                         qp->sq_signal_bits;
2578
2579                 ctrl->imm = send_ieth(wr);
2580
2581                 wqe += sizeof *ctrl;
2582                 size = sizeof *ctrl / 16;
2583
2584                 switch (qp->mlx4_ib_qp_type) {
2585                 case MLX4_IB_QPT_RC:
2586                 case MLX4_IB_QPT_UC:
2587                         switch (wr->opcode) {
2588                         case IB_WR_ATOMIC_CMP_AND_SWP:
2589                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2590                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2591                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2592                                               wr->wr.atomic.rkey);
2593                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2594
2595                                 set_atomic_seg(wqe, wr);
2596                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2597
2598                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2599                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2600
2601                                 break;
2602
2603                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2604                                 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
2605                                               wr->wr.atomic.rkey);
2606                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2607
2608                                 set_masked_atomic_seg(wqe, wr);
2609                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2610
2611                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2612                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2613
2614                                 break;
2615
2616                         case IB_WR_RDMA_READ:
2617                         case IB_WR_RDMA_WRITE:
2618                         case IB_WR_RDMA_WRITE_WITH_IMM:
2619                                 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
2620                                               wr->wr.rdma.rkey);
2621                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2622                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2623                                 break;
2624
2625                         case IB_WR_LOCAL_INV:
2626                                 ctrl->srcrb_flags |=
2627                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2628                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2629                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2630                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2631                                 break;
2632
2633                         case IB_WR_FAST_REG_MR:
2634                                 ctrl->srcrb_flags |=
2635                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2636                                 set_fmr_seg(wqe, wr);
2637                                 wqe  += sizeof (struct mlx4_wqe_fmr_seg);
2638                                 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
2639                                 break;
2640
2641                         case IB_WR_BIND_MW:
2642                                 ctrl->srcrb_flags |=
2643                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2644                                 set_bind_seg(wqe, wr);
2645                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2646                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2647                                 break;
2648                         default:
2649                                 /* No extra segments required for sends */
2650                                 break;
2651                         }
2652                         break;
2653
2654                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2655                         err =  build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2656                         if (unlikely(err)) {
2657                                 *bad_wr = wr;
2658                                 goto out;
2659                         }
2660                         wqe  += seglen;
2661                         size += seglen / 16;
2662                         break;
2663                 case MLX4_IB_QPT_TUN_SMI:
2664                 case MLX4_IB_QPT_TUN_GSI:
2665                         /* this is a UD qp used in MAD responses to slaves. */
2666                         set_datagram_seg(wqe, wr);
2667                         /* set the forced-loopback bit in the data seg av */
2668                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2669                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2670                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2671                         break;
2672                 case MLX4_IB_QPT_UD:
2673                         set_datagram_seg(wqe, wr);
2674                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2675                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2676
2677                         if (wr->opcode == IB_WR_LSO) {
2678                                 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
2679                                 if (unlikely(err)) {
2680                                         *bad_wr = wr;
2681                                         goto out;
2682                                 }
2683                                 lso_wqe = (__be32 *) wqe;
2684                                 wqe  += seglen;
2685                                 size += seglen / 16;
2686                         }
2687                         break;
2688
2689                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2690                         if (unlikely(!mlx4_is_master(to_mdev(ibqp->device)->dev))) {
2691                                 err = -ENOSYS;
2692                                 *bad_wr = wr;
2693                                 goto out;
2694                         }
2695                         err = build_sriov_qp0_header(to_msqp(qp), wr, ctrl, &seglen);
2696                         if (unlikely(err)) {
2697                                 *bad_wr = wr;
2698                                 goto out;
2699                         }
2700                         wqe  += seglen;
2701                         size += seglen / 16;
2702                         /* to start tunnel header on a cache-line boundary */
2703                         add_zero_len_inline(wqe);
2704                         wqe += 16;
2705                         size++;
2706                         build_tunnel_header(wr, wqe, &seglen);
2707                         wqe  += seglen;
2708                         size += seglen / 16;
2709                         break;
2710                 case MLX4_IB_QPT_PROXY_SMI:
2711                         /* don't allow QP0 sends on guests */
2712                         err = -ENOSYS;
2713                         *bad_wr = wr;
2714                         goto out;
2715                 case MLX4_IB_QPT_PROXY_GSI:
2716                         /* If we are tunneling special qps, this is a UD qp.
2717                          * In this case we first add a UD segment targeting
2718                          * the tunnel qp, and then add a header with address
2719                          * information */
2720                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, wr, ibqp->qp_type);
2721                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2722                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2723                         build_tunnel_header(wr, wqe, &seglen);
2724                         wqe  += seglen;
2725                         size += seglen / 16;
2726                         break;
2727
2728                 case MLX4_IB_QPT_SMI:
2729                 case MLX4_IB_QPT_GSI:
2730                         err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
2731                         if (unlikely(err)) {
2732                                 *bad_wr = wr;
2733                                 goto out;
2734                         }
2735                         wqe  += seglen;
2736                         size += seglen / 16;
2737                         break;
2738
2739                 default:
2740                         break;
2741                 }
2742
2743                 /*
2744                  * Write data segments in reverse order, so as to
2745                  * overwrite cacheline stamp last within each
2746                  * cacheline.  This avoids issues with WQE
2747                  * prefetching.
2748                  */
2749
2750                 dseg = wqe;
2751                 dseg += wr->num_sge - 1;
2752                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2753
2754                 /* Add one more inline data segment for ICRC for MLX sends */
2755                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2756                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2757                              qp->mlx4_ib_qp_type &
2758                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2759                         set_mlx_icrc_seg(dseg + 1);
2760                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2761                 }
2762
2763                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2764                         set_data_seg(dseg, wr->sg_list + i);
2765
2766                 /*
2767                  * Possibly overwrite stamping in cacheline with LSO
2768                  * segment only after making sure all data segments
2769                  * are written.
2770                  */
2771                 wmb();
2772                 *lso_wqe = lso_hdr_sz;
2773
2774                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2775                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2776
2777                 /*
2778                  * Make sure descriptor is fully written before
2779                  * setting ownership bit (because HW can start
2780                  * executing as soon as we do).
2781                  */
2782                 wmb();
2783
2784                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
2785                         *bad_wr = wr;
2786                         err = -EINVAL;
2787                         goto out;
2788                 }
2789
2790                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
2791                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
2792
2793                 stamp = ind + qp->sq_spare_wqes;
2794                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
2795
2796                 /*
2797                  * We can improve latency by not stamping the last
2798                  * send queue WQE until after ringing the doorbell, so
2799                  * only stamp here if there are still more WQEs to post.
2800                  *
2801                  * Same optimization applies to padding with NOP wqe
2802                  * in case of WQE shrinking (used to prevent wrap-around
2803                  * in the middle of WR).
2804                  */
2805                 if (wr->next) {
2806                         stamp_send_wqe(qp, stamp, size * 16);
2807                         ind = pad_wraparound(qp, ind);
2808                 }
2809         }
2810
2811 out:
2812         if (likely(nreq)) {
2813                 qp->sq.head += nreq;
2814
2815                 /*
2816                  * Make sure that descriptors are written before
2817                  * doorbell record.
2818                  */
2819                 wmb();
2820
2821                 writel(qp->doorbell_qpn,
2822                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
2823
2824                 /*
2825                  * Make sure doorbells don't leak out of SQ spinlock
2826                  * and reach the HCA out of order.
2827                  */
2828                 mmiowb();
2829
2830                 stamp_send_wqe(qp, stamp, size * 16);
2831
2832                 ind = pad_wraparound(qp, ind);
2833                 qp->sq_next_wqe = ind;
2834         }
2835
2836         spin_unlock_irqrestore(&qp->sq.lock, flags);
2837
2838         return err;
2839 }
2840
2841 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2842                       struct ib_recv_wr **bad_wr)
2843 {
2844         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2845         struct mlx4_wqe_data_seg *scat;
2846         unsigned long flags;
2847         int err = 0;
2848         int nreq;
2849         int ind;
2850         int max_gs;
2851         int i;
2852
2853         max_gs = qp->rq.max_gs;
2854         spin_lock_irqsave(&qp->rq.lock, flags);
2855
2856         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2857
2858         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2859                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2860                         err = -ENOMEM;
2861                         *bad_wr = wr;
2862                         goto out;
2863                 }
2864
2865                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2866                         err = -EINVAL;
2867                         *bad_wr = wr;
2868                         goto out;
2869                 }
2870
2871                 scat = get_recv_wqe(qp, ind);
2872
2873                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
2874                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
2875                         ib_dma_sync_single_for_device(ibqp->device,
2876                                                       qp->sqp_proxy_rcv[ind].map,
2877                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
2878                                                       DMA_FROM_DEVICE);
2879                         scat->byte_count =
2880                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
2881                         /* use dma lkey from upper layer entry */
2882                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
2883                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
2884                         scat++;
2885                         max_gs--;
2886                 }
2887
2888                 for (i = 0; i < wr->num_sge; ++i)
2889                         __set_data_seg(scat + i, wr->sg_list + i);
2890
2891                 if (i < max_gs) {
2892                         scat[i].byte_count = 0;
2893                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
2894                         scat[i].addr       = 0;
2895                 }
2896
2897                 qp->rq.wrid[ind] = wr->wr_id;
2898
2899                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2900         }
2901
2902 out:
2903         if (likely(nreq)) {
2904                 qp->rq.head += nreq;
2905
2906                 /*
2907                  * Make sure that descriptors are written before
2908                  * doorbell record.
2909                  */
2910                 wmb();
2911
2912                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2913         }
2914
2915         spin_unlock_irqrestore(&qp->rq.lock, flags);
2916
2917         return err;
2918 }
2919
2920 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
2921 {
2922         switch (mlx4_state) {
2923         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
2924         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
2925         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
2926         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
2927         case MLX4_QP_STATE_SQ_DRAINING:
2928         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
2929         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
2930         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
2931         default:                     return -1;
2932         }
2933 }
2934
2935 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
2936 {
2937         switch (mlx4_mig_state) {
2938         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
2939         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
2940         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2941         default: return -1;
2942         }
2943 }
2944
2945 static int to_ib_qp_access_flags(int mlx4_flags)
2946 {
2947         int ib_flags = 0;
2948
2949         if (mlx4_flags & MLX4_QP_BIT_RRE)
2950                 ib_flags |= IB_ACCESS_REMOTE_READ;
2951         if (mlx4_flags & MLX4_QP_BIT_RWE)
2952                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2953         if (mlx4_flags & MLX4_QP_BIT_RAE)
2954                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2955
2956         return ib_flags;
2957 }
2958
2959 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2960                                 struct mlx4_qp_path *path)
2961 {
2962         struct mlx4_dev *dev = ibdev->dev;
2963         int is_eth;
2964
2965         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
2966         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
2967
2968         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2969                 return;
2970
2971         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
2972                 IB_LINK_LAYER_ETHERNET;
2973         if (is_eth)
2974                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
2975                 ((path->sched_queue & 4) << 1);
2976         else
2977                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
2978
2979         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2980         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
2981         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2982         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
2983         if (ib_ah_attr->ah_flags) {
2984                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2985                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2986                 ib_ah_attr->grh.traffic_class =
2987                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2988                 ib_ah_attr->grh.flow_label =
2989                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2990                 memcpy(ib_ah_attr->grh.dgid.raw,
2991                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
2992         }
2993 }
2994
2995 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2996                      struct ib_qp_init_attr *qp_init_attr)
2997 {
2998         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2999         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3000         struct mlx4_qp_context context;
3001         int mlx4_state;
3002         int err = 0;
3003
3004         mutex_lock(&qp->mutex);
3005
3006         if (qp->state == IB_QPS_RESET) {
3007                 qp_attr->qp_state = IB_QPS_RESET;
3008                 goto done;
3009         }
3010
3011         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3012         if (err) {
3013                 err = -EINVAL;
3014                 goto out;
3015         }
3016
3017         mlx4_state = be32_to_cpu(context.flags) >> 28;
3018
3019         qp->state                    = to_ib_qp_state(mlx4_state);
3020         qp_attr->qp_state            = qp->state;
3021         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3022         qp_attr->path_mig_state      =
3023                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3024         qp_attr->qkey                = be32_to_cpu(context.qkey);
3025         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3026         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3027         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3028         qp_attr->qp_access_flags     =
3029                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3030
3031         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3032                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3033                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3034                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3035                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3036         }
3037
3038         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3039         if (qp_attr->qp_state == IB_QPS_INIT)
3040                 qp_attr->port_num = qp->port;
3041         else
3042                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3043
3044         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3045         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3046
3047         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3048
3049         qp_attr->max_dest_rd_atomic =
3050                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3051         qp_attr->min_rnr_timer      =
3052                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3053         qp_attr->timeout            = context.pri_path.ackto >> 3;
3054         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3055         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3056         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3057
3058 done:
3059         qp_attr->cur_qp_state        = qp_attr->qp_state;
3060         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3061         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3062
3063         if (!ibqp->uobject) {
3064                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3065                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3066         } else {
3067                 qp_attr->cap.max_send_wr  = 0;
3068                 qp_attr->cap.max_send_sge = 0;
3069         }
3070
3071         /*
3072          * We don't support inline sends for kernel QPs (yet), and we
3073          * don't know what userspace's value should be.
3074          */
3075         qp_attr->cap.max_inline_data = 0;
3076
3077         qp_init_attr->cap            = qp_attr->cap;
3078
3079         qp_init_attr->create_flags = 0;
3080         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3081                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3082
3083         if (qp->flags & MLX4_IB_QP_LSO)
3084                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3085
3086         if (qp->flags & MLX4_IB_QP_NETIF)
3087                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3088
3089         qp_init_attr->sq_sig_type =
3090                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3091                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3092
3093 out:
3094         mutex_unlock(&qp->mutex);
3095         return err;
3096 }
3097