drivers/infiniband/hw/mlx5/qp.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <rdma/ib_umem.h>
  35 #include "mlx5_ib.h"
  36 #include "user.h"
  37
  38 /* not supported currently */
  39 static int wq_signature;
  40
  41 enum {
  42         MLX5_IB_ACK_REQ_FREQ    = 8,
  43 };
  44
  45 enum {
  46         MLX5_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  47         MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  48         MLX5_IB_LINK_TYPE_IB            = 0,
  49         MLX5_IB_LINK_TYPE_ETH           = 1
  50 };
  51
  52 enum {
  53         MLX5_IB_SQ_STRIDE       = 6,
  54         MLX5_IB_CACHE_LINE_SIZE = 64,
  55 };
  56
  57 static const u32 mlx5_ib_opcode[] = {
  58         [IB_WR_SEND]                            = MLX5_OPCODE_SEND,
  59         [IB_WR_SEND_WITH_IMM]                   = MLX5_OPCODE_SEND_IMM,
  60         [IB_WR_RDMA_WRITE]                      = MLX5_OPCODE_RDMA_WRITE,
  61         [IB_WR_RDMA_WRITE_WITH_IMM]             = MLX5_OPCODE_RDMA_WRITE_IMM,
  62         [IB_WR_RDMA_READ]                       = MLX5_OPCODE_RDMA_READ,
  63         [IB_WR_ATOMIC_CMP_AND_SWP]              = MLX5_OPCODE_ATOMIC_CS,
  64         [IB_WR_ATOMIC_FETCH_AND_ADD]            = MLX5_OPCODE_ATOMIC_FA,
  65         [IB_WR_SEND_WITH_INV]                   = MLX5_OPCODE_SEND_INVAL,
  66         [IB_WR_LOCAL_INV]                       = MLX5_OPCODE_UMR,
  67         [IB_WR_FAST_REG_MR]                     = MLX5_OPCODE_UMR,
  68         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = MLX5_OPCODE_ATOMIC_MASKED_CS,
  69         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = MLX5_OPCODE_ATOMIC_MASKED_FA,
  70         [MLX5_IB_WR_UMR]                        = MLX5_OPCODE_UMR,
  71 };
  72
  73 struct umr_wr {
  74         u64                             virt_addr;
  75         struct ib_pd                   *pd;
  76         unsigned int                    page_shift;
  77         unsigned int                    npages;
  78         u32                             length;
  79         int                             access_flags;
  80         u32                             mkey;
  81 };
  82
  83 static int is_qp0(enum ib_qp_type qp_type)
  84 {
  85         return qp_type == IB_QPT_SMI;
  86 }
  87
  88 static int is_qp1(enum ib_qp_type qp_type)
  89 {
  90         return qp_type == IB_QPT_GSI;
  91 }
  92
  93 static int is_sqp(enum ib_qp_type qp_type)
  94 {
  95         return is_qp0(qp_type) || is_qp1(qp_type);
  96 }
  97
  98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
  99 {
 100         return mlx5_buf_offset(&qp->buf, offset);
 101 }
 102
 103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
 104 {
 105         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 106 }
 107
 108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
 109 {
 110         return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
 111 }
 112
 113 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
 114 {
 115         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 116         struct ib_event event;
 117
 118         if (type == MLX5_EVENT_TYPE_PATH_MIG)
 119                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 120
 121         if (ibqp->event_handler) {
 122                 event.device     = ibqp->device;
 123                 event.element.qp = ibqp;
 124                 switch (type) {
 125                 case MLX5_EVENT_TYPE_PATH_MIG:
 126                         event.event = IB_EVENT_PATH_MIG;
 127                         break;
 128                 case MLX5_EVENT_TYPE_COMM_EST:
 129                         event.event = IB_EVENT_COMM_EST;
 130                         break;
 131                 case MLX5_EVENT_TYPE_SQ_DRAINED:
 132                         event.event = IB_EVENT_SQ_DRAINED;
 133                         break;
 134                 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
 135                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 136                         break;
 137                 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
 138                         event.event = IB_EVENT_QP_FATAL;
 139                         break;
 140                 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
 141                         event.event = IB_EVENT_PATH_MIG_ERR;
 142                         break;
 143                 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 144                         event.event = IB_EVENT_QP_REQ_ERR;
 145                         break;
 146                 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
 147                         event.event = IB_EVENT_QP_ACCESS_ERR;
 148                         break;
 149                 default:
 150                         pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
 151                         return;
 152                 }
 153
 154                 ibqp->event_handler(&event, ibqp->qp_context);
 155         }
 156 }
 157
 158 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
 159                        int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
 160 {
 161         int wqe_size;
 162         int wq_size;
 163
 164         /* Sanity check RQ size before proceeding */
 165         if (cap->max_recv_wr  > dev->mdev.caps.max_wqes)
 166                 return -EINVAL;
 167
 168         if (!has_rq) {
 169                 qp->rq.max_gs = 0;
 170                 qp->rq.wqe_cnt = 0;
 171                 qp->rq.wqe_shift = 0;
 172         } else {
 173                 if (ucmd) {
 174                         qp->rq.wqe_cnt = ucmd->rq_wqe_count;
 175                         qp->rq.wqe_shift = ucmd->rq_wqe_shift;
 176                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 177                         qp->rq.max_post = qp->rq.wqe_cnt;
 178                 } else {
 179                         wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
 180                         wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
 181                         wqe_size = roundup_pow_of_two(wqe_size);
 182                         wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
 183                         wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
 184                         qp->rq.wqe_cnt = wq_size / wqe_size;
 185                         if (wqe_size > dev->mdev.caps.max_rq_desc_sz) {
 186                                 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
 187                                             wqe_size,
 188                                             dev->mdev.caps.max_rq_desc_sz);
 189                                 return -EINVAL;
 190                         }
 191                         qp->rq.wqe_shift = ilog2(wqe_size);
 192                         qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
 193                         qp->rq.max_post = qp->rq.wqe_cnt;
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int sq_overhead(enum ib_qp_type qp_type)
 201 {
 202         int size = 0;
 203
 204         switch (qp_type) {
 205         case IB_QPT_XRC_INI:
 206                 size += sizeof(struct mlx5_wqe_xrc_seg);
 207                 /* fall through */
 208         case IB_QPT_RC:
 209                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 210                         sizeof(struct mlx5_wqe_atomic_seg) +
 211                         sizeof(struct mlx5_wqe_raddr_seg);
 212                 break;
 213
 214         case IB_QPT_XRC_TGT:
 215                 return 0;
 216
 217         case IB_QPT_UC:
 218                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 219                         sizeof(struct mlx5_wqe_raddr_seg) +
 220                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 221                         sizeof(struct mlx5_mkey_seg);
 222                 break;
 223
 224         case IB_QPT_UD:
 225         case IB_QPT_SMI:
 226         case IB_QPT_GSI:
 227                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 228                         sizeof(struct mlx5_wqe_datagram_seg);
 229                 break;
 230
 231         case MLX5_IB_QPT_REG_UMR:
 232                 size += sizeof(struct mlx5_wqe_ctrl_seg) +
 233                         sizeof(struct mlx5_wqe_umr_ctrl_seg) +
 234                         sizeof(struct mlx5_mkey_seg);
 235                 break;
 236
 237         default:
 238                 return -EINVAL;
 239         }
 240
 241         return size;
 242 }
 243
 244 static int calc_send_wqe(struct ib_qp_init_attr *attr)
 245 {
 246         int inl_size = 0;
 247         int size;
 248
 249         size = sq_overhead(attr->qp_type);
 250         if (size < 0)
 251                 return size;
 252
 253         if (attr->cap.max_inline_data) {
 254                 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
 255                         attr->cap.max_inline_data;
 256         }
 257
 258         size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
 259
 260         return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
 261 }
 262
 263 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
 264                         struct mlx5_ib_qp *qp)
 265 {
 266         int wqe_size;
 267         int wq_size;
 268
 269         if (!attr->cap.max_send_wr)
 270                 return 0;
 271
 272         wqe_size = calc_send_wqe(attr);
 273         mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
 274         if (wqe_size < 0)
 275                 return wqe_size;
 276
 277         if (wqe_size > dev->mdev.caps.max_sq_desc_sz) {
 278                 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
 279                             wqe_size, dev->mdev.caps.max_sq_desc_sz);
 280                 return -EINVAL;
 281         }
 282
 283         qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
 284                 sizeof(struct mlx5_wqe_inline_seg);
 285         attr->cap.max_inline_data = qp->max_inline_data;
 286
 287         wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
 288         qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
 289         if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
 290                 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
 291                             qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
 292                 return -ENOMEM;
 293         }
 294         qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
 295         qp->sq.max_gs = attr->cap.max_send_sge;
 296         qp->sq.max_post = wq_size / wqe_size;
 297         attr->cap.max_send_wr = qp->sq.max_post;
 298
 299         return wq_size;
 300 }
 301
 302 static int set_user_buf_size(struct mlx5_ib_dev *dev,
 303                             struct mlx5_ib_qp *qp,
 304                             struct mlx5_ib_create_qp *ucmd)
 305 {
 306         int desc_sz = 1 << qp->sq.wqe_shift;
 307
 308         if (desc_sz > dev->mdev.caps.max_sq_desc_sz) {
 309                 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
 310                              desc_sz, dev->mdev.caps.max_sq_desc_sz);
 311                 return -EINVAL;
 312         }
 313
 314         if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
 315                 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
 316                              ucmd->sq_wqe_count, ucmd->sq_wqe_count);
 317                 return -EINVAL;
 318         }
 319
 320         qp->sq.wqe_cnt = ucmd->sq_wqe_count;
 321
 322         if (qp->sq.wqe_cnt > dev->mdev.caps.max_wqes) {
 323                 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
 324                              qp->sq.wqe_cnt, dev->mdev.caps.max_wqes);
 325                 return -EINVAL;
 326         }
 327
 328         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 329                 (qp->sq.wqe_cnt << 6);
 330
 331         return 0;
 332 }
 333
 334 static int qp_has_rq(struct ib_qp_init_attr *attr)
 335 {
 336         if (attr->qp_type == IB_QPT_XRC_INI ||
 337             attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
 338             attr->qp_type == MLX5_IB_QPT_REG_UMR ||
 339             !attr->cap.max_recv_wr)
 340                 return 0;
 341
 342         return 1;
 343 }
 344
 345 static int first_med_uuar(void)
 346 {
 347         return 1;
 348 }
 349
 350 static int next_uuar(int n)
 351 {
 352         n++;
 353
 354         while (((n % 4) & 2))
 355                 n++;
 356
 357         return n;
 358 }
 359
 360 static int num_med_uuar(struct mlx5_uuar_info *uuari)
 361 {
 362         int n;
 363
 364         n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
 365                 uuari->num_low_latency_uuars - 1;
 366
 367         return n >= 0 ? n : 0;
 368 }
 369
 370 static int max_uuari(struct mlx5_uuar_info *uuari)
 371 {
 372         return uuari->num_uars * 4;
 373 }
 374
 375 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
 376 {
 377         int med;
 378         int i;
 379         int t;
 380
 381         med = num_med_uuar(uuari);
 382         for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
 383                 t++;
 384                 if (t == med)
 385                         return next_uuar(i);
 386         }
 387
 388         return 0;
 389 }
 390
 391 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
 392 {
 393         int i;
 394
 395         for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
 396                 if (!test_bit(i, uuari->bitmap)) {
 397                         set_bit(i, uuari->bitmap);
 398                         uuari->count[i]++;
 399                         return i;
 400                 }
 401         }
 402
 403         return -ENOMEM;
 404 }
 405
 406 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
 407 {
 408         int minidx = first_med_uuar();
 409         int i;
 410
 411         for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
 412                 if (uuari->count[i] < uuari->count[minidx])
 413                         minidx = i;
 414         }
 415
 416         uuari->count[minidx]++;
 417         return minidx;
 418 }
 419
 420 static int alloc_uuar(struct mlx5_uuar_info *uuari,
 421                       enum mlx5_ib_latency_class lat)
 422 {
 423         int uuarn = -EINVAL;
 424
 425         mutex_lock(&uuari->lock);
 426         switch (lat) {
 427         case MLX5_IB_LATENCY_CLASS_LOW:
 428                 uuarn = 0;
 429                 uuari->count[uuarn]++;
 430                 break;
 431
 432         case MLX5_IB_LATENCY_CLASS_MEDIUM:
 433                 uuarn = alloc_med_class_uuar(uuari);
 434                 break;
 435
 436         case MLX5_IB_LATENCY_CLASS_HIGH:
 437                 uuarn = alloc_high_class_uuar(uuari);
 438                 break;
 439
 440         case MLX5_IB_LATENCY_CLASS_FAST_PATH:
 441                 uuarn = 2;
 442                 break;
 443         }
 444         mutex_unlock(&uuari->lock);
 445
 446         return uuarn;
 447 }
 448
 449 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 450 {
 451         clear_bit(uuarn, uuari->bitmap);
 452         --uuari->count[uuarn];
 453 }
 454
 455 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 456 {
 457         clear_bit(uuarn, uuari->bitmap);
 458         --uuari->count[uuarn];
 459 }
 460
 461 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
 462 {
 463         int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
 464         int high_uuar = nuuars - uuari->num_low_latency_uuars;
 465
 466         mutex_lock(&uuari->lock);
 467         if (uuarn == 0) {
 468                 --uuari->count[uuarn];
 469                 goto out;
 470         }
 471
 472         if (uuarn < high_uuar) {
 473                 free_med_class_uuar(uuari, uuarn);
 474                 goto out;
 475         }
 476
 477         free_high_class_uuar(uuari, uuarn);
 478
 479 out:
 480         mutex_unlock(&uuari->lock);
 481 }
 482
 483 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
 484 {
 485         switch (state) {
 486         case IB_QPS_RESET:      return MLX5_QP_STATE_RST;
 487         case IB_QPS_INIT:       return MLX5_QP_STATE_INIT;
 488         case IB_QPS_RTR:        return MLX5_QP_STATE_RTR;
 489         case IB_QPS_RTS:        return MLX5_QP_STATE_RTS;
 490         case IB_QPS_SQD:        return MLX5_QP_STATE_SQD;
 491         case IB_QPS_SQE:        return MLX5_QP_STATE_SQER;
 492         case IB_QPS_ERR:        return MLX5_QP_STATE_ERR;
 493         default:                return -1;
 494         }
 495 }
 496
 497 static int to_mlx5_st(enum ib_qp_type type)
 498 {
 499         switch (type) {
 500         case IB_QPT_RC:                 return MLX5_QP_ST_RC;
 501         case IB_QPT_UC:                 return MLX5_QP_ST_UC;
 502         case IB_QPT_UD:                 return MLX5_QP_ST_UD;
 503         case MLX5_IB_QPT_REG_UMR:       return MLX5_QP_ST_REG_UMR;
 504         case IB_QPT_XRC_INI:
 505         case IB_QPT_XRC_TGT:            return MLX5_QP_ST_XRC;
 506         case IB_QPT_SMI:                return MLX5_QP_ST_QP0;
 507         case IB_QPT_GSI:                return MLX5_QP_ST_QP1;
 508         case IB_QPT_RAW_IPV6:           return MLX5_QP_ST_RAW_IPV6;
 509         case IB_QPT_RAW_ETHERTYPE:      return MLX5_QP_ST_RAW_ETHERTYPE;
 510         case IB_QPT_RAW_PACKET:
 511         case IB_QPT_MAX:
 512         default:                return -EINVAL;
 513         }
 514 }
 515
 516 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
 517 {
 518         return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
 519 }
 520
 521 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 522                           struct mlx5_ib_qp *qp, struct ib_udata *udata,
 523                           struct mlx5_create_qp_mbox_in **in,
 524                           struct mlx5_ib_create_qp_resp *resp, int *inlen)
 525 {
 526         struct mlx5_ib_ucontext *context;
 527         struct mlx5_ib_create_qp ucmd;
 528         int page_shift = 0;
 529         int uar_index;
 530         int npages;
 531         u32 offset = 0;
 532         int uuarn;
 533         int ncont = 0;
 534         int err;
 535
 536         err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
 537         if (err) {
 538                 mlx5_ib_dbg(dev, "copy failed\n");
 539                 return err;
 540         }
 541
 542         context = to_mucontext(pd->uobject->context);
 543         /*
 544          * TBD: should come from the verbs when we have the API
 545          */
 546         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
 547         if (uuarn < 0) {
 548                 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
 549                 mlx5_ib_dbg(dev, "reverting to medium latency\n");
 550                 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
 551                 if (uuarn < 0) {
 552                         mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
 553                         mlx5_ib_dbg(dev, "reverting to high latency\n");
 554                         uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
 555                         if (uuarn < 0) {
 556                                 mlx5_ib_warn(dev, "uuar allocation failed\n");
 557                                 return uuarn;
 558                         }
 559                 }
 560         }
 561
 562         uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
 563         mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
 564
 565         err = set_user_buf_size(dev, qp, &ucmd);
 566         if (err)
 567                 goto err_uuar;
 568
 569         if (ucmd.buf_addr && qp->buf_size) {
 570                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 571                                        qp->buf_size, 0, 0);
 572                 if (IS_ERR(qp->umem)) {
 573                         mlx5_ib_dbg(dev, "umem_get failed\n");
 574                         err = PTR_ERR(qp->umem);
 575                         goto err_uuar;
 576                 }
 577         } else {
 578                 qp->umem = NULL;
 579         }
 580
 581         if (qp->umem) {
 582                 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
 583                                    &ncont, NULL);
 584                 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
 585                 if (err) {
 586                         mlx5_ib_warn(dev, "bad offset\n");
 587                         goto err_umem;
 588                 }
 589                 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
 590                             ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
 591         }
 592
 593         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
 594         *in = mlx5_vzalloc(*inlen);
 595         if (!*in) {
 596                 err = -ENOMEM;
 597                 goto err_umem;
 598         }
 599         if (qp->umem)
 600                 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
 601         (*in)->ctx.log_pg_sz_remote_qpn =
 602                 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 603         (*in)->ctx.params2 = cpu_to_be32(offset << 6);
 604
 605         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 606         resp->uuar_index = uuarn;
 607         qp->uuarn = uuarn;
 608
 609         err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
 610         if (err) {
 611                 mlx5_ib_dbg(dev, "map failed\n");
 612                 goto err_free;
 613         }
 614
 615         err = ib_copy_to_udata(udata, resp, sizeof(*resp));
 616         if (err) {
 617                 mlx5_ib_dbg(dev, "copy failed\n");
 618                 goto err_unmap;
 619         }
 620         qp->create_type = MLX5_QP_USER;
 621
 622         return 0;
 623
 624 err_unmap:
 625         mlx5_ib_db_unmap_user(context, &qp->db);
 626
 627 err_free:
 628         mlx5_vfree(*in);
 629
 630 err_umem:
 631         if (qp->umem)
 632                 ib_umem_release(qp->umem);
 633
 634 err_uuar:
 635         free_uuar(&context->uuari, uuarn);
 636         return err;
 637 }
 638
 639 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
 640 {
 641         struct mlx5_ib_ucontext *context;
 642
 643         context = to_mucontext(pd->uobject->context);
 644         mlx5_ib_db_unmap_user(context, &qp->db);
 645         if (qp->umem)
 646                 ib_umem_release(qp->umem);
 647         free_uuar(&context->uuari, qp->uuarn);
 648 }
 649
 650 static int create_kernel_qp(struct mlx5_ib_dev *dev,
 651                             struct ib_qp_init_attr *init_attr,
 652                             struct mlx5_ib_qp *qp,
 653                             struct mlx5_create_qp_mbox_in **in, int *inlen)
 654 {
 655         enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
 656         struct mlx5_uuar_info *uuari;
 657         int uar_index;
 658         int uuarn;
 659         int err;
 660
 661         uuari = &dev->mdev.priv.uuari;
 662         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 663                 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 664
 665         if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
 666                 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
 667
 668         uuarn = alloc_uuar(uuari, lc);
 669         if (uuarn < 0) {
 670                 mlx5_ib_dbg(dev, "\n");
 671                 return -ENOMEM;
 672         }
 673
 674         qp->bf = &uuari->bfs[uuarn];
 675         uar_index = qp->bf->uar->index;
 676
 677         err = calc_sq_size(dev, init_attr, qp);
 678         if (err < 0) {
 679                 mlx5_ib_dbg(dev, "err %d\n", err);
 680                 goto err_uuar;
 681         }
 682
 683         qp->rq.offset = 0;
 684         qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 685         qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
 686
 687         err = mlx5_buf_alloc(&dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
 688         if (err) {
 689                 mlx5_ib_dbg(dev, "err %d\n", err);
 690                 goto err_uuar;
 691         }
 692
 693         qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
 694         *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
 695         *in = mlx5_vzalloc(*inlen);
 696         if (!*in) {
 697                 err = -ENOMEM;
 698                 goto err_buf;
 699         }
 700         (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
 701         (*in)->ctx.log_pg_sz_remote_qpn =
 702                 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
 703         /* Set "fast registration enabled" for all kernel QPs */
 704         (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
 705         (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
 706
 707         mlx5_fill_page_array(&qp->buf, (*in)->pas);
 708
 709         err = mlx5_db_alloc(&dev->mdev, &qp->db);
 710         if (err) {
 711                 mlx5_ib_dbg(dev, "err %d\n", err);
 712                 goto err_free;
 713         }
 714
 715         qp->db.db[0] = 0;
 716         qp->db.db[1] = 0;
 717
 718         qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
 719         qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
 720         qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
 721         qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
 722         qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
 723
 724         if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
 725             !qp->sq.w_list || !qp->sq.wqe_head) {
 726                 err = -ENOMEM;
 727                 goto err_wrid;
 728         }
 729         qp->create_type = MLX5_QP_KERNEL;
 730
 731         return 0;
 732
 733 err_wrid:
 734         mlx5_db_free(&dev->mdev, &qp->db);
 735         kfree(qp->sq.wqe_head);
 736         kfree(qp->sq.w_list);
 737         kfree(qp->sq.wrid);
 738         kfree(qp->sq.wr_data);
 739         kfree(qp->rq.wrid);
 740
 741 err_free:
 742         mlx5_vfree(*in);
 743
 744 err_buf:
 745         mlx5_buf_free(&dev->mdev, &qp->buf);
 746
 747 err_uuar:
 748         free_uuar(&dev->mdev.priv.uuari, uuarn);
 749         return err;
 750 }
 751
 752 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
 753 {
 754         mlx5_db_free(&dev->mdev, &qp->db);
 755         kfree(qp->sq.wqe_head);
 756         kfree(qp->sq.w_list);
 757         kfree(qp->sq.wrid);
 758         kfree(qp->sq.wr_data);
 759         kfree(qp->rq.wrid);
 760         mlx5_buf_free(&dev->mdev, &qp->buf);
 761         free_uuar(&dev->mdev.priv.uuari, qp->bf->uuarn);
 762 }
 763
 764 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
 765 {
 766         if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
 767             (attr->qp_type == IB_QPT_XRC_INI))
 768                 return cpu_to_be32(MLX5_SRQ_RQ);
 769         else if (!qp->has_rq)
 770                 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
 771         else
 772                 return cpu_to_be32(MLX5_NON_ZERO_RQ);
 773 }
 774
 775 static int is_connected(enum ib_qp_type qp_type)
 776 {
 777         if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
 778                 return 1;
 779
 780         return 0;
 781 }
 782
 783 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
 784                             struct ib_qp_init_attr *init_attr,
 785                             struct ib_udata *udata, struct mlx5_ib_qp *qp)
 786 {
 787         struct mlx5_ib_resources *devr = &dev->devr;
 788         struct mlx5_ib_create_qp_resp resp;
 789         struct mlx5_create_qp_mbox_in *in;
 790         struct mlx5_ib_create_qp ucmd;
 791         int inlen = sizeof(*in);
 792         int err;
 793
 794         mutex_init(&qp->mutex);
 795         spin_lock_init(&qp->sq.lock);
 796         spin_lock_init(&qp->rq.lock);
 797
 798         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 799                 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
 800
 801         if (pd && pd->uobject) {
 802                 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
 803                         mlx5_ib_dbg(dev, "copy failed\n");
 804                         return -EFAULT;
 805                 }
 806
 807                 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
 808                 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
 809         } else {
 810                 qp->wq_sig = !!wq_signature;
 811         }
 812
 813         qp->has_rq = qp_has_rq(init_attr);
 814         err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
 815                           qp, (pd && pd->uobject) ? &ucmd : NULL);
 816         if (err) {
 817                 mlx5_ib_dbg(dev, "err %d\n", err);
 818                 return err;
 819         }
 820
 821         if (pd) {
 822                 if (pd->uobject) {
 823                         mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
 824                         if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
 825                             ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
 826                                 mlx5_ib_dbg(dev, "invalid rq params\n");
 827                                 return -EINVAL;
 828                         }
 829                         if (ucmd.sq_wqe_count > dev->mdev.caps.max_wqes) {
 830                                 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
 831                                             ucmd.sq_wqe_count, dev->mdev.caps.max_wqes);
 832                                 return -EINVAL;
 833                         }
 834                         err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
 835                         if (err)
 836                                 mlx5_ib_dbg(dev, "err %d\n", err);
 837                 } else {
 838                         err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
 839                         if (err)
 840                                 mlx5_ib_dbg(dev, "err %d\n", err);
 841                         else
 842                                 qp->pa_lkey = to_mpd(pd)->pa_lkey;
 843                 }
 844
 845                 if (err)
 846                         return err;
 847         } else {
 848                 in = mlx5_vzalloc(sizeof(*in));
 849                 if (!in)
 850                         return -ENOMEM;
 851
 852                 qp->create_type = MLX5_QP_EMPTY;
 853         }
 854
 855         if (is_sqp(init_attr->qp_type))
 856                 qp->port = init_attr->port_num;
 857
 858         in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
 859                                     MLX5_QP_PM_MIGRATED << 11);
 860
 861         if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
 862                 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
 863         else
 864                 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
 865
 866         if (qp->wq_sig)
 867                 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
 868
 869         if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
 870                 int rcqe_sz;
 871                 int scqe_sz;
 872
 873                 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
 874                 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
 875
 876                 if (rcqe_sz == 128)
 877                         in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
 878                 else
 879                         in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
 880
 881                 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
 882                         if (scqe_sz == 128)
 883                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
 884                         else
 885                                 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
 886                 }
 887         }
 888
 889         if (qp->rq.wqe_cnt) {
 890                 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
 891                 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
 892         }
 893
 894         in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
 895
 896         if (qp->sq.wqe_cnt)
 897                 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
 898         else
 899                 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
 900
 901         /* Set default resources */
 902         switch (init_attr->qp_type) {
 903         case IB_QPT_XRC_TGT:
 904                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 905                 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 906                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 907                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
 908                 break;
 909         case IB_QPT_XRC_INI:
 910                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
 911                 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
 912                 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 913                 break;
 914         default:
 915                 if (init_attr->srq) {
 916                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
 917                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
 918                 } else {
 919                         in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
 920                         in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
 921                 }
 922         }
 923
 924         if (init_attr->send_cq)
 925                 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
 926
 927         if (init_attr->recv_cq)
 928                 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
 929
 930         in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
 931
 932         err = mlx5_core_create_qp(&dev->mdev, &qp->mqp, in, inlen);
 933         if (err) {
 934                 mlx5_ib_dbg(dev, "create qp failed\n");
 935                 goto err_create;
 936         }
 937
 938         mlx5_vfree(in);
 939         /* Hardware wants QPN written in big-endian order (after
 940          * shifting) for send doorbell.  Precompute this value to save
 941          * a little bit when posting sends.
 942          */
 943         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 944
 945         qp->mqp.event = mlx5_ib_qp_event;
 946
 947         return 0;
 948
 949 err_create:
 950         if (qp->create_type == MLX5_QP_USER)
 951                 destroy_qp_user(pd, qp);
 952         else if (qp->create_type == MLX5_QP_KERNEL)
 953                 destroy_qp_kernel(dev, qp);
 954
 955         mlx5_vfree(in);
 956         return err;
 957 }
 958
 959 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
 960         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 961 {
 962         if (send_cq) {
 963                 if (recv_cq) {
 964                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
 965                                 spin_lock_irq(&send_cq->lock);
 966                                 spin_lock_nested(&recv_cq->lock,
 967                                                  SINGLE_DEPTH_NESTING);
 968                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
 969                                 spin_lock_irq(&send_cq->lock);
 970                                 __acquire(&recv_cq->lock);
 971                         } else {
 972                                 spin_lock_irq(&recv_cq->lock);
 973                                 spin_lock_nested(&send_cq->lock,
 974                                                  SINGLE_DEPTH_NESTING);
 975                         }
 976                 } else {
 977                         spin_lock_irq(&send_cq->lock);
 978                 }
 979         } else if (recv_cq) {
 980                 spin_lock_irq(&recv_cq->lock);
 981         }
 982 }
 983
 984 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
 985         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 986 {
 987         if (send_cq) {
 988                 if (recv_cq) {
 989                         if (send_cq->mcq.cqn < recv_cq->mcq.cqn)  {
 990                                 spin_unlock(&recv_cq->lock);
 991                                 spin_unlock_irq(&send_cq->lock);
 992                         } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
 993                                 __release(&recv_cq->lock);
 994                                 spin_unlock_irq(&send_cq->lock);
 995                         } else {
 996                                 spin_unlock(&send_cq->lock);
 997                                 spin_unlock_irq(&recv_cq->lock);
 998                         }
 999                 } else {
1000                         spin_unlock_irq(&send_cq->lock);
1001                 }
1002         } else if (recv_cq) {
1003                 spin_unlock_irq(&recv_cq->lock);
1004         }
1005 }
1006
1007 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1008 {
1009         return to_mpd(qp->ibqp.pd);
1010 }
1011
1012 static void get_cqs(struct mlx5_ib_qp *qp,
1013                     struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1014 {
1015         switch (qp->ibqp.qp_type) {
1016         case IB_QPT_XRC_TGT:
1017                 *send_cq = NULL;
1018                 *recv_cq = NULL;
1019                 break;
1020         case MLX5_IB_QPT_REG_UMR:
1021         case IB_QPT_XRC_INI:
1022                 *send_cq = to_mcq(qp->ibqp.send_cq);
1023                 *recv_cq = NULL;
1024                 break;
1025
1026         case IB_QPT_SMI:
1027         case IB_QPT_GSI:
1028         case IB_QPT_RC:
1029         case IB_QPT_UC:
1030         case IB_QPT_UD:
1031         case IB_QPT_RAW_IPV6:
1032         case IB_QPT_RAW_ETHERTYPE:
1033                 *send_cq = to_mcq(qp->ibqp.send_cq);
1034                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1035                 break;
1036
1037         case IB_QPT_RAW_PACKET:
1038         case IB_QPT_MAX:
1039         default:
1040                 *send_cq = NULL;
1041                 *recv_cq = NULL;
1042                 break;
1043         }
1044 }
1045
1046 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1047 {
1048         struct mlx5_ib_cq *send_cq, *recv_cq;
1049         struct mlx5_modify_qp_mbox_in *in;
1050         int err;
1051
1052         in = kzalloc(sizeof(*in), GFP_KERNEL);
1053         if (!in)
1054                 return;
1055         if (qp->state != IB_QPS_RESET)
1056                 if (mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(qp->state),
1057                                         MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1058                         mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1059                                      qp->mqp.qpn);
1060
1061         get_cqs(qp, &send_cq, &recv_cq);
1062
1063         if (qp->create_type == MLX5_QP_KERNEL) {
1064                 mlx5_ib_lock_cqs(send_cq, recv_cq);
1065                 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1066                                    qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1067                 if (send_cq != recv_cq)
1068                         __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1069                 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1070         }
1071
1072         err = mlx5_core_destroy_qp(&dev->mdev, &qp->mqp);
1073         if (err)
1074                 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1075         kfree(in);
1076
1077
1078         if (qp->create_type == MLX5_QP_KERNEL)
1079                 destroy_qp_kernel(dev, qp);
1080         else if (qp->create_type == MLX5_QP_USER)
1081                 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1082 }
1083
1084 static const char *ib_qp_type_str(enum ib_qp_type type)
1085 {
1086         switch (type) {
1087         case IB_QPT_SMI:
1088                 return "IB_QPT_SMI";
1089         case IB_QPT_GSI:
1090                 return "IB_QPT_GSI";
1091         case IB_QPT_RC:
1092                 return "IB_QPT_RC";
1093         case IB_QPT_UC:
1094                 return "IB_QPT_UC";
1095         case IB_QPT_UD:
1096                 return "IB_QPT_UD";
1097         case IB_QPT_RAW_IPV6:
1098                 return "IB_QPT_RAW_IPV6";
1099         case IB_QPT_RAW_ETHERTYPE:
1100                 return "IB_QPT_RAW_ETHERTYPE";
1101         case IB_QPT_XRC_INI:
1102                 return "IB_QPT_XRC_INI";
1103         case IB_QPT_XRC_TGT:
1104                 return "IB_QPT_XRC_TGT";
1105         case IB_QPT_RAW_PACKET:
1106                 return "IB_QPT_RAW_PACKET";
1107         case MLX5_IB_QPT_REG_UMR:
1108                 return "MLX5_IB_QPT_REG_UMR";
1109         case IB_QPT_MAX:
1110         default:
1111                 return "Invalid QP type";
1112         }
1113 }
1114
1115 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1116                                 struct ib_qp_init_attr *init_attr,
1117                                 struct ib_udata *udata)
1118 {
1119         struct mlx5_ib_dev *dev;
1120         struct mlx5_ib_qp *qp;
1121         u16 xrcdn = 0;
1122         int err;
1123
1124         if (pd) {
1125                 dev = to_mdev(pd->device);
1126         } else {
1127                 /* being cautious here */
1128                 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1129                     init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1130                         pr_warn("%s: no PD for transport %s\n", __func__,
1131                                 ib_qp_type_str(init_attr->qp_type));
1132                         return ERR_PTR(-EINVAL);
1133                 }
1134                 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1135         }
1136
1137         switch (init_attr->qp_type) {
1138         case IB_QPT_XRC_TGT:
1139         case IB_QPT_XRC_INI:
1140                 if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC)) {
1141                         mlx5_ib_dbg(dev, "XRC not supported\n");
1142                         return ERR_PTR(-ENOSYS);
1143                 }
1144                 init_attr->recv_cq = NULL;
1145                 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1146                         xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1147                         init_attr->send_cq = NULL;
1148                 }
1149
1150                 /* fall through */
1151         case IB_QPT_RC:
1152         case IB_QPT_UC:
1153         case IB_QPT_UD:
1154         case IB_QPT_SMI:
1155         case IB_QPT_GSI:
1156         case MLX5_IB_QPT_REG_UMR:
1157                 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1158                 if (!qp)
1159                         return ERR_PTR(-ENOMEM);
1160
1161                 err = create_qp_common(dev, pd, init_attr, udata, qp);
1162                 if (err) {
1163                         mlx5_ib_dbg(dev, "create_qp_common failed\n");
1164                         kfree(qp);
1165                         return ERR_PTR(err);
1166                 }
1167
1168                 if (is_qp0(init_attr->qp_type))
1169                         qp->ibqp.qp_num = 0;
1170                 else if (is_qp1(init_attr->qp_type))
1171                         qp->ibqp.qp_num = 1;
1172                 else
1173                         qp->ibqp.qp_num = qp->mqp.qpn;
1174
1175                 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1176                             qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1177                             to_mcq(init_attr->send_cq)->mcq.cqn);
1178
1179                 qp->xrcdn = xrcdn;
1180
1181                 break;
1182
1183         case IB_QPT_RAW_IPV6:
1184         case IB_QPT_RAW_ETHERTYPE:
1185         case IB_QPT_RAW_PACKET:
1186         case IB_QPT_MAX:
1187         default:
1188                 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1189                             init_attr->qp_type);
1190                 /* Don't support raw QPs */
1191                 return ERR_PTR(-EINVAL);
1192         }
1193
1194         return &qp->ibqp;
1195 }
1196
1197 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1198 {
1199         struct mlx5_ib_dev *dev = to_mdev(qp->device);
1200         struct mlx5_ib_qp *mqp = to_mqp(qp);
1201
1202         destroy_qp_common(dev, mqp);
1203
1204         kfree(mqp);
1205
1206         return 0;
1207 }
1208
1209 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1210                                    int attr_mask)
1211 {
1212         u32 hw_access_flags = 0;
1213         u8 dest_rd_atomic;
1214         u32 access_flags;
1215
1216         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1217                 dest_rd_atomic = attr->max_dest_rd_atomic;
1218         else
1219                 dest_rd_atomic = qp->resp_depth;
1220
1221         if (attr_mask & IB_QP_ACCESS_FLAGS)
1222                 access_flags = attr->qp_access_flags;
1223         else
1224                 access_flags = qp->atomic_rd_en;
1225
1226         if (!dest_rd_atomic)
1227                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1228
1229         if (access_flags & IB_ACCESS_REMOTE_READ)
1230                 hw_access_flags |= MLX5_QP_BIT_RRE;
1231         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1232                 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1233         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1234                 hw_access_flags |= MLX5_QP_BIT_RWE;
1235
1236         return cpu_to_be32(hw_access_flags);
1237 }
1238
1239 enum {
1240         MLX5_PATH_FLAG_FL       = 1 << 0,
1241         MLX5_PATH_FLAG_FREE_AR  = 1 << 1,
1242         MLX5_PATH_FLAG_COUNTER  = 1 << 2,
1243 };
1244
1245 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1246 {
1247         if (rate == IB_RATE_PORT_CURRENT) {
1248                 return 0;
1249         } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1250                 return -EINVAL;
1251         } else {
1252                 while (rate != IB_RATE_2_5_GBPS &&
1253                        !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1254                          dev->mdev.caps.stat_rate_support))
1255                         --rate;
1256         }
1257
1258         return rate + MLX5_STAT_RATE_OFFSET;
1259 }
1260
1261 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1262                          struct mlx5_qp_path *path, u8 port, int attr_mask,
1263                          u32 path_flags, const struct ib_qp_attr *attr)
1264 {
1265         int err;
1266
1267         path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1268         path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1269
1270         if (attr_mask & IB_QP_PKEY_INDEX)
1271                 path->pkey_index = attr->pkey_index;
1272
1273         path->grh_mlid  = ah->src_path_bits & 0x7f;
1274         path->rlid      = cpu_to_be16(ah->dlid);
1275
1276         if (ah->ah_flags & IB_AH_GRH) {
1277                 path->grh_mlid |= 1 << 7;
1278                 path->mgid_index = ah->grh.sgid_index;
1279                 path->hop_limit  = ah->grh.hop_limit;
1280                 path->tclass_flowlabel =
1281                         cpu_to_be32((ah->grh.traffic_class << 20) |
1282                                     (ah->grh.flow_label));
1283                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1284         }
1285
1286         err = ib_rate_to_mlx5(dev, ah->static_rate);
1287         if (err < 0)
1288                 return err;
1289         path->static_rate = err;
1290         path->port = port;
1291
1292         if (ah->ah_flags & IB_AH_GRH) {
1293                 if (ah->grh.sgid_index >= dev->mdev.caps.port[port - 1].gid_table_len) {
1294                         pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1295                                ah->grh.sgid_index, dev->mdev.caps.port[port - 1].gid_table_len);
1296                         return -EINVAL;
1297                 }
1298
1299                 path->grh_mlid |= 1 << 7;
1300                 path->mgid_index = ah->grh.sgid_index;
1301                 path->hop_limit  = ah->grh.hop_limit;
1302                 path->tclass_flowlabel =
1303                         cpu_to_be32((ah->grh.traffic_class << 20) |
1304                                     (ah->grh.flow_label));
1305                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1306         }
1307
1308         if (attr_mask & IB_QP_TIMEOUT)
1309                 path->ackto_lt = attr->timeout << 3;
1310
1311         path->sl = ah->sl & 0xf;
1312
1313         return 0;
1314 }
1315
1316 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1317         [MLX5_QP_STATE_INIT] = {
1318                 [MLX5_QP_STATE_INIT] = {
1319                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1320                                           MLX5_QP_OPTPAR_RAE            |
1321                                           MLX5_QP_OPTPAR_RWE            |
1322                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1323                                           MLX5_QP_OPTPAR_PRI_PORT,
1324                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1325                                           MLX5_QP_OPTPAR_PKEY_INDEX     |
1326                                           MLX5_QP_OPTPAR_PRI_PORT,
1327                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1328                                           MLX5_QP_OPTPAR_Q_KEY          |
1329                                           MLX5_QP_OPTPAR_PRI_PORT,
1330                 },
1331                 [MLX5_QP_STATE_RTR] = {
1332                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1333                                           MLX5_QP_OPTPAR_RRE            |
1334                                           MLX5_QP_OPTPAR_RAE            |
1335                                           MLX5_QP_OPTPAR_RWE            |
1336                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1337                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1338                                           MLX5_QP_OPTPAR_RWE            |
1339                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1340                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX     |
1341                                           MLX5_QP_OPTPAR_Q_KEY,
1342                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX    |
1343                                            MLX5_QP_OPTPAR_Q_KEY,
1344                         [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1345                                           MLX5_QP_OPTPAR_RRE            |
1346                                           MLX5_QP_OPTPAR_RAE            |
1347                                           MLX5_QP_OPTPAR_RWE            |
1348                                           MLX5_QP_OPTPAR_PKEY_INDEX,
1349                 },
1350         },
1351         [MLX5_QP_STATE_RTR] = {
1352                 [MLX5_QP_STATE_RTS] = {
1353                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1354                                           MLX5_QP_OPTPAR_RRE            |
1355                                           MLX5_QP_OPTPAR_RAE            |
1356                                           MLX5_QP_OPTPAR_RWE            |
1357                                           MLX5_QP_OPTPAR_PM_STATE       |
1358                                           MLX5_QP_OPTPAR_RNR_TIMEOUT,
1359                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH  |
1360                                           MLX5_QP_OPTPAR_RWE            |
1361                                           MLX5_QP_OPTPAR_PM_STATE,
1362                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1363                 },
1364         },
1365         [MLX5_QP_STATE_RTS] = {
1366                 [MLX5_QP_STATE_RTS] = {
1367                         [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE            |
1368                                           MLX5_QP_OPTPAR_RAE            |
1369                                           MLX5_QP_OPTPAR_RWE            |
1370                                           MLX5_QP_OPTPAR_RNR_TIMEOUT    |
1371                                           MLX5_QP_OPTPAR_PM_STATE       |
1372                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1373                         [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE            |
1374                                           MLX5_QP_OPTPAR_PM_STATE       |
1375                                           MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1376                         [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY          |
1377                                           MLX5_QP_OPTPAR_SRQN           |
1378                                           MLX5_QP_OPTPAR_CQN_RCV,
1379                 },
1380         },
1381         [MLX5_QP_STATE_SQER] = {
1382                 [MLX5_QP_STATE_RTS] = {
1383                         [MLX5_QP_ST_UD]  = MLX5_QP_OPTPAR_Q_KEY,
1384                         [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1385                         [MLX5_QP_ST_UC]  = MLX5_QP_OPTPAR_RWE,
1386                         [MLX5_QP_ST_RC]  = MLX5_QP_OPTPAR_RNR_TIMEOUT   |
1387                                            MLX5_QP_OPTPAR_RWE           |
1388                                            MLX5_QP_OPTPAR_RAE           |
1389                                            MLX5_QP_OPTPAR_RRE,
1390                 },
1391         },
1392 };
1393
1394 static int ib_nr_to_mlx5_nr(int ib_mask)
1395 {
1396         switch (ib_mask) {
1397         case IB_QP_STATE:
1398                 return 0;
1399         case IB_QP_CUR_STATE:
1400                 return 0;
1401         case IB_QP_EN_SQD_ASYNC_NOTIFY:
1402                 return 0;
1403         case IB_QP_ACCESS_FLAGS:
1404                 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1405                         MLX5_QP_OPTPAR_RAE;
1406         case IB_QP_PKEY_INDEX:
1407                 return MLX5_QP_OPTPAR_PKEY_INDEX;
1408         case IB_QP_PORT:
1409                 return MLX5_QP_OPTPAR_PRI_PORT;
1410         case IB_QP_QKEY:
1411                 return MLX5_QP_OPTPAR_Q_KEY;
1412         case IB_QP_AV:
1413                 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1414                         MLX5_QP_OPTPAR_PRI_PORT;
1415         case IB_QP_PATH_MTU:
1416                 return 0;
1417         case IB_QP_TIMEOUT:
1418                 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1419         case IB_QP_RETRY_CNT:
1420                 return MLX5_QP_OPTPAR_RETRY_COUNT;
1421         case IB_QP_RNR_RETRY:
1422                 return MLX5_QP_OPTPAR_RNR_RETRY;
1423         case IB_QP_RQ_PSN:
1424                 return 0;
1425         case IB_QP_MAX_QP_RD_ATOMIC:
1426                 return MLX5_QP_OPTPAR_SRA_MAX;
1427         case IB_QP_ALT_PATH:
1428                 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1429         case IB_QP_MIN_RNR_TIMER:
1430                 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1431         case IB_QP_SQ_PSN:
1432                 return 0;
1433         case IB_QP_MAX_DEST_RD_ATOMIC:
1434                 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1435                         MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1436         case IB_QP_PATH_MIG_STATE:
1437                 return MLX5_QP_OPTPAR_PM_STATE;
1438         case IB_QP_CAP:
1439                 return 0;
1440         case IB_QP_DEST_QPN:
1441                 return 0;
1442         }
1443         return 0;
1444 }
1445
1446 static int ib_mask_to_mlx5_opt(int ib_mask)
1447 {
1448         int result = 0;
1449         int i;
1450
1451         for (i = 0; i < 8 * sizeof(int); i++) {
1452                 if ((1 << i) & ib_mask)
1453                         result |= ib_nr_to_mlx5_nr(1 << i);
1454         }
1455
1456         return result;
1457 }
1458
1459 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1460                                const struct ib_qp_attr *attr, int attr_mask,
1461                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1462 {
1463         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1464         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1465         struct mlx5_ib_cq *send_cq, *recv_cq;
1466         struct mlx5_qp_context *context;
1467         struct mlx5_modify_qp_mbox_in *in;
1468         struct mlx5_ib_pd *pd;
1469         enum mlx5_qp_state mlx5_cur, mlx5_new;
1470         enum mlx5_qp_optpar optpar;
1471         int sqd_event;
1472         int mlx5_st;
1473         int err;
1474
1475         in = kzalloc(sizeof(*in), GFP_KERNEL);
1476         if (!in)
1477                 return -ENOMEM;
1478
1479         context = &in->ctx;
1480         err = to_mlx5_st(ibqp->qp_type);
1481         if (err < 0)
1482                 goto out;
1483
1484         context->flags = cpu_to_be32(err << 16);
1485
1486         if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1487                 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1488         } else {
1489                 switch (attr->path_mig_state) {
1490                 case IB_MIG_MIGRATED:
1491                         context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1492                         break;
1493                 case IB_MIG_REARM:
1494                         context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1495                         break;
1496                 case IB_MIG_ARMED:
1497                         context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1498                         break;
1499                 }
1500         }
1501
1502         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1503                 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1504         } else if (ibqp->qp_type == IB_QPT_UD ||
1505                    ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1506                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1507         } else if (attr_mask & IB_QP_PATH_MTU) {
1508                 if (attr->path_mtu < IB_MTU_256 ||
1509                     attr->path_mtu > IB_MTU_4096) {
1510                         mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1511                         err = -EINVAL;
1512                         goto out;
1513                 }
1514                 context->mtu_msgmax = (attr->path_mtu << 5) | dev->mdev.caps.log_max_msg;
1515         }
1516
1517         if (attr_mask & IB_QP_DEST_QPN)
1518                 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1519
1520         if (attr_mask & IB_QP_PKEY_INDEX)
1521                 context->pri_path.pkey_index = attr->pkey_index;
1522
1523         /* todo implement counter_index functionality */
1524
1525         if (is_sqp(ibqp->qp_type))
1526                 context->pri_path.port = qp->port;
1527
1528         if (attr_mask & IB_QP_PORT)
1529                 context->pri_path.port = attr->port_num;
1530
1531         if (attr_mask & IB_QP_AV) {
1532                 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1533                                     attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1534                                     attr_mask, 0, attr);
1535                 if (err)
1536                         goto out;
1537         }
1538
1539         if (attr_mask & IB_QP_TIMEOUT)
1540                 context->pri_path.ackto_lt |= attr->timeout << 3;
1541
1542         if (attr_mask & IB_QP_ALT_PATH) {
1543                 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1544                                     attr->alt_port_num, attr_mask, 0, attr);
1545                 if (err)
1546                         goto out;
1547         }
1548
1549         pd = get_pd(qp);
1550         get_cqs(qp, &send_cq, &recv_cq);
1551
1552         context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1553         context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1554         context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1555         context->params1  = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1556
1557         if (attr_mask & IB_QP_RNR_RETRY)
1558                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1559
1560         if (attr_mask & IB_QP_RETRY_CNT)
1561                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1562
1563         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1564                 if (attr->max_rd_atomic)
1565                         context->params1 |=
1566                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1567         }
1568
1569         if (attr_mask & IB_QP_SQ_PSN)
1570                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1571
1572         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1573                 if (attr->max_dest_rd_atomic)
1574                         context->params2 |=
1575                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1576         }
1577
1578         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1579                 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1580
1581         if (attr_mask & IB_QP_MIN_RNR_TIMER)
1582                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1583
1584         if (attr_mask & IB_QP_RQ_PSN)
1585                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1586
1587         if (attr_mask & IB_QP_QKEY)
1588                 context->qkey = cpu_to_be32(attr->qkey);
1589
1590         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1591                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1592
1593         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1594             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1595                 sqd_event = 1;
1596         else
1597                 sqd_event = 0;
1598
1599         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1600                 context->sq_crq_size |= cpu_to_be16(1 << 4);
1601
1602
1603         mlx5_cur = to_mlx5_state(cur_state);
1604         mlx5_new = to_mlx5_state(new_state);
1605         mlx5_st = to_mlx5_st(ibqp->qp_type);
1606         if (mlx5_st < 0)
1607                 goto out;
1608
1609         optpar = ib_mask_to_mlx5_opt(attr_mask);
1610         optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1611         in->optparam = cpu_to_be32(optpar);
1612         err = mlx5_core_qp_modify(&dev->mdev, to_mlx5_state(cur_state),
1613                                   to_mlx5_state(new_state), in, sqd_event,
1614                                   &qp->mqp);
1615         if (err)
1616                 goto out;
1617
1618         qp->state = new_state;
1619
1620         if (attr_mask & IB_QP_ACCESS_FLAGS)
1621                 qp->atomic_rd_en = attr->qp_access_flags;
1622         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1623                 qp->resp_depth = attr->max_dest_rd_atomic;
1624         if (attr_mask & IB_QP_PORT)
1625                 qp->port = attr->port_num;
1626         if (attr_mask & IB_QP_ALT_PATH)
1627                 qp->alt_port = attr->alt_port_num;
1628
1629         /*
1630          * If we moved a kernel QP to RESET, clean up all old CQ
1631          * entries and reinitialize the QP.
1632          */
1633         if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1634                 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1635                                  ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1636                 if (send_cq != recv_cq)
1637                         mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1638
1639                 qp->rq.head = 0;
1640                 qp->rq.tail = 0;
1641                 qp->sq.head = 0;
1642                 qp->sq.tail = 0;
1643                 qp->sq.cur_post = 0;
1644                 qp->sq.last_poll = 0;
1645                 qp->db.db[MLX5_RCV_DBR] = 0;
1646                 qp->db.db[MLX5_SND_DBR] = 0;
1647         }
1648
1649 out:
1650         kfree(in);
1651         return err;
1652 }
1653
1654 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1655                       int attr_mask, struct ib_udata *udata)
1656 {
1657         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1658         struct mlx5_ib_qp *qp = to_mqp(ibqp);
1659         enum ib_qp_state cur_state, new_state;
1660         int err = -EINVAL;
1661         int port;
1662
1663         mutex_lock(&qp->mutex);
1664
1665         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1666         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1667
1668         if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1669             !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1670                                 IB_LINK_LAYER_UNSPECIFIED))
1671                 goto out;
1672
1673         if ((attr_mask & IB_QP_PORT) &&
1674             (attr->port_num == 0 || attr->port_num > dev->mdev.caps.num_ports))
1675                 goto out;
1676
1677         if (attr_mask & IB_QP_PKEY_INDEX) {
1678                 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1679                 if (attr->pkey_index >= dev->mdev.caps.port[port - 1].pkey_table_len)
1680                         goto out;
1681         }
1682
1683         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1684             attr->max_rd_atomic > dev->mdev.caps.max_ra_res_qp)
1685                 goto out;
1686
1687         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1688             attr->max_dest_rd_atomic > dev->mdev.caps.max_ra_req_qp)
1689                 goto out;
1690
1691         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1692                 err = 0;
1693                 goto out;
1694         }
1695
1696         err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1697
1698 out:
1699         mutex_unlock(&qp->mutex);
1700         return err;
1701 }
1702
1703 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1704 {
1705         struct mlx5_ib_cq *cq;
1706         unsigned cur;
1707
1708         cur = wq->head - wq->tail;
1709         if (likely(cur + nreq < wq->max_post))
1710                 return 0;
1711
1712         cq = to_mcq(ib_cq);
1713         spin_lock(&cq->lock);
1714         cur = wq->head - wq->tail;
1715         spin_unlock(&cq->lock);
1716
1717         return cur + nreq >= wq->max_post;
1718 }
1719
1720 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1721                                           u64 remote_addr, u32 rkey)
1722 {
1723         rseg->raddr    = cpu_to_be64(remote_addr);
1724         rseg->rkey     = cpu_to_be32(rkey);
1725         rseg->reserved = 0;
1726 }
1727
1728 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1729                              struct ib_send_wr *wr)
1730 {
1731         memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1732         dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1733         dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1734 }
1735
1736 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1737 {
1738         dseg->byte_count = cpu_to_be32(sg->length);
1739         dseg->lkey       = cpu_to_be32(sg->lkey);
1740         dseg->addr       = cpu_to_be64(sg->addr);
1741 }
1742
1743 static __be16 get_klm_octo(int npages)
1744 {
1745         return cpu_to_be16(ALIGN(npages, 8) / 2);
1746 }
1747
1748 static __be64 frwr_mkey_mask(void)
1749 {
1750         u64 result;
1751
1752         result = MLX5_MKEY_MASK_LEN             |
1753                 MLX5_MKEY_MASK_PAGE_SIZE        |
1754                 MLX5_MKEY_MASK_START_ADDR       |
1755                 MLX5_MKEY_MASK_EN_RINVAL        |
1756                 MLX5_MKEY_MASK_KEY              |
1757                 MLX5_MKEY_MASK_LR               |
1758                 MLX5_MKEY_MASK_LW               |
1759                 MLX5_MKEY_MASK_RR               |
1760                 MLX5_MKEY_MASK_RW               |
1761                 MLX5_MKEY_MASK_A                |
1762                 MLX5_MKEY_MASK_SMALL_FENCE      |
1763                 MLX5_MKEY_MASK_FREE;
1764
1765         return cpu_to_be64(result);
1766 }
1767
1768 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1769                                  struct ib_send_wr *wr, int li)
1770 {
1771         memset(umr, 0, sizeof(*umr));
1772
1773         if (li) {
1774                 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1775                 umr->flags = 1 << 7;
1776                 return;
1777         }
1778
1779         umr->flags = (1 << 5); /* fail if not free */
1780         umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1781         umr->mkey_mask = frwr_mkey_mask();
1782 }
1783
1784 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1785                                 struct ib_send_wr *wr)
1786 {
1787         struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1788         u64 mask;
1789
1790         memset(umr, 0, sizeof(*umr));
1791
1792         if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1793                 umr->flags = 1 << 5; /* fail if not free */
1794                 umr->klm_octowords = get_klm_octo(umrwr->npages);
1795                 mask =  MLX5_MKEY_MASK_LEN              |
1796                         MLX5_MKEY_MASK_PAGE_SIZE        |
1797                         MLX5_MKEY_MASK_START_ADDR       |
1798                         MLX5_MKEY_MASK_PD               |
1799                         MLX5_MKEY_MASK_LR               |
1800                         MLX5_MKEY_MASK_LW               |
1801                         MLX5_MKEY_MASK_KEY              |
1802                         MLX5_MKEY_MASK_RR               |
1803                         MLX5_MKEY_MASK_RW               |
1804                         MLX5_MKEY_MASK_A                |
1805                         MLX5_MKEY_MASK_FREE;
1806                 umr->mkey_mask = cpu_to_be64(mask);
1807         } else {
1808                 umr->flags = 2 << 5; /* fail if free */
1809                 mask = MLX5_MKEY_MASK_FREE;
1810                 umr->mkey_mask = cpu_to_be64(mask);
1811         }
1812
1813         if (!wr->num_sge)
1814                 umr->flags |= (1 << 7); /* inline */
1815 }
1816
1817 static u8 get_umr_flags(int acc)
1818 {
1819         return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC       : 0) |
1820                (acc & IB_ACCESS_REMOTE_WRITE  ? MLX5_PERM_REMOTE_WRITE : 0) |
1821                (acc & IB_ACCESS_REMOTE_READ   ? MLX5_PERM_REMOTE_READ  : 0) |
1822                (acc & IB_ACCESS_LOCAL_WRITE   ? MLX5_PERM_LOCAL_WRITE  : 0) |
1823                 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
1824 }
1825
1826 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1827                              int li, int *writ)
1828 {
1829         memset(seg, 0, sizeof(*seg));
1830         if (li) {
1831                 seg->status = 1 << 6;
1832                 return;
1833         }
1834
1835         seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags);
1836         *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1837         seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1838         seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1839         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1840         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1841         seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1842         seg->log2_page_size = wr->wr.fast_reg.page_shift;
1843 }
1844
1845 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1846 {
1847         memset(seg, 0, sizeof(*seg));
1848         if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1849                 seg->status = 1 << 6;
1850                 return;
1851         }
1852
1853         seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1854         seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1855         seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1856         seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1857         seg->log2_page_size = wr->wr.fast_reg.page_shift;
1858         seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
1859                                        mlx5_mkey_variant(wr->wr.fast_reg.rkey));
1860 }
1861
1862 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1863                            struct ib_send_wr *wr,
1864                            struct mlx5_core_dev *mdev,
1865                            struct mlx5_ib_pd *pd,
1866                            int writ)
1867 {
1868         struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1869         u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1870         u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1871         int i;
1872
1873         for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1874                 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1875         dseg->addr = cpu_to_be64(mfrpl->map);
1876         dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1877         dseg->lkey = cpu_to_be32(pd->pa_lkey);
1878 }
1879
1880 static __be32 send_ieth(struct ib_send_wr *wr)
1881 {
1882         switch (wr->opcode) {
1883         case IB_WR_SEND_WITH_IMM:
1884         case IB_WR_RDMA_WRITE_WITH_IMM:
1885                 return wr->ex.imm_data;
1886
1887         case IB_WR_SEND_WITH_INV:
1888                 return cpu_to_be32(wr->ex.invalidate_rkey);
1889
1890         default:
1891                 return 0;
1892         }
1893 }
1894
1895 static u8 calc_sig(void *wqe, int size)
1896 {
1897         u8 *p = wqe;
1898         u8 res = 0;
1899         int i;
1900
1901         for (i = 0; i < size; i++)
1902                 res ^= p[i];
1903
1904         return ~res;
1905 }
1906
1907 static u8 wq_sig(void *wqe)
1908 {
1909         return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1910 }
1911
1912 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1913                             void *wqe, int *sz)
1914 {
1915         struct mlx5_wqe_inline_seg *seg;
1916         void *qend = qp->sq.qend;
1917         void *addr;
1918         int inl = 0;
1919         int copy;
1920         int len;
1921         int i;
1922
1923         seg = wqe;
1924         wqe += sizeof(*seg);
1925         for (i = 0; i < wr->num_sge; i++) {
1926                 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1927                 len  = wr->sg_list[i].length;
1928                 inl += len;
1929
1930                 if (unlikely(inl > qp->max_inline_data))
1931                         return -ENOMEM;
1932
1933                 if (unlikely(wqe + len > qend)) {
1934                         copy = qend - wqe;
1935                         memcpy(wqe, addr, copy);
1936                         addr += copy;
1937                         len -= copy;
1938                         wqe = mlx5_get_send_wqe(qp, 0);
1939                 }
1940                 memcpy(wqe, addr, len);
1941                 wqe += len;
1942         }
1943
1944         seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
1945
1946         *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
1947
1948         return 0;
1949 }
1950
1951 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
1952                           struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
1953 {
1954         int writ = 0;
1955         int li;
1956
1957         li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
1958         if (unlikely(wr->send_flags & IB_SEND_INLINE))
1959                 return -EINVAL;
1960
1961         set_frwr_umr_segment(*seg, wr, li);
1962         *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
1963         *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
1964         if (unlikely((*seg == qp->sq.qend)))
1965                 *seg = mlx5_get_send_wqe(qp, 0);
1966         set_mkey_segment(*seg, wr, li, &writ);
1967         *seg += sizeof(struct mlx5_mkey_seg);
1968         *size += sizeof(struct mlx5_mkey_seg) / 16;
1969         if (unlikely((*seg == qp->sq.qend)))
1970                 *seg = mlx5_get_send_wqe(qp, 0);
1971         if (!li) {
1972                 if (unlikely(wr->wr.fast_reg.page_list_len >
1973                              wr->wr.fast_reg.page_list->max_page_list_len))
1974                         return  -ENOMEM;
1975
1976                 set_frwr_pages(*seg, wr, mdev, pd, writ);
1977                 *seg += sizeof(struct mlx5_wqe_data_seg);
1978                 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
1979         }
1980         return 0;
1981 }
1982
1983 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
1984 {
1985         __be32 *p = NULL;
1986         int tidx = idx;
1987         int i, j;
1988
1989         pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
1990         for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
1991                 if ((i & 0xf) == 0) {
1992                         void *buf = mlx5_get_send_wqe(qp, tidx);
1993                         tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
1994                         p = buf;
1995                         j = 0;
1996                 }
1997                 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
1998                          be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
1999                          be32_to_cpu(p[j + 3]));
2000         }
2001 }
2002
2003 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2004                          unsigned bytecnt, struct mlx5_ib_qp *qp)
2005 {
2006         while (bytecnt > 0) {
2007                 __iowrite64_copy(dst++, src++, 8);
2008                 __iowrite64_copy(dst++, src++, 8);
2009                 __iowrite64_copy(dst++, src++, 8);
2010                 __iowrite64_copy(dst++, src++, 8);
2011                 __iowrite64_copy(dst++, src++, 8);
2012                 __iowrite64_copy(dst++, src++, 8);
2013                 __iowrite64_copy(dst++, src++, 8);
2014                 __iowrite64_copy(dst++, src++, 8);
2015                 bytecnt -= 64;
2016                 if (unlikely(src == qp->sq.qend))
2017                         src = mlx5_get_send_wqe(qp, 0);
2018         }
2019 }
2020
2021 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2022 {
2023         if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2024                      wr->send_flags & IB_SEND_FENCE))
2025                 return MLX5_FENCE_MODE_STRONG_ORDERING;
2026
2027         if (unlikely(fence)) {
2028                 if (wr->send_flags & IB_SEND_FENCE)
2029                         return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2030                 else
2031                         return fence;
2032
2033         } else {
2034                 return 0;
2035         }
2036 }
2037
2038 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2039                       struct ib_send_wr **bad_wr)
2040 {
2041         struct mlx5_wqe_ctrl_seg *ctrl = NULL;  /* compiler warning */
2042         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2043         struct mlx5_core_dev *mdev = &dev->mdev;
2044         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2045         struct mlx5_wqe_data_seg *dpseg;
2046         struct mlx5_wqe_xrc_seg *xrc;
2047         struct mlx5_bf *bf = qp->bf;
2048         int uninitialized_var(size);
2049         void *qend = qp->sq.qend;
2050         unsigned long flags;
2051         u32 mlx5_opcode;
2052         unsigned idx;
2053         int err = 0;
2054         int inl = 0;
2055         int num_sge;
2056         void *seg;
2057         int nreq;
2058         int i;
2059         u8 next_fence = 0;
2060         u8 opmod = 0;
2061         u8 fence;
2062
2063         spin_lock_irqsave(&qp->sq.lock, flags);
2064
2065         for (nreq = 0; wr; nreq++, wr = wr->next) {
2066                 if (unlikely(wr->opcode >= sizeof(mlx5_ib_opcode) / sizeof(mlx5_ib_opcode[0]))) {
2067                         mlx5_ib_warn(dev, "\n");
2068                         err = -EINVAL;
2069                         *bad_wr = wr;
2070                         goto out;
2071                 }
2072
2073                 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2074                         mlx5_ib_warn(dev, "\n");
2075                         err = -ENOMEM;
2076                         *bad_wr = wr;
2077                         goto out;
2078                 }
2079
2080                 fence = qp->fm_cache;
2081                 num_sge = wr->num_sge;
2082                 if (unlikely(num_sge > qp->sq.max_gs)) {
2083                         mlx5_ib_warn(dev, "\n");
2084                         err = -ENOMEM;
2085                         *bad_wr = wr;
2086                         goto out;
2087                 }
2088
2089                 idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2090                 seg = mlx5_get_send_wqe(qp, idx);
2091                 ctrl = seg;
2092                 *(uint32_t *)(seg + 8) = 0;
2093                 ctrl->imm = send_ieth(wr);
2094                 ctrl->fm_ce_se = qp->sq_signal_bits |
2095                         (wr->send_flags & IB_SEND_SIGNALED ?
2096                          MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2097                         (wr->send_flags & IB_SEND_SOLICITED ?
2098                          MLX5_WQE_CTRL_SOLICITED : 0);
2099
2100                 seg += sizeof(*ctrl);
2101                 size = sizeof(*ctrl) / 16;
2102
2103                 switch (ibqp->qp_type) {
2104                 case IB_QPT_XRC_INI:
2105                         xrc = seg;
2106                         xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2107                         seg += sizeof(*xrc);
2108                         size += sizeof(*xrc) / 16;
2109                         /* fall through */
2110                 case IB_QPT_RC:
2111                         switch (wr->opcode) {
2112                         case IB_WR_RDMA_READ:
2113                         case IB_WR_RDMA_WRITE:
2114                         case IB_WR_RDMA_WRITE_WITH_IMM:
2115                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2116                                               wr->wr.rdma.rkey);
2117                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2118                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2119                                 break;
2120
2121                         case IB_WR_ATOMIC_CMP_AND_SWP:
2122                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2123                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2124                                 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2125                                 err = -ENOSYS;
2126                                 *bad_wr = wr;
2127                                 goto out;
2128
2129                         case IB_WR_LOCAL_INV:
2130                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2131                                 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2132                                 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2133                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2134                                 if (err) {
2135                                         mlx5_ib_warn(dev, "\n");
2136                                         *bad_wr = wr;
2137                                         goto out;
2138                                 }
2139                                 num_sge = 0;
2140                                 break;
2141
2142                         case IB_WR_FAST_REG_MR:
2143                                 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2144                                 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2145                                 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2146                                 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2147                                 if (err) {
2148                                         mlx5_ib_warn(dev, "\n");
2149                                         *bad_wr = wr;
2150                                         goto out;
2151                                 }
2152                                 num_sge = 0;
2153                                 break;
2154
2155                         default:
2156                                 break;
2157                         }
2158                         break;
2159
2160                 case IB_QPT_UC:
2161                         switch (wr->opcode) {
2162                         case IB_WR_RDMA_WRITE:
2163                         case IB_WR_RDMA_WRITE_WITH_IMM:
2164                                 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2165                                               wr->wr.rdma.rkey);
2166                                 seg  += sizeof(struct mlx5_wqe_raddr_seg);
2167                                 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2168                                 break;
2169
2170                         default:
2171                                 break;
2172                         }
2173                         break;
2174
2175                 case IB_QPT_UD:
2176                 case IB_QPT_SMI:
2177                 case IB_QPT_GSI:
2178                         set_datagram_seg(seg, wr);
2179                         seg  += sizeof(struct mlx5_wqe_datagram_seg);
2180                         size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2181                         if (unlikely((seg == qend)))
2182                                 seg = mlx5_get_send_wqe(qp, 0);
2183                         break;
2184
2185                 case MLX5_IB_QPT_REG_UMR:
2186                         if (wr->opcode != MLX5_IB_WR_UMR) {
2187                                 err = -EINVAL;
2188                                 mlx5_ib_warn(dev, "bad opcode\n");
2189                                 goto out;
2190                         }
2191                         qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2192                         ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2193                         set_reg_umr_segment(seg, wr);
2194                         seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2195                         size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2196                         if (unlikely((seg == qend)))
2197                                 seg = mlx5_get_send_wqe(qp, 0);
2198                         set_reg_mkey_segment(seg, wr);
2199                         seg += sizeof(struct mlx5_mkey_seg);
2200                         size += sizeof(struct mlx5_mkey_seg) / 16;
2201                         if (unlikely((seg == qend)))
2202                                 seg = mlx5_get_send_wqe(qp, 0);
2203                         break;
2204
2205                 default:
2206                         break;
2207                 }
2208
2209                 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2210                         int uninitialized_var(sz);
2211
2212                         err = set_data_inl_seg(qp, wr, seg, &sz);
2213                         if (unlikely(err)) {
2214                                 mlx5_ib_warn(dev, "\n");
2215                                 *bad_wr = wr;
2216                                 goto out;
2217                         }
2218                         inl = 1;
2219                         size += sz;
2220                 } else {
2221                         dpseg = seg;
2222                         for (i = 0; i < num_sge; i++) {
2223                                 if (unlikely(dpseg == qend)) {
2224                                         seg = mlx5_get_send_wqe(qp, 0);
2225                                         dpseg = seg;
2226                                 }
2227                                 if (likely(wr->sg_list[i].length)) {
2228                                         set_data_ptr_seg(dpseg, wr->sg_list + i);
2229                                         size += sizeof(struct mlx5_wqe_data_seg) / 16;
2230                                         dpseg++;
2231                                 }
2232                         }
2233                 }
2234
2235                 mlx5_opcode = mlx5_ib_opcode[wr->opcode];
2236                 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8)      |
2237                                                      mlx5_opcode                        |
2238                                                      ((u32)opmod << 24));
2239                 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2240                 ctrl->fm_ce_se |= get_fence(fence, wr);
2241                 qp->fm_cache = next_fence;
2242                 if (unlikely(qp->wq_sig))
2243                         ctrl->signature = wq_sig(ctrl);
2244
2245                 qp->sq.wrid[idx] = wr->wr_id;
2246                 qp->sq.w_list[idx].opcode = mlx5_opcode;
2247                 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2248                 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2249                 qp->sq.w_list[idx].next = qp->sq.cur_post;
2250
2251                 if (0)
2252                         dump_wqe(qp, idx, size);
2253         }
2254
2255 out:
2256         if (likely(nreq)) {
2257                 qp->sq.head += nreq;
2258
2259                 /* Make sure that descriptors are written before
2260                  * updating doorbell record and ringing the doorbell
2261                  */
2262                 wmb();
2263
2264                 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2265
2266                 /* Make sure doorbell record is visible to the HCA before
2267                  * we hit doorbell */
2268                 wmb();
2269
2270                 if (bf->need_lock)
2271                         spin_lock(&bf->lock);
2272
2273                 /* TBD enable WC */
2274                 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2275                         mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2276                         /* wc_wmb(); */
2277                 } else {
2278                         mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2279                                      MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2280                         /* Make sure doorbells don't leak out of SQ spinlock
2281                          * and reach the HCA out of order.
2282                          */
2283                         mmiowb();
2284                 }
2285                 bf->offset ^= bf->buf_size;
2286                 if (bf->need_lock)
2287                         spin_unlock(&bf->lock);
2288         }
2289
2290         spin_unlock_irqrestore(&qp->sq.lock, flags);
2291
2292         return err;
2293 }
2294
2295 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2296 {
2297         sig->signature = calc_sig(sig, size);
2298 }
2299
2300 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2301                       struct ib_recv_wr **bad_wr)
2302 {
2303         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2304         struct mlx5_wqe_data_seg *scat;
2305         struct mlx5_rwqe_sig *sig;
2306         unsigned long flags;
2307         int err = 0;
2308         int nreq;
2309         int ind;
2310         int i;
2311
2312         spin_lock_irqsave(&qp->rq.lock, flags);
2313
2314         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2315
2316         for (nreq = 0; wr; nreq++, wr = wr->next) {
2317                 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2318                         err = -ENOMEM;
2319                         *bad_wr = wr;
2320                         goto out;
2321                 }
2322
2323                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2324                         err = -EINVAL;
2325                         *bad_wr = wr;
2326                         goto out;
2327                 }
2328
2329                 scat = get_recv_wqe(qp, ind);
2330                 if (qp->wq_sig)
2331                         scat++;
2332
2333                 for (i = 0; i < wr->num_sge; i++)
2334                         set_data_ptr_seg(scat + i, wr->sg_list + i);
2335
2336                 if (i < qp->rq.max_gs) {
2337                         scat[i].byte_count = 0;
2338                         scat[i].lkey       = cpu_to_be32(MLX5_INVALID_LKEY);
2339                         scat[i].addr       = 0;
2340                 }
2341
2342                 if (qp->wq_sig) {
2343                         sig = (struct mlx5_rwqe_sig *)scat;
2344                         set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2345                 }
2346
2347                 qp->rq.wrid[ind] = wr->wr_id;
2348
2349                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2350         }
2351
2352 out:
2353         if (likely(nreq)) {
2354                 qp->rq.head += nreq;
2355
2356                 /* Make sure that descriptors are written before
2357                  * doorbell record.
2358                  */
2359                 wmb();
2360
2361                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2362         }
2363
2364         spin_unlock_irqrestore(&qp->rq.lock, flags);
2365
2366         return err;
2367 }
2368
2369 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2370 {
2371         switch (mlx5_state) {
2372         case MLX5_QP_STATE_RST:      return IB_QPS_RESET;
2373         case MLX5_QP_STATE_INIT:     return IB_QPS_INIT;
2374         case MLX5_QP_STATE_RTR:      return IB_QPS_RTR;
2375         case MLX5_QP_STATE_RTS:      return IB_QPS_RTS;
2376         case MLX5_QP_STATE_SQ_DRAINING:
2377         case MLX5_QP_STATE_SQD:      return IB_QPS_SQD;
2378         case MLX5_QP_STATE_SQER:     return IB_QPS_SQE;
2379         case MLX5_QP_STATE_ERR:      return IB_QPS_ERR;
2380         default:                     return -1;
2381         }
2382 }
2383
2384 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2385 {
2386         switch (mlx5_mig_state) {
2387         case MLX5_QP_PM_ARMED:          return IB_MIG_ARMED;
2388         case MLX5_QP_PM_REARM:          return IB_MIG_REARM;
2389         case MLX5_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
2390         default: return -1;
2391         }
2392 }
2393
2394 static int to_ib_qp_access_flags(int mlx5_flags)
2395 {
2396         int ib_flags = 0;
2397
2398         if (mlx5_flags & MLX5_QP_BIT_RRE)
2399                 ib_flags |= IB_ACCESS_REMOTE_READ;
2400         if (mlx5_flags & MLX5_QP_BIT_RWE)
2401                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2402         if (mlx5_flags & MLX5_QP_BIT_RAE)
2403                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2404
2405         return ib_flags;
2406 }
2407
2408 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2409                                 struct mlx5_qp_path *path)
2410 {
2411         struct mlx5_core_dev *dev = &ibdev->mdev;
2412
2413         memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2414         ib_ah_attr->port_num      = path->port;
2415
2416         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
2417                 return;
2418
2419         ib_ah_attr->sl = path->sl & 0xf;
2420
2421         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
2422         ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2423         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
2424         ib_ah_attr->ah_flags      = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2425         if (ib_ah_attr->ah_flags) {
2426                 ib_ah_attr->grh.sgid_index = path->mgid_index;
2427                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
2428                 ib_ah_attr->grh.traffic_class =
2429                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2430                 ib_ah_attr->grh.flow_label =
2431                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2432                 memcpy(ib_ah_attr->grh.dgid.raw,
2433                        path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2434         }
2435 }
2436
2437 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2438                      struct ib_qp_init_attr *qp_init_attr)
2439 {
2440         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2441         struct mlx5_ib_qp *qp = to_mqp(ibqp);
2442         struct mlx5_query_qp_mbox_out *outb;
2443         struct mlx5_qp_context *context;
2444         int mlx5_state;
2445         int err = 0;
2446
2447         mutex_lock(&qp->mutex);
2448         outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2449         if (!outb) {
2450                 err = -ENOMEM;
2451                 goto out;
2452         }
2453         context = &outb->ctx;
2454         err = mlx5_core_qp_query(&dev->mdev, &qp->mqp, outb, sizeof(*outb));
2455         if (err)
2456                 goto out_free;
2457
2458         mlx5_state = be32_to_cpu(context->flags) >> 28;
2459
2460         qp->state                    = to_ib_qp_state(mlx5_state);
2461         qp_attr->qp_state            = qp->state;
2462         qp_attr->path_mtu            = context->mtu_msgmax >> 5;
2463         qp_attr->path_mig_state      =
2464                 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2465         qp_attr->qkey                = be32_to_cpu(context->qkey);
2466         qp_attr->rq_psn              = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2467         qp_attr->sq_psn              = be32_to_cpu(context->next_send_psn) & 0xffffff;
2468         qp_attr->dest_qp_num         = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2469         qp_attr->qp_access_flags     =
2470                 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2471
2472         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2473                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2474                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2475                 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2476                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
2477         }
2478
2479         qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2480         qp_attr->port_num = context->pri_path.port;
2481
2482         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2483         qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2484
2485         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2486
2487         qp_attr->max_dest_rd_atomic =
2488                 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2489         qp_attr->min_rnr_timer      =
2490                 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2491         qp_attr->timeout            = context->pri_path.ackto_lt >> 3;
2492         qp_attr->retry_cnt          = (be32_to_cpu(context->params1) >> 16) & 0x7;
2493         qp_attr->rnr_retry          = (be32_to_cpu(context->params1) >> 13) & 0x7;
2494         qp_attr->alt_timeout        = context->alt_path.ackto_lt >> 3;
2495         qp_attr->cur_qp_state        = qp_attr->qp_state;
2496         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
2497         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
2498
2499         if (!ibqp->uobject) {
2500                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
2501                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
2502         } else {
2503                 qp_attr->cap.max_send_wr  = 0;
2504                 qp_attr->cap.max_send_sge = 0;
2505         }
2506
2507         /* We don't support inline sends for kernel QPs (yet), and we
2508          * don't know what userspace's value should be.
2509          */
2510         qp_attr->cap.max_inline_data = 0;
2511
2512         qp_init_attr->cap            = qp_attr->cap;
2513
2514         qp_init_attr->create_flags = 0;
2515         if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
2516                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
2517
2518         qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
2519                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
2520
2521 out_free:
2522         kfree(outb);
2523
2524 out:
2525         mutex_unlock(&qp->mutex);
2526         return err;
2527 }
2528
2529 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
2530                                           struct ib_ucontext *context,
2531                                           struct ib_udata *udata)
2532 {
2533         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2534         struct mlx5_ib_xrcd *xrcd;
2535         int err;
2536
2537         if (!(dev->mdev.caps.flags & MLX5_DEV_CAP_FLAG_XRC))
2538                 return ERR_PTR(-ENOSYS);
2539
2540         xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
2541         if (!xrcd)
2542                 return ERR_PTR(-ENOMEM);
2543
2544         err = mlx5_core_xrcd_alloc(&dev->mdev, &xrcd->xrcdn);
2545         if (err) {
2546                 kfree(xrcd);
2547                 return ERR_PTR(-ENOMEM);
2548         }
2549
2550         return &xrcd->ibxrcd;
2551 }
2552
2553 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
2554 {
2555         struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
2556         u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
2557         int err;
2558
2559         err = mlx5_core_xrcd_dealloc(&dev->mdev, xrcdn);
2560         if (err) {
2561                 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
2562                 return err;
2563         }
2564
2565         kfree(xrcd);
2566
2567         return 0;
2568 }