2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef MLX5_IB_USER_H
34 #define MLX5_IB_USER_H
36 #include <linux/types.h>
41 MLX5_QP_FLAG_SIGNATURE = 1 << 0,
42 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
46 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
50 MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
54 /* Increment this value if any changes that break userspace ABI
55 * compatibility are made.
57 #define MLX5_IB_UVERBS_ABI_VERSION 1
59 /* Make sure that all structs defined in this file remain laid out so
60 * that they pack the same way on 32-bit and 64-bit architectures (to
61 * avoid incompatibility between 32-bit userspace and 64-bit kernels).
62 * In particular do not use pointer types -- pass pointers in __u64
66 struct mlx5_ib_alloc_ucontext_req {
67 __u32 total_num_uuars;
68 __u32 num_low_latency_uuars;
71 struct mlx5_ib_alloc_ucontext_req_v2 {
72 __u32 total_num_uuars;
73 __u32 num_low_latency_uuars;
82 enum mlx5_ib_alloc_ucontext_resp_mask {
83 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
86 enum mlx5_user_cmds_supp_uhw {
87 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
90 struct mlx5_ib_alloc_ucontext_resp {
94 __u32 cache_line_size;
99 __u32 max_srq_recv_wr;
103 __u32 response_length;
107 __u64 hca_core_clock_offset;
110 struct mlx5_ib_alloc_pd_resp {
114 struct mlx5_ib_tso_caps {
115 __u32 max_tso; /* Maximum tso payload size in bytes */
117 /* Corresponding bit will be set if qp type from
118 * 'enum ib_qp_type' is supported, e.g.
119 * supported_qpts |= 1 << IB_QPT_UD
121 __u32 supported_qpts;
124 struct mlx5_ib_rss_caps {
125 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
126 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
130 struct mlx5_ib_query_device_resp {
132 __u32 response_length;
133 struct mlx5_ib_tso_caps tso_caps;
134 struct mlx5_ib_rss_caps rss_caps;
137 struct mlx5_ib_create_cq {
141 __u32 reserved; /* explicit padding (optional on i386) */
144 struct mlx5_ib_create_cq_resp {
149 struct mlx5_ib_resize_cq {
156 struct mlx5_ib_create_srq {
160 __u32 reserved0; /* explicit padding (optional on i386) */
165 struct mlx5_ib_create_srq_resp {
170 struct mlx5_ib_create_qp {
182 /* RX Hash function flags */
183 enum mlx5_rx_hash_function_flags {
184 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
188 * RX Hash flags, these flags allows to set which incoming packet's field should
189 * participates in RX Hash. Each flag represent certain packet's field,
190 * when the flag is set the field that is represented by the flag will
191 * participate in RX Hash calculation.
192 * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
193 * and *TCP and *UDP flags can't be enabled together on the same QP.
195 enum mlx5_rx_hash_fields {
196 MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
197 MLX5_RX_HASH_DST_IPV4 = 1 << 1,
198 MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
199 MLX5_RX_HASH_DST_IPV6 = 1 << 3,
200 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
201 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
202 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
203 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7
206 struct mlx5_ib_create_qp_rss {
207 __u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
208 __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
209 __u8 rx_key_len; /* valid only for Toeplitz */
211 __u8 rx_hash_key[128]; /* valid only for Toeplitz */
216 struct mlx5_ib_create_qp_resp {
220 struct mlx5_ib_alloc_mw {
227 struct mlx5_ib_create_wq {
238 struct mlx5_ib_create_wq_resp {
239 __u32 response_length;
243 struct mlx5_ib_create_rwq_ind_tbl_resp {
244 __u32 response_length;
248 struct mlx5_ib_modify_wq {
253 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
254 struct mlx5_ib_create_qp *ucmd,
258 u8 cqe_version = ucontext->cqe_version;
260 if (field_avail(struct mlx5_ib_create_qp, uidx, inlen) &&
261 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
264 if (!!(field_avail(struct mlx5_ib_create_qp, uidx, inlen) !=
268 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
271 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
272 struct mlx5_ib_create_srq *ucmd,
276 u8 cqe_version = ucontext->cqe_version;
278 if (field_avail(struct mlx5_ib_create_srq, uidx, inlen) &&
279 !cqe_version && (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
282 if (!!(field_avail(struct mlx5_ib_create_srq, uidx, inlen) !=
286 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
288 #endif /* MLX5_IB_USER_H */