drivers/infiniband/hw/ocrdma/ocrdma_hw.c

   1 /*******************************************************************
   2  * This file is part of the Emulex RoCE Device Driver for          *
   3  * RoCE (RDMA over Converged Ethernet) CNA Adapters.              *
   4  * Copyright (C) 2008-2012 Emulex. All rights reserved.            *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *
  20  * Contact Information:
  21  * linux-drivers@emulex.com
  22  *
  23  * Emulex
  24  * 3333 Susan Street
  25  * Costa Mesa, CA 92626
  26  *******************************************************************/
  27
  28 #include <linux/sched.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/log2.h>
  31 #include <linux/dma-mapping.h>
  32
  33 #include <rdma/ib_verbs.h>
  34 #include <rdma/ib_user_verbs.h>
  35 #include <rdma/ib_addr.h>
  36
  37 #include "ocrdma.h"
  38 #include "ocrdma_hw.h"
  39 #include "ocrdma_verbs.h"
  40 #include "ocrdma_ah.h"
  41
  42 enum mbx_status {
  43         OCRDMA_MBX_STATUS_FAILED                = 1,
  44         OCRDMA_MBX_STATUS_ILLEGAL_FIELD         = 3,
  45         OCRDMA_MBX_STATUS_OOR                   = 100,
  46         OCRDMA_MBX_STATUS_INVALID_PD            = 101,
  47         OCRDMA_MBX_STATUS_PD_INUSE              = 102,
  48         OCRDMA_MBX_STATUS_INVALID_CQ            = 103,
  49         OCRDMA_MBX_STATUS_INVALID_QP            = 104,
  50         OCRDMA_MBX_STATUS_INVALID_LKEY          = 105,
  51         OCRDMA_MBX_STATUS_ORD_EXCEEDS           = 106,
  52         OCRDMA_MBX_STATUS_IRD_EXCEEDS           = 107,
  53         OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS     = 108,
  54         OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS     = 109,
  55         OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS      = 110,
  56         OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS     = 111,
  57         OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS      = 112,
  58         OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE  = 113,
  59         OCRDMA_MBX_STATUS_MW_BOUND              = 114,
  60         OCRDMA_MBX_STATUS_INVALID_VA            = 115,
  61         OCRDMA_MBX_STATUS_INVALID_LENGTH        = 116,
  62         OCRDMA_MBX_STATUS_INVALID_FBO           = 117,
  63         OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS    = 118,
  64         OCRDMA_MBX_STATUS_INVALID_PBE_SIZE      = 119,
  65         OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY     = 120,
  66         OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT     = 121,
  67         OCRDMA_MBX_STATUS_INVALID_SRQ_ID        = 129,
  68         OCRDMA_MBX_STATUS_SRQ_ERROR             = 133,
  69         OCRDMA_MBX_STATUS_RQE_EXCEEDS           = 134,
  70         OCRDMA_MBX_STATUS_MTU_EXCEEDS           = 135,
  71         OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS        = 136,
  72         OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS     = 137,
  73         OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS     = 138,
  74         OCRDMA_MBX_STATUS_QP_BOUND              = 130,
  75         OCRDMA_MBX_STATUS_INVALID_CHANGE        = 139,
  76         OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP      = 140,
  77         OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
  78         OCRDMA_MBX_STATUS_MW_STILL_BOUND        = 142,
  79         OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID    = 143,
  80         OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS    = 144
  81 };
  82
  83 enum additional_status {
  84         OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
  85 };
  86
  87 enum cqe_status {
  88         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES  = 1,
  89         OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER         = 2,
  90         OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES    = 3,
  91         OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING            = 4,
  92         OCRDMA_MBX_CQE_STATUS_DMA_FAILED                = 5
  93 };
  94
  95 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
  96 {
  97         return (u8 *)eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
  98 }
  99
 100 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
 101 {
 102         eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
 103 }
 104
 105 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
 106 {
 107         struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
 108             ((u8 *) dev->mq.cq.va +
 109              (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
 110
 111         if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
 112                 return NULL;
 113         return cqe;
 114 }
 115
 116 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
 117 {
 118         dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
 119 }
 120
 121 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
 122 {
 123         return (struct ocrdma_mqe *)((u8 *) dev->mq.sq.va +
 124                                      (dev->mq.sq.head *
 125                                       sizeof(struct ocrdma_mqe)));
 126 }
 127
 128 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
 129 {
 130         dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
 131         atomic_inc(&dev->mq.sq.used);
 132 }
 133
 134 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
 135 {
 136         return (void *)((u8 *) dev->mq.sq.va +
 137                         (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe)));
 138 }
 139
 140 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
 141 {
 142         switch (qps) {
 143         case OCRDMA_QPS_RST:
 144                 return IB_QPS_RESET;
 145         case OCRDMA_QPS_INIT:
 146                 return IB_QPS_INIT;
 147         case OCRDMA_QPS_RTR:
 148                 return IB_QPS_RTR;
 149         case OCRDMA_QPS_RTS:
 150                 return IB_QPS_RTS;
 151         case OCRDMA_QPS_SQD:
 152         case OCRDMA_QPS_SQ_DRAINING:
 153                 return IB_QPS_SQD;
 154         case OCRDMA_QPS_SQE:
 155                 return IB_QPS_SQE;
 156         case OCRDMA_QPS_ERR:
 157                 return IB_QPS_ERR;
 158         };
 159         return IB_QPS_ERR;
 160 }
 161
 162 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
 163 {
 164         switch (qps) {
 165         case IB_QPS_RESET:
 166                 return OCRDMA_QPS_RST;
 167         case IB_QPS_INIT:
 168                 return OCRDMA_QPS_INIT;
 169         case IB_QPS_RTR:
 170                 return OCRDMA_QPS_RTR;
 171         case IB_QPS_RTS:
 172                 return OCRDMA_QPS_RTS;
 173         case IB_QPS_SQD:
 174                 return OCRDMA_QPS_SQD;
 175         case IB_QPS_SQE:
 176                 return OCRDMA_QPS_SQE;
 177         case IB_QPS_ERR:
 178                 return OCRDMA_QPS_ERR;
 179         };
 180         return OCRDMA_QPS_ERR;
 181 }
 182
 183 static int ocrdma_get_mbx_errno(u32 status)
 184 {
 185         int err_num = -EFAULT;
 186         u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
 187                                         OCRDMA_MBX_RSP_STATUS_SHIFT;
 188         u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
 189                                         OCRDMA_MBX_RSP_ASTATUS_SHIFT;
 190
 191         switch (mbox_status) {
 192         case OCRDMA_MBX_STATUS_OOR:
 193         case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
 194                 err_num = -EAGAIN;
 195                 break;
 196
 197         case OCRDMA_MBX_STATUS_INVALID_PD:
 198         case OCRDMA_MBX_STATUS_INVALID_CQ:
 199         case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
 200         case OCRDMA_MBX_STATUS_INVALID_QP:
 201         case OCRDMA_MBX_STATUS_INVALID_CHANGE:
 202         case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
 203         case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
 204         case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
 205         case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
 206         case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
 207         case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
 208         case OCRDMA_MBX_STATUS_INVALID_LKEY:
 209         case OCRDMA_MBX_STATUS_INVALID_VA:
 210         case OCRDMA_MBX_STATUS_INVALID_LENGTH:
 211         case OCRDMA_MBX_STATUS_INVALID_FBO:
 212         case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
 213         case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
 214         case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
 215         case OCRDMA_MBX_STATUS_SRQ_ERROR:
 216         case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
 217                 err_num = -EINVAL;
 218                 break;
 219
 220         case OCRDMA_MBX_STATUS_PD_INUSE:
 221         case OCRDMA_MBX_STATUS_QP_BOUND:
 222         case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
 223         case OCRDMA_MBX_STATUS_MW_BOUND:
 224                 err_num = -EBUSY;
 225                 break;
 226
 227         case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
 228         case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
 229         case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
 230         case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
 231         case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
 232         case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
 233         case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
 234         case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
 235         case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
 236                 err_num = -ENOBUFS;
 237                 break;
 238
 239         case OCRDMA_MBX_STATUS_FAILED:
 240                 switch (add_status) {
 241                 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
 242                         err_num = -EAGAIN;
 243                         break;
 244                 }
 245         default:
 246                 err_num = -EFAULT;
 247         }
 248         return err_num;
 249 }
 250
 251 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
 252 {
 253         int err_num = -EINVAL;
 254
 255         switch (cqe_status) {
 256         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
 257                 err_num = -EPERM;
 258                 break;
 259         case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
 260                 err_num = -EINVAL;
 261                 break;
 262         case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
 263         case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
 264                 err_num = -EAGAIN;
 265                 break;
 266         case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
 267                 err_num = -EIO;
 268                 break;
 269         }
 270         return err_num;
 271 }
 272
 273 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
 274                        bool solicited, u16 cqe_popped)
 275 {
 276         u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
 277
 278         val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
 279              OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
 280
 281         if (armed)
 282                 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
 283         if (solicited)
 284                 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
 285         val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
 286         iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
 287 }
 288
 289 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
 290 {
 291         u32 val = 0;
 292
 293         val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
 294         val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
 295         iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
 296 }
 297
 298 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
 299                               bool arm, bool clear_int, u16 num_eqe)
 300 {
 301         u32 val = 0;
 302
 303         val |= eq_id & OCRDMA_EQ_ID_MASK;
 304         val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
 305         if (arm)
 306                 val |= (1 << OCRDMA_REARM_SHIFT);
 307         if (clear_int)
 308                 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
 309         val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
 310         val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
 311         iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
 312 }
 313
 314 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
 315                             u8 opcode, u8 subsys, u32 cmd_len)
 316 {
 317         cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
 318         cmd_hdr->timeout = 20; /* seconds */
 319         cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
 320 }
 321
 322 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
 323 {
 324         struct ocrdma_mqe *mqe;
 325
 326         mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
 327         if (!mqe)
 328                 return NULL;
 329         mqe->hdr.spcl_sge_cnt_emb |=
 330                 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
 331                                         OCRDMA_MQE_HDR_EMB_MASK;
 332         mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
 333
 334         ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
 335                         mqe->hdr.pyld_len);
 336         return mqe;
 337 }
 338
 339 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
 340 {
 341         dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
 342 }
 343
 344 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
 345                           struct ocrdma_queue_info *q, u16 len, u16 entry_size)
 346 {
 347         memset(q, 0, sizeof(*q));
 348         q->len = len;
 349         q->entry_size = entry_size;
 350         q->size = len * entry_size;
 351         q->va = dma_alloc_coherent(&dev->nic_info.pdev->dev, q->size,
 352                                    &q->dma, GFP_KERNEL);
 353         if (!q->va)
 354                 return -ENOMEM;
 355         memset(q->va, 0, q->size);
 356         return 0;
 357 }
 358
 359 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
 360                                         dma_addr_t host_pa, int hw_page_size)
 361 {
 362         int i;
 363
 364         for (i = 0; i < cnt; i++) {
 365                 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
 366                 q_pa[i].hi = (u32) upper_32_bits(host_pa);
 367                 host_pa += hw_page_size;
 368         }
 369 }
 370
 371 static void ocrdma_assign_eq_vect_gen2(struct ocrdma_dev *dev,
 372                                        struct ocrdma_eq *eq)
 373 {
 374         /* assign vector and update vector id for next EQ */
 375         eq->vector = dev->nic_info.msix.start_vector;
 376         dev->nic_info.msix.start_vector += 1;
 377 }
 378
 379 static void ocrdma_free_eq_vect_gen2(struct ocrdma_dev *dev)
 380 {
 381         /* this assumes that EQs are freed in exactly reverse order
 382          * as its allocation.
 383          */
 384         dev->nic_info.msix.start_vector -= 1;
 385 }
 386
 387 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q,
 388                                int queue_type)
 389 {
 390         u8 opcode = 0;
 391         int status;
 392         struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
 393
 394         switch (queue_type) {
 395         case QTYPE_MCCQ:
 396                 opcode = OCRDMA_CMD_DELETE_MQ;
 397                 break;
 398         case QTYPE_CQ:
 399                 opcode = OCRDMA_CMD_DELETE_CQ;
 400                 break;
 401         case QTYPE_EQ:
 402                 opcode = OCRDMA_CMD_DELETE_EQ;
 403                 break;
 404         default:
 405                 BUG();
 406         }
 407         memset(cmd, 0, sizeof(*cmd));
 408         ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 409         cmd->id = q->id;
 410
 411         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 412                                  cmd, sizeof(*cmd), NULL, NULL);
 413         if (!status)
 414                 q->created = false;
 415         return status;
 416 }
 417
 418 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 419 {
 420         int status;
 421         struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
 422         struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
 423
 424         memset(cmd, 0, sizeof(*cmd));
 425         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
 426                         sizeof(*cmd));
 427         if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
 428                 cmd->req.rsvd_version = 0;
 429         else
 430                 cmd->req.rsvd_version = 2;
 431
 432         cmd->num_pages = 4;
 433         cmd->valid = OCRDMA_CREATE_EQ_VALID;
 434         cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
 435
 436         ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
 437                              PAGE_SIZE_4K);
 438         status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
 439                                  NULL);
 440         if (!status) {
 441                 eq->q.id = rsp->vector_eqid & 0xffff;
 442                 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
 443                         ocrdma_assign_eq_vect_gen2(dev, eq);
 444                 else {
 445                         eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
 446                         dev->nic_info.msix.start_vector += 1;
 447                 }
 448                 eq->q.created = true;
 449         }
 450         return status;
 451 }
 452
 453 static int ocrdma_create_eq(struct ocrdma_dev *dev,
 454                             struct ocrdma_eq *eq, u16 q_len)
 455 {
 456         int status;
 457
 458         status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
 459                                 sizeof(struct ocrdma_eqe));
 460         if (status)
 461                 return status;
 462
 463         status = ocrdma_mbx_create_eq(dev, eq);
 464         if (status)
 465                 goto mbx_err;
 466         eq->dev = dev;
 467         ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 468
 469         return 0;
 470 mbx_err:
 471         ocrdma_free_q(dev, &eq->q);
 472         return status;
 473 }
 474
 475 static int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 476 {
 477         int irq;
 478
 479         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 480                 irq = dev->nic_info.pdev->irq;
 481         else
 482                 irq = dev->nic_info.msix.vector_list[eq->vector];
 483         return irq;
 484 }
 485
 486 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 487 {
 488         if (eq->q.created) {
 489                 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
 490                 if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY)
 491                         ocrdma_free_eq_vect_gen2(dev);
 492                 ocrdma_free_q(dev, &eq->q);
 493         }
 494 }
 495
 496 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
 497 {
 498         int irq;
 499
 500         /* disarm EQ so that interrupts are not generated
 501          * during freeing and EQ delete is in progress.
 502          */
 503         ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
 504
 505         irq = ocrdma_get_irq(dev, eq);
 506         free_irq(irq, eq);
 507         _ocrdma_destroy_eq(dev, eq);
 508 }
 509
 510 static void ocrdma_destroy_qp_eqs(struct ocrdma_dev *dev)
 511 {
 512         int i;
 513
 514         /* deallocate the data path eqs */
 515         for (i = 0; i < dev->eq_cnt; i++)
 516                 ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
 517 }
 518
 519 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
 520                                    struct ocrdma_queue_info *cq,
 521                                    struct ocrdma_queue_info *eq)
 522 {
 523         struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
 524         struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
 525         int status;
 526
 527         memset(cmd, 0, sizeof(*cmd));
 528         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
 529                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 530
 531         cmd->pgsz_pgcnt = PAGES_4K_SPANNED(cq->va, cq->size);
 532         cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
 533         cmd->eqn = (eq->id << OCRDMA_CREATE_CQ_EQID_SHIFT);
 534
 535         ocrdma_build_q_pages(&cmd->pa[0], cmd->pgsz_pgcnt,
 536                              cq->dma, PAGE_SIZE_4K);
 537         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 538                                  cmd, sizeof(*cmd), NULL, NULL);
 539         if (!status) {
 540                 cq->id = (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
 541                 cq->created = true;
 542         }
 543         return status;
 544 }
 545
 546 static u32 ocrdma_encoded_q_len(int q_len)
 547 {
 548         u32 len_encoded = fls(q_len);   /* log2(len) + 1 */
 549
 550         if (len_encoded == 16)
 551                 len_encoded = 0;
 552         return len_encoded;
 553 }
 554
 555 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
 556                                 struct ocrdma_queue_info *mq,
 557                                 struct ocrdma_queue_info *cq)
 558 {
 559         int num_pages, status;
 560         struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
 561         struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
 562         struct ocrdma_pa *pa;
 563
 564         memset(cmd, 0, sizeof(*cmd));
 565         num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
 566
 567         if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
 568                 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ,
 569                                 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 570                 cmd->v0.pages = num_pages;
 571                 cmd->v0.async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 572                 cmd->v0.async_cqid_valid = (cq->id << 1);
 573                 cmd->v0.cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 574                                              OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 575                 cmd->v0.cqid_ringsize |=
 576                         (cq->id << OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT);
 577                 cmd->v0.valid = OCRDMA_CREATE_MQ_VALID;
 578                 pa = &cmd->v0.pa[0];
 579         } else {
 580                 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
 581                                 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
 582                 cmd->req.rsvd_version = 1;
 583                 cmd->v1.cqid_pages = num_pages;
 584                 cmd->v1.cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
 585                 cmd->v1.async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
 586                 cmd->v1.async_event_bitmap = Bit(20);
 587                 cmd->v1.async_cqid_ringsize = cq->id;
 588                 cmd->v1.async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
 589                                              OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
 590                 cmd->v1.valid = OCRDMA_CREATE_MQ_VALID;
 591                 pa = &cmd->v1.pa[0];
 592         }
 593         ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
 594         status = be_roce_mcc_cmd(dev->nic_info.netdev,
 595                                  cmd, sizeof(*cmd), NULL, NULL);
 596         if (!status) {
 597                 mq->id = rsp->id;
 598                 mq->created = true;
 599         }
 600         return status;
 601 }
 602
 603 static int ocrdma_create_mq(struct ocrdma_dev *dev)
 604 {
 605         int status;
 606
 607         /* Alloc completion queue for Mailbox queue */
 608         status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
 609                                 sizeof(struct ocrdma_mcqe));
 610         if (status)
 611                 goto alloc_err;
 612
 613         status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->meq.q);
 614         if (status)
 615                 goto mbx_cq_free;
 616
 617         memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
 618         init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
 619         mutex_init(&dev->mqe_ctx.lock);
 620
 621         /* Alloc Mailbox queue */
 622         status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
 623                                 sizeof(struct ocrdma_mqe));
 624         if (status)
 625                 goto mbx_cq_destroy;
 626         status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
 627         if (status)
 628                 goto mbx_q_free;
 629         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
 630         return 0;
 631
 632 mbx_q_free:
 633         ocrdma_free_q(dev, &dev->mq.sq);
 634 mbx_cq_destroy:
 635         ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
 636 mbx_cq_free:
 637         ocrdma_free_q(dev, &dev->mq.cq);
 638 alloc_err:
 639         return status;
 640 }
 641
 642 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
 643 {
 644         struct ocrdma_queue_info *mbxq, *cq;
 645
 646         /* mqe_ctx lock synchronizes with any other pending cmds. */
 647         mutex_lock(&dev->mqe_ctx.lock);
 648         mbxq = &dev->mq.sq;
 649         if (mbxq->created) {
 650                 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
 651                 ocrdma_free_q(dev, mbxq);
 652         }
 653         mutex_unlock(&dev->mqe_ctx.lock);
 654
 655         cq = &dev->mq.cq;
 656         if (cq->created) {
 657                 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
 658                 ocrdma_free_q(dev, cq);
 659         }
 660 }
 661
 662 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
 663                                        struct ocrdma_qp *qp)
 664 {
 665         enum ib_qp_state new_ib_qps = IB_QPS_ERR;
 666         enum ib_qp_state old_ib_qps;
 667
 668         if (qp == NULL)
 669                 BUG();
 670         ocrdma_qp_state_machine(qp, new_ib_qps, &old_ib_qps);
 671 }
 672
 673 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
 674                                     struct ocrdma_ae_mcqe *cqe)
 675 {
 676         struct ocrdma_qp *qp = NULL;
 677         struct ocrdma_cq *cq = NULL;
 678         struct ib_event ib_evt;
 679         int cq_event = 0;
 680         int qp_event = 1;
 681         int srq_event = 0;
 682         int dev_event = 0;
 683         int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
 684             OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
 685
 686         if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID)
 687                 qp = dev->qp_tbl[cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK];
 688         if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID)
 689                 cq = dev->cq_tbl[cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK];
 690
 691         ib_evt.device = &dev->ibdev;
 692
 693         switch (type) {
 694         case OCRDMA_CQ_ERROR:
 695                 ib_evt.element.cq = &cq->ibcq;
 696                 ib_evt.event = IB_EVENT_CQ_ERR;
 697                 cq_event = 1;
 698                 qp_event = 0;
 699                 break;
 700         case OCRDMA_CQ_OVERRUN_ERROR:
 701                 ib_evt.element.cq = &cq->ibcq;
 702                 ib_evt.event = IB_EVENT_CQ_ERR;
 703                 break;
 704         case OCRDMA_CQ_QPCAT_ERROR:
 705                 ib_evt.element.qp = &qp->ibqp;
 706                 ib_evt.event = IB_EVENT_QP_FATAL;
 707                 ocrdma_process_qpcat_error(dev, qp);
 708                 break;
 709         case OCRDMA_QP_ACCESS_ERROR:
 710                 ib_evt.element.qp = &qp->ibqp;
 711                 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
 712                 break;
 713         case OCRDMA_QP_COMM_EST_EVENT:
 714                 ib_evt.element.qp = &qp->ibqp;
 715                 ib_evt.event = IB_EVENT_COMM_EST;
 716                 break;
 717         case OCRDMA_SQ_DRAINED_EVENT:
 718                 ib_evt.element.qp = &qp->ibqp;
 719                 ib_evt.event = IB_EVENT_SQ_DRAINED;
 720                 break;
 721         case OCRDMA_DEVICE_FATAL_EVENT:
 722                 ib_evt.element.port_num = 1;
 723                 ib_evt.event = IB_EVENT_DEVICE_FATAL;
 724                 qp_event = 0;
 725                 dev_event = 1;
 726                 break;
 727         case OCRDMA_SRQCAT_ERROR:
 728                 ib_evt.element.srq = &qp->srq->ibsrq;
 729                 ib_evt.event = IB_EVENT_SRQ_ERR;
 730                 srq_event = 1;
 731                 qp_event = 0;
 732                 break;
 733         case OCRDMA_SRQ_LIMIT_EVENT:
 734                 ib_evt.element.srq = &qp->srq->ibsrq;
 735                 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
 736                 srq_event = 1;
 737                 qp_event = 0;
 738                 break;
 739         case OCRDMA_QP_LAST_WQE_EVENT:
 740                 ib_evt.element.qp = &qp->ibqp;
 741                 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
 742                 break;
 743         default:
 744                 cq_event = 0;
 745                 qp_event = 0;
 746                 srq_event = 0;
 747                 dev_event = 0;
 748                 ocrdma_err("%s() unknown type=0x%x\n", __func__, type);
 749                 break;
 750         }
 751
 752         if (qp_event) {
 753                 if (qp->ibqp.event_handler)
 754                         qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
 755         } else if (cq_event) {
 756                 if (cq->ibcq.event_handler)
 757                         cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
 758         } else if (srq_event) {
 759                 if (qp->srq->ibsrq.event_handler)
 760                         qp->srq->ibsrq.event_handler(&ib_evt,
 761                                                      qp->srq->ibsrq.
 762                                                      srq_context);
 763         } else if (dev_event)
 764                 ib_dispatch_event(&ib_evt);
 765
 766 }
 767
 768 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
 769 {
 770         /* async CQE processing */
 771         struct ocrdma_ae_mcqe *cqe = ae_cqe;
 772         u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
 773                         OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
 774
 775         if (evt_code == OCRDMA_ASYNC_EVE_CODE)
 776                 ocrdma_dispatch_ibevent(dev, cqe);
 777         else
 778                 ocrdma_err("%s(%d) invalid evt code=0x%x\n",
 779                            __func__, dev->id, evt_code);
 780 }
 781
 782 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
 783 {
 784         if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
 785                 dev->mqe_ctx.cqe_status = (cqe->status &
 786                      OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
 787                 dev->mqe_ctx.ext_status =
 788                     (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
 789                     >> OCRDMA_MCQE_ESTATUS_SHIFT;
 790                 dev->mqe_ctx.cmd_done = true;
 791                 wake_up(&dev->mqe_ctx.cmd_wait);
 792         } else
 793                 ocrdma_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
 794                            __func__, cqe->tag_lo, dev->mqe_ctx.tag);
 795 }
 796
 797 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 798 {
 799         u16 cqe_popped = 0;
 800         struct ocrdma_mcqe *cqe;
 801
 802         while (1) {
 803                 cqe = ocrdma_get_mcqe(dev);
 804                 if (cqe == NULL)
 805                         break;
 806                 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
 807                 cqe_popped += 1;
 808                 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
 809                         ocrdma_process_acqe(dev, cqe);
 810                 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
 811                         ocrdma_process_mcqe(dev, cqe);
 812                 else
 813                         ocrdma_err("%s() cqe->compl is not set.\n", __func__);
 814                 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
 815                 ocrdma_mcq_inc_tail(dev);
 816         }
 817         ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
 818         return 0;
 819 }
 820
 821 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
 822                                        struct ocrdma_cq *cq)
 823 {
 824         unsigned long flags;
 825         struct ocrdma_qp *qp;
 826         bool buddy_cq_found = false;
 827         /* Go through list of QPs in error state which are using this CQ
 828          * and invoke its callback handler to trigger CQE processing for
 829          * error/flushed CQE. It is rare to find more than few entries in
 830          * this list as most consumers stops after getting error CQE.
 831          * List is traversed only once when a matching buddy cq found for a QP.
 832          */
 833         spin_lock_irqsave(&dev->flush_q_lock, flags);
 834         list_for_each_entry(qp, &cq->sq_head, sq_entry) {
 835                 if (qp->srq)
 836                         continue;
 837                 /* if wq and rq share the same cq, than comp_handler
 838                  * is already invoked.
 839                  */
 840                 if (qp->sq_cq == qp->rq_cq)
 841                         continue;
 842                 /* if completion came on sq, rq's cq is buddy cq.
 843                  * if completion came on rq, sq's cq is buddy cq.
 844                  */
 845                 if (qp->sq_cq == cq)
 846                         cq = qp->rq_cq;
 847                 else
 848                         cq = qp->sq_cq;
 849                 buddy_cq_found = true;
 850                 break;
 851         }
 852         spin_unlock_irqrestore(&dev->flush_q_lock, flags);
 853         if (buddy_cq_found == false)
 854                 return;
 855         if (cq->ibcq.comp_handler) {
 856                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 857                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 858                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 859         }
 860 }
 861
 862 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
 863 {
 864         unsigned long flags;
 865         struct ocrdma_cq *cq;
 866
 867         if (cq_idx >= OCRDMA_MAX_CQ)
 868                 BUG();
 869
 870         cq = dev->cq_tbl[cq_idx];
 871         if (cq == NULL) {
 872                 ocrdma_err("%s%d invalid id=0x%x\n", __func__, dev->id, cq_idx);
 873                 return;
 874         }
 875         spin_lock_irqsave(&cq->cq_lock, flags);
 876         cq->armed = false;
 877         cq->solicited = false;
 878         spin_unlock_irqrestore(&cq->cq_lock, flags);
 879
 880         ocrdma_ring_cq_db(dev, cq->id, false, false, 0);
 881
 882         if (cq->ibcq.comp_handler) {
 883                 spin_lock_irqsave(&cq->comp_handler_lock, flags);
 884                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 885                 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
 886         }
 887         ocrdma_qp_buddy_cq_handler(dev, cq);
 888 }
 889
 890 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
 891 {
 892         /* process the MQ-CQE. */
 893         if (cq_id == dev->mq.cq.id)
 894                 ocrdma_mq_cq_handler(dev, cq_id);
 895         else
 896                 ocrdma_qp_cq_handler(dev, cq_id);
 897 }
 898
 899 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
 900 {
 901         struct ocrdma_eq *eq = handle;
 902         struct ocrdma_dev *dev = eq->dev;
 903         struct ocrdma_eqe eqe;
 904         struct ocrdma_eqe *ptr;
 905         u16 eqe_popped = 0;
 906         u16 cq_id;
 907         while (1) {
 908                 ptr = ocrdma_get_eqe(eq);
 909                 eqe = *ptr;
 910                 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
 911                 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
 912                         break;
 913                 eqe_popped += 1;
 914                 ptr->id_valid = 0;
 915                 /* check whether its CQE or not. */
 916                 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
 917                         cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
 918                         ocrdma_cq_handler(dev, cq_id);
 919                 }
 920                 ocrdma_eq_inc_tail(eq);
 921         }
 922         ocrdma_ring_eq_db(dev, eq->q.id, true, true, eqe_popped);
 923         /* Ring EQ doorbell with num_popped to 0 to enable interrupts again. */
 924         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
 925                 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
 926         return IRQ_HANDLED;
 927 }
 928
 929 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
 930 {
 931         struct ocrdma_mqe *mqe;
 932
 933         dev->mqe_ctx.tag = dev->mq.sq.head;
 934         dev->mqe_ctx.cmd_done = false;
 935         mqe = ocrdma_get_mqe(dev);
 936         cmd->hdr.tag_lo = dev->mq.sq.head;
 937         ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
 938         /* make sure descriptor is written before ringing doorbell */
 939         wmb();
 940         ocrdma_mq_inc_head(dev);
 941         ocrdma_ring_mq_db(dev);
 942 }
 943
 944 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
 945 {
 946         long status;
 947         /* 30 sec timeout */
 948         status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
 949                                     (dev->mqe_ctx.cmd_done != false),
 950                                     msecs_to_jiffies(30000));
 951         if (status)
 952                 return 0;
 953         else
 954                 return -1;
 955 }
 956
 957 /* issue a mailbox command on the MQ */
 958 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
 959 {
 960         int status = 0;
 961         u16 cqe_status, ext_status;
 962         struct ocrdma_mqe *rsp;
 963
 964         mutex_lock(&dev->mqe_ctx.lock);
 965         ocrdma_post_mqe(dev, mqe);
 966         status = ocrdma_wait_mqe_cmpl(dev);
 967         if (status)
 968                 goto mbx_err;
 969         cqe_status = dev->mqe_ctx.cqe_status;
 970         ext_status = dev->mqe_ctx.ext_status;
 971         rsp = ocrdma_get_mqe_rsp(dev);
 972         ocrdma_copy_le32_to_cpu(mqe, rsp, (sizeof(*mqe)));
 973         if (cqe_status || ext_status) {
 974                 ocrdma_err
 975                     ("%s() opcode=0x%x, cqe_status=0x%x, ext_status=0x%x\n",
 976                      __func__,
 977                      (rsp->u.rsp.subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
 978                      OCRDMA_MBX_RSP_OPCODE_SHIFT, cqe_status, ext_status);
 979                 status = ocrdma_get_mbx_cqe_errno(cqe_status);
 980                 goto mbx_err;
 981         }
 982         if (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK)
 983                 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
 984 mbx_err:
 985         mutex_unlock(&dev->mqe_ctx.lock);
 986         return status;
 987 }
 988
 989 static void ocrdma_get_attr(struct ocrdma_dev *dev,
 990                               struct ocrdma_dev_attr *attr,
 991                               struct ocrdma_mbx_query_config *rsp)
 992 {
 993         int max_q_mem;
 994
 995         attr->max_pd =
 996             (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
 997             OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
 998         attr->max_qp =
 999             (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1000             OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1001         attr->max_send_sge = ((rsp->max_write_send_sge &
1002                                OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1003                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1004         attr->max_recv_sge = (rsp->max_write_send_sge &
1005                               OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1006             OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT;
1007         attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1008                                 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1009             OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1010         attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1011                                 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1012             OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1013         attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1014                                     OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1015             OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1016         attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1017                                OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1018             OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1019         attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1020                                     OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1021             OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1022         attr->max_mr = rsp->max_mr;
1023         attr->max_mr_size = ~0ull;
1024         attr->max_fmr = 0;
1025         attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1026         attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1027         attr->max_cqe = rsp->max_cq_cqes_per_cq &
1028                         OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1029         attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1030                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1031                 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1032                 OCRDMA_WQE_STRIDE;
1033         attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1034                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1035                 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1036                 OCRDMA_WQE_STRIDE;
1037         attr->max_inline_data =
1038             attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1039                               sizeof(struct ocrdma_sge));
1040         max_q_mem = OCRDMA_Q_PAGE_BASE_SIZE << (OCRDMA_MAX_Q_PAGE_SIZE_CNT - 1);
1041         /* hw can queue one less then the configured size,
1042          * so publish less by one to stack.
1043          */
1044         if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1045                 dev->attr.max_wqe = max_q_mem / dev->attr.wqe_size;
1046                 attr->ird = 1;
1047                 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1048                 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1049         } else
1050                 dev->attr.max_wqe = (max_q_mem / dev->attr.wqe_size) - 1;
1051         dev->attr.max_rqe = (max_q_mem / dev->attr.rqe_size) - 1;
1052 }
1053
1054 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1055                                    struct ocrdma_fw_conf_rsp *conf)
1056 {
1057         u32 fn_mode;
1058
1059         fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1060         if (fn_mode != OCRDMA_FN_MODE_RDMA)
1061                 return -EINVAL;
1062         dev->base_eqid = conf->base_eqid;
1063         dev->max_eq = conf->max_eq;
1064         dev->attr.max_cq = OCRDMA_MAX_CQ - 1;
1065         return 0;
1066 }
1067
1068 /* can be issued only during init time. */
1069 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1070 {
1071         int status = -ENOMEM;
1072         struct ocrdma_mqe *cmd;
1073         struct ocrdma_fw_ver_rsp *rsp;
1074
1075         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1076         if (!cmd)
1077                 return -ENOMEM;
1078         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1079                         OCRDMA_CMD_GET_FW_VER,
1080                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1081
1082         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1083         if (status)
1084                 goto mbx_err;
1085         rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1086         memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1087         memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1088                sizeof(rsp->running_ver));
1089         ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1090 mbx_err:
1091         kfree(cmd);
1092         return status;
1093 }
1094
1095 /* can be issued only during init time. */
1096 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1097 {
1098         int status = -ENOMEM;
1099         struct ocrdma_mqe *cmd;
1100         struct ocrdma_fw_conf_rsp *rsp;
1101
1102         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1103         if (!cmd)
1104                 return -ENOMEM;
1105         ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1106                         OCRDMA_CMD_GET_FW_CONFIG,
1107                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1108         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1109         if (status)
1110                 goto mbx_err;
1111         rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1112         status = ocrdma_check_fw_config(dev, rsp);
1113 mbx_err:
1114         kfree(cmd);
1115         return status;
1116 }
1117
1118 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1119 {
1120         int status = -ENOMEM;
1121         struct ocrdma_mbx_query_config *rsp;
1122         struct ocrdma_mqe *cmd;
1123
1124         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1125         if (!cmd)
1126                 return status;
1127         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1128         if (status)
1129                 goto mbx_err;
1130         rsp = (struct ocrdma_mbx_query_config *)cmd;
1131         ocrdma_get_attr(dev, &dev->attr, rsp);
1132 mbx_err:
1133         kfree(cmd);
1134         return status;
1135 }
1136
1137 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1138 {
1139         int status = -ENOMEM;
1140         struct ocrdma_alloc_pd *cmd;
1141         struct ocrdma_alloc_pd_rsp *rsp;
1142
1143         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1144         if (!cmd)
1145                 return status;
1146         if (pd->dpp_enabled)
1147                 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1148         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1149         if (status)
1150                 goto mbx_err;
1151         rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1152         pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1153         if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1154                 pd->dpp_enabled = true;
1155                 pd->dpp_page = rsp->dpp_page_pdid >>
1156                                 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1157         } else {
1158                 pd->dpp_enabled = false;
1159                 pd->num_dpp_qp = 0;
1160         }
1161 mbx_err:
1162         kfree(cmd);
1163         return status;
1164 }
1165
1166 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1167 {
1168         int status = -ENOMEM;
1169         struct ocrdma_dealloc_pd *cmd;
1170
1171         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1172         if (!cmd)
1173                 return status;
1174         cmd->id = pd->id;
1175         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1176         kfree(cmd);
1177         return status;
1178 }
1179
1180 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1181                                int *num_pages, int *page_size)
1182 {
1183         int i;
1184         int mem_size;
1185
1186         *num_entries = roundup_pow_of_two(*num_entries);
1187         mem_size = *num_entries * entry_size;
1188         /* find the possible lowest possible multiplier */
1189         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1190                 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1191                         break;
1192         }
1193         if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1194                 return -EINVAL;
1195         mem_size = roundup(mem_size,
1196                        ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1197         *num_pages =
1198             mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1199         *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1200         *num_entries = mem_size / entry_size;
1201         return 0;
1202 }
1203
1204 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1205 {
1206         int i ;
1207         int status = 0;
1208         int max_ah;
1209         struct ocrdma_create_ah_tbl *cmd;
1210         struct ocrdma_create_ah_tbl_rsp *rsp;
1211         struct pci_dev *pdev = dev->nic_info.pdev;
1212         dma_addr_t pa;
1213         struct ocrdma_pbe *pbes;
1214
1215         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1216         if (!cmd)
1217                 return status;
1218
1219         max_ah = OCRDMA_MAX_AH;
1220         dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1221
1222         /* number of PBEs in PBL */
1223         cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1224                                 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1225                                 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1226
1227         /* page size */
1228         for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1229                 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1230                         break;
1231         }
1232         cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1233                                 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1234
1235         /* ah_entry size */
1236         cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1237                                 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1238                                 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1239
1240         dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1241                                                 &dev->av_tbl.pbl.pa,
1242                                                 GFP_KERNEL);
1243         if (dev->av_tbl.pbl.va == NULL)
1244                 goto mem_err;
1245
1246         dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1247                                             &pa, GFP_KERNEL);
1248         if (dev->av_tbl.va == NULL)
1249                 goto mem_err_ah;
1250         dev->av_tbl.pa = pa;
1251         dev->av_tbl.num_ah = max_ah;
1252         memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1253
1254         pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1255         for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1256                 pbes[i].pa_lo = (u32) (pa & 0xffffffff);
1257                 pbes[i].pa_hi = (u32) upper_32_bits(pa);
1258                 pa += PAGE_SIZE;
1259         }
1260         cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1261         cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1262         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1263         if (status)
1264                 goto mbx_err;
1265         rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1266         dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1267         kfree(cmd);
1268         return 0;
1269
1270 mbx_err:
1271         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1272                           dev->av_tbl.pa);
1273         dev->av_tbl.va = NULL;
1274 mem_err_ah:
1275         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1276                           dev->av_tbl.pbl.pa);
1277         dev->av_tbl.pbl.va = NULL;
1278         dev->av_tbl.size = 0;
1279 mem_err:
1280         kfree(cmd);
1281         return status;
1282 }
1283
1284 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1285 {
1286         struct ocrdma_delete_ah_tbl *cmd;
1287         struct pci_dev *pdev = dev->nic_info.pdev;
1288
1289         if (dev->av_tbl.va == NULL)
1290                 return;
1291
1292         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1293         if (!cmd)
1294                 return;
1295         cmd->ahid = dev->av_tbl.ahid;
1296
1297         ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1298         dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1299                           dev->av_tbl.pa);
1300         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1301                           dev->av_tbl.pbl.pa);
1302         kfree(cmd);
1303 }
1304
1305 /* Multiple CQs uses the EQ. This routine returns least used
1306  * EQ to associate with CQ. This will distributes the interrupt
1307  * processing and CPU load to associated EQ, vector and so to that CPU.
1308  */
1309 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1310 {
1311         int i, selected_eq = 0, cq_cnt = 0;
1312         u16 eq_id;
1313
1314         mutex_lock(&dev->dev_lock);
1315         cq_cnt = dev->qp_eq_tbl[0].cq_cnt;
1316         eq_id = dev->qp_eq_tbl[0].q.id;
1317         /* find the EQ which is has the least number of
1318          * CQs associated with it.
1319          */
1320         for (i = 0; i < dev->eq_cnt; i++) {
1321                 if (dev->qp_eq_tbl[i].cq_cnt < cq_cnt) {
1322                         cq_cnt = dev->qp_eq_tbl[i].cq_cnt;
1323                         eq_id = dev->qp_eq_tbl[i].q.id;
1324                         selected_eq = i;
1325                 }
1326         }
1327         dev->qp_eq_tbl[selected_eq].cq_cnt += 1;
1328         mutex_unlock(&dev->dev_lock);
1329         return eq_id;
1330 }
1331
1332 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1333 {
1334         int i;
1335
1336         mutex_lock(&dev->dev_lock);
1337         for (i = 0; i < dev->eq_cnt; i++) {
1338                 if (dev->qp_eq_tbl[i].q.id != eq_id)
1339                         continue;
1340                 dev->qp_eq_tbl[i].cq_cnt -= 1;
1341                 break;
1342         }
1343         mutex_unlock(&dev->dev_lock);
1344 }
1345
1346 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1347                          int entries, int dpp_cq)
1348 {
1349         int status = -ENOMEM; int max_hw_cqe;
1350         struct pci_dev *pdev = dev->nic_info.pdev;
1351         struct ocrdma_create_cq *cmd;
1352         struct ocrdma_create_cq_rsp *rsp;
1353         u32 hw_pages, cqe_size, page_size, cqe_count;
1354
1355         if (dpp_cq)
1356                 return -EINVAL;
1357         if (entries > dev->attr.max_cqe) {
1358                 ocrdma_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1359                            __func__, dev->id, dev->attr.max_cqe, entries);
1360                 return -EINVAL;
1361         }
1362         if (dpp_cq && (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY))
1363                 return -EINVAL;
1364
1365         if (dpp_cq) {
1366                 cq->max_hw_cqe = 1;
1367                 max_hw_cqe = 1;
1368                 cqe_size = OCRDMA_DPP_CQE_SIZE;
1369                 hw_pages = 1;
1370         } else {
1371                 cq->max_hw_cqe = dev->attr.max_cqe;
1372                 max_hw_cqe = dev->attr.max_cqe;
1373                 cqe_size = sizeof(struct ocrdma_cqe);
1374                 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1375         }
1376
1377         cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1378
1379         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1380         if (!cmd)
1381                 return -ENOMEM;
1382         ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1383                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1384         cq->va = dma_alloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1385         if (!cq->va) {
1386                 status = -ENOMEM;
1387                 goto mem_err;
1388         }
1389         memset(cq->va, 0, cq->len);
1390         page_size = cq->len / hw_pages;
1391         cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1392                                         OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1393         cmd->cmd.pgsz_pgcnt |= hw_pages;
1394         cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1395
1396         if (dev->eq_cnt < 0)
1397                 goto eq_err;
1398         cq->eqn = ocrdma_bind_eq(dev);
1399         cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
1400         cqe_count = cq->len / cqe_size;
1401         if (cqe_count > 1024)
1402                 /* Set cnt to 3 to indicate more than 1024 cq entries */
1403                 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1404         else {
1405                 u8 count = 0;
1406                 switch (cqe_count) {
1407                 case 256:
1408                         count = 0;
1409                         break;
1410                 case 512:
1411                         count = 1;
1412                         break;
1413                 case 1024:
1414                         count = 2;
1415                         break;
1416                 default:
1417                         goto mbx_err;
1418                 }
1419                 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1420         }
1421         /* shared eq between all the consumer cqs. */
1422         cmd->cmd.eqn = cq->eqn;
1423         if (dev->nic_info.dev_family == OCRDMA_GEN2_FAMILY) {
1424                 if (dpp_cq)
1425                         cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1426                                 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1427                 cq->phase_change = false;
1428                 cmd->cmd.cqe_count = (cq->len / cqe_size);
1429         } else {
1430                 cmd->cmd.cqe_count = (cq->len / cqe_size) - 1;
1431                 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1432                 cq->phase_change = true;
1433         }
1434
1435         ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1436         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1437         if (status)
1438                 goto mbx_err;
1439
1440         rsp = (struct ocrdma_create_cq_rsp *)cmd;
1441         cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1442         kfree(cmd);
1443         return 0;
1444 mbx_err:
1445         ocrdma_unbind_eq(dev, cq->eqn);
1446 eq_err:
1447         dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1448 mem_err:
1449         kfree(cmd);
1450         return status;
1451 }
1452
1453 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1454 {
1455         int status = -ENOMEM;
1456         struct ocrdma_destroy_cq *cmd;
1457
1458         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1459         if (!cmd)
1460                 return status;
1461         ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1462                         OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1463
1464         cmd->bypass_flush_qid |=
1465             (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1466             OCRDMA_DESTROY_CQ_QID_MASK;
1467
1468         ocrdma_unbind_eq(dev, cq->eqn);
1469         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1470         if (status)
1471                 goto mbx_err;
1472         dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1473 mbx_err:
1474         kfree(cmd);
1475         return status;
1476 }
1477
1478 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1479                           u32 pdid, int addr_check)
1480 {
1481         int status = -ENOMEM;
1482         struct ocrdma_alloc_lkey *cmd;
1483         struct ocrdma_alloc_lkey_rsp *rsp;
1484
1485         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1486         if (!cmd)
1487                 return status;
1488         cmd->pdid = pdid;
1489         cmd->pbl_sz_flags |= addr_check;
1490         cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1491         cmd->pbl_sz_flags |=
1492             (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1493         cmd->pbl_sz_flags |=
1494             (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1495         cmd->pbl_sz_flags |=
1496             (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1497         cmd->pbl_sz_flags |=
1498             (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1499         cmd->pbl_sz_flags |=
1500             (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1501
1502         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1503         if (status)
1504                 goto mbx_err;
1505         rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1506         hwmr->lkey = rsp->lrkey;
1507 mbx_err:
1508         kfree(cmd);
1509         return status;
1510 }
1511
1512 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1513 {
1514         int status = -ENOMEM;
1515         struct ocrdma_dealloc_lkey *cmd;
1516
1517         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1518         if (!cmd)
1519                 return -ENOMEM;
1520         cmd->lkey = lkey;
1521         cmd->rsvd_frmr = fr_mr ? 1 : 0;
1522         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1523         if (status)
1524                 goto mbx_err;
1525 mbx_err:
1526         kfree(cmd);
1527         return status;
1528 }
1529
1530 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1531                              u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1532 {
1533         int status = -ENOMEM;
1534         int i;
1535         struct ocrdma_reg_nsmr *cmd;
1536         struct ocrdma_reg_nsmr_rsp *rsp;
1537
1538         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1539         if (!cmd)
1540                 return -ENOMEM;
1541         cmd->num_pbl_pdid =
1542             pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1543
1544         cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1545                                     OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1546         cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1547                                     OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1548         cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1549                                     OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1550         cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1551                                     OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1552         cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1553                                     OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1554         cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1555
1556         cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1557         cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1558                                         OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1559         cmd->totlen_low = hwmr->len;
1560         cmd->totlen_high = upper_32_bits(hwmr->len);
1561         cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1562         cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1563         cmd->va_loaddr = (u32) hwmr->va;
1564         cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1565
1566         for (i = 0; i < pbl_cnt; i++) {
1567                 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
1568                 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
1569         }
1570         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1571         if (status)
1572                 goto mbx_err;
1573         rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
1574         hwmr->lkey = rsp->lrkey;
1575 mbx_err:
1576         kfree(cmd);
1577         return status;
1578 }
1579
1580 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
1581                                   struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
1582                                   u32 pbl_offset, u32 last)
1583 {
1584         int status = -ENOMEM;
1585         int i;
1586         struct ocrdma_reg_nsmr_cont *cmd;
1587
1588         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
1589         if (!cmd)
1590                 return -ENOMEM;
1591         cmd->lrkey = hwmr->lkey;
1592         cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
1593             (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
1594         cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
1595
1596         for (i = 0; i < pbl_cnt; i++) {
1597                 cmd->pbl[i].lo =
1598                     (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
1599                 cmd->pbl[i].hi =
1600                     upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
1601         }
1602         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1603         if (status)
1604                 goto mbx_err;
1605 mbx_err:
1606         kfree(cmd);
1607         return status;
1608 }
1609
1610 int ocrdma_reg_mr(struct ocrdma_dev *dev,
1611                   struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
1612 {
1613         int status;
1614         u32 last = 0;
1615         u32 cur_pbl_cnt, pbl_offset;
1616         u32 pending_pbl_cnt = hwmr->num_pbls;
1617
1618         pbl_offset = 0;
1619         cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1620         if (cur_pbl_cnt == pending_pbl_cnt)
1621                 last = 1;
1622
1623         status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
1624                                    cur_pbl_cnt, hwmr->pbe_size, last);
1625         if (status) {
1626                 ocrdma_err("%s() status=%d\n", __func__, status);
1627                 return status;
1628         }
1629         /* if there is no more pbls to register then exit. */
1630         if (last)
1631                 return 0;
1632
1633         while (!last) {
1634                 pbl_offset += cur_pbl_cnt;
1635                 pending_pbl_cnt -= cur_pbl_cnt;
1636                 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
1637                 /* if we reach the end of the pbls, then need to set the last
1638                  * bit, indicating no more pbls to register for this memory key.
1639                  */
1640                 if (cur_pbl_cnt == pending_pbl_cnt)
1641                         last = 1;
1642
1643                 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
1644                                                 pbl_offset, last);
1645                 if (status)
1646                         break;
1647         }
1648         if (status)
1649                 ocrdma_err("%s() err. status=%d\n", __func__, status);
1650
1651         return status;
1652 }
1653
1654 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1655 {
1656         struct ocrdma_qp *tmp;
1657         bool found = false;
1658         list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
1659                 if (qp == tmp) {
1660                         found = true;
1661                         break;
1662                 }
1663         }
1664         return found;
1665 }
1666
1667 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
1668 {
1669         struct ocrdma_qp *tmp;
1670         bool found = false;
1671         list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
1672                 if (qp == tmp) {
1673                         found = true;
1674                         break;
1675                 }
1676         }
1677         return found;
1678 }
1679
1680 void ocrdma_flush_qp(struct ocrdma_qp *qp)
1681 {
1682         bool found;
1683         unsigned long flags;
1684
1685         spin_lock_irqsave(&qp->dev->flush_q_lock, flags);
1686         found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
1687         if (!found)
1688                 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
1689         if (!qp->srq) {
1690                 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
1691                 if (!found)
1692                         list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
1693         }
1694         spin_unlock_irqrestore(&qp->dev->flush_q_lock, flags);
1695 }
1696
1697 int ocrdma_qp_state_machine(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
1698                             enum ib_qp_state *old_ib_state)
1699 {
1700         unsigned long flags;
1701         int status = 0;
1702         enum ocrdma_qp_state new_state;
1703         new_state = get_ocrdma_qp_state(new_ib_state);
1704
1705         /* sync with wqe and rqe posting */
1706         spin_lock_irqsave(&qp->q_lock, flags);
1707
1708         if (old_ib_state)
1709                 *old_ib_state = get_ibqp_state(qp->state);
1710         if (new_state == qp->state) {
1711                 spin_unlock_irqrestore(&qp->q_lock, flags);
1712                 return 1;
1713         }
1714
1715         switch (qp->state) {
1716         case OCRDMA_QPS_RST:
1717                 switch (new_state) {
1718                 case OCRDMA_QPS_RST:
1719                 case OCRDMA_QPS_INIT:
1720                         break;
1721                 default:
1722                         status = -EINVAL;
1723                         break;
1724                 };
1725                 break;
1726         case OCRDMA_QPS_INIT:
1727                 /* qps: INIT->XXX */
1728                 switch (new_state) {
1729                 case OCRDMA_QPS_INIT:
1730                 case OCRDMA_QPS_RTR:
1731                         break;
1732                 case OCRDMA_QPS_ERR:
1733                         ocrdma_flush_qp(qp);
1734                         break;
1735                 default:
1736                         status = -EINVAL;
1737                         break;
1738                 };
1739                 break;
1740         case OCRDMA_QPS_RTR:
1741                 /* qps: RTS->XXX */
1742                 switch (new_state) {
1743                 case OCRDMA_QPS_RTS:
1744                         break;
1745                 case OCRDMA_QPS_ERR:
1746                         ocrdma_flush_qp(qp);
1747                         break;
1748                 default:
1749                         status = -EINVAL;
1750                         break;
1751                 };
1752                 break;
1753         case OCRDMA_QPS_RTS:
1754                 /* qps: RTS->XXX */
1755                 switch (new_state) {
1756                 case OCRDMA_QPS_SQD:
1757                 case OCRDMA_QPS_SQE:
1758                         break;
1759                 case OCRDMA_QPS_ERR:
1760                         ocrdma_flush_qp(qp);
1761                         break;
1762                 default:
1763                         status = -EINVAL;
1764                         break;
1765                 };
1766                 break;
1767         case OCRDMA_QPS_SQD:
1768                 /* qps: SQD->XXX */
1769                 switch (new_state) {
1770                 case OCRDMA_QPS_RTS:
1771                 case OCRDMA_QPS_SQE:
1772                 case OCRDMA_QPS_ERR:
1773                         break;
1774                 default:
1775                         status = -EINVAL;
1776                         break;
1777                 };
1778                 break;
1779         case OCRDMA_QPS_SQE:
1780                 switch (new_state) {
1781                 case OCRDMA_QPS_RTS:
1782                 case OCRDMA_QPS_ERR:
1783                         break;
1784                 default:
1785                         status = -EINVAL;
1786                         break;
1787                 };
1788                 break;
1789         case OCRDMA_QPS_ERR:
1790                 /* qps: ERR->XXX */
1791                 switch (new_state) {
1792                 case OCRDMA_QPS_RST:
1793                         break;
1794                 default:
1795                         status = -EINVAL;
1796                         break;
1797                 };
1798                 break;
1799         default:
1800                 status = -EINVAL;
1801                 break;
1802         };
1803         if (!status)
1804                 qp->state = new_state;
1805
1806         spin_unlock_irqrestore(&qp->q_lock, flags);
1807         return status;
1808 }
1809
1810 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
1811 {
1812         u32 flags = 0;
1813         if (qp->cap_flags & OCRDMA_QP_INB_RD)
1814                 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
1815         if (qp->cap_flags & OCRDMA_QP_INB_WR)
1816                 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
1817         if (qp->cap_flags & OCRDMA_QP_MW_BIND)
1818                 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
1819         if (qp->cap_flags & OCRDMA_QP_LKEY0)
1820                 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
1821         if (qp->cap_flags & OCRDMA_QP_FAST_REG)
1822                 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
1823         return flags;
1824 }
1825
1826 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
1827                                         struct ib_qp_init_attr *attrs,
1828                                         struct ocrdma_qp *qp)
1829 {
1830         int status;
1831         u32 len, hw_pages, hw_page_size;
1832         dma_addr_t pa;
1833         struct ocrdma_dev *dev = qp->dev;
1834         struct pci_dev *pdev = dev->nic_info.pdev;
1835         u32 max_wqe_allocated;
1836         u32 max_sges = attrs->cap.max_send_sge;
1837
1838         max_wqe_allocated = attrs->cap.max_send_wr;
1839         /* need to allocate one extra to for GEN1 family */
1840         if (dev->nic_info.dev_family != OCRDMA_GEN2_FAMILY)
1841                 max_wqe_allocated += 1;
1842
1843         status = ocrdma_build_q_conf(&max_wqe_allocated,
1844                 dev->attr.wqe_size, &hw_pages, &hw_page_size);
1845         if (status) {
1846                 ocrdma_err("%s() req. max_send_wr=0x%x\n", __func__,
1847                            max_wqe_allocated);
1848                 return -EINVAL;
1849         }
1850         qp->sq.max_cnt = max_wqe_allocated;
1851         len = (hw_pages * hw_page_size);
1852
1853         qp->sq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1854         if (!qp->sq.va)
1855                 return -EINVAL;
1856         memset(qp->sq.va, 0, len);
1857         qp->sq.len = len;
1858         qp->sq.pa = pa;
1859         qp->sq.entry_size = dev->attr.wqe_size;
1860         ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
1861
1862         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
1863                                 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
1864         cmd->num_wq_rq_pages |= (hw_pages <<
1865                                  OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
1866             OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
1867         cmd->max_sge_send_write |= (max_sges <<
1868                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
1869             OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
1870         cmd->max_sge_send_write |= (max_sges <<
1871                                     OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
1872                                         OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
1873         cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
1874                              OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
1875                                 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
1876         cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
1877                               OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
1878                                 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
1879         return 0;
1880 }
1881
1882 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
1883                                         struct ib_qp_init_attr *attrs,
1884                                         struct ocrdma_qp *qp)
1885 {
1886         int status;
1887         u32 len, hw_pages, hw_page_size;
1888         dma_addr_t pa = 0;
1889         struct ocrdma_dev *dev = qp->dev;
1890         struct pci_dev *pdev = dev->nic_info.pdev;
1891         u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
1892
1893         status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
1894                                      &hw_pages, &hw_page_size);
1895         if (status) {
1896                 ocrdma_err("%s() req. max_recv_wr=0x%x\n", __func__,
1897                            attrs->cap.max_recv_wr + 1);
1898                 return status;
1899         }
1900         qp->rq.max_cnt = max_rqe_allocated;
1901         len = (hw_pages * hw_page_size);
1902
1903         qp->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
1904         if (!qp->rq.va)
1905                 return status;
1906         memset(qp->rq.va, 0, len);
1907         qp->rq.pa = pa;
1908         qp->rq.len = len;
1909         qp->rq.entry_size = dev->attr.rqe_size;
1910
1911         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
1912         cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1913                 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
1914         cmd->num_wq_rq_pages |=
1915             (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
1916             OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
1917         cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
1918                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
1919                                 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
1920         cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
1921                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
1922                                 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
1923         cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
1924                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
1925                         OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
1926         return 0;
1927 }
1928
1929 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
1930                                          struct ocrdma_pd *pd,
1931                                          struct ocrdma_qp *qp,
1932                                          u8 enable_dpp_cq, u16 dpp_cq_id)
1933 {
1934         pd->num_dpp_qp--;
1935         qp->dpp_enabled = true;
1936         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1937         if (!enable_dpp_cq)
1938                 return;
1939         cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
1940         cmd->dpp_credits_cqid = dpp_cq_id;
1941         cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
1942                                         OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
1943 }
1944
1945 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
1946                                         struct ocrdma_qp *qp)
1947 {
1948         struct ocrdma_dev *dev = qp->dev;
1949         struct pci_dev *pdev = dev->nic_info.pdev;
1950         dma_addr_t pa = 0;
1951         int ird_page_size = dev->attr.ird_page_size;
1952         int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
1953
1954         if (dev->attr.ird == 0)
1955                 return 0;
1956
1957         qp->ird_q_va = dma_alloc_coherent(&pdev->dev, ird_q_len,
1958                                         &pa, GFP_KERNEL);
1959         if (!qp->ird_q_va)
1960                 return -ENOMEM;
1961         memset(qp->ird_q_va, 0, ird_q_len);
1962         ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
1963                              pa, ird_page_size);
1964         return 0;
1965 }
1966
1967 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
1968                                      struct ocrdma_qp *qp,
1969                                      struct ib_qp_init_attr *attrs,
1970                                      u16 *dpp_offset, u16 *dpp_credit_lmt)
1971 {
1972         u32 max_wqe_allocated, max_rqe_allocated;
1973         qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
1974         qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
1975         qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
1976         qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
1977         qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
1978         qp->dpp_enabled = false;
1979         if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
1980                 qp->dpp_enabled = true;
1981                 *dpp_credit_lmt = (rsp->dpp_response &
1982                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
1983                                 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
1984                 *dpp_offset = (rsp->dpp_response &
1985                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
1986                                 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
1987         }
1988         max_wqe_allocated =
1989                 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
1990         max_wqe_allocated = 1 << max_wqe_allocated;
1991         max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
1992
1993         qp->sq.max_cnt = max_wqe_allocated;
1994         qp->sq.max_wqe_idx = max_wqe_allocated - 1;
1995
1996         if (!attrs->srq) {
1997                 qp->rq.max_cnt = max_rqe_allocated;
1998                 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
1999         }
2000 }
2001
2002 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2003                          u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2004                          u16 *dpp_credit_lmt)
2005 {
2006         int status = -ENOMEM;
2007         u32 flags = 0;
2008         struct ocrdma_dev *dev = qp->dev;
2009         struct ocrdma_pd *pd = qp->pd;
2010         struct pci_dev *pdev = dev->nic_info.pdev;
2011         struct ocrdma_cq *cq;
2012         struct ocrdma_create_qp_req *cmd;
2013         struct ocrdma_create_qp_rsp *rsp;
2014         int qptype;
2015
2016         switch (attrs->qp_type) {
2017         case IB_QPT_GSI:
2018                 qptype = OCRDMA_QPT_GSI;
2019                 break;
2020         case IB_QPT_RC:
2021                 qptype = OCRDMA_QPT_RC;
2022                 break;
2023         case IB_QPT_UD:
2024                 qptype = OCRDMA_QPT_UD;
2025                 break;
2026         default:
2027                 return -EINVAL;
2028         };
2029
2030         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2031         if (!cmd)
2032                 return status;
2033         cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2034                                                 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2035         status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2036         if (status)
2037                 goto sq_err;
2038
2039         if (attrs->srq) {
2040                 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2041                 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2042                 cmd->rq_addr[0].lo = srq->id;
2043                 qp->srq = srq;
2044         } else {
2045                 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2046                 if (status)
2047                         goto rq_err;
2048         }
2049
2050         status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2051         if (status)
2052                 goto mbx_err;
2053
2054         cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2055                                 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2056
2057         flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2058
2059         cmd->max_sge_recv_flags |= flags;
2060         cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2061                              OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2062                                 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2063         cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2064                              OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2065                                 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2066         cq = get_ocrdma_cq(attrs->send_cq);
2067         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2068                                 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2069         qp->sq_cq = cq;
2070         cq = get_ocrdma_cq(attrs->recv_cq);
2071         cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2072                                 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2073         qp->rq_cq = cq;
2074
2075         if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2076             (attrs->cap.max_inline_data <= dev->attr.max_inline_data))
2077                 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2078                                              dpp_cq_id);
2079
2080         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2081         if (status)
2082                 goto mbx_err;
2083         rsp = (struct ocrdma_create_qp_rsp *)cmd;
2084         ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2085         qp->state = OCRDMA_QPS_RST;
2086         kfree(cmd);
2087         return 0;
2088 mbx_err:
2089         if (qp->rq.va)
2090                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2091 rq_err:
2092         ocrdma_err("%s(%d) rq_err\n", __func__, dev->id);
2093         dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2094 sq_err:
2095         ocrdma_err("%s(%d) sq_err\n", __func__, dev->id);
2096         kfree(cmd);
2097         return status;
2098 }
2099
2100 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2101                         struct ocrdma_qp_params *param)
2102 {
2103         int status = -ENOMEM;
2104         struct ocrdma_query_qp *cmd;
2105         struct ocrdma_query_qp_rsp *rsp;
2106
2107         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*cmd));
2108         if (!cmd)
2109                 return status;
2110         cmd->qp_id = qp->id;
2111         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2112         if (status)
2113                 goto mbx_err;
2114         rsp = (struct ocrdma_query_qp_rsp *)cmd;
2115         memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2116 mbx_err:
2117         kfree(cmd);
2118         return status;
2119 }
2120
2121 int ocrdma_resolve_dgid(struct ocrdma_dev *dev, union ib_gid *dgid,
2122                         u8 *mac_addr)
2123 {
2124         struct in6_addr in6;
2125
2126         memcpy(&in6, dgid, sizeof in6);
2127         if (rdma_is_multicast_addr(&in6))
2128                 rdma_get_mcast_mac(&in6, mac_addr);
2129         else if (rdma_link_local_addr(&in6))
2130                 rdma_get_ll_mac(&in6, mac_addr);
2131         else {
2132                 ocrdma_err("%s() fail to resolve mac_addr.\n", __func__);
2133                 return -EINVAL;
2134         }
2135         return 0;
2136 }
2137
2138 static void ocrdma_set_av_params(struct ocrdma_qp *qp,
2139                                 struct ocrdma_modify_qp *cmd,
2140                                 struct ib_qp_attr *attrs)
2141 {
2142         struct ib_ah_attr *ah_attr = &attrs->ah_attr;
2143         union ib_gid sgid;
2144         u32 vlan_id;
2145         u8 mac_addr[6];
2146         if ((ah_attr->ah_flags & IB_AH_GRH) == 0)
2147                 return;
2148         cmd->params.tclass_sq_psn |=
2149             (ah_attr->grh.traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2150         cmd->params.rnt_rc_sl_fl |=
2151             (ah_attr->grh.flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2152         cmd->params.hop_lmt_rq_psn |=
2153             (ah_attr->grh.hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2154         cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2155         memcpy(&cmd->params.dgid[0], &ah_attr->grh.dgid.raw[0],
2156                sizeof(cmd->params.dgid));
2157         ocrdma_query_gid(&qp->dev->ibdev, 1,
2158                          ah_attr->grh.sgid_index, &sgid);
2159         qp->sgid_idx = ah_attr->grh.sgid_index;
2160         memcpy(&cmd->params.sgid[0], &sgid.raw[0], sizeof(cmd->params.sgid));
2161         ocrdma_resolve_dgid(qp->dev, &ah_attr->grh.dgid, &mac_addr[0]);
2162         cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2163                                 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2164         /* convert them to LE format. */
2165         ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2166         ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2167         cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2168         vlan_id = rdma_get_vlan_id(&sgid);
2169         if (vlan_id && (vlan_id < 0x1000)) {
2170                 cmd->params.vlan_dmac_b4_to_b5 |=
2171                     vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2172                 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2173         }
2174 }
2175
2176 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2177                                 struct ocrdma_modify_qp *cmd,
2178                                 struct ib_qp_attr *attrs, int attr_mask,
2179                                 enum ib_qp_state old_qps)
2180 {
2181         int status = 0;
2182         struct net_device *netdev = qp->dev->nic_info.netdev;
2183         int eth_mtu = iboe_get_mtu(netdev->mtu);
2184
2185         if (attr_mask & IB_QP_PKEY_INDEX) {
2186                 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2187                                             OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2188                 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2189         }
2190         if (attr_mask & IB_QP_QKEY) {
2191                 qp->qkey = attrs->qkey;
2192                 cmd->params.qkey = attrs->qkey;
2193                 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2194         }
2195         if (attr_mask & IB_QP_AV)
2196                 ocrdma_set_av_params(qp, cmd, attrs);
2197         else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2198                 /* set the default mac address for UD, GSI QPs */
2199                 cmd->params.dmac_b0_to_b3 = qp->dev->nic_info.mac_addr[0] |
2200                         (qp->dev->nic_info.mac_addr[1] << 8) |
2201                         (qp->dev->nic_info.mac_addr[2] << 16) |
2202                         (qp->dev->nic_info.mac_addr[3] << 24);
2203                 cmd->params.vlan_dmac_b4_to_b5 = qp->dev->nic_info.mac_addr[4] |
2204                                         (qp->dev->nic_info.mac_addr[5] << 8);
2205         }
2206         if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2207             attrs->en_sqd_async_notify) {
2208                 cmd->params.max_sge_recv_flags |=
2209                         OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2210                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2211         }
2212         if (attr_mask & IB_QP_DEST_QPN) {
2213                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2214                                 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2215                 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2216         }
2217         if (attr_mask & IB_QP_PATH_MTU) {
2218                 if (ib_mtu_enum_to_int(eth_mtu) <
2219                     ib_mtu_enum_to_int(attrs->path_mtu)) {
2220                         status = -EINVAL;
2221                         goto pmtu_err;
2222                 }
2223                 cmd->params.path_mtu_pkey_indx |=
2224                     (ib_mtu_enum_to_int(attrs->path_mtu) <<
2225                      OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2226                     OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2227                 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2228         }
2229         if (attr_mask & IB_QP_TIMEOUT) {
2230                 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2231                     OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2232                 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2233         }
2234         if (attr_mask & IB_QP_RETRY_CNT) {
2235                 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2236                                       OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2237                     OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2238                 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2239         }
2240         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2241                 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2242                                       OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2243                     OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2244                 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2245         }
2246         if (attr_mask & IB_QP_RNR_RETRY) {
2247                 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2248                         OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2249                         & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2250                 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2251         }
2252         if (attr_mask & IB_QP_SQ_PSN) {
2253                 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2254                 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2255         }
2256         if (attr_mask & IB_QP_RQ_PSN) {
2257                 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2258                 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2259         }
2260         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2261                 if (attrs->max_rd_atomic > qp->dev->attr.max_ord_per_qp) {
2262                         status = -EINVAL;
2263                         goto pmtu_err;
2264                 }
2265                 qp->max_ord = attrs->max_rd_atomic;
2266                 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2267         }
2268         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2269                 if (attrs->max_dest_rd_atomic > qp->dev->attr.max_ird_per_qp) {
2270                         status = -EINVAL;
2271                         goto pmtu_err;
2272                 }
2273                 qp->max_ird = attrs->max_dest_rd_atomic;
2274                 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2275         }
2276         cmd->params.max_ord_ird = (qp->max_ord <<
2277                                 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2278                                 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2279 pmtu_err:
2280         return status;
2281 }
2282
2283 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2284                          struct ib_qp_attr *attrs, int attr_mask,
2285                          enum ib_qp_state old_qps)
2286 {
2287         int status = -ENOMEM;
2288         struct ocrdma_modify_qp *cmd;
2289
2290         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2291         if (!cmd)
2292                 return status;
2293
2294         cmd->params.id = qp->id;
2295         cmd->flags = 0;
2296         if (attr_mask & IB_QP_STATE) {
2297                 cmd->params.max_sge_recv_flags |=
2298                     (get_ocrdma_qp_state(attrs->qp_state) <<
2299                      OCRDMA_QP_PARAMS_STATE_SHIFT) &
2300                     OCRDMA_QP_PARAMS_STATE_MASK;
2301                 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2302         } else
2303                 cmd->params.max_sge_recv_flags |=
2304                     (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2305                     OCRDMA_QP_PARAMS_STATE_MASK;
2306         status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask, old_qps);
2307         if (status)
2308                 goto mbx_err;
2309         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2310         if (status)
2311                 goto mbx_err;
2312
2313 mbx_err:
2314         kfree(cmd);
2315         return status;
2316 }
2317
2318 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2319 {
2320         int status = -ENOMEM;
2321         struct ocrdma_destroy_qp *cmd;
2322         struct pci_dev *pdev = dev->nic_info.pdev;
2323
2324         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2325         if (!cmd)
2326                 return status;
2327         cmd->qp_id = qp->id;
2328         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2329         if (status)
2330                 goto mbx_err;
2331
2332 mbx_err:
2333         kfree(cmd);
2334         if (qp->sq.va)
2335                 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2336         if (!qp->srq && qp->rq.va)
2337                 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2338         if (qp->dpp_enabled)
2339                 qp->pd->num_dpp_qp++;
2340         return status;
2341 }
2342
2343 int ocrdma_mbx_create_srq(struct ocrdma_srq *srq,
2344                           struct ib_srq_init_attr *srq_attr,
2345                           struct ocrdma_pd *pd)
2346 {
2347         int status = -ENOMEM;
2348         int hw_pages, hw_page_size;
2349         int len;
2350         struct ocrdma_create_srq_rsp *rsp;
2351         struct ocrdma_create_srq *cmd;
2352         dma_addr_t pa;
2353         struct ocrdma_dev *dev = srq->dev;
2354         struct pci_dev *pdev = dev->nic_info.pdev;
2355         u32 max_rqe_allocated;
2356
2357         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2358         if (!cmd)
2359                 return status;
2360
2361         cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2362         max_rqe_allocated = srq_attr->attr.max_wr + 1;
2363         status = ocrdma_build_q_conf(&max_rqe_allocated,
2364                                 dev->attr.rqe_size,
2365                                 &hw_pages, &hw_page_size);
2366         if (status) {
2367                 ocrdma_err("%s() req. max_wr=0x%x\n", __func__,
2368                            srq_attr->attr.max_wr);
2369                 status = -EINVAL;
2370                 goto ret;
2371         }
2372         len = hw_pages * hw_page_size;
2373         srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2374         if (!srq->rq.va) {
2375                 status = -ENOMEM;
2376                 goto ret;
2377         }
2378         ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2379
2380         srq->rq.entry_size = dev->attr.rqe_size;
2381         srq->rq.pa = pa;
2382         srq->rq.len = len;
2383         srq->rq.max_cnt = max_rqe_allocated;
2384
2385         cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2386         cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2387                                 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2388
2389         cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2390                 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2391         cmd->pages_rqe_sz |= (dev->attr.rqe_size
2392                 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2393                 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2394         cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2395
2396         status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2397         if (status)
2398                 goto mbx_err;
2399         rsp = (struct ocrdma_create_srq_rsp *)cmd;
2400         srq->id = rsp->id;
2401         srq->rq.dbid = rsp->id;
2402         max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2403                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2404                 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2405         max_rqe_allocated = (1 << max_rqe_allocated);
2406         srq->rq.max_cnt = max_rqe_allocated;
2407         srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2408         srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2409                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2410                 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2411         goto ret;
2412 mbx_err:
2413         dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2414 ret:
2415         kfree(cmd);
2416         return status;
2417 }
2418
2419 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2420 {
2421         int status = -ENOMEM;
2422         struct ocrdma_modify_srq *cmd;
2423         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2424         if (!cmd)
2425                 return status;
2426         cmd->id = srq->id;
2427         cmd->limit_max_rqe |= srq_attr->srq_limit <<
2428             OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2429         status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2430         kfree(cmd);
2431         return status;
2432 }
2433
2434 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2435 {
2436         int status = -ENOMEM;
2437         struct ocrdma_query_srq *cmd;
2438         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2439         if (!cmd)
2440                 return status;
2441         cmd->id = srq->rq.dbid;
2442         status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2443         if (status == 0) {
2444                 struct ocrdma_query_srq_rsp *rsp =
2445                     (struct ocrdma_query_srq_rsp *)cmd;
2446                 srq_attr->max_sge =
2447                     rsp->srq_lmt_max_sge &
2448                     OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2449                 srq_attr->max_wr =
2450                     rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2451                 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2452                     OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2453         }
2454         kfree(cmd);
2455         return status;
2456 }
2457
2458 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2459 {
2460         int status = -ENOMEM;
2461         struct ocrdma_destroy_srq *cmd;
2462         struct pci_dev *pdev = dev->nic_info.pdev;
2463         cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2464         if (!cmd)
2465                 return status;
2466         cmd->id = srq->id;
2467         status = ocrdma_mbx_cmd(srq->dev, (struct ocrdma_mqe *)cmd);
2468         if (srq->rq.va)
2469                 dma_free_coherent(&pdev->dev, srq->rq.len,
2470                                   srq->rq.va, srq->rq.pa);
2471         kfree(cmd);
2472         return status;
2473 }
2474
2475 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2476 {
2477         int i;
2478         int status = -EINVAL;
2479         struct ocrdma_av *av;
2480         unsigned long flags;
2481
2482         av = dev->av_tbl.va;
2483         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2484         for (i = 0; i < dev->av_tbl.num_ah; i++) {
2485                 if (av->valid == 0) {
2486                         av->valid = OCRDMA_AV_VALID;
2487                         ah->av = av;
2488                         ah->id = i;
2489                         status = 0;
2490                         break;
2491                 }
2492                 av++;
2493         }
2494         if (i == dev->av_tbl.num_ah)
2495                 status = -EAGAIN;
2496         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2497         return status;
2498 }
2499
2500 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
2501 {
2502         unsigned long flags;
2503         spin_lock_irqsave(&dev->av_tbl.lock, flags);
2504         ah->av->valid = 0;
2505         spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
2506         return 0;
2507 }
2508
2509 static int ocrdma_create_mq_eq(struct ocrdma_dev *dev)
2510 {
2511         int status;
2512         int irq;
2513         unsigned long flags = 0;
2514         int num_eq = 0;
2515
2516         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
2517                 flags = IRQF_SHARED;
2518         else {
2519                 num_eq = dev->nic_info.msix.num_vectors -
2520                                 dev->nic_info.msix.start_vector;
2521                 /* minimum two vectors/eq are required for rdma to work.
2522                  * one for control path and one for data path.
2523                  */
2524                 if (num_eq < 2)
2525                         return -EBUSY;
2526         }
2527
2528         status = ocrdma_create_eq(dev, &dev->meq, OCRDMA_EQ_LEN);
2529         if (status)
2530                 return status;
2531         sprintf(dev->meq.irq_name, "ocrdma_mq%d", dev->id);
2532         irq = ocrdma_get_irq(dev, &dev->meq);
2533         status = request_irq(irq, ocrdma_irq_handler, flags, dev->meq.irq_name,
2534                              &dev->meq);
2535         if (status)
2536                 _ocrdma_destroy_eq(dev, &dev->meq);
2537         return status;
2538 }
2539
2540 static int ocrdma_create_qp_eqs(struct ocrdma_dev *dev)
2541 {
2542         int num_eq, i, status = 0;
2543         int irq;
2544         unsigned long flags = 0;
2545
2546         num_eq = dev->nic_info.msix.num_vectors -
2547                         dev->nic_info.msix.start_vector;
2548         if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
2549                 num_eq = 1;
2550                 flags = IRQF_SHARED;
2551         } else
2552                 num_eq = min_t(u32, num_eq, num_online_cpus());
2553         dev->qp_eq_tbl = kzalloc(sizeof(struct ocrdma_eq) * num_eq, GFP_KERNEL);
2554         if (!dev->qp_eq_tbl)
2555                 return -ENOMEM;
2556
2557         for (i = 0; i < num_eq; i++) {
2558                 status = ocrdma_create_eq(dev, &dev->qp_eq_tbl[i],
2559                                           OCRDMA_EQ_LEN);
2560                 if (status) {
2561                         status = -EINVAL;
2562                         break;
2563                 }
2564                 sprintf(dev->qp_eq_tbl[i].irq_name, "ocrdma_qp%d-%d",
2565                         dev->id, i);
2566                 irq = ocrdma_get_irq(dev, &dev->qp_eq_tbl[i]);
2567                 status = request_irq(irq, ocrdma_irq_handler, flags,
2568                                      dev->qp_eq_tbl[i].irq_name,
2569                                      &dev->qp_eq_tbl[i]);
2570                 if (status) {
2571                         _ocrdma_destroy_eq(dev, &dev->qp_eq_tbl[i]);
2572                         status = -EINVAL;
2573                         break;
2574                 }
2575                 dev->eq_cnt += 1;
2576         }
2577         /* one eq is sufficient for data path to work */
2578         if (dev->eq_cnt >= 1)
2579                 return 0;
2580         if (status)
2581                 ocrdma_destroy_qp_eqs(dev);
2582         return status;
2583 }
2584
2585 int ocrdma_init_hw(struct ocrdma_dev *dev)
2586 {
2587         int status;
2588         /* set up control path eq */
2589         status = ocrdma_create_mq_eq(dev);
2590         if (status)
2591                 return status;
2592         /* set up data path eq */
2593         status = ocrdma_create_qp_eqs(dev);
2594         if (status)
2595                 goto qpeq_err;
2596         status = ocrdma_create_mq(dev);
2597         if (status)
2598                 goto mq_err;
2599         status = ocrdma_mbx_query_fw_config(dev);
2600         if (status)
2601                 goto conf_err;
2602         status = ocrdma_mbx_query_dev(dev);
2603         if (status)
2604                 goto conf_err;
2605         status = ocrdma_mbx_query_fw_ver(dev);
2606         if (status)
2607                 goto conf_err;
2608         status = ocrdma_mbx_create_ah_tbl(dev);
2609         if (status)
2610                 goto conf_err;
2611         return 0;
2612
2613 conf_err:
2614         ocrdma_destroy_mq(dev);
2615 mq_err:
2616         ocrdma_destroy_qp_eqs(dev);
2617 qpeq_err:
2618         ocrdma_destroy_eq(dev, &dev->meq);
2619         ocrdma_err("%s() status=%d\n", __func__, status);
2620         return status;
2621 }
2622
2623 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
2624 {
2625         ocrdma_mbx_delete_ah_tbl(dev);
2626
2627         /* cleanup the data path eqs */
2628         ocrdma_destroy_qp_eqs(dev);
2629
2630         /* cleanup the control path */
2631         ocrdma_destroy_mq(dev);
2632         ocrdma_destroy_eq(dev, &dev->meq);
2633 }