2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
59 #define LOOP_TIMEOUT 100000
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
78 * 512GB Pages are not supported due to a hardware bug
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
88 LIST_HEAD(ioapic_map);
90 LIST_HEAD(acpihid_map);
92 #define FLUSH_QUEUE_SIZE 256
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
97 struct dma_ops_domain *dma_dom;
103 struct flush_queue_entry *entries;
106 DEFINE_PER_CPU(struct flush_queue, flush_queue);
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
115 static const struct iommu_ops amd_iommu_ops;
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
120 static struct dma_map_ops amd_iommu_dma_ops;
123 * This struct contains device specific data for the IOMMU
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
139 u32 errata; /* Bitmap for errata to apply */
143 * general struct to manage commands send to an IOMMU
149 struct kmem_cache *amd_iommu_irq_cache;
151 static void update_domain(struct protection_domain *domain);
152 static int protection_domain_init(struct protection_domain *domain);
153 static void detach_device(struct device *dev);
156 * Data container for a dma_ops specific protection domain
158 struct dma_ops_domain {
159 /* generic protection domain information */
160 struct protection_domain domain;
163 struct iova_domain iovad;
166 static struct iova_domain reserved_iova_ranges;
167 static struct lock_class_key reserved_rbtree_key;
169 /****************************************************************************
173 ****************************************************************************/
175 static inline int match_hid_uid(struct device *dev,
176 struct acpihid_map_entry *entry)
178 const char *hid, *uid;
180 hid = acpi_device_hid(ACPI_COMPANION(dev));
181 uid = acpi_device_uid(ACPI_COMPANION(dev));
187 return strcmp(hid, entry->hid);
190 return strcmp(hid, entry->hid);
192 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
195 static inline u16 get_pci_device_id(struct device *dev)
197 struct pci_dev *pdev = to_pci_dev(dev);
199 return PCI_DEVID(pdev->bus->number, pdev->devfn);
202 static inline int get_acpihid_device_id(struct device *dev,
203 struct acpihid_map_entry **entry)
205 struct acpihid_map_entry *p;
207 list_for_each_entry(p, &acpihid_map, list) {
208 if (!match_hid_uid(dev, p)) {
217 static inline int get_device_id(struct device *dev)
222 devid = get_pci_device_id(dev);
224 devid = get_acpihid_device_id(dev, NULL);
229 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
231 return container_of(dom, struct protection_domain, domain);
234 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
236 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
237 return container_of(domain, struct dma_ops_domain, domain);
240 static struct iommu_dev_data *alloc_dev_data(u16 devid)
242 struct iommu_dev_data *dev_data;
245 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
249 dev_data->devid = devid;
251 spin_lock_irqsave(&dev_data_list_lock, flags);
252 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
253 spin_unlock_irqrestore(&dev_data_list_lock, flags);
258 static struct iommu_dev_data *search_dev_data(u16 devid)
260 struct iommu_dev_data *dev_data;
263 spin_lock_irqsave(&dev_data_list_lock, flags);
264 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
265 if (dev_data->devid == devid)
272 spin_unlock_irqrestore(&dev_data_list_lock, flags);
277 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
279 *(u16 *)data = alias;
283 static u16 get_alias(struct device *dev)
285 struct pci_dev *pdev = to_pci_dev(dev);
286 u16 devid, ivrs_alias, pci_alias;
288 /* The callers make sure that get_device_id() does not fail here */
289 devid = get_device_id(dev);
290 ivrs_alias = amd_iommu_alias_table[devid];
291 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
293 if (ivrs_alias == pci_alias)
299 * The IVRS is fairly reliable in telling us about aliases, but it
300 * can't know about every screwy device. If we don't have an IVRS
301 * reported alias, use the PCI reported alias. In that case we may
302 * still need to initialize the rlookup and dev_table entries if the
303 * alias is to a non-existent device.
305 if (ivrs_alias == devid) {
306 if (!amd_iommu_rlookup_table[pci_alias]) {
307 amd_iommu_rlookup_table[pci_alias] =
308 amd_iommu_rlookup_table[devid];
309 memcpy(amd_iommu_dev_table[pci_alias].data,
310 amd_iommu_dev_table[devid].data,
311 sizeof(amd_iommu_dev_table[pci_alias].data));
317 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
318 "for device %s[%04x:%04x], kernel reported alias "
319 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
320 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
321 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
322 PCI_FUNC(pci_alias));
325 * If we don't have a PCI DMA alias and the IVRS alias is on the same
326 * bus, then the IVRS table may know about a quirk that we don't.
328 if (pci_alias == devid &&
329 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
330 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
331 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
332 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
339 static struct iommu_dev_data *find_dev_data(u16 devid)
341 struct iommu_dev_data *dev_data;
343 dev_data = search_dev_data(devid);
345 if (dev_data == NULL)
346 dev_data = alloc_dev_data(devid);
351 static struct iommu_dev_data *get_dev_data(struct device *dev)
353 return dev->archdata.iommu;
357 * Find or create an IOMMU group for a acpihid device.
359 static struct iommu_group *acpihid_device_group(struct device *dev)
361 struct acpihid_map_entry *p, *entry = NULL;
364 devid = get_acpihid_device_id(dev, &entry);
366 return ERR_PTR(devid);
368 list_for_each_entry(p, &acpihid_map, list) {
369 if ((devid == p->devid) && p->group)
370 entry->group = p->group;
374 entry->group = generic_device_group(dev);
379 static bool pci_iommuv2_capable(struct pci_dev *pdev)
381 static const int caps[] = {
384 PCI_EXT_CAP_ID_PASID,
388 for (i = 0; i < 3; ++i) {
389 pos = pci_find_ext_capability(pdev, caps[i]);
397 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
399 struct iommu_dev_data *dev_data;
401 dev_data = get_dev_data(&pdev->dev);
403 return dev_data->errata & (1 << erratum) ? true : false;
407 * This function checks if the driver got a valid device from the caller to
408 * avoid dereferencing invalid pointers.
410 static bool check_device(struct device *dev)
414 if (!dev || !dev->dma_mask)
417 devid = get_device_id(dev);
421 /* Out of our scope? */
422 if (devid > amd_iommu_last_bdf)
425 if (amd_iommu_rlookup_table[devid] == NULL)
431 static void init_iommu_group(struct device *dev)
433 struct iommu_group *group;
435 group = iommu_group_get_for_dev(dev);
439 iommu_group_put(group);
442 static int iommu_init_device(struct device *dev)
444 struct iommu_dev_data *dev_data;
447 if (dev->archdata.iommu)
450 devid = get_device_id(dev);
454 dev_data = find_dev_data(devid);
458 dev_data->alias = get_alias(dev);
460 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
461 struct amd_iommu *iommu;
463 iommu = amd_iommu_rlookup_table[dev_data->devid];
464 dev_data->iommu_v2 = iommu->is_iommu_v2;
467 dev->archdata.iommu = dev_data;
469 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
475 static void iommu_ignore_device(struct device *dev)
480 devid = get_device_id(dev);
484 alias = get_alias(dev);
486 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
487 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
489 amd_iommu_rlookup_table[devid] = NULL;
490 amd_iommu_rlookup_table[alias] = NULL;
493 static void iommu_uninit_device(struct device *dev)
496 struct iommu_dev_data *dev_data;
498 devid = get_device_id(dev);
502 dev_data = search_dev_data(devid);
506 if (dev_data->domain)
509 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
512 iommu_group_remove_device(dev);
515 dev->archdata.dma_ops = NULL;
518 * We keep dev_data around for unplugged devices and reuse it when the
519 * device is re-plugged - not doing so would introduce a ton of races.
523 /****************************************************************************
525 * Interrupt handling functions
527 ****************************************************************************/
529 static void dump_dte_entry(u16 devid)
533 for (i = 0; i < 4; ++i)
534 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
535 amd_iommu_dev_table[devid].data[i]);
538 static void dump_command(unsigned long phys_addr)
540 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
543 for (i = 0; i < 4; ++i)
544 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
547 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 int type, devid, domid, flags;
550 volatile u32 *event = __evt;
555 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
556 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
557 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
558 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
559 address = (u64)(((u64)event[3]) << 32) | event[2];
562 /* Did we hit the erratum? */
563 if (++count == LOOP_TIMEOUT) {
564 pr_err("AMD-Vi: No event written to event log\n");
571 printk(KERN_ERR "AMD-Vi: Event logged [");
574 case EVENT_TYPE_ILL_DEV:
575 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
576 "address=0x%016llx flags=0x%04x]\n",
577 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
579 dump_dte_entry(devid);
581 case EVENT_TYPE_IO_FAULT:
582 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
583 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
584 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
585 domid, address, flags);
587 case EVENT_TYPE_DEV_TAB_ERR:
588 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
589 "address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
593 case EVENT_TYPE_PAGE_TAB_ERR:
594 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
595 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
596 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
597 domid, address, flags);
599 case EVENT_TYPE_ILL_CMD:
600 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
601 dump_command(address);
603 case EVENT_TYPE_CMD_HARD_ERR:
604 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
605 "flags=0x%04x]\n", address, flags);
607 case EVENT_TYPE_IOTLB_INV_TO:
608 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
609 "address=0x%016llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
613 case EVENT_TYPE_INV_DEV_REQ:
614 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
615 "address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
620 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
623 memset(__evt, 0, 4 * sizeof(u32));
626 static void iommu_poll_events(struct amd_iommu *iommu)
630 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
631 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
633 while (head != tail) {
634 iommu_print_event(iommu, iommu->evt_buf + head);
635 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
638 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
641 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
643 struct amd_iommu_fault fault;
645 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
646 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
650 fault.address = raw[1];
651 fault.pasid = PPR_PASID(raw[0]);
652 fault.device_id = PPR_DEVID(raw[0]);
653 fault.tag = PPR_TAG(raw[0]);
654 fault.flags = PPR_FLAGS(raw[0]);
656 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
659 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
663 if (iommu->ppr_log == NULL)
666 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
669 while (head != tail) {
674 raw = (u64 *)(iommu->ppr_log + head);
677 * Hardware bug: Interrupt may arrive before the entry is
678 * written to memory. If this happens we need to wait for the
681 for (i = 0; i < LOOP_TIMEOUT; ++i) {
682 if (PPR_REQ_TYPE(raw[0]) != 0)
687 /* Avoid memcpy function-call overhead */
692 * To detect the hardware bug we need to clear the entry
695 raw[0] = raw[1] = 0UL;
697 /* Update head pointer of hardware ring-buffer */
698 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
699 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
701 /* Handle PPR entry */
702 iommu_handle_ppr_entry(iommu, entry);
704 /* Refresh ring-buffer information */
705 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
706 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
710 irqreturn_t amd_iommu_int_thread(int irq, void *data)
712 struct amd_iommu *iommu = (struct amd_iommu *) data;
713 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
715 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
716 /* Enable EVT and PPR interrupts again */
717 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
718 iommu->mmio_base + MMIO_STATUS_OFFSET);
720 if (status & MMIO_STATUS_EVT_INT_MASK) {
721 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
722 iommu_poll_events(iommu);
725 if (status & MMIO_STATUS_PPR_INT_MASK) {
726 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
727 iommu_poll_ppr_log(iommu);
731 * Hardware bug: ERBT1312
732 * When re-enabling interrupt (by writing 1
733 * to clear the bit), the hardware might also try to set
734 * the interrupt bit in the event status register.
735 * In this scenario, the bit will be set, and disable
736 * subsequent interrupts.
738 * Workaround: The IOMMU driver should read back the
739 * status register and check if the interrupt bits are cleared.
740 * If not, driver will need to go through the interrupt handler
741 * again and re-clear the bits
743 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
748 irqreturn_t amd_iommu_int_handler(int irq, void *data)
750 return IRQ_WAKE_THREAD;
753 /****************************************************************************
755 * IOMMU command queuing functions
757 ****************************************************************************/
759 static int wait_on_sem(volatile u64 *sem)
763 while (*sem == 0 && i < LOOP_TIMEOUT) {
768 if (i == LOOP_TIMEOUT) {
769 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
776 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
777 struct iommu_cmd *cmd,
782 target = iommu->cmd_buf + tail;
783 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
785 /* Copy command to buffer */
786 memcpy(target, cmd, sizeof(*cmd));
788 /* Tell the IOMMU about it */
789 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
792 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
794 WARN_ON(address & 0x7ULL);
796 memset(cmd, 0, sizeof(*cmd));
797 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
798 cmd->data[1] = upper_32_bits(__pa(address));
800 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
803 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
805 memset(cmd, 0, sizeof(*cmd));
806 cmd->data[0] = devid;
807 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
810 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
811 size_t size, u16 domid, int pde)
816 pages = iommu_num_pages(address, size, PAGE_SIZE);
821 * If we have to flush more than one page, flush all
822 * TLB entries for this domain
824 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
828 address &= PAGE_MASK;
830 memset(cmd, 0, sizeof(*cmd));
831 cmd->data[1] |= domid;
832 cmd->data[2] = lower_32_bits(address);
833 cmd->data[3] = upper_32_bits(address);
834 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
835 if (s) /* size bit - we flush more than one 4kb page */
836 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
837 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
838 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
841 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
842 u64 address, size_t size)
847 pages = iommu_num_pages(address, size, PAGE_SIZE);
852 * If we have to flush more than one page, flush all
853 * TLB entries for this domain
855 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
859 address &= PAGE_MASK;
861 memset(cmd, 0, sizeof(*cmd));
862 cmd->data[0] = devid;
863 cmd->data[0] |= (qdep & 0xff) << 24;
864 cmd->data[1] = devid;
865 cmd->data[2] = lower_32_bits(address);
866 cmd->data[3] = upper_32_bits(address);
867 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
869 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
872 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
873 u64 address, bool size)
875 memset(cmd, 0, sizeof(*cmd));
877 address &= ~(0xfffULL);
879 cmd->data[0] = pasid;
880 cmd->data[1] = domid;
881 cmd->data[2] = lower_32_bits(address);
882 cmd->data[3] = upper_32_bits(address);
883 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
884 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
886 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
887 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
890 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
891 int qdep, u64 address, bool size)
893 memset(cmd, 0, sizeof(*cmd));
895 address &= ~(0xfffULL);
897 cmd->data[0] = devid;
898 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
899 cmd->data[0] |= (qdep & 0xff) << 24;
900 cmd->data[1] = devid;
901 cmd->data[1] |= (pasid & 0xff) << 16;
902 cmd->data[2] = lower_32_bits(address);
903 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
904 cmd->data[3] = upper_32_bits(address);
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
907 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
910 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
911 int status, int tag, bool gn)
913 memset(cmd, 0, sizeof(*cmd));
915 cmd->data[0] = devid;
917 cmd->data[1] = pasid;
918 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
920 cmd->data[3] = tag & 0x1ff;
921 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
923 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
926 static void build_inv_all(struct iommu_cmd *cmd)
928 memset(cmd, 0, sizeof(*cmd));
929 CMD_SET_TYPE(cmd, CMD_INV_ALL);
932 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
934 memset(cmd, 0, sizeof(*cmd));
935 cmd->data[0] = devid;
936 CMD_SET_TYPE(cmd, CMD_INV_IRT);
940 * Writes the command to the IOMMUs command buffer and informs the
941 * hardware about the new command.
943 static int iommu_queue_command_sync(struct amd_iommu *iommu,
944 struct iommu_cmd *cmd,
947 u32 left, tail, head, next_tail;
951 spin_lock_irqsave(&iommu->lock, flags);
953 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
954 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
955 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
956 left = (head - next_tail) % CMD_BUFFER_SIZE;
959 struct iommu_cmd sync_cmd;
960 volatile u64 sem = 0;
963 build_completion_wait(&sync_cmd, (u64)&sem);
964 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
966 spin_unlock_irqrestore(&iommu->lock, flags);
968 if ((ret = wait_on_sem(&sem)) != 0)
974 copy_cmd_to_buffer(iommu, cmd, tail);
976 /* We need to sync now to make sure all commands are processed */
977 iommu->need_sync = sync;
979 spin_unlock_irqrestore(&iommu->lock, flags);
984 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
986 return iommu_queue_command_sync(iommu, cmd, true);
990 * This function queues a completion wait command into the command
993 static int iommu_completion_wait(struct amd_iommu *iommu)
995 struct iommu_cmd cmd;
996 volatile u64 sem = 0;
999 if (!iommu->need_sync)
1002 build_completion_wait(&cmd, (u64)&sem);
1004 ret = iommu_queue_command_sync(iommu, &cmd, false);
1008 return wait_on_sem(&sem);
1011 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1013 struct iommu_cmd cmd;
1015 build_inv_dte(&cmd, devid);
1017 return iommu_queue_command(iommu, &cmd);
1020 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1024 for (devid = 0; devid <= 0xffff; ++devid)
1025 iommu_flush_dte(iommu, devid);
1027 iommu_completion_wait(iommu);
1031 * This function uses heavy locking and may disable irqs for some time. But
1032 * this is no issue because it is only called during resume.
1034 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1038 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1039 struct iommu_cmd cmd;
1040 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1042 iommu_queue_command(iommu, &cmd);
1045 iommu_completion_wait(iommu);
1048 static void iommu_flush_all(struct amd_iommu *iommu)
1050 struct iommu_cmd cmd;
1052 build_inv_all(&cmd);
1054 iommu_queue_command(iommu, &cmd);
1055 iommu_completion_wait(iommu);
1058 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1060 struct iommu_cmd cmd;
1062 build_inv_irt(&cmd, devid);
1064 iommu_queue_command(iommu, &cmd);
1067 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1071 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1072 iommu_flush_irt(iommu, devid);
1074 iommu_completion_wait(iommu);
1077 void iommu_flush_all_caches(struct amd_iommu *iommu)
1079 if (iommu_feature(iommu, FEATURE_IA)) {
1080 iommu_flush_all(iommu);
1082 iommu_flush_dte_all(iommu);
1083 iommu_flush_irt_all(iommu);
1084 iommu_flush_tlb_all(iommu);
1089 * Command send function for flushing on-device TLB
1091 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1092 u64 address, size_t size)
1094 struct amd_iommu *iommu;
1095 struct iommu_cmd cmd;
1098 qdep = dev_data->ats.qdep;
1099 iommu = amd_iommu_rlookup_table[dev_data->devid];
1101 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1103 return iommu_queue_command(iommu, &cmd);
1107 * Command send function for invalidating a device table entry
1109 static int device_flush_dte(struct iommu_dev_data *dev_data)
1111 struct amd_iommu *iommu;
1115 iommu = amd_iommu_rlookup_table[dev_data->devid];
1116 alias = dev_data->alias;
1118 ret = iommu_flush_dte(iommu, dev_data->devid);
1119 if (!ret && alias != dev_data->devid)
1120 ret = iommu_flush_dte(iommu, alias);
1124 if (dev_data->ats.enabled)
1125 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1131 * TLB invalidation function which is called from the mapping functions.
1132 * It invalidates a single PTE if the range to flush is within a single
1133 * page. Otherwise it flushes the whole TLB of the IOMMU.
1135 static void __domain_flush_pages(struct protection_domain *domain,
1136 u64 address, size_t size, int pde)
1138 struct iommu_dev_data *dev_data;
1139 struct iommu_cmd cmd;
1142 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1144 for (i = 0; i < amd_iommus_present; ++i) {
1145 if (!domain->dev_iommu[i])
1149 * Devices of this domain are behind this IOMMU
1150 * We need a TLB flush
1152 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1155 list_for_each_entry(dev_data, &domain->dev_list, list) {
1157 if (!dev_data->ats.enabled)
1160 ret |= device_flush_iotlb(dev_data, address, size);
1166 static void domain_flush_pages(struct protection_domain *domain,
1167 u64 address, size_t size)
1169 __domain_flush_pages(domain, address, size, 0);
1172 /* Flush the whole IO/TLB for a given protection domain */
1173 static void domain_flush_tlb(struct protection_domain *domain)
1175 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1178 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1179 static void domain_flush_tlb_pde(struct protection_domain *domain)
1181 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1184 static void domain_flush_complete(struct protection_domain *domain)
1188 for (i = 0; i < amd_iommus_present; ++i) {
1189 if (domain && !domain->dev_iommu[i])
1193 * Devices of this domain are behind this IOMMU
1194 * We need to wait for completion of all commands.
1196 iommu_completion_wait(amd_iommus[i]);
1202 * This function flushes the DTEs for all devices in domain
1204 static void domain_flush_devices(struct protection_domain *domain)
1206 struct iommu_dev_data *dev_data;
1208 list_for_each_entry(dev_data, &domain->dev_list, list)
1209 device_flush_dte(dev_data);
1212 /****************************************************************************
1214 * The functions below are used the create the page table mappings for
1215 * unity mapped regions.
1217 ****************************************************************************/
1220 * This function is used to add another level to an IO page table. Adding
1221 * another level increases the size of the address space by 9 bits to a size up
1224 static bool increase_address_space(struct protection_domain *domain,
1229 if (domain->mode == PAGE_MODE_6_LEVEL)
1230 /* address space already 64 bit large */
1233 pte = (void *)get_zeroed_page(gfp);
1237 *pte = PM_LEVEL_PDE(domain->mode,
1238 virt_to_phys(domain->pt_root));
1239 domain->pt_root = pte;
1241 domain->updated = true;
1246 static u64 *alloc_pte(struct protection_domain *domain,
1247 unsigned long address,
1248 unsigned long page_size,
1255 BUG_ON(!is_power_of_2(page_size));
1257 while (address > PM_LEVEL_SIZE(domain->mode))
1258 increase_address_space(domain, gfp);
1260 level = domain->mode - 1;
1261 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1262 address = PAGE_SIZE_ALIGN(address, page_size);
1263 end_lvl = PAGE_SIZE_LEVEL(page_size);
1265 while (level > end_lvl) {
1270 if (!IOMMU_PTE_PRESENT(__pte)) {
1271 page = (u64 *)get_zeroed_page(gfp);
1275 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1277 if (cmpxchg64(pte, __pte, __npte)) {
1278 free_page((unsigned long)page);
1283 /* No level skipping support yet */
1284 if (PM_PTE_LEVEL(*pte) != level)
1289 pte = IOMMU_PTE_PAGE(*pte);
1291 if (pte_page && level == end_lvl)
1294 pte = &pte[PM_LEVEL_INDEX(level, address)];
1301 * This function checks if there is a PTE for a given dma address. If
1302 * there is one, it returns the pointer to it.
1304 static u64 *fetch_pte(struct protection_domain *domain,
1305 unsigned long address,
1306 unsigned long *page_size)
1311 if (address > PM_LEVEL_SIZE(domain->mode))
1314 level = domain->mode - 1;
1315 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1316 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1321 if (!IOMMU_PTE_PRESENT(*pte))
1325 if (PM_PTE_LEVEL(*pte) == 7 ||
1326 PM_PTE_LEVEL(*pte) == 0)
1329 /* No level skipping support yet */
1330 if (PM_PTE_LEVEL(*pte) != level)
1335 /* Walk to the next level */
1336 pte = IOMMU_PTE_PAGE(*pte);
1337 pte = &pte[PM_LEVEL_INDEX(level, address)];
1338 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1341 if (PM_PTE_LEVEL(*pte) == 0x07) {
1342 unsigned long pte_mask;
1345 * If we have a series of large PTEs, make
1346 * sure to return a pointer to the first one.
1348 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1349 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1350 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1357 * Generic mapping functions. It maps a physical address into a DMA
1358 * address space. It allocates the page table pages if necessary.
1359 * In the future it can be extended to a generic mapping function
1360 * supporting all features of AMD IOMMU page tables like level skipping
1361 * and full 64 bit address spaces.
1363 static int iommu_map_page(struct protection_domain *dom,
1364 unsigned long bus_addr,
1365 unsigned long phys_addr,
1366 unsigned long page_size,
1373 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1374 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1376 if (!(prot & IOMMU_PROT_MASK))
1379 count = PAGE_SIZE_PTE_COUNT(page_size);
1380 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1385 for (i = 0; i < count; ++i)
1386 if (IOMMU_PTE_PRESENT(pte[i]))
1390 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1391 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1393 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1395 if (prot & IOMMU_PROT_IR)
1396 __pte |= IOMMU_PTE_IR;
1397 if (prot & IOMMU_PROT_IW)
1398 __pte |= IOMMU_PTE_IW;
1400 for (i = 0; i < count; ++i)
1408 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1409 unsigned long bus_addr,
1410 unsigned long page_size)
1412 unsigned long long unmapped;
1413 unsigned long unmap_size;
1416 BUG_ON(!is_power_of_2(page_size));
1420 while (unmapped < page_size) {
1422 pte = fetch_pte(dom, bus_addr, &unmap_size);
1427 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1428 for (i = 0; i < count; i++)
1432 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1433 unmapped += unmap_size;
1436 BUG_ON(unmapped && !is_power_of_2(unmapped));
1441 /****************************************************************************
1443 * The next functions belong to the address allocator for the dma_ops
1444 * interface functions.
1446 ****************************************************************************/
1449 static unsigned long dma_ops_alloc_iova(struct device *dev,
1450 struct dma_ops_domain *dma_dom,
1451 unsigned int pages, u64 dma_mask)
1453 unsigned long pfn = 0;
1455 pages = __roundup_pow_of_two(pages);
1457 if (dma_mask > DMA_BIT_MASK(32))
1458 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1459 IOVA_PFN(DMA_BIT_MASK(32)));
1462 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1464 return (pfn << PAGE_SHIFT);
1467 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1468 unsigned long address,
1471 pages = __roundup_pow_of_two(pages);
1472 address >>= PAGE_SHIFT;
1474 free_iova_fast(&dma_dom->iovad, address, pages);
1477 /****************************************************************************
1479 * The next functions belong to the domain allocation. A domain is
1480 * allocated for every IOMMU as the default domain. If device isolation
1481 * is enabled, every device get its own domain. The most important thing
1482 * about domains is the page table mapping the DMA address space they
1485 ****************************************************************************/
1488 * This function adds a protection domain to the global protection domain list
1490 static void add_domain_to_list(struct protection_domain *domain)
1492 unsigned long flags;
1494 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1495 list_add(&domain->list, &amd_iommu_pd_list);
1496 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1500 * This function removes a protection domain to the global
1501 * protection domain list
1503 static void del_domain_from_list(struct protection_domain *domain)
1505 unsigned long flags;
1507 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1508 list_del(&domain->list);
1509 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1512 static u16 domain_id_alloc(void)
1514 unsigned long flags;
1517 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1518 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1520 if (id > 0 && id < MAX_DOMAIN_ID)
1521 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1524 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1529 static void domain_id_free(int id)
1531 unsigned long flags;
1533 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1534 if (id > 0 && id < MAX_DOMAIN_ID)
1535 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1536 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1539 #define DEFINE_FREE_PT_FN(LVL, FN) \
1540 static void free_pt_##LVL (unsigned long __pt) \
1548 for (i = 0; i < 512; ++i) { \
1549 /* PTE present? */ \
1550 if (!IOMMU_PTE_PRESENT(pt[i])) \
1554 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1555 PM_PTE_LEVEL(pt[i]) == 7) \
1558 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1561 free_page((unsigned long)pt); \
1564 DEFINE_FREE_PT_FN(l2, free_page)
1565 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1566 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1567 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1568 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1570 static void free_pagetable(struct protection_domain *domain)
1572 unsigned long root = (unsigned long)domain->pt_root;
1574 switch (domain->mode) {
1575 case PAGE_MODE_NONE:
1577 case PAGE_MODE_1_LEVEL:
1580 case PAGE_MODE_2_LEVEL:
1583 case PAGE_MODE_3_LEVEL:
1586 case PAGE_MODE_4_LEVEL:
1589 case PAGE_MODE_5_LEVEL:
1592 case PAGE_MODE_6_LEVEL:
1600 static void free_gcr3_tbl_level1(u64 *tbl)
1605 for (i = 0; i < 512; ++i) {
1606 if (!(tbl[i] & GCR3_VALID))
1609 ptr = __va(tbl[i] & PAGE_MASK);
1611 free_page((unsigned long)ptr);
1615 static void free_gcr3_tbl_level2(u64 *tbl)
1620 for (i = 0; i < 512; ++i) {
1621 if (!(tbl[i] & GCR3_VALID))
1624 ptr = __va(tbl[i] & PAGE_MASK);
1626 free_gcr3_tbl_level1(ptr);
1630 static void free_gcr3_table(struct protection_domain *domain)
1632 if (domain->glx == 2)
1633 free_gcr3_tbl_level2(domain->gcr3_tbl);
1634 else if (domain->glx == 1)
1635 free_gcr3_tbl_level1(domain->gcr3_tbl);
1637 BUG_ON(domain->glx != 0);
1639 free_page((unsigned long)domain->gcr3_tbl);
1643 * Free a domain, only used if something went wrong in the
1644 * allocation path and we need to free an already allocated page table
1646 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1651 del_domain_from_list(&dom->domain);
1653 put_iova_domain(&dom->iovad);
1655 free_pagetable(&dom->domain);
1661 * Allocates a new protection domain usable for the dma_ops functions.
1662 * It also initializes the page table and the address allocator data
1663 * structures required for the dma_ops interface
1665 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1667 struct dma_ops_domain *dma_dom;
1669 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1673 if (protection_domain_init(&dma_dom->domain))
1676 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1677 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1678 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1679 if (!dma_dom->domain.pt_root)
1682 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1683 IOVA_START_PFN, DMA_32BIT_PFN);
1685 /* Initialize reserved ranges */
1686 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1688 add_domain_to_list(&dma_dom->domain);
1693 dma_ops_domain_free(dma_dom);
1699 * little helper function to check whether a given protection domain is a
1702 static bool dma_ops_domain(struct protection_domain *domain)
1704 return domain->flags & PD_DMA_OPS_MASK;
1707 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1712 if (domain->mode != PAGE_MODE_NONE)
1713 pte_root = virt_to_phys(domain->pt_root);
1715 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1716 << DEV_ENTRY_MODE_SHIFT;
1717 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1719 flags = amd_iommu_dev_table[devid].data[1];
1722 flags |= DTE_FLAG_IOTLB;
1724 if (domain->flags & PD_IOMMUV2_MASK) {
1725 u64 gcr3 = __pa(domain->gcr3_tbl);
1726 u64 glx = domain->glx;
1729 pte_root |= DTE_FLAG_GV;
1730 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1732 /* First mask out possible old values for GCR3 table */
1733 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1736 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1739 /* Encode GCR3 table into DTE */
1740 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1743 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1746 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1750 flags &= ~(0xffffUL);
1751 flags |= domain->id;
1753 amd_iommu_dev_table[devid].data[1] = flags;
1754 amd_iommu_dev_table[devid].data[0] = pte_root;
1757 static void clear_dte_entry(u16 devid)
1759 /* remove entry from the device table seen by the hardware */
1760 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1761 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1763 amd_iommu_apply_erratum_63(devid);
1766 static void do_attach(struct iommu_dev_data *dev_data,
1767 struct protection_domain *domain)
1769 struct amd_iommu *iommu;
1773 iommu = amd_iommu_rlookup_table[dev_data->devid];
1774 alias = dev_data->alias;
1775 ats = dev_data->ats.enabled;
1777 /* Update data structures */
1778 dev_data->domain = domain;
1779 list_add(&dev_data->list, &domain->dev_list);
1781 /* Do reference counting */
1782 domain->dev_iommu[iommu->index] += 1;
1783 domain->dev_cnt += 1;
1785 /* Update device table */
1786 set_dte_entry(dev_data->devid, domain, ats);
1787 if (alias != dev_data->devid)
1788 set_dte_entry(alias, domain, ats);
1790 device_flush_dte(dev_data);
1793 static void do_detach(struct iommu_dev_data *dev_data)
1795 struct amd_iommu *iommu;
1799 * First check if the device is still attached. It might already
1800 * be detached from its domain because the generic
1801 * iommu_detach_group code detached it and we try again here in
1802 * our alias handling.
1804 if (!dev_data->domain)
1807 iommu = amd_iommu_rlookup_table[dev_data->devid];
1808 alias = dev_data->alias;
1810 /* decrease reference counters */
1811 dev_data->domain->dev_iommu[iommu->index] -= 1;
1812 dev_data->domain->dev_cnt -= 1;
1814 /* Update data structures */
1815 dev_data->domain = NULL;
1816 list_del(&dev_data->list);
1817 clear_dte_entry(dev_data->devid);
1818 if (alias != dev_data->devid)
1819 clear_dte_entry(alias);
1821 /* Flush the DTE entry */
1822 device_flush_dte(dev_data);
1826 * If a device is not yet associated with a domain, this function does
1827 * assigns it visible for the hardware
1829 static int __attach_device(struct iommu_dev_data *dev_data,
1830 struct protection_domain *domain)
1835 * Must be called with IRQs disabled. Warn here to detect early
1838 WARN_ON(!irqs_disabled());
1841 spin_lock(&domain->lock);
1844 if (dev_data->domain != NULL)
1847 /* Attach alias group root */
1848 do_attach(dev_data, domain);
1855 spin_unlock(&domain->lock);
1861 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1863 pci_disable_ats(pdev);
1864 pci_disable_pri(pdev);
1865 pci_disable_pasid(pdev);
1868 /* FIXME: Change generic reset-function to do the same */
1869 static int pri_reset_while_enabled(struct pci_dev *pdev)
1874 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1878 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1879 control |= PCI_PRI_CTRL_RESET;
1880 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1885 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1890 /* FIXME: Hardcode number of outstanding requests for now */
1892 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1894 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1896 /* Only allow access to user-accessible pages */
1897 ret = pci_enable_pasid(pdev, 0);
1901 /* First reset the PRI state of the device */
1902 ret = pci_reset_pri(pdev);
1907 ret = pci_enable_pri(pdev, reqs);
1912 ret = pri_reset_while_enabled(pdev);
1917 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1924 pci_disable_pri(pdev);
1925 pci_disable_pasid(pdev);
1930 /* FIXME: Move this to PCI code */
1931 #define PCI_PRI_TLP_OFF (1 << 15)
1933 static bool pci_pri_tlp_required(struct pci_dev *pdev)
1938 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1942 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
1944 return (status & PCI_PRI_TLP_OFF) ? true : false;
1948 * If a device is not yet associated with a domain, this function
1949 * assigns it visible for the hardware
1951 static int attach_device(struct device *dev,
1952 struct protection_domain *domain)
1954 struct pci_dev *pdev;
1955 struct iommu_dev_data *dev_data;
1956 unsigned long flags;
1959 dev_data = get_dev_data(dev);
1961 if (!dev_is_pci(dev))
1962 goto skip_ats_check;
1964 pdev = to_pci_dev(dev);
1965 if (domain->flags & PD_IOMMUV2_MASK) {
1966 if (!dev_data->passthrough)
1969 if (dev_data->iommu_v2) {
1970 if (pdev_iommuv2_enable(pdev) != 0)
1973 dev_data->ats.enabled = true;
1974 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1975 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
1977 } else if (amd_iommu_iotlb_sup &&
1978 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1979 dev_data->ats.enabled = true;
1980 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1984 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1985 ret = __attach_device(dev_data, domain);
1986 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1989 * We might boot into a crash-kernel here. The crashed kernel
1990 * left the caches in the IOMMU dirty. So we have to flush
1991 * here to evict all dirty stuff.
1993 domain_flush_tlb_pde(domain);
1999 * Removes a device from a protection domain (unlocked)
2001 static void __detach_device(struct iommu_dev_data *dev_data)
2003 struct protection_domain *domain;
2006 * Must be called with IRQs disabled. Warn here to detect early
2009 WARN_ON(!irqs_disabled());
2011 if (WARN_ON(!dev_data->domain))
2014 domain = dev_data->domain;
2016 spin_lock(&domain->lock);
2018 do_detach(dev_data);
2020 spin_unlock(&domain->lock);
2024 * Removes a device from a protection domain (with devtable_lock held)
2026 static void detach_device(struct device *dev)
2028 struct protection_domain *domain;
2029 struct iommu_dev_data *dev_data;
2030 unsigned long flags;
2032 dev_data = get_dev_data(dev);
2033 domain = dev_data->domain;
2035 /* lock device table */
2036 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2037 __detach_device(dev_data);
2038 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2040 if (!dev_is_pci(dev))
2043 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2044 pdev_iommuv2_disable(to_pci_dev(dev));
2045 else if (dev_data->ats.enabled)
2046 pci_disable_ats(to_pci_dev(dev));
2048 dev_data->ats.enabled = false;
2051 static int amd_iommu_add_device(struct device *dev)
2053 struct iommu_dev_data *dev_data;
2054 struct iommu_domain *domain;
2055 struct amd_iommu *iommu;
2058 if (!check_device(dev) || get_dev_data(dev))
2061 devid = get_device_id(dev);
2065 iommu = amd_iommu_rlookup_table[devid];
2067 ret = iommu_init_device(dev);
2069 if (ret != -ENOTSUPP)
2070 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2073 iommu_ignore_device(dev);
2074 dev->archdata.dma_ops = &nommu_dma_ops;
2077 init_iommu_group(dev);
2079 dev_data = get_dev_data(dev);
2083 if (iommu_pass_through || dev_data->iommu_v2)
2084 iommu_request_dm_for_dev(dev);
2086 /* Domains are initialized for this device - have a look what we ended up with */
2087 domain = iommu_get_domain_for_dev(dev);
2088 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2089 dev_data->passthrough = true;
2091 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2094 iommu_completion_wait(iommu);
2099 static void amd_iommu_remove_device(struct device *dev)
2101 struct amd_iommu *iommu;
2104 if (!check_device(dev))
2107 devid = get_device_id(dev);
2111 iommu = amd_iommu_rlookup_table[devid];
2113 iommu_uninit_device(dev);
2114 iommu_completion_wait(iommu);
2117 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2119 if (dev_is_pci(dev))
2120 return pci_device_group(dev);
2122 return acpihid_device_group(dev);
2125 /*****************************************************************************
2127 * The next functions belong to the dma_ops mapping/unmapping code.
2129 *****************************************************************************/
2131 static void __queue_flush(struct flush_queue *queue)
2133 struct protection_domain *domain;
2134 unsigned long flags;
2137 /* First flush TLB of all known domains */
2138 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2139 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2140 domain_flush_tlb(domain);
2141 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2143 /* Wait until flushes have completed */
2144 domain_flush_complete(NULL);
2146 for (idx = 0; idx < queue->next; ++idx) {
2147 struct flush_queue_entry *entry;
2149 entry = queue->entries + idx;
2151 free_iova_fast(&entry->dma_dom->iovad,
2155 /* Not really necessary, just to make sure we catch any bugs */
2156 entry->dma_dom = NULL;
2162 static void queue_flush_all(void)
2166 for_each_possible_cpu(cpu) {
2167 struct flush_queue *queue;
2168 unsigned long flags;
2170 queue = per_cpu_ptr(&flush_queue, cpu);
2171 spin_lock_irqsave(&queue->lock, flags);
2172 if (queue->next > 0)
2173 __queue_flush(queue);
2174 spin_unlock_irqrestore(&queue->lock, flags);
2178 static void queue_flush_timeout(unsigned long unsused)
2180 atomic_set(&queue_timer_on, 0);
2184 static void queue_add(struct dma_ops_domain *dma_dom,
2185 unsigned long address, unsigned long pages)
2187 struct flush_queue_entry *entry;
2188 struct flush_queue *queue;
2189 unsigned long flags;
2192 pages = __roundup_pow_of_two(pages);
2193 address >>= PAGE_SHIFT;
2195 queue = get_cpu_ptr(&flush_queue);
2196 spin_lock_irqsave(&queue->lock, flags);
2198 if (queue->next == FLUSH_QUEUE_SIZE)
2199 __queue_flush(queue);
2201 idx = queue->next++;
2202 entry = queue->entries + idx;
2204 entry->iova_pfn = address;
2205 entry->pages = pages;
2206 entry->dma_dom = dma_dom;
2208 spin_unlock_irqrestore(&queue->lock, flags);
2210 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2211 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2213 put_cpu_ptr(&flush_queue);
2218 * In the dma_ops path we only have the struct device. This function
2219 * finds the corresponding IOMMU, the protection domain and the
2220 * requestor id for a given device.
2221 * If the device is not yet associated with a domain this is also done
2224 static struct protection_domain *get_domain(struct device *dev)
2226 struct protection_domain *domain;
2228 if (!check_device(dev))
2229 return ERR_PTR(-EINVAL);
2231 domain = get_dev_data(dev)->domain;
2232 if (!dma_ops_domain(domain))
2233 return ERR_PTR(-EBUSY);
2238 static void update_device_table(struct protection_domain *domain)
2240 struct iommu_dev_data *dev_data;
2242 list_for_each_entry(dev_data, &domain->dev_list, list)
2243 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2246 static void update_domain(struct protection_domain *domain)
2248 if (!domain->updated)
2251 update_device_table(domain);
2253 domain_flush_devices(domain);
2254 domain_flush_tlb_pde(domain);
2256 domain->updated = false;
2259 static int dir2prot(enum dma_data_direction direction)
2261 if (direction == DMA_TO_DEVICE)
2262 return IOMMU_PROT_IR;
2263 else if (direction == DMA_FROM_DEVICE)
2264 return IOMMU_PROT_IW;
2265 else if (direction == DMA_BIDIRECTIONAL)
2266 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2271 * This function contains common code for mapping of a physically
2272 * contiguous memory region into DMA address space. It is used by all
2273 * mapping functions provided with this IOMMU driver.
2274 * Must be called with the domain lock held.
2276 static dma_addr_t __map_single(struct device *dev,
2277 struct dma_ops_domain *dma_dom,
2280 enum dma_data_direction direction,
2283 dma_addr_t offset = paddr & ~PAGE_MASK;
2284 dma_addr_t address, start, ret;
2289 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2292 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2293 if (address == DMA_ERROR_CODE)
2296 prot = dir2prot(direction);
2299 for (i = 0; i < pages; ++i) {
2300 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2301 PAGE_SIZE, prot, GFP_ATOMIC);
2310 if (unlikely(amd_iommu_np_cache)) {
2311 domain_flush_pages(&dma_dom->domain, address, size);
2312 domain_flush_complete(&dma_dom->domain);
2320 for (--i; i >= 0; --i) {
2322 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2325 domain_flush_tlb(&dma_dom->domain);
2326 domain_flush_complete(&dma_dom->domain);
2328 dma_ops_free_iova(dma_dom, address, pages);
2330 return DMA_ERROR_CODE;
2334 * Does the reverse of the __map_single function. Must be called with
2335 * the domain lock held too
2337 static void __unmap_single(struct dma_ops_domain *dma_dom,
2338 dma_addr_t dma_addr,
2342 dma_addr_t flush_addr;
2343 dma_addr_t i, start;
2346 flush_addr = dma_addr;
2347 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2348 dma_addr &= PAGE_MASK;
2351 for (i = 0; i < pages; ++i) {
2352 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2356 if (amd_iommu_unmap_flush) {
2357 dma_ops_free_iova(dma_dom, dma_addr, pages);
2358 domain_flush_tlb(&dma_dom->domain);
2359 domain_flush_complete(&dma_dom->domain);
2361 queue_add(dma_dom, dma_addr, pages);
2366 * The exported map_single function for dma_ops.
2368 static dma_addr_t map_page(struct device *dev, struct page *page,
2369 unsigned long offset, size_t size,
2370 enum dma_data_direction dir,
2371 struct dma_attrs *attrs)
2373 phys_addr_t paddr = page_to_phys(page) + offset;
2374 struct protection_domain *domain;
2375 struct dma_ops_domain *dma_dom;
2378 domain = get_domain(dev);
2379 if (PTR_ERR(domain) == -EINVAL)
2380 return (dma_addr_t)paddr;
2381 else if (IS_ERR(domain))
2382 return DMA_ERROR_CODE;
2384 dma_mask = *dev->dma_mask;
2385 dma_dom = to_dma_ops_domain(domain);
2387 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2391 * The exported unmap_single function for dma_ops.
2393 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2394 enum dma_data_direction dir, struct dma_attrs *attrs)
2396 struct protection_domain *domain;
2397 struct dma_ops_domain *dma_dom;
2399 domain = get_domain(dev);
2403 dma_dom = to_dma_ops_domain(domain);
2405 __unmap_single(dma_dom, dma_addr, size, dir);
2408 static int sg_num_pages(struct device *dev,
2409 struct scatterlist *sglist,
2412 unsigned long mask, boundary_size;
2413 struct scatterlist *s;
2416 mask = dma_get_seg_boundary(dev);
2417 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2418 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2420 for_each_sg(sglist, s, nelems, i) {
2423 s->dma_address = npages << PAGE_SHIFT;
2424 p = npages % boundary_size;
2425 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2426 if (p + n > boundary_size)
2427 npages += boundary_size - p;
2435 * The exported map_sg function for dma_ops (handles scatter-gather
2438 static int map_sg(struct device *dev, struct scatterlist *sglist,
2439 int nelems, enum dma_data_direction direction,
2440 struct dma_attrs *attrs)
2442 int mapped_pages = 0, npages = 0, prot = 0, i;
2443 struct protection_domain *domain;
2444 struct dma_ops_domain *dma_dom;
2445 struct scatterlist *s;
2446 unsigned long address;
2449 domain = get_domain(dev);
2453 dma_dom = to_dma_ops_domain(domain);
2454 dma_mask = *dev->dma_mask;
2456 npages = sg_num_pages(dev, sglist, nelems);
2458 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2459 if (address == DMA_ERROR_CODE)
2462 prot = dir2prot(direction);
2464 /* Map all sg entries */
2465 for_each_sg(sglist, s, nelems, i) {
2466 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2468 for (j = 0; j < pages; ++j) {
2469 unsigned long bus_addr, phys_addr;
2472 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2473 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2474 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2482 /* Everything is mapped - write the right values into s->dma_address */
2483 for_each_sg(sglist, s, nelems, i) {
2484 s->dma_address += address + s->offset;
2485 s->dma_length = s->length;
2491 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2492 dev_name(dev), npages);
2494 for_each_sg(sglist, s, nelems, i) {
2495 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2497 for (j = 0; j < pages; ++j) {
2498 unsigned long bus_addr;
2500 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2501 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2509 free_iova_fast(&dma_dom->iovad, address, npages);
2516 * The exported map_sg function for dma_ops (handles scatter-gather
2519 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2520 int nelems, enum dma_data_direction dir,
2521 struct dma_attrs *attrs)
2523 struct protection_domain *domain;
2524 struct dma_ops_domain *dma_dom;
2525 unsigned long startaddr;
2528 domain = get_domain(dev);
2532 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2533 dma_dom = to_dma_ops_domain(domain);
2534 npages = sg_num_pages(dev, sglist, nelems);
2536 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2540 * The exported alloc_coherent function for dma_ops.
2542 static void *alloc_coherent(struct device *dev, size_t size,
2543 dma_addr_t *dma_addr, gfp_t flag,
2544 struct dma_attrs *attrs)
2546 u64 dma_mask = dev->coherent_dma_mask;
2547 struct protection_domain *domain;
2548 struct dma_ops_domain *dma_dom;
2551 domain = get_domain(dev);
2552 if (PTR_ERR(domain) == -EINVAL) {
2553 page = alloc_pages(flag, get_order(size));
2554 *dma_addr = page_to_phys(page);
2555 return page_address(page);
2556 } else if (IS_ERR(domain))
2559 dma_dom = to_dma_ops_domain(domain);
2560 size = PAGE_ALIGN(size);
2561 dma_mask = dev->coherent_dma_mask;
2562 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2565 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2567 if (!gfpflags_allow_blocking(flag))
2570 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2577 dma_mask = *dev->dma_mask;
2579 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2580 size, DMA_BIDIRECTIONAL, dma_mask);
2582 if (*dma_addr == DMA_ERROR_CODE)
2585 return page_address(page);
2589 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2590 __free_pages(page, get_order(size));
2596 * The exported free_coherent function for dma_ops.
2598 static void free_coherent(struct device *dev, size_t size,
2599 void *virt_addr, dma_addr_t dma_addr,
2600 struct dma_attrs *attrs)
2602 struct protection_domain *domain;
2603 struct dma_ops_domain *dma_dom;
2606 page = virt_to_page(virt_addr);
2607 size = PAGE_ALIGN(size);
2609 domain = get_domain(dev);
2613 dma_dom = to_dma_ops_domain(domain);
2615 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2618 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2619 __free_pages(page, get_order(size));
2623 * This function is called by the DMA layer to find out if we can handle a
2624 * particular device. It is part of the dma_ops.
2626 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2628 return check_device(dev);
2631 static struct dma_map_ops amd_iommu_dma_ops = {
2632 .alloc = alloc_coherent,
2633 .free = free_coherent,
2634 .map_page = map_page,
2635 .unmap_page = unmap_page,
2637 .unmap_sg = unmap_sg,
2638 .dma_supported = amd_iommu_dma_supported,
2641 static int init_reserved_iova_ranges(void)
2643 struct pci_dev *pdev = NULL;
2646 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2647 IOVA_START_PFN, DMA_32BIT_PFN);
2649 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2650 &reserved_rbtree_key);
2652 /* MSI memory range */
2653 val = reserve_iova(&reserved_iova_ranges,
2654 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2656 pr_err("Reserving MSI range failed\n");
2660 /* HT memory range */
2661 val = reserve_iova(&reserved_iova_ranges,
2662 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2664 pr_err("Reserving HT range failed\n");
2669 * Memory used for PCI resources
2670 * FIXME: Check whether we can reserve the PCI-hole completly
2672 for_each_pci_dev(pdev) {
2675 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2676 struct resource *r = &pdev->resource[i];
2678 if (!(r->flags & IORESOURCE_MEM))
2681 val = reserve_iova(&reserved_iova_ranges,
2685 pr_err("Reserve pci-resource range failed\n");
2694 int __init amd_iommu_init_api(void)
2696 int ret, cpu, err = 0;
2698 ret = iova_cache_get();
2702 ret = init_reserved_iova_ranges();
2706 for_each_possible_cpu(cpu) {
2707 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2709 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2710 sizeof(*queue->entries),
2712 if (!queue->entries)
2715 spin_lock_init(&queue->lock);
2718 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2721 #ifdef CONFIG_ARM_AMBA
2722 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2726 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2732 for_each_possible_cpu(cpu) {
2733 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2735 kfree(queue->entries);
2741 int __init amd_iommu_init_dma_ops(void)
2743 setup_timer(&queue_timer, queue_flush_timeout, 0);
2744 atomic_set(&queue_timer_on, 0);
2746 swiotlb = iommu_pass_through ? 1 : 0;
2750 * In case we don't initialize SWIOTLB (actually the common case
2751 * when AMD IOMMU is enabled), make sure there are global
2752 * dma_ops set as a fall-back for devices not handled by this
2753 * driver (for example non-PCI devices).
2756 dma_ops = &nommu_dma_ops;
2758 if (amd_iommu_unmap_flush)
2759 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2761 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2767 /*****************************************************************************
2769 * The following functions belong to the exported interface of AMD IOMMU
2771 * This interface allows access to lower level functions of the IOMMU
2772 * like protection domain handling and assignement of devices to domains
2773 * which is not possible with the dma_ops interface.
2775 *****************************************************************************/
2777 static void cleanup_domain(struct protection_domain *domain)
2779 struct iommu_dev_data *entry;
2780 unsigned long flags;
2782 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2784 while (!list_empty(&domain->dev_list)) {
2785 entry = list_first_entry(&domain->dev_list,
2786 struct iommu_dev_data, list);
2787 __detach_device(entry);
2790 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2793 static void protection_domain_free(struct protection_domain *domain)
2798 del_domain_from_list(domain);
2801 domain_id_free(domain->id);
2806 static int protection_domain_init(struct protection_domain *domain)
2808 spin_lock_init(&domain->lock);
2809 mutex_init(&domain->api_lock);
2810 domain->id = domain_id_alloc();
2813 INIT_LIST_HEAD(&domain->dev_list);
2818 static struct protection_domain *protection_domain_alloc(void)
2820 struct protection_domain *domain;
2822 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2826 if (protection_domain_init(domain))
2829 add_domain_to_list(domain);
2839 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2841 struct protection_domain *pdomain;
2842 struct dma_ops_domain *dma_domain;
2845 case IOMMU_DOMAIN_UNMANAGED:
2846 pdomain = protection_domain_alloc();
2850 pdomain->mode = PAGE_MODE_3_LEVEL;
2851 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2852 if (!pdomain->pt_root) {
2853 protection_domain_free(pdomain);
2857 pdomain->domain.geometry.aperture_start = 0;
2858 pdomain->domain.geometry.aperture_end = ~0ULL;
2859 pdomain->domain.geometry.force_aperture = true;
2862 case IOMMU_DOMAIN_DMA:
2863 dma_domain = dma_ops_domain_alloc();
2865 pr_err("AMD-Vi: Failed to allocate\n");
2868 pdomain = &dma_domain->domain;
2870 case IOMMU_DOMAIN_IDENTITY:
2871 pdomain = protection_domain_alloc();
2875 pdomain->mode = PAGE_MODE_NONE;
2881 return &pdomain->domain;
2884 static void amd_iommu_domain_free(struct iommu_domain *dom)
2886 struct protection_domain *domain;
2887 struct dma_ops_domain *dma_dom;
2889 domain = to_pdomain(dom);
2891 if (domain->dev_cnt > 0)
2892 cleanup_domain(domain);
2894 BUG_ON(domain->dev_cnt != 0);
2899 switch (dom->type) {
2900 case IOMMU_DOMAIN_DMA:
2902 * First make sure the domain is no longer referenced from the
2907 /* Now release the domain */
2908 dma_dom = to_dma_ops_domain(domain);
2909 dma_ops_domain_free(dma_dom);
2912 if (domain->mode != PAGE_MODE_NONE)
2913 free_pagetable(domain);
2915 if (domain->flags & PD_IOMMUV2_MASK)
2916 free_gcr3_table(domain);
2918 protection_domain_free(domain);
2923 static void amd_iommu_detach_device(struct iommu_domain *dom,
2926 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2927 struct amd_iommu *iommu;
2930 if (!check_device(dev))
2933 devid = get_device_id(dev);
2937 if (dev_data->domain != NULL)
2940 iommu = amd_iommu_rlookup_table[devid];
2944 iommu_completion_wait(iommu);
2947 static int amd_iommu_attach_device(struct iommu_domain *dom,
2950 struct protection_domain *domain = to_pdomain(dom);
2951 struct iommu_dev_data *dev_data;
2952 struct amd_iommu *iommu;
2955 if (!check_device(dev))
2958 dev_data = dev->archdata.iommu;
2960 iommu = amd_iommu_rlookup_table[dev_data->devid];
2964 if (dev_data->domain)
2967 ret = attach_device(dev, domain);
2969 iommu_completion_wait(iommu);
2974 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2975 phys_addr_t paddr, size_t page_size, int iommu_prot)
2977 struct protection_domain *domain = to_pdomain(dom);
2981 if (domain->mode == PAGE_MODE_NONE)
2984 if (iommu_prot & IOMMU_READ)
2985 prot |= IOMMU_PROT_IR;
2986 if (iommu_prot & IOMMU_WRITE)
2987 prot |= IOMMU_PROT_IW;
2989 mutex_lock(&domain->api_lock);
2990 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
2991 mutex_unlock(&domain->api_lock);
2996 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2999 struct protection_domain *domain = to_pdomain(dom);
3002 if (domain->mode == PAGE_MODE_NONE)
3005 mutex_lock(&domain->api_lock);
3006 unmap_size = iommu_unmap_page(domain, iova, page_size);
3007 mutex_unlock(&domain->api_lock);
3009 domain_flush_tlb_pde(domain);
3014 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3017 struct protection_domain *domain = to_pdomain(dom);
3018 unsigned long offset_mask, pte_pgsize;
3021 if (domain->mode == PAGE_MODE_NONE)
3024 pte = fetch_pte(domain, iova, &pte_pgsize);
3026 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3029 offset_mask = pte_pgsize - 1;
3030 __pte = *pte & PM_ADDR_MASK;
3032 return (__pte & ~offset_mask) | (iova & offset_mask);
3035 static bool amd_iommu_capable(enum iommu_cap cap)
3038 case IOMMU_CAP_CACHE_COHERENCY:
3040 case IOMMU_CAP_INTR_REMAP:
3041 return (irq_remapping_enabled == 1);
3042 case IOMMU_CAP_NOEXEC:
3049 static void amd_iommu_get_dm_regions(struct device *dev,
3050 struct list_head *head)
3052 struct unity_map_entry *entry;
3055 devid = get_device_id(dev);
3059 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3060 struct iommu_dm_region *region;
3062 if (devid < entry->devid_start || devid > entry->devid_end)
3065 region = kzalloc(sizeof(*region), GFP_KERNEL);
3067 pr_err("Out of memory allocating dm-regions for %s\n",
3072 region->start = entry->address_start;
3073 region->length = entry->address_end - entry->address_start;
3074 if (entry->prot & IOMMU_PROT_IR)
3075 region->prot |= IOMMU_READ;
3076 if (entry->prot & IOMMU_PROT_IW)
3077 region->prot |= IOMMU_WRITE;
3079 list_add_tail(®ion->list, head);
3083 static void amd_iommu_put_dm_regions(struct device *dev,
3084 struct list_head *head)
3086 struct iommu_dm_region *entry, *next;
3088 list_for_each_entry_safe(entry, next, head, list)
3092 static void amd_iommu_apply_dm_region(struct device *dev,
3093 struct iommu_domain *domain,
3094 struct iommu_dm_region *region)
3096 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3097 unsigned long start, end;
3099 start = IOVA_PFN(region->start);
3100 end = IOVA_PFN(region->start + region->length);
3102 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3105 static const struct iommu_ops amd_iommu_ops = {
3106 .capable = amd_iommu_capable,
3107 .domain_alloc = amd_iommu_domain_alloc,
3108 .domain_free = amd_iommu_domain_free,
3109 .attach_dev = amd_iommu_attach_device,
3110 .detach_dev = amd_iommu_detach_device,
3111 .map = amd_iommu_map,
3112 .unmap = amd_iommu_unmap,
3113 .map_sg = default_iommu_map_sg,
3114 .iova_to_phys = amd_iommu_iova_to_phys,
3115 .add_device = amd_iommu_add_device,
3116 .remove_device = amd_iommu_remove_device,
3117 .device_group = amd_iommu_device_group,
3118 .get_dm_regions = amd_iommu_get_dm_regions,
3119 .put_dm_regions = amd_iommu_put_dm_regions,
3120 .apply_dm_region = amd_iommu_apply_dm_region,
3121 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3124 /*****************************************************************************
3126 * The next functions do a basic initialization of IOMMU for pass through
3129 * In passthrough mode the IOMMU is initialized and enabled but not used for
3130 * DMA-API translation.
3132 *****************************************************************************/
3134 /* IOMMUv2 specific functions */
3135 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3137 return atomic_notifier_chain_register(&ppr_notifier, nb);
3139 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3141 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3143 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3145 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3147 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3149 struct protection_domain *domain = to_pdomain(dom);
3150 unsigned long flags;
3152 spin_lock_irqsave(&domain->lock, flags);
3154 /* Update data structure */
3155 domain->mode = PAGE_MODE_NONE;
3156 domain->updated = true;
3158 /* Make changes visible to IOMMUs */
3159 update_domain(domain);
3161 /* Page-table is not visible to IOMMU anymore, so free it */
3162 free_pagetable(domain);
3164 spin_unlock_irqrestore(&domain->lock, flags);
3166 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3168 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3170 struct protection_domain *domain = to_pdomain(dom);
3171 unsigned long flags;
3174 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3177 /* Number of GCR3 table levels required */
3178 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3181 if (levels > amd_iommu_max_glx_val)
3184 spin_lock_irqsave(&domain->lock, flags);
3187 * Save us all sanity checks whether devices already in the
3188 * domain support IOMMUv2. Just force that the domain has no
3189 * devices attached when it is switched into IOMMUv2 mode.
3192 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3196 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3197 if (domain->gcr3_tbl == NULL)
3200 domain->glx = levels;
3201 domain->flags |= PD_IOMMUV2_MASK;
3202 domain->updated = true;
3204 update_domain(domain);
3209 spin_unlock_irqrestore(&domain->lock, flags);
3213 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3215 static int __flush_pasid(struct protection_domain *domain, int pasid,
3216 u64 address, bool size)
3218 struct iommu_dev_data *dev_data;
3219 struct iommu_cmd cmd;
3222 if (!(domain->flags & PD_IOMMUV2_MASK))
3225 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3228 * IOMMU TLB needs to be flushed before Device TLB to
3229 * prevent device TLB refill from IOMMU TLB
3231 for (i = 0; i < amd_iommus_present; ++i) {
3232 if (domain->dev_iommu[i] == 0)
3235 ret = iommu_queue_command(amd_iommus[i], &cmd);
3240 /* Wait until IOMMU TLB flushes are complete */
3241 domain_flush_complete(domain);
3243 /* Now flush device TLBs */
3244 list_for_each_entry(dev_data, &domain->dev_list, list) {
3245 struct amd_iommu *iommu;
3249 There might be non-IOMMUv2 capable devices in an IOMMUv2
3252 if (!dev_data->ats.enabled)
3255 qdep = dev_data->ats.qdep;
3256 iommu = amd_iommu_rlookup_table[dev_data->devid];
3258 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3259 qdep, address, size);
3261 ret = iommu_queue_command(iommu, &cmd);
3266 /* Wait until all device TLBs are flushed */
3267 domain_flush_complete(domain);
3276 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3279 return __flush_pasid(domain, pasid, address, false);
3282 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3285 struct protection_domain *domain = to_pdomain(dom);
3286 unsigned long flags;
3289 spin_lock_irqsave(&domain->lock, flags);
3290 ret = __amd_iommu_flush_page(domain, pasid, address);
3291 spin_unlock_irqrestore(&domain->lock, flags);
3295 EXPORT_SYMBOL(amd_iommu_flush_page);
3297 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3299 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3303 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3305 struct protection_domain *domain = to_pdomain(dom);
3306 unsigned long flags;
3309 spin_lock_irqsave(&domain->lock, flags);
3310 ret = __amd_iommu_flush_tlb(domain, pasid);
3311 spin_unlock_irqrestore(&domain->lock, flags);
3315 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3317 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3324 index = (pasid >> (9 * level)) & 0x1ff;
3330 if (!(*pte & GCR3_VALID)) {
3334 root = (void *)get_zeroed_page(GFP_ATOMIC);
3338 *pte = __pa(root) | GCR3_VALID;
3341 root = __va(*pte & PAGE_MASK);
3349 static int __set_gcr3(struct protection_domain *domain, int pasid,
3354 if (domain->mode != PAGE_MODE_NONE)
3357 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3361 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3363 return __amd_iommu_flush_tlb(domain, pasid);
3366 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3370 if (domain->mode != PAGE_MODE_NONE)
3373 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3379 return __amd_iommu_flush_tlb(domain, pasid);
3382 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3385 struct protection_domain *domain = to_pdomain(dom);
3386 unsigned long flags;
3389 spin_lock_irqsave(&domain->lock, flags);
3390 ret = __set_gcr3(domain, pasid, cr3);
3391 spin_unlock_irqrestore(&domain->lock, flags);
3395 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3397 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3399 struct protection_domain *domain = to_pdomain(dom);
3400 unsigned long flags;
3403 spin_lock_irqsave(&domain->lock, flags);
3404 ret = __clear_gcr3(domain, pasid);
3405 spin_unlock_irqrestore(&domain->lock, flags);
3409 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3411 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3412 int status, int tag)
3414 struct iommu_dev_data *dev_data;
3415 struct amd_iommu *iommu;
3416 struct iommu_cmd cmd;
3418 dev_data = get_dev_data(&pdev->dev);
3419 iommu = amd_iommu_rlookup_table[dev_data->devid];
3421 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3422 tag, dev_data->pri_tlp);
3424 return iommu_queue_command(iommu, &cmd);
3426 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3428 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3430 struct protection_domain *pdomain;
3432 pdomain = get_domain(&pdev->dev);
3433 if (IS_ERR(pdomain))
3436 /* Only return IOMMUv2 domains */
3437 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3440 return &pdomain->domain;
3442 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3444 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3446 struct iommu_dev_data *dev_data;
3448 if (!amd_iommu_v2_supported())
3451 dev_data = get_dev_data(&pdev->dev);
3452 dev_data->errata |= (1 << erratum);
3454 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3456 int amd_iommu_device_info(struct pci_dev *pdev,
3457 struct amd_iommu_device_info *info)
3462 if (pdev == NULL || info == NULL)
3465 if (!amd_iommu_v2_supported())
3468 memset(info, 0, sizeof(*info));
3470 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3472 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3474 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3476 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3478 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3482 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3483 max_pasids = min(max_pasids, (1 << 20));
3485 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3486 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3488 features = pci_pasid_features(pdev);
3489 if (features & PCI_PASID_CAP_EXEC)
3490 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3491 if (features & PCI_PASID_CAP_PRIV)
3492 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3497 EXPORT_SYMBOL(amd_iommu_device_info);
3499 #ifdef CONFIG_IRQ_REMAP
3501 /*****************************************************************************
3503 * Interrupt Remapping Implementation
3505 *****************************************************************************/
3523 u16 devid; /* Device ID for IRTE table */
3524 u16 index; /* Index into IRTE table*/
3527 struct amd_ir_data {
3528 struct irq_2_irte irq_2_irte;
3529 union irte irte_entry;
3531 struct msi_msg msi_entry;
3535 static struct irq_chip amd_ir_chip;
3537 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3538 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3539 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3540 #define DTE_IRQ_REMAP_ENABLE 1ULL
3542 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3546 dte = amd_iommu_dev_table[devid].data[2];
3547 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3548 dte |= virt_to_phys(table->table);
3549 dte |= DTE_IRQ_REMAP_INTCTL;
3550 dte |= DTE_IRQ_TABLE_LEN;
3551 dte |= DTE_IRQ_REMAP_ENABLE;
3553 amd_iommu_dev_table[devid].data[2] = dte;
3556 #define IRTE_ALLOCATED (~1U)
3558 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3560 struct irq_remap_table *table = NULL;
3561 struct amd_iommu *iommu;
3562 unsigned long flags;
3565 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3567 iommu = amd_iommu_rlookup_table[devid];
3571 table = irq_lookup_table[devid];
3575 alias = amd_iommu_alias_table[devid];
3576 table = irq_lookup_table[alias];
3578 irq_lookup_table[devid] = table;
3579 set_dte_irq_entry(devid, table);
3580 iommu_flush_dte(iommu, devid);
3584 /* Nothing there yet, allocate new irq remapping table */
3585 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3589 /* Initialize table spin-lock */
3590 spin_lock_init(&table->lock);
3593 /* Keep the first 32 indexes free for IOAPIC interrupts */
3594 table->min_index = 32;
3596 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3597 if (!table->table) {
3603 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3608 for (i = 0; i < 32; ++i)
3609 table->table[i] = IRTE_ALLOCATED;
3612 irq_lookup_table[devid] = table;
3613 set_dte_irq_entry(devid, table);
3614 iommu_flush_dte(iommu, devid);
3615 if (devid != alias) {
3616 irq_lookup_table[alias] = table;
3617 set_dte_irq_entry(alias, table);
3618 iommu_flush_dte(iommu, alias);
3622 iommu_completion_wait(iommu);
3625 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3630 static int alloc_irq_index(u16 devid, int count)
3632 struct irq_remap_table *table;
3633 unsigned long flags;
3636 table = get_irq_table(devid, false);
3640 spin_lock_irqsave(&table->lock, flags);
3642 /* Scan table for free entries */
3643 for (c = 0, index = table->min_index;
3644 index < MAX_IRQS_PER_TABLE;
3646 if (table->table[index] == 0)
3653 table->table[index - c + 1] = IRTE_ALLOCATED;
3663 spin_unlock_irqrestore(&table->lock, flags);
3668 static int modify_irte(u16 devid, int index, union irte irte)
3670 struct irq_remap_table *table;
3671 struct amd_iommu *iommu;
3672 unsigned long flags;
3674 iommu = amd_iommu_rlookup_table[devid];
3678 table = get_irq_table(devid, false);
3682 spin_lock_irqsave(&table->lock, flags);
3683 table->table[index] = irte.val;
3684 spin_unlock_irqrestore(&table->lock, flags);
3686 iommu_flush_irt(iommu, devid);
3687 iommu_completion_wait(iommu);
3692 static void free_irte(u16 devid, int index)
3694 struct irq_remap_table *table;
3695 struct amd_iommu *iommu;
3696 unsigned long flags;
3698 iommu = amd_iommu_rlookup_table[devid];
3702 table = get_irq_table(devid, false);
3706 spin_lock_irqsave(&table->lock, flags);
3707 table->table[index] = 0;
3708 spin_unlock_irqrestore(&table->lock, flags);
3710 iommu_flush_irt(iommu, devid);
3711 iommu_completion_wait(iommu);
3714 static int get_devid(struct irq_alloc_info *info)
3718 switch (info->type) {
3719 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3720 devid = get_ioapic_devid(info->ioapic_id);
3722 case X86_IRQ_ALLOC_TYPE_HPET:
3723 devid = get_hpet_devid(info->hpet_id);
3725 case X86_IRQ_ALLOC_TYPE_MSI:
3726 case X86_IRQ_ALLOC_TYPE_MSIX:
3727 devid = get_device_id(&info->msi_dev->dev);
3737 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3739 struct amd_iommu *iommu;
3745 devid = get_devid(info);
3747 iommu = amd_iommu_rlookup_table[devid];
3749 return iommu->ir_domain;
3755 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3757 struct amd_iommu *iommu;
3763 switch (info->type) {
3764 case X86_IRQ_ALLOC_TYPE_MSI:
3765 case X86_IRQ_ALLOC_TYPE_MSIX:
3766 devid = get_device_id(&info->msi_dev->dev);
3770 iommu = amd_iommu_rlookup_table[devid];
3772 return iommu->msi_domain;
3781 struct irq_remap_ops amd_iommu_irq_ops = {
3782 .prepare = amd_iommu_prepare,
3783 .enable = amd_iommu_enable,
3784 .disable = amd_iommu_disable,
3785 .reenable = amd_iommu_reenable,
3786 .enable_faulting = amd_iommu_enable_faulting,
3787 .get_ir_irq_domain = get_ir_irq_domain,
3788 .get_irq_domain = get_irq_domain,
3791 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3792 struct irq_cfg *irq_cfg,
3793 struct irq_alloc_info *info,
3794 int devid, int index, int sub_handle)
3796 struct irq_2_irte *irte_info = &data->irq_2_irte;
3797 struct msi_msg *msg = &data->msi_entry;
3798 union irte *irte = &data->irte_entry;
3799 struct IO_APIC_route_entry *entry;
3801 data->irq_2_irte.devid = devid;
3802 data->irq_2_irte.index = index + sub_handle;
3804 /* Setup IRTE for IOMMU */
3806 irte->fields.vector = irq_cfg->vector;
3807 irte->fields.int_type = apic->irq_delivery_mode;
3808 irte->fields.destination = irq_cfg->dest_apicid;
3809 irte->fields.dm = apic->irq_dest_mode;
3810 irte->fields.valid = 1;
3812 switch (info->type) {
3813 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3814 /* Setup IOAPIC entry */
3815 entry = info->ioapic_entry;
3816 info->ioapic_entry = NULL;
3817 memset(entry, 0, sizeof(*entry));
3818 entry->vector = index;
3820 entry->trigger = info->ioapic_trigger;
3821 entry->polarity = info->ioapic_polarity;
3822 /* Mask level triggered irqs. */
3823 if (info->ioapic_trigger)
3827 case X86_IRQ_ALLOC_TYPE_HPET:
3828 case X86_IRQ_ALLOC_TYPE_MSI:
3829 case X86_IRQ_ALLOC_TYPE_MSIX:
3830 msg->address_hi = MSI_ADDR_BASE_HI;
3831 msg->address_lo = MSI_ADDR_BASE_LO;
3832 msg->data = irte_info->index;
3841 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3842 unsigned int nr_irqs, void *arg)
3844 struct irq_alloc_info *info = arg;
3845 struct irq_data *irq_data;
3846 struct amd_ir_data *data;
3847 struct irq_cfg *cfg;
3853 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3854 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3858 * With IRQ remapping enabled, don't need contiguous CPU vectors
3859 * to support multiple MSI interrupts.
3861 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3862 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3864 devid = get_devid(info);
3868 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3872 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3873 if (get_irq_table(devid, true))
3874 index = info->ioapic_pin;
3878 index = alloc_irq_index(devid, nr_irqs);
3881 pr_warn("Failed to allocate IRTE\n");
3882 goto out_free_parent;
3885 for (i = 0; i < nr_irqs; i++) {
3886 irq_data = irq_domain_get_irq_data(domain, virq + i);
3887 cfg = irqd_cfg(irq_data);
3888 if (!irq_data || !cfg) {
3894 data = kzalloc(sizeof(*data), GFP_KERNEL);
3898 irq_data->hwirq = (devid << 16) + i;
3899 irq_data->chip_data = data;
3900 irq_data->chip = &amd_ir_chip;
3901 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3902 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3908 for (i--; i >= 0; i--) {
3909 irq_data = irq_domain_get_irq_data(domain, virq + i);
3911 kfree(irq_data->chip_data);
3913 for (i = 0; i < nr_irqs; i++)
3914 free_irte(devid, index + i);
3916 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3920 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3921 unsigned int nr_irqs)
3923 struct irq_2_irte *irte_info;
3924 struct irq_data *irq_data;
3925 struct amd_ir_data *data;
3928 for (i = 0; i < nr_irqs; i++) {
3929 irq_data = irq_domain_get_irq_data(domain, virq + i);
3930 if (irq_data && irq_data->chip_data) {
3931 data = irq_data->chip_data;
3932 irte_info = &data->irq_2_irte;
3933 free_irte(irte_info->devid, irte_info->index);
3937 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3940 static void irq_remapping_activate(struct irq_domain *domain,
3941 struct irq_data *irq_data)
3943 struct amd_ir_data *data = irq_data->chip_data;
3944 struct irq_2_irte *irte_info = &data->irq_2_irte;
3946 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
3949 static void irq_remapping_deactivate(struct irq_domain *domain,
3950 struct irq_data *irq_data)
3952 struct amd_ir_data *data = irq_data->chip_data;
3953 struct irq_2_irte *irte_info = &data->irq_2_irte;
3957 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
3960 static struct irq_domain_ops amd_ir_domain_ops = {
3961 .alloc = irq_remapping_alloc,
3962 .free = irq_remapping_free,
3963 .activate = irq_remapping_activate,
3964 .deactivate = irq_remapping_deactivate,
3967 static int amd_ir_set_affinity(struct irq_data *data,
3968 const struct cpumask *mask, bool force)
3970 struct amd_ir_data *ir_data = data->chip_data;
3971 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3972 struct irq_cfg *cfg = irqd_cfg(data);
3973 struct irq_data *parent = data->parent_data;
3976 ret = parent->chip->irq_set_affinity(parent, mask, force);
3977 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3981 * Atomically updates the IRTE with the new destination, vector
3982 * and flushes the interrupt entry cache.
3984 ir_data->irte_entry.fields.vector = cfg->vector;
3985 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
3986 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
3989 * After this point, all the interrupts will start arriving
3990 * at the new destination. So, time to cleanup the previous
3991 * vector allocation.
3993 send_cleanup_vector(cfg);
3995 return IRQ_SET_MASK_OK_DONE;
3998 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4000 struct amd_ir_data *ir_data = irq_data->chip_data;
4002 *msg = ir_data->msi_entry;
4005 static struct irq_chip amd_ir_chip = {
4006 .irq_ack = ir_ack_apic_edge,
4007 .irq_set_affinity = amd_ir_set_affinity,
4008 .irq_compose_msi_msg = ir_compose_msi_msg,
4011 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4013 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4014 if (!iommu->ir_domain)
4017 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4018 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);