2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
59 #define LOOP_TIMEOUT 100000
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
78 * 512GB Pages are not supported due to a hardware bug
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
88 LIST_HEAD(ioapic_map);
90 LIST_HEAD(acpihid_map);
93 * Domain for untranslated devices - only allocated
94 * if iommu=pt passed on kernel cmd line.
96 static const struct iommu_ops amd_iommu_ops;
98 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
99 int amd_iommu_max_glx_val = -1;
101 static struct dma_map_ops amd_iommu_dma_ops;
104 * This struct contains device specific data for the IOMMU
106 struct iommu_dev_data {
107 struct list_head list; /* For domain->dev_list */
108 struct list_head dev_data_list; /* For global dev_data_list */
109 struct protection_domain *domain; /* Domain the device is bound to */
110 u16 devid; /* PCI Device ID */
111 u16 alias; /* Alias Device ID */
112 bool iommu_v2; /* Device can make use of IOMMUv2 */
113 bool passthrough; /* Device is identity mapped */
117 } ats; /* ATS state */
118 bool pri_tlp; /* PASID TLB required for
120 u32 errata; /* Bitmap for errata to apply */
124 * general struct to manage commands send to an IOMMU
130 struct kmem_cache *amd_iommu_irq_cache;
132 static void update_domain(struct protection_domain *domain);
133 static int protection_domain_init(struct protection_domain *domain);
134 static void detach_device(struct device *dev);
137 * For dynamic growth the aperture size is split into ranges of 128MB of
138 * DMA address space each. This struct represents one such range.
140 struct aperture_range {
142 spinlock_t bitmap_lock;
144 /* address allocation bitmap */
145 unsigned long *bitmap;
146 unsigned long offset;
147 unsigned long next_bit;
150 * Array of PTE pages for the aperture. In this array we save all the
151 * leaf pages of the domain page table used for the aperture. This way
152 * we don't need to walk the page table to find a specific PTE. We can
153 * just calculate its address in constant time.
159 * Data container for a dma_ops specific protection domain
161 struct dma_ops_domain {
162 /* generic protection domain information */
163 struct protection_domain domain;
165 /* size of the aperture for the mappings */
166 unsigned long aperture_size;
168 /* aperture index we start searching for free addresses */
169 u32 __percpu *next_index;
171 /* address space relevant data */
172 struct aperture_range *aperture[APERTURE_MAX_RANGES];
175 struct iova_domain iovad;
178 static struct iova_domain reserved_iova_ranges;
179 static struct lock_class_key reserved_rbtree_key;
181 /****************************************************************************
185 ****************************************************************************/
187 static inline int match_hid_uid(struct device *dev,
188 struct acpihid_map_entry *entry)
190 const char *hid, *uid;
192 hid = acpi_device_hid(ACPI_COMPANION(dev));
193 uid = acpi_device_uid(ACPI_COMPANION(dev));
199 return strcmp(hid, entry->hid);
202 return strcmp(hid, entry->hid);
204 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
207 static inline u16 get_pci_device_id(struct device *dev)
209 struct pci_dev *pdev = to_pci_dev(dev);
211 return PCI_DEVID(pdev->bus->number, pdev->devfn);
214 static inline int get_acpihid_device_id(struct device *dev,
215 struct acpihid_map_entry **entry)
217 struct acpihid_map_entry *p;
219 list_for_each_entry(p, &acpihid_map, list) {
220 if (!match_hid_uid(dev, p)) {
229 static inline int get_device_id(struct device *dev)
234 devid = get_pci_device_id(dev);
236 devid = get_acpihid_device_id(dev, NULL);
241 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
243 return container_of(dom, struct protection_domain, domain);
246 static struct iommu_dev_data *alloc_dev_data(u16 devid)
248 struct iommu_dev_data *dev_data;
251 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
255 dev_data->devid = devid;
257 spin_lock_irqsave(&dev_data_list_lock, flags);
258 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
259 spin_unlock_irqrestore(&dev_data_list_lock, flags);
264 static struct iommu_dev_data *search_dev_data(u16 devid)
266 struct iommu_dev_data *dev_data;
269 spin_lock_irqsave(&dev_data_list_lock, flags);
270 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
271 if (dev_data->devid == devid)
278 spin_unlock_irqrestore(&dev_data_list_lock, flags);
283 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
285 *(u16 *)data = alias;
289 static u16 get_alias(struct device *dev)
291 struct pci_dev *pdev = to_pci_dev(dev);
292 u16 devid, ivrs_alias, pci_alias;
294 /* The callers make sure that get_device_id() does not fail here */
295 devid = get_device_id(dev);
296 ivrs_alias = amd_iommu_alias_table[devid];
297 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
299 if (ivrs_alias == pci_alias)
305 * The IVRS is fairly reliable in telling us about aliases, but it
306 * can't know about every screwy device. If we don't have an IVRS
307 * reported alias, use the PCI reported alias. In that case we may
308 * still need to initialize the rlookup and dev_table entries if the
309 * alias is to a non-existent device.
311 if (ivrs_alias == devid) {
312 if (!amd_iommu_rlookup_table[pci_alias]) {
313 amd_iommu_rlookup_table[pci_alias] =
314 amd_iommu_rlookup_table[devid];
315 memcpy(amd_iommu_dev_table[pci_alias].data,
316 amd_iommu_dev_table[devid].data,
317 sizeof(amd_iommu_dev_table[pci_alias].data));
323 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
324 "for device %s[%04x:%04x], kernel reported alias "
325 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
326 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
327 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
328 PCI_FUNC(pci_alias));
331 * If we don't have a PCI DMA alias and the IVRS alias is on the same
332 * bus, then the IVRS table may know about a quirk that we don't.
334 if (pci_alias == devid &&
335 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
336 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
337 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
338 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
345 static struct iommu_dev_data *find_dev_data(u16 devid)
347 struct iommu_dev_data *dev_data;
349 dev_data = search_dev_data(devid);
351 if (dev_data == NULL)
352 dev_data = alloc_dev_data(devid);
357 static struct iommu_dev_data *get_dev_data(struct device *dev)
359 return dev->archdata.iommu;
363 * Find or create an IOMMU group for a acpihid device.
365 static struct iommu_group *acpihid_device_group(struct device *dev)
367 struct acpihid_map_entry *p, *entry = NULL;
370 devid = get_acpihid_device_id(dev, &entry);
372 return ERR_PTR(devid);
374 list_for_each_entry(p, &acpihid_map, list) {
375 if ((devid == p->devid) && p->group)
376 entry->group = p->group;
380 entry->group = generic_device_group(dev);
385 static bool pci_iommuv2_capable(struct pci_dev *pdev)
387 static const int caps[] = {
390 PCI_EXT_CAP_ID_PASID,
394 for (i = 0; i < 3; ++i) {
395 pos = pci_find_ext_capability(pdev, caps[i]);
403 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
405 struct iommu_dev_data *dev_data;
407 dev_data = get_dev_data(&pdev->dev);
409 return dev_data->errata & (1 << erratum) ? true : false;
413 * This function actually applies the mapping to the page table of the
416 static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
417 struct unity_map_entry *e)
421 for (addr = e->address_start; addr < e->address_end;
423 if (addr < dma_dom->aperture_size)
424 __set_bit(addr >> PAGE_SHIFT,
425 dma_dom->aperture[0]->bitmap);
430 * Inits the unity mappings required for a specific device
432 static void init_unity_mappings_for_device(struct device *dev,
433 struct dma_ops_domain *dma_dom)
435 struct unity_map_entry *e;
438 devid = get_device_id(dev);
442 list_for_each_entry(e, &amd_iommu_unity_map, list) {
443 if (!(devid >= e->devid_start && devid <= e->devid_end))
445 alloc_unity_mapping(dma_dom, e);
450 * This function checks if the driver got a valid device from the caller to
451 * avoid dereferencing invalid pointers.
453 static bool check_device(struct device *dev)
457 if (!dev || !dev->dma_mask)
460 devid = get_device_id(dev);
464 /* Out of our scope? */
465 if (devid > amd_iommu_last_bdf)
468 if (amd_iommu_rlookup_table[devid] == NULL)
474 static void init_iommu_group(struct device *dev)
476 struct dma_ops_domain *dma_domain;
477 struct iommu_domain *domain;
478 struct iommu_group *group;
480 group = iommu_group_get_for_dev(dev);
484 domain = iommu_group_default_domain(group);
488 if (to_pdomain(domain)->flags == PD_DMA_OPS_MASK) {
489 dma_domain = to_pdomain(domain)->priv;
490 init_unity_mappings_for_device(dev, dma_domain);
494 iommu_group_put(group);
497 static int iommu_init_device(struct device *dev)
499 struct iommu_dev_data *dev_data;
502 if (dev->archdata.iommu)
505 devid = get_device_id(dev);
509 dev_data = find_dev_data(devid);
513 dev_data->alias = get_alias(dev);
515 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
516 struct amd_iommu *iommu;
518 iommu = amd_iommu_rlookup_table[dev_data->devid];
519 dev_data->iommu_v2 = iommu->is_iommu_v2;
522 dev->archdata.iommu = dev_data;
524 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
530 static void iommu_ignore_device(struct device *dev)
535 devid = get_device_id(dev);
539 alias = get_alias(dev);
541 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
542 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
544 amd_iommu_rlookup_table[devid] = NULL;
545 amd_iommu_rlookup_table[alias] = NULL;
548 static void iommu_uninit_device(struct device *dev)
551 struct iommu_dev_data *dev_data;
553 devid = get_device_id(dev);
557 dev_data = search_dev_data(devid);
561 if (dev_data->domain)
564 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
567 iommu_group_remove_device(dev);
570 dev->archdata.dma_ops = NULL;
573 * We keep dev_data around for unplugged devices and reuse it when the
574 * device is re-plugged - not doing so would introduce a ton of races.
578 /****************************************************************************
580 * Interrupt handling functions
582 ****************************************************************************/
584 static void dump_dte_entry(u16 devid)
588 for (i = 0; i < 4; ++i)
589 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
590 amd_iommu_dev_table[devid].data[i]);
593 static void dump_command(unsigned long phys_addr)
595 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
598 for (i = 0; i < 4; ++i)
599 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
602 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
604 int type, devid, domid, flags;
605 volatile u32 *event = __evt;
610 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
611 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
612 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
613 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
614 address = (u64)(((u64)event[3]) << 32) | event[2];
617 /* Did we hit the erratum? */
618 if (++count == LOOP_TIMEOUT) {
619 pr_err("AMD-Vi: No event written to event log\n");
626 printk(KERN_ERR "AMD-Vi: Event logged [");
629 case EVENT_TYPE_ILL_DEV:
630 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
631 "address=0x%016llx flags=0x%04x]\n",
632 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
634 dump_dte_entry(devid);
636 case EVENT_TYPE_IO_FAULT:
637 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
638 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
639 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
640 domid, address, flags);
642 case EVENT_TYPE_DEV_TAB_ERR:
643 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
644 "address=0x%016llx flags=0x%04x]\n",
645 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
648 case EVENT_TYPE_PAGE_TAB_ERR:
649 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
650 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
651 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
652 domid, address, flags);
654 case EVENT_TYPE_ILL_CMD:
655 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
656 dump_command(address);
658 case EVENT_TYPE_CMD_HARD_ERR:
659 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
660 "flags=0x%04x]\n", address, flags);
662 case EVENT_TYPE_IOTLB_INV_TO:
663 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
664 "address=0x%016llx]\n",
665 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
668 case EVENT_TYPE_INV_DEV_REQ:
669 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
670 "address=0x%016llx flags=0x%04x]\n",
671 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
675 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
678 memset(__evt, 0, 4 * sizeof(u32));
681 static void iommu_poll_events(struct amd_iommu *iommu)
685 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
686 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
688 while (head != tail) {
689 iommu_print_event(iommu, iommu->evt_buf + head);
690 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
693 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
696 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
698 struct amd_iommu_fault fault;
700 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
701 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
705 fault.address = raw[1];
706 fault.pasid = PPR_PASID(raw[0]);
707 fault.device_id = PPR_DEVID(raw[0]);
708 fault.tag = PPR_TAG(raw[0]);
709 fault.flags = PPR_FLAGS(raw[0]);
711 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
714 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
718 if (iommu->ppr_log == NULL)
721 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
722 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
724 while (head != tail) {
729 raw = (u64 *)(iommu->ppr_log + head);
732 * Hardware bug: Interrupt may arrive before the entry is
733 * written to memory. If this happens we need to wait for the
736 for (i = 0; i < LOOP_TIMEOUT; ++i) {
737 if (PPR_REQ_TYPE(raw[0]) != 0)
742 /* Avoid memcpy function-call overhead */
747 * To detect the hardware bug we need to clear the entry
750 raw[0] = raw[1] = 0UL;
752 /* Update head pointer of hardware ring-buffer */
753 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
754 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
756 /* Handle PPR entry */
757 iommu_handle_ppr_entry(iommu, entry);
759 /* Refresh ring-buffer information */
760 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
761 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
765 irqreturn_t amd_iommu_int_thread(int irq, void *data)
767 struct amd_iommu *iommu = (struct amd_iommu *) data;
768 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
770 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
771 /* Enable EVT and PPR interrupts again */
772 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
773 iommu->mmio_base + MMIO_STATUS_OFFSET);
775 if (status & MMIO_STATUS_EVT_INT_MASK) {
776 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
777 iommu_poll_events(iommu);
780 if (status & MMIO_STATUS_PPR_INT_MASK) {
781 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
782 iommu_poll_ppr_log(iommu);
786 * Hardware bug: ERBT1312
787 * When re-enabling interrupt (by writing 1
788 * to clear the bit), the hardware might also try to set
789 * the interrupt bit in the event status register.
790 * In this scenario, the bit will be set, and disable
791 * subsequent interrupts.
793 * Workaround: The IOMMU driver should read back the
794 * status register and check if the interrupt bits are cleared.
795 * If not, driver will need to go through the interrupt handler
796 * again and re-clear the bits
798 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
803 irqreturn_t amd_iommu_int_handler(int irq, void *data)
805 return IRQ_WAKE_THREAD;
808 /****************************************************************************
810 * IOMMU command queuing functions
812 ****************************************************************************/
814 static int wait_on_sem(volatile u64 *sem)
818 while (*sem == 0 && i < LOOP_TIMEOUT) {
823 if (i == LOOP_TIMEOUT) {
824 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
831 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
832 struct iommu_cmd *cmd,
837 target = iommu->cmd_buf + tail;
838 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
840 /* Copy command to buffer */
841 memcpy(target, cmd, sizeof(*cmd));
843 /* Tell the IOMMU about it */
844 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
847 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
849 WARN_ON(address & 0x7ULL);
851 memset(cmd, 0, sizeof(*cmd));
852 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
853 cmd->data[1] = upper_32_bits(__pa(address));
855 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
858 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
860 memset(cmd, 0, sizeof(*cmd));
861 cmd->data[0] = devid;
862 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
865 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
866 size_t size, u16 domid, int pde)
871 pages = iommu_num_pages(address, size, PAGE_SIZE);
876 * If we have to flush more than one page, flush all
877 * TLB entries for this domain
879 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
883 address &= PAGE_MASK;
885 memset(cmd, 0, sizeof(*cmd));
886 cmd->data[1] |= domid;
887 cmd->data[2] = lower_32_bits(address);
888 cmd->data[3] = upper_32_bits(address);
889 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
890 if (s) /* size bit - we flush more than one 4kb page */
891 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
892 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
893 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
896 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
897 u64 address, size_t size)
902 pages = iommu_num_pages(address, size, PAGE_SIZE);
907 * If we have to flush more than one page, flush all
908 * TLB entries for this domain
910 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
914 address &= PAGE_MASK;
916 memset(cmd, 0, sizeof(*cmd));
917 cmd->data[0] = devid;
918 cmd->data[0] |= (qdep & 0xff) << 24;
919 cmd->data[1] = devid;
920 cmd->data[2] = lower_32_bits(address);
921 cmd->data[3] = upper_32_bits(address);
922 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
924 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
927 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
928 u64 address, bool size)
930 memset(cmd, 0, sizeof(*cmd));
932 address &= ~(0xfffULL);
934 cmd->data[0] = pasid;
935 cmd->data[1] = domid;
936 cmd->data[2] = lower_32_bits(address);
937 cmd->data[3] = upper_32_bits(address);
938 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
941 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
942 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
945 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
946 int qdep, u64 address, bool size)
948 memset(cmd, 0, sizeof(*cmd));
950 address &= ~(0xfffULL);
952 cmd->data[0] = devid;
953 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
954 cmd->data[0] |= (qdep & 0xff) << 24;
955 cmd->data[1] = devid;
956 cmd->data[1] |= (pasid & 0xff) << 16;
957 cmd->data[2] = lower_32_bits(address);
958 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
959 cmd->data[3] = upper_32_bits(address);
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
962 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
965 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
966 int status, int tag, bool gn)
968 memset(cmd, 0, sizeof(*cmd));
970 cmd->data[0] = devid;
972 cmd->data[1] = pasid;
973 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
975 cmd->data[3] = tag & 0x1ff;
976 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
978 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
981 static void build_inv_all(struct iommu_cmd *cmd)
983 memset(cmd, 0, sizeof(*cmd));
984 CMD_SET_TYPE(cmd, CMD_INV_ALL);
987 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
989 memset(cmd, 0, sizeof(*cmd));
990 cmd->data[0] = devid;
991 CMD_SET_TYPE(cmd, CMD_INV_IRT);
995 * Writes the command to the IOMMUs command buffer and informs the
996 * hardware about the new command.
998 static int iommu_queue_command_sync(struct amd_iommu *iommu,
999 struct iommu_cmd *cmd,
1002 u32 left, tail, head, next_tail;
1003 unsigned long flags;
1006 spin_lock_irqsave(&iommu->lock, flags);
1008 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1009 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1010 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1011 left = (head - next_tail) % CMD_BUFFER_SIZE;
1014 struct iommu_cmd sync_cmd;
1015 volatile u64 sem = 0;
1018 build_completion_wait(&sync_cmd, (u64)&sem);
1019 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1021 spin_unlock_irqrestore(&iommu->lock, flags);
1023 if ((ret = wait_on_sem(&sem)) != 0)
1029 copy_cmd_to_buffer(iommu, cmd, tail);
1031 /* We need to sync now to make sure all commands are processed */
1032 iommu->need_sync = sync;
1034 spin_unlock_irqrestore(&iommu->lock, flags);
1039 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1041 return iommu_queue_command_sync(iommu, cmd, true);
1045 * This function queues a completion wait command into the command
1046 * buffer of an IOMMU
1048 static int iommu_completion_wait(struct amd_iommu *iommu)
1050 struct iommu_cmd cmd;
1051 volatile u64 sem = 0;
1054 if (!iommu->need_sync)
1057 build_completion_wait(&cmd, (u64)&sem);
1059 ret = iommu_queue_command_sync(iommu, &cmd, false);
1063 return wait_on_sem(&sem);
1066 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1068 struct iommu_cmd cmd;
1070 build_inv_dte(&cmd, devid);
1072 return iommu_queue_command(iommu, &cmd);
1075 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1079 for (devid = 0; devid <= 0xffff; ++devid)
1080 iommu_flush_dte(iommu, devid);
1082 iommu_completion_wait(iommu);
1086 * This function uses heavy locking and may disable irqs for some time. But
1087 * this is no issue because it is only called during resume.
1089 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1093 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1094 struct iommu_cmd cmd;
1095 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1097 iommu_queue_command(iommu, &cmd);
1100 iommu_completion_wait(iommu);
1103 static void iommu_flush_all(struct amd_iommu *iommu)
1105 struct iommu_cmd cmd;
1107 build_inv_all(&cmd);
1109 iommu_queue_command(iommu, &cmd);
1110 iommu_completion_wait(iommu);
1113 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1115 struct iommu_cmd cmd;
1117 build_inv_irt(&cmd, devid);
1119 iommu_queue_command(iommu, &cmd);
1122 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1126 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1127 iommu_flush_irt(iommu, devid);
1129 iommu_completion_wait(iommu);
1132 void iommu_flush_all_caches(struct amd_iommu *iommu)
1134 if (iommu_feature(iommu, FEATURE_IA)) {
1135 iommu_flush_all(iommu);
1137 iommu_flush_dte_all(iommu);
1138 iommu_flush_irt_all(iommu);
1139 iommu_flush_tlb_all(iommu);
1144 * Command send function for flushing on-device TLB
1146 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1147 u64 address, size_t size)
1149 struct amd_iommu *iommu;
1150 struct iommu_cmd cmd;
1153 qdep = dev_data->ats.qdep;
1154 iommu = amd_iommu_rlookup_table[dev_data->devid];
1156 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1158 return iommu_queue_command(iommu, &cmd);
1162 * Command send function for invalidating a device table entry
1164 static int device_flush_dte(struct iommu_dev_data *dev_data)
1166 struct amd_iommu *iommu;
1170 iommu = amd_iommu_rlookup_table[dev_data->devid];
1171 alias = dev_data->alias;
1173 ret = iommu_flush_dte(iommu, dev_data->devid);
1174 if (!ret && alias != dev_data->devid)
1175 ret = iommu_flush_dte(iommu, alias);
1179 if (dev_data->ats.enabled)
1180 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1186 * TLB invalidation function which is called from the mapping functions.
1187 * It invalidates a single PTE if the range to flush is within a single
1188 * page. Otherwise it flushes the whole TLB of the IOMMU.
1190 static void __domain_flush_pages(struct protection_domain *domain,
1191 u64 address, size_t size, int pde)
1193 struct iommu_dev_data *dev_data;
1194 struct iommu_cmd cmd;
1197 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1199 for (i = 0; i < amd_iommus_present; ++i) {
1200 if (!domain->dev_iommu[i])
1204 * Devices of this domain are behind this IOMMU
1205 * We need a TLB flush
1207 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1210 list_for_each_entry(dev_data, &domain->dev_list, list) {
1212 if (!dev_data->ats.enabled)
1215 ret |= device_flush_iotlb(dev_data, address, size);
1221 static void domain_flush_pages(struct protection_domain *domain,
1222 u64 address, size_t size)
1224 __domain_flush_pages(domain, address, size, 0);
1227 /* Flush the whole IO/TLB for a given protection domain */
1228 static void domain_flush_tlb(struct protection_domain *domain)
1230 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1233 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1234 static void domain_flush_tlb_pde(struct protection_domain *domain)
1236 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1239 static void domain_flush_complete(struct protection_domain *domain)
1243 for (i = 0; i < amd_iommus_present; ++i) {
1244 if (!domain->dev_iommu[i])
1248 * Devices of this domain are behind this IOMMU
1249 * We need to wait for completion of all commands.
1251 iommu_completion_wait(amd_iommus[i]);
1257 * This function flushes the DTEs for all devices in domain
1259 static void domain_flush_devices(struct protection_domain *domain)
1261 struct iommu_dev_data *dev_data;
1263 list_for_each_entry(dev_data, &domain->dev_list, list)
1264 device_flush_dte(dev_data);
1267 /****************************************************************************
1269 * The functions below are used the create the page table mappings for
1270 * unity mapped regions.
1272 ****************************************************************************/
1275 * This function is used to add another level to an IO page table. Adding
1276 * another level increases the size of the address space by 9 bits to a size up
1279 static bool increase_address_space(struct protection_domain *domain,
1284 if (domain->mode == PAGE_MODE_6_LEVEL)
1285 /* address space already 64 bit large */
1288 pte = (void *)get_zeroed_page(gfp);
1292 *pte = PM_LEVEL_PDE(domain->mode,
1293 virt_to_phys(domain->pt_root));
1294 domain->pt_root = pte;
1296 domain->updated = true;
1301 static u64 *alloc_pte(struct protection_domain *domain,
1302 unsigned long address,
1303 unsigned long page_size,
1310 BUG_ON(!is_power_of_2(page_size));
1312 while (address > PM_LEVEL_SIZE(domain->mode))
1313 increase_address_space(domain, gfp);
1315 level = domain->mode - 1;
1316 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1317 address = PAGE_SIZE_ALIGN(address, page_size);
1318 end_lvl = PAGE_SIZE_LEVEL(page_size);
1320 while (level > end_lvl) {
1325 if (!IOMMU_PTE_PRESENT(__pte)) {
1326 page = (u64 *)get_zeroed_page(gfp);
1330 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1332 if (cmpxchg64(pte, __pte, __npte)) {
1333 free_page((unsigned long)page);
1338 /* No level skipping support yet */
1339 if (PM_PTE_LEVEL(*pte) != level)
1344 pte = IOMMU_PTE_PAGE(*pte);
1346 if (pte_page && level == end_lvl)
1349 pte = &pte[PM_LEVEL_INDEX(level, address)];
1356 * This function checks if there is a PTE for a given dma address. If
1357 * there is one, it returns the pointer to it.
1359 static u64 *fetch_pte(struct protection_domain *domain,
1360 unsigned long address,
1361 unsigned long *page_size)
1366 if (address > PM_LEVEL_SIZE(domain->mode))
1369 level = domain->mode - 1;
1370 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1371 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1376 if (!IOMMU_PTE_PRESENT(*pte))
1380 if (PM_PTE_LEVEL(*pte) == 7 ||
1381 PM_PTE_LEVEL(*pte) == 0)
1384 /* No level skipping support yet */
1385 if (PM_PTE_LEVEL(*pte) != level)
1390 /* Walk to the next level */
1391 pte = IOMMU_PTE_PAGE(*pte);
1392 pte = &pte[PM_LEVEL_INDEX(level, address)];
1393 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1396 if (PM_PTE_LEVEL(*pte) == 0x07) {
1397 unsigned long pte_mask;
1400 * If we have a series of large PTEs, make
1401 * sure to return a pointer to the first one.
1403 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1404 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1405 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1412 * Generic mapping functions. It maps a physical address into a DMA
1413 * address space. It allocates the page table pages if necessary.
1414 * In the future it can be extended to a generic mapping function
1415 * supporting all features of AMD IOMMU page tables like level skipping
1416 * and full 64 bit address spaces.
1418 static int iommu_map_page(struct protection_domain *dom,
1419 unsigned long bus_addr,
1420 unsigned long phys_addr,
1421 unsigned long page_size,
1428 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1429 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1431 if (!(prot & IOMMU_PROT_MASK))
1434 count = PAGE_SIZE_PTE_COUNT(page_size);
1435 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1440 for (i = 0; i < count; ++i)
1441 if (IOMMU_PTE_PRESENT(pte[i]))
1445 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1446 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1448 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1450 if (prot & IOMMU_PROT_IR)
1451 __pte |= IOMMU_PTE_IR;
1452 if (prot & IOMMU_PROT_IW)
1453 __pte |= IOMMU_PTE_IW;
1455 for (i = 0; i < count; ++i)
1463 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1464 unsigned long bus_addr,
1465 unsigned long page_size)
1467 unsigned long long unmapped;
1468 unsigned long unmap_size;
1471 BUG_ON(!is_power_of_2(page_size));
1475 while (unmapped < page_size) {
1477 pte = fetch_pte(dom, bus_addr, &unmap_size);
1482 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1483 for (i = 0; i < count; i++)
1487 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1488 unmapped += unmap_size;
1491 BUG_ON(unmapped && !is_power_of_2(unmapped));
1496 /****************************************************************************
1498 * The next functions belong to the address allocator for the dma_ops
1499 * interface functions. They work like the allocators in the other IOMMU
1500 * drivers. Its basically a bitmap which marks the allocated pages in
1501 * the aperture. Maybe it could be enhanced in the future to a more
1502 * efficient allocator.
1504 ****************************************************************************/
1507 * The address allocator core functions.
1509 * called with domain->lock held
1513 * Used to reserve address ranges in the aperture (e.g. for exclusion
1516 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1517 unsigned long start_page,
1520 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1522 if (start_page + pages > last_page)
1523 pages = last_page - start_page;
1525 for (i = start_page; i < start_page + pages; ++i) {
1526 int index = i / APERTURE_RANGE_PAGES;
1527 int page = i % APERTURE_RANGE_PAGES;
1528 __set_bit(page, dom->aperture[index]->bitmap);
1533 * This function is used to add a new aperture range to an existing
1534 * aperture in case of dma_ops domain allocation or address allocation
1537 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1538 bool populate, gfp_t gfp)
1540 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1541 unsigned long i, old_size, pte_pgsize;
1542 struct aperture_range *range;
1543 struct amd_iommu *iommu;
1544 unsigned long flags;
1546 #ifdef CONFIG_IOMMU_STRESS
1550 if (index >= APERTURE_MAX_RANGES)
1553 range = kzalloc(sizeof(struct aperture_range), gfp);
1557 range->bitmap = (void *)get_zeroed_page(gfp);
1561 range->offset = dma_dom->aperture_size;
1563 spin_lock_init(&range->bitmap_lock);
1566 unsigned long address = dma_dom->aperture_size;
1567 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1568 u64 *pte, *pte_page;
1570 for (i = 0; i < num_ptes; ++i) {
1571 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1576 range->pte_pages[i] = pte_page;
1578 address += APERTURE_RANGE_SIZE / 64;
1582 spin_lock_irqsave(&dma_dom->domain.lock, flags);
1584 /* First take the bitmap_lock and then publish the range */
1585 spin_lock(&range->bitmap_lock);
1587 old_size = dma_dom->aperture_size;
1588 dma_dom->aperture[index] = range;
1589 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1591 /* Reserve address range used for MSI messages */
1592 if (old_size < MSI_ADDR_BASE_LO &&
1593 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1594 unsigned long spage;
1597 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1598 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1600 dma_ops_reserve_addresses(dma_dom, spage, pages);
1603 /* Initialize the exclusion range if necessary */
1604 for_each_iommu(iommu) {
1605 if (iommu->exclusion_start &&
1606 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1607 && iommu->exclusion_start < dma_dom->aperture_size) {
1608 unsigned long startpage;
1609 int pages = iommu_num_pages(iommu->exclusion_start,
1610 iommu->exclusion_length,
1612 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1613 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1618 * Check for areas already mapped as present in the new aperture
1619 * range and mark those pages as reserved in the allocator. Such
1620 * mappings may already exist as a result of requested unity
1621 * mappings for devices.
1623 for (i = dma_dom->aperture[index]->offset;
1624 i < dma_dom->aperture_size;
1626 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1627 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1630 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1634 update_domain(&dma_dom->domain);
1636 spin_unlock(&range->bitmap_lock);
1638 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
1643 update_domain(&dma_dom->domain);
1645 free_page((unsigned long)range->bitmap);
1652 static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom,
1653 struct aperture_range *range,
1654 unsigned long pages,
1655 unsigned long dma_mask,
1656 unsigned long boundary_size,
1657 unsigned long align_mask,
1660 unsigned long offset, limit, flags;
1664 offset = range->offset >> PAGE_SHIFT;
1665 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1666 dma_mask >> PAGE_SHIFT);
1669 if (!spin_trylock_irqsave(&range->bitmap_lock, flags))
1672 spin_lock_irqsave(&range->bitmap_lock, flags);
1675 address = iommu_area_alloc(range->bitmap, limit, range->next_bit,
1676 pages, offset, boundary_size, align_mask);
1677 if (address == -1) {
1678 /* Nothing found, retry one time */
1679 address = iommu_area_alloc(range->bitmap, limit,
1680 0, pages, offset, boundary_size,
1686 range->next_bit = address + pages;
1688 spin_unlock_irqrestore(&range->bitmap_lock, flags);
1691 domain_flush_tlb(&dom->domain);
1692 domain_flush_complete(&dom->domain);
1698 static unsigned long dma_ops_area_alloc(struct device *dev,
1699 struct dma_ops_domain *dom,
1701 unsigned long align_mask,
1704 unsigned long boundary_size, mask;
1705 unsigned long address = -1;
1711 mask = dma_get_seg_boundary(dev);
1714 start = this_cpu_read(*dom->next_index);
1716 /* Sanity check - is it really necessary? */
1717 if (unlikely(start > APERTURE_MAX_RANGES)) {
1719 this_cpu_write(*dom->next_index, 0);
1722 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1723 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1725 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1726 struct aperture_range *range;
1729 index = (start + i) % APERTURE_MAX_RANGES;
1731 range = dom->aperture[index];
1733 if (!range || range->offset >= dma_mask)
1736 address = dma_ops_aperture_alloc(dom, range, pages,
1737 dma_mask, boundary_size,
1739 if (address != -1) {
1740 address = range->offset + (address << PAGE_SHIFT);
1741 this_cpu_write(*dom->next_index, index);
1746 if (address == -1 && first) {
1756 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1757 struct dma_ops_domain *dom,
1759 unsigned long align_mask,
1762 unsigned long address = -1;
1764 while (address == -1) {
1765 address = dma_ops_area_alloc(dev, dom, pages,
1766 align_mask, dma_mask);
1768 if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC))
1772 if (unlikely(address == -1))
1773 address = DMA_ERROR_CODE;
1775 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1781 * The address free function.
1783 * called with domain->lock held
1785 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1786 unsigned long address,
1789 unsigned i = address >> APERTURE_RANGE_SHIFT;
1790 struct aperture_range *range = dom->aperture[i];
1791 unsigned long flags;
1793 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1795 #ifdef CONFIG_IOMMU_STRESS
1800 if (amd_iommu_unmap_flush) {
1801 domain_flush_tlb(&dom->domain);
1802 domain_flush_complete(&dom->domain);
1805 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1807 spin_lock_irqsave(&range->bitmap_lock, flags);
1808 if (address + pages > range->next_bit)
1809 range->next_bit = address + pages;
1810 bitmap_clear(range->bitmap, address, pages);
1811 spin_unlock_irqrestore(&range->bitmap_lock, flags);
1815 /****************************************************************************
1817 * The next functions belong to the domain allocation. A domain is
1818 * allocated for every IOMMU as the default domain. If device isolation
1819 * is enabled, every device get its own domain. The most important thing
1820 * about domains is the page table mapping the DMA address space they
1823 ****************************************************************************/
1826 * This function adds a protection domain to the global protection domain list
1828 static void add_domain_to_list(struct protection_domain *domain)
1830 unsigned long flags;
1832 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1833 list_add(&domain->list, &amd_iommu_pd_list);
1834 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1838 * This function removes a protection domain to the global
1839 * protection domain list
1841 static void del_domain_from_list(struct protection_domain *domain)
1843 unsigned long flags;
1845 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1846 list_del(&domain->list);
1847 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1850 static u16 domain_id_alloc(void)
1852 unsigned long flags;
1855 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1856 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1858 if (id > 0 && id < MAX_DOMAIN_ID)
1859 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1862 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1867 static void domain_id_free(int id)
1869 unsigned long flags;
1871 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1872 if (id > 0 && id < MAX_DOMAIN_ID)
1873 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1874 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1877 #define DEFINE_FREE_PT_FN(LVL, FN) \
1878 static void free_pt_##LVL (unsigned long __pt) \
1886 for (i = 0; i < 512; ++i) { \
1887 /* PTE present? */ \
1888 if (!IOMMU_PTE_PRESENT(pt[i])) \
1892 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1893 PM_PTE_LEVEL(pt[i]) == 7) \
1896 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1899 free_page((unsigned long)pt); \
1902 DEFINE_FREE_PT_FN(l2, free_page)
1903 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1904 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1905 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1906 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1908 static void free_pagetable(struct protection_domain *domain)
1910 unsigned long root = (unsigned long)domain->pt_root;
1912 switch (domain->mode) {
1913 case PAGE_MODE_NONE:
1915 case PAGE_MODE_1_LEVEL:
1918 case PAGE_MODE_2_LEVEL:
1921 case PAGE_MODE_3_LEVEL:
1924 case PAGE_MODE_4_LEVEL:
1927 case PAGE_MODE_5_LEVEL:
1930 case PAGE_MODE_6_LEVEL:
1938 static void free_gcr3_tbl_level1(u64 *tbl)
1943 for (i = 0; i < 512; ++i) {
1944 if (!(tbl[i] & GCR3_VALID))
1947 ptr = __va(tbl[i] & PAGE_MASK);
1949 free_page((unsigned long)ptr);
1953 static void free_gcr3_tbl_level2(u64 *tbl)
1958 for (i = 0; i < 512; ++i) {
1959 if (!(tbl[i] & GCR3_VALID))
1962 ptr = __va(tbl[i] & PAGE_MASK);
1964 free_gcr3_tbl_level1(ptr);
1968 static void free_gcr3_table(struct protection_domain *domain)
1970 if (domain->glx == 2)
1971 free_gcr3_tbl_level2(domain->gcr3_tbl);
1972 else if (domain->glx == 1)
1973 free_gcr3_tbl_level1(domain->gcr3_tbl);
1975 BUG_ON(domain->glx != 0);
1977 free_page((unsigned long)domain->gcr3_tbl);
1981 * Free a domain, only used if something went wrong in the
1982 * allocation path and we need to free an already allocated page table
1984 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1991 put_iova_domain(&dom->iovad);
1993 free_percpu(dom->next_index);
1995 del_domain_from_list(&dom->domain);
1997 free_pagetable(&dom->domain);
1999 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
2000 if (!dom->aperture[i])
2002 free_page((unsigned long)dom->aperture[i]->bitmap);
2003 kfree(dom->aperture[i]);
2009 static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom,
2012 int ret, i, apertures;
2014 apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
2017 for (i = apertures; i < max_apertures; ++i) {
2018 ret = alloc_new_range(dma_dom, false, GFP_KERNEL);
2027 * Allocates a new protection domain usable for the dma_ops functions.
2028 * It also initializes the page table and the address allocator data
2029 * structures required for the dma_ops interface
2031 static struct dma_ops_domain *dma_ops_domain_alloc(void)
2033 struct dma_ops_domain *dma_dom;
2036 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
2040 if (protection_domain_init(&dma_dom->domain))
2043 dma_dom->next_index = alloc_percpu(u32);
2044 if (!dma_dom->next_index)
2047 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2048 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2049 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2050 dma_dom->domain.priv = dma_dom;
2051 if (!dma_dom->domain.pt_root)
2054 add_domain_to_list(&dma_dom->domain);
2056 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2060 * mark the first page as allocated so we never return 0 as
2061 * a valid dma-address. So we can use 0 as error value
2063 dma_dom->aperture[0]->bitmap[0] = 1;
2065 for_each_possible_cpu(cpu)
2066 *per_cpu_ptr(dma_dom->next_index, cpu) = 0;
2068 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
2069 IOVA_START_PFN, DMA_32BIT_PFN);
2071 /* Initialize reserved ranges */
2072 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
2077 dma_ops_domain_free(dma_dom);
2083 * little helper function to check whether a given protection domain is a
2086 static bool dma_ops_domain(struct protection_domain *domain)
2088 return domain->flags & PD_DMA_OPS_MASK;
2091 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2096 if (domain->mode != PAGE_MODE_NONE)
2097 pte_root = virt_to_phys(domain->pt_root);
2099 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2100 << DEV_ENTRY_MODE_SHIFT;
2101 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2103 flags = amd_iommu_dev_table[devid].data[1];
2106 flags |= DTE_FLAG_IOTLB;
2108 if (domain->flags & PD_IOMMUV2_MASK) {
2109 u64 gcr3 = __pa(domain->gcr3_tbl);
2110 u64 glx = domain->glx;
2113 pte_root |= DTE_FLAG_GV;
2114 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2116 /* First mask out possible old values for GCR3 table */
2117 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2120 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2123 /* Encode GCR3 table into DTE */
2124 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2127 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2130 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2134 flags &= ~(0xffffUL);
2135 flags |= domain->id;
2137 amd_iommu_dev_table[devid].data[1] = flags;
2138 amd_iommu_dev_table[devid].data[0] = pte_root;
2141 static void clear_dte_entry(u16 devid)
2143 /* remove entry from the device table seen by the hardware */
2144 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2145 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2147 amd_iommu_apply_erratum_63(devid);
2150 static void do_attach(struct iommu_dev_data *dev_data,
2151 struct protection_domain *domain)
2153 struct amd_iommu *iommu;
2157 iommu = amd_iommu_rlookup_table[dev_data->devid];
2158 alias = dev_data->alias;
2159 ats = dev_data->ats.enabled;
2161 /* Update data structures */
2162 dev_data->domain = domain;
2163 list_add(&dev_data->list, &domain->dev_list);
2165 /* Do reference counting */
2166 domain->dev_iommu[iommu->index] += 1;
2167 domain->dev_cnt += 1;
2169 /* Update device table */
2170 set_dte_entry(dev_data->devid, domain, ats);
2171 if (alias != dev_data->devid)
2172 set_dte_entry(alias, domain, ats);
2174 device_flush_dte(dev_data);
2177 static void do_detach(struct iommu_dev_data *dev_data)
2179 struct amd_iommu *iommu;
2183 * First check if the device is still attached. It might already
2184 * be detached from its domain because the generic
2185 * iommu_detach_group code detached it and we try again here in
2186 * our alias handling.
2188 if (!dev_data->domain)
2191 iommu = amd_iommu_rlookup_table[dev_data->devid];
2192 alias = dev_data->alias;
2194 /* decrease reference counters */
2195 dev_data->domain->dev_iommu[iommu->index] -= 1;
2196 dev_data->domain->dev_cnt -= 1;
2198 /* Update data structures */
2199 dev_data->domain = NULL;
2200 list_del(&dev_data->list);
2201 clear_dte_entry(dev_data->devid);
2202 if (alias != dev_data->devid)
2203 clear_dte_entry(alias);
2205 /* Flush the DTE entry */
2206 device_flush_dte(dev_data);
2210 * If a device is not yet associated with a domain, this function does
2211 * assigns it visible for the hardware
2213 static int __attach_device(struct iommu_dev_data *dev_data,
2214 struct protection_domain *domain)
2219 * Must be called with IRQs disabled. Warn here to detect early
2222 WARN_ON(!irqs_disabled());
2225 spin_lock(&domain->lock);
2228 if (dev_data->domain != NULL)
2231 /* Attach alias group root */
2232 do_attach(dev_data, domain);
2239 spin_unlock(&domain->lock);
2245 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2247 pci_disable_ats(pdev);
2248 pci_disable_pri(pdev);
2249 pci_disable_pasid(pdev);
2252 /* FIXME: Change generic reset-function to do the same */
2253 static int pri_reset_while_enabled(struct pci_dev *pdev)
2258 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2262 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2263 control |= PCI_PRI_CTRL_RESET;
2264 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2269 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2274 /* FIXME: Hardcode number of outstanding requests for now */
2276 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2278 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2280 /* Only allow access to user-accessible pages */
2281 ret = pci_enable_pasid(pdev, 0);
2285 /* First reset the PRI state of the device */
2286 ret = pci_reset_pri(pdev);
2291 ret = pci_enable_pri(pdev, reqs);
2296 ret = pri_reset_while_enabled(pdev);
2301 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2308 pci_disable_pri(pdev);
2309 pci_disable_pasid(pdev);
2314 /* FIXME: Move this to PCI code */
2315 #define PCI_PRI_TLP_OFF (1 << 15)
2317 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2322 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2326 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2328 return (status & PCI_PRI_TLP_OFF) ? true : false;
2332 * If a device is not yet associated with a domain, this function
2333 * assigns it visible for the hardware
2335 static int attach_device(struct device *dev,
2336 struct protection_domain *domain)
2338 struct pci_dev *pdev;
2339 struct iommu_dev_data *dev_data;
2340 unsigned long flags;
2343 dev_data = get_dev_data(dev);
2345 if (!dev_is_pci(dev))
2346 goto skip_ats_check;
2348 pdev = to_pci_dev(dev);
2349 if (domain->flags & PD_IOMMUV2_MASK) {
2350 if (!dev_data->passthrough)
2353 if (dev_data->iommu_v2) {
2354 if (pdev_iommuv2_enable(pdev) != 0)
2357 dev_data->ats.enabled = true;
2358 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2359 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2361 } else if (amd_iommu_iotlb_sup &&
2362 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2363 dev_data->ats.enabled = true;
2364 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2368 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2369 ret = __attach_device(dev_data, domain);
2370 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2373 * We might boot into a crash-kernel here. The crashed kernel
2374 * left the caches in the IOMMU dirty. So we have to flush
2375 * here to evict all dirty stuff.
2377 domain_flush_tlb_pde(domain);
2383 * Removes a device from a protection domain (unlocked)
2385 static void __detach_device(struct iommu_dev_data *dev_data)
2387 struct protection_domain *domain;
2390 * Must be called with IRQs disabled. Warn here to detect early
2393 WARN_ON(!irqs_disabled());
2395 if (WARN_ON(!dev_data->domain))
2398 domain = dev_data->domain;
2400 spin_lock(&domain->lock);
2402 do_detach(dev_data);
2404 spin_unlock(&domain->lock);
2408 * Removes a device from a protection domain (with devtable_lock held)
2410 static void detach_device(struct device *dev)
2412 struct protection_domain *domain;
2413 struct iommu_dev_data *dev_data;
2414 unsigned long flags;
2416 dev_data = get_dev_data(dev);
2417 domain = dev_data->domain;
2419 /* lock device table */
2420 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2421 __detach_device(dev_data);
2422 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2424 if (!dev_is_pci(dev))
2427 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2428 pdev_iommuv2_disable(to_pci_dev(dev));
2429 else if (dev_data->ats.enabled)
2430 pci_disable_ats(to_pci_dev(dev));
2432 dev_data->ats.enabled = false;
2435 static int amd_iommu_add_device(struct device *dev)
2437 struct iommu_dev_data *dev_data;
2438 struct iommu_domain *domain;
2439 struct amd_iommu *iommu;
2442 if (!check_device(dev) || get_dev_data(dev))
2445 devid = get_device_id(dev);
2449 iommu = amd_iommu_rlookup_table[devid];
2451 ret = iommu_init_device(dev);
2453 if (ret != -ENOTSUPP)
2454 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2457 iommu_ignore_device(dev);
2458 dev->archdata.dma_ops = &nommu_dma_ops;
2461 init_iommu_group(dev);
2463 dev_data = get_dev_data(dev);
2467 if (iommu_pass_through || dev_data->iommu_v2)
2468 iommu_request_dm_for_dev(dev);
2470 /* Domains are initialized for this device - have a look what we ended up with */
2471 domain = iommu_get_domain_for_dev(dev);
2472 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2473 dev_data->passthrough = true;
2475 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2478 iommu_completion_wait(iommu);
2483 static void amd_iommu_remove_device(struct device *dev)
2485 struct amd_iommu *iommu;
2488 if (!check_device(dev))
2491 devid = get_device_id(dev);
2495 iommu = amd_iommu_rlookup_table[devid];
2497 iommu_uninit_device(dev);
2498 iommu_completion_wait(iommu);
2501 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2503 if (dev_is_pci(dev))
2504 return pci_device_group(dev);
2506 return acpihid_device_group(dev);
2509 /*****************************************************************************
2511 * The next functions belong to the dma_ops mapping/unmapping code.
2513 *****************************************************************************/
2516 * In the dma_ops path we only have the struct device. This function
2517 * finds the corresponding IOMMU, the protection domain and the
2518 * requestor id for a given device.
2519 * If the device is not yet associated with a domain this is also done
2522 static struct protection_domain *get_domain(struct device *dev)
2524 struct protection_domain *domain;
2525 struct iommu_domain *io_domain;
2527 if (!check_device(dev))
2528 return ERR_PTR(-EINVAL);
2530 io_domain = iommu_get_domain_for_dev(dev);
2534 domain = to_pdomain(io_domain);
2535 if (!dma_ops_domain(domain))
2536 return ERR_PTR(-EBUSY);
2541 static void update_device_table(struct protection_domain *domain)
2543 struct iommu_dev_data *dev_data;
2545 list_for_each_entry(dev_data, &domain->dev_list, list)
2546 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2549 static void update_domain(struct protection_domain *domain)
2551 if (!domain->updated)
2554 update_device_table(domain);
2556 domain_flush_devices(domain);
2557 domain_flush_tlb_pde(domain);
2559 domain->updated = false;
2563 * This function fetches the PTE for a given address in the aperture
2565 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2566 unsigned long address)
2568 struct aperture_range *aperture;
2569 u64 *pte, *pte_page;
2571 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2575 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2577 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2579 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2581 pte += PM_LEVEL_INDEX(0, address);
2583 update_domain(&dom->domain);
2589 * This is the generic map function. It maps one 4kb page at paddr to
2590 * the given address in the DMA address space for the domain.
2592 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2593 unsigned long address,
2599 WARN_ON(address > dom->aperture_size);
2603 pte = dma_ops_get_pte(dom, address);
2605 return DMA_ERROR_CODE;
2607 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2609 if (direction == DMA_TO_DEVICE)
2610 __pte |= IOMMU_PTE_IR;
2611 else if (direction == DMA_FROM_DEVICE)
2612 __pte |= IOMMU_PTE_IW;
2613 else if (direction == DMA_BIDIRECTIONAL)
2614 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2620 return (dma_addr_t)address;
2624 * The generic unmapping function for on page in the DMA address space.
2626 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2627 unsigned long address)
2629 struct aperture_range *aperture;
2632 if (address >= dom->aperture_size)
2635 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2639 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2643 pte += PM_LEVEL_INDEX(0, address);
2645 WARN_ON_ONCE(!*pte);
2651 * This function contains common code for mapping of a physically
2652 * contiguous memory region into DMA address space. It is used by all
2653 * mapping functions provided with this IOMMU driver.
2654 * Must be called with the domain lock held.
2656 static dma_addr_t __map_single(struct device *dev,
2657 struct dma_ops_domain *dma_dom,
2664 dma_addr_t offset = paddr & ~PAGE_MASK;
2665 dma_addr_t address, start, ret;
2667 unsigned long align_mask = 0;
2670 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2674 align_mask = (1UL << get_order(size)) - 1;
2676 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2679 if (address == DMA_ERROR_CODE)
2683 for (i = 0; i < pages; ++i) {
2684 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2685 if (ret == DMA_ERROR_CODE)
2693 if (unlikely(amd_iommu_np_cache)) {
2694 domain_flush_pages(&dma_dom->domain, address, size);
2695 domain_flush_complete(&dma_dom->domain);
2703 for (--i; i >= 0; --i) {
2705 dma_ops_domain_unmap(dma_dom, start);
2708 dma_ops_free_addresses(dma_dom, address, pages);
2710 return DMA_ERROR_CODE;
2714 * Does the reverse of the __map_single function. Must be called with
2715 * the domain lock held too
2717 static void __unmap_single(struct dma_ops_domain *dma_dom,
2718 dma_addr_t dma_addr,
2722 dma_addr_t flush_addr;
2723 dma_addr_t i, start;
2726 if ((dma_addr == DMA_ERROR_CODE) ||
2727 (dma_addr + size > dma_dom->aperture_size))
2730 flush_addr = dma_addr;
2731 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2732 dma_addr &= PAGE_MASK;
2735 for (i = 0; i < pages; ++i) {
2736 dma_ops_domain_unmap(dma_dom, start);
2740 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2744 * The exported map_single function for dma_ops.
2746 static dma_addr_t map_page(struct device *dev, struct page *page,
2747 unsigned long offset, size_t size,
2748 enum dma_data_direction dir,
2749 struct dma_attrs *attrs)
2751 phys_addr_t paddr = page_to_phys(page) + offset;
2752 struct protection_domain *domain;
2755 domain = get_domain(dev);
2756 if (PTR_ERR(domain) == -EINVAL)
2757 return (dma_addr_t)paddr;
2758 else if (IS_ERR(domain))
2759 return DMA_ERROR_CODE;
2761 dma_mask = *dev->dma_mask;
2763 return __map_single(dev, domain->priv, paddr, size, dir, false,
2768 * The exported unmap_single function for dma_ops.
2770 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2771 enum dma_data_direction dir, struct dma_attrs *attrs)
2773 struct protection_domain *domain;
2775 domain = get_domain(dev);
2779 __unmap_single(domain->priv, dma_addr, size, dir);
2783 * The exported map_sg function for dma_ops (handles scatter-gather
2786 static int map_sg(struct device *dev, struct scatterlist *sglist,
2787 int nelems, enum dma_data_direction dir,
2788 struct dma_attrs *attrs)
2790 struct protection_domain *domain;
2792 struct scatterlist *s;
2794 int mapped_elems = 0;
2797 domain = get_domain(dev);
2801 dma_mask = *dev->dma_mask;
2803 for_each_sg(sglist, s, nelems, i) {
2806 s->dma_address = __map_single(dev, domain->priv,
2807 paddr, s->length, dir, false,
2810 if (s->dma_address) {
2811 s->dma_length = s->length;
2817 return mapped_elems;
2820 for_each_sg(sglist, s, mapped_elems, i) {
2822 __unmap_single(domain->priv, s->dma_address,
2823 s->dma_length, dir);
2824 s->dma_address = s->dma_length = 0;
2831 * The exported map_sg function for dma_ops (handles scatter-gather
2834 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2835 int nelems, enum dma_data_direction dir,
2836 struct dma_attrs *attrs)
2838 struct protection_domain *domain;
2839 struct scatterlist *s;
2842 domain = get_domain(dev);
2846 for_each_sg(sglist, s, nelems, i) {
2847 __unmap_single(domain->priv, s->dma_address,
2848 s->dma_length, dir);
2849 s->dma_address = s->dma_length = 0;
2854 * The exported alloc_coherent function for dma_ops.
2856 static void *alloc_coherent(struct device *dev, size_t size,
2857 dma_addr_t *dma_addr, gfp_t flag,
2858 struct dma_attrs *attrs)
2860 u64 dma_mask = dev->coherent_dma_mask;
2861 struct protection_domain *domain;
2864 domain = get_domain(dev);
2865 if (PTR_ERR(domain) == -EINVAL) {
2866 page = alloc_pages(flag, get_order(size));
2867 *dma_addr = page_to_phys(page);
2868 return page_address(page);
2869 } else if (IS_ERR(domain))
2872 size = PAGE_ALIGN(size);
2873 dma_mask = dev->coherent_dma_mask;
2874 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2877 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2879 if (!gfpflags_allow_blocking(flag))
2882 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2889 dma_mask = *dev->dma_mask;
2891 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2892 size, DMA_BIDIRECTIONAL, true, dma_mask);
2894 if (*dma_addr == DMA_ERROR_CODE)
2897 return page_address(page);
2901 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2902 __free_pages(page, get_order(size));
2908 * The exported free_coherent function for dma_ops.
2910 static void free_coherent(struct device *dev, size_t size,
2911 void *virt_addr, dma_addr_t dma_addr,
2912 struct dma_attrs *attrs)
2914 struct protection_domain *domain;
2917 page = virt_to_page(virt_addr);
2918 size = PAGE_ALIGN(size);
2920 domain = get_domain(dev);
2924 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2927 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2928 __free_pages(page, get_order(size));
2932 * This function is called by the DMA layer to find out if we can handle a
2933 * particular device. It is part of the dma_ops.
2935 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2937 return check_device(dev);
2940 static int set_dma_mask(struct device *dev, u64 mask)
2942 struct protection_domain *domain;
2943 int max_apertures = 1;
2945 domain = get_domain(dev);
2947 return PTR_ERR(domain);
2949 if (mask == DMA_BIT_MASK(64))
2951 else if (mask > DMA_BIT_MASK(32))
2955 * To prevent lock contention it doesn't make sense to allocate more
2956 * apertures than online cpus
2958 if (max_apertures > num_online_cpus())
2959 max_apertures = num_online_cpus();
2961 if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures))
2962 dev_err(dev, "Can't allocate %d iommu apertures\n",
2968 static struct dma_map_ops amd_iommu_dma_ops = {
2969 .alloc = alloc_coherent,
2970 .free = free_coherent,
2971 .map_page = map_page,
2972 .unmap_page = unmap_page,
2974 .unmap_sg = unmap_sg,
2975 .dma_supported = amd_iommu_dma_supported,
2976 .set_dma_mask = set_dma_mask,
2979 static int init_reserved_iova_ranges(void)
2981 struct pci_dev *pdev = NULL;
2984 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2985 IOVA_START_PFN, DMA_32BIT_PFN);
2987 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2988 &reserved_rbtree_key);
2990 /* MSI memory range */
2991 val = reserve_iova(&reserved_iova_ranges,
2992 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2994 pr_err("Reserving MSI range failed\n");
2998 /* HT memory range */
2999 val = reserve_iova(&reserved_iova_ranges,
3000 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
3002 pr_err("Reserving HT range failed\n");
3007 * Memory used for PCI resources
3008 * FIXME: Check whether we can reserve the PCI-hole completly
3010 for_each_pci_dev(pdev) {
3013 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
3014 struct resource *r = &pdev->resource[i];
3016 if (!(r->flags & IORESOURCE_MEM))
3019 val = reserve_iova(&reserved_iova_ranges,
3023 pr_err("Reserve pci-resource range failed\n");
3032 int __init amd_iommu_init_api(void)
3036 ret = iova_cache_get();
3040 ret = init_reserved_iova_ranges();
3044 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3047 #ifdef CONFIG_ARM_AMBA
3048 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
3052 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
3058 int __init amd_iommu_init_dma_ops(void)
3060 swiotlb = iommu_pass_through ? 1 : 0;
3064 * In case we don't initialize SWIOTLB (actually the common case
3065 * when AMD IOMMU is enabled), make sure there are global
3066 * dma_ops set as a fall-back for devices not handled by this
3067 * driver (for example non-PCI devices).
3070 dma_ops = &nommu_dma_ops;
3072 if (amd_iommu_unmap_flush)
3073 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3075 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3080 /*****************************************************************************
3082 * The following functions belong to the exported interface of AMD IOMMU
3084 * This interface allows access to lower level functions of the IOMMU
3085 * like protection domain handling and assignement of devices to domains
3086 * which is not possible with the dma_ops interface.
3088 *****************************************************************************/
3090 static void cleanup_domain(struct protection_domain *domain)
3092 struct iommu_dev_data *entry;
3093 unsigned long flags;
3095 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3097 while (!list_empty(&domain->dev_list)) {
3098 entry = list_first_entry(&domain->dev_list,
3099 struct iommu_dev_data, list);
3100 __detach_device(entry);
3103 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3106 static void protection_domain_free(struct protection_domain *domain)
3111 del_domain_from_list(domain);
3114 domain_id_free(domain->id);
3119 static int protection_domain_init(struct protection_domain *domain)
3121 spin_lock_init(&domain->lock);
3122 mutex_init(&domain->api_lock);
3123 domain->id = domain_id_alloc();
3126 INIT_LIST_HEAD(&domain->dev_list);
3131 static struct protection_domain *protection_domain_alloc(void)
3133 struct protection_domain *domain;
3135 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3139 if (protection_domain_init(domain))
3142 add_domain_to_list(domain);
3152 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
3154 struct protection_domain *pdomain;
3155 struct dma_ops_domain *dma_domain;
3158 case IOMMU_DOMAIN_UNMANAGED:
3159 pdomain = protection_domain_alloc();
3163 pdomain->mode = PAGE_MODE_3_LEVEL;
3164 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3165 if (!pdomain->pt_root) {
3166 protection_domain_free(pdomain);
3170 pdomain->domain.geometry.aperture_start = 0;
3171 pdomain->domain.geometry.aperture_end = ~0ULL;
3172 pdomain->domain.geometry.force_aperture = true;
3175 case IOMMU_DOMAIN_DMA:
3176 dma_domain = dma_ops_domain_alloc();
3178 pr_err("AMD-Vi: Failed to allocate\n");
3181 pdomain = &dma_domain->domain;
3183 case IOMMU_DOMAIN_IDENTITY:
3184 pdomain = protection_domain_alloc();
3188 pdomain->mode = PAGE_MODE_NONE;
3194 return &pdomain->domain;
3197 static void amd_iommu_domain_free(struct iommu_domain *dom)
3199 struct protection_domain *domain;
3204 domain = to_pdomain(dom);
3206 if (domain->dev_cnt > 0)
3207 cleanup_domain(domain);
3209 BUG_ON(domain->dev_cnt != 0);
3211 if (domain->mode != PAGE_MODE_NONE)
3212 free_pagetable(domain);
3214 if (domain->flags & PD_IOMMUV2_MASK)
3215 free_gcr3_table(domain);
3217 protection_domain_free(domain);
3220 static void amd_iommu_detach_device(struct iommu_domain *dom,
3223 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3224 struct amd_iommu *iommu;
3227 if (!check_device(dev))
3230 devid = get_device_id(dev);
3234 if (dev_data->domain != NULL)
3237 iommu = amd_iommu_rlookup_table[devid];
3241 iommu_completion_wait(iommu);
3244 static int amd_iommu_attach_device(struct iommu_domain *dom,
3247 struct protection_domain *domain = to_pdomain(dom);
3248 struct iommu_dev_data *dev_data;
3249 struct amd_iommu *iommu;
3252 if (!check_device(dev))
3255 dev_data = dev->archdata.iommu;
3257 iommu = amd_iommu_rlookup_table[dev_data->devid];
3261 if (dev_data->domain)
3264 ret = attach_device(dev, domain);
3266 iommu_completion_wait(iommu);
3271 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3272 phys_addr_t paddr, size_t page_size, int iommu_prot)
3274 struct protection_domain *domain = to_pdomain(dom);
3278 if (domain->mode == PAGE_MODE_NONE)
3281 if (iommu_prot & IOMMU_READ)
3282 prot |= IOMMU_PROT_IR;
3283 if (iommu_prot & IOMMU_WRITE)
3284 prot |= IOMMU_PROT_IW;
3286 mutex_lock(&domain->api_lock);
3287 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3288 mutex_unlock(&domain->api_lock);
3293 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3296 struct protection_domain *domain = to_pdomain(dom);
3299 if (domain->mode == PAGE_MODE_NONE)
3302 mutex_lock(&domain->api_lock);
3303 unmap_size = iommu_unmap_page(domain, iova, page_size);
3304 mutex_unlock(&domain->api_lock);
3306 domain_flush_tlb_pde(domain);
3311 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3314 struct protection_domain *domain = to_pdomain(dom);
3315 unsigned long offset_mask, pte_pgsize;
3318 if (domain->mode == PAGE_MODE_NONE)
3321 pte = fetch_pte(domain, iova, &pte_pgsize);
3323 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3326 offset_mask = pte_pgsize - 1;
3327 __pte = *pte & PM_ADDR_MASK;
3329 return (__pte & ~offset_mask) | (iova & offset_mask);
3332 static bool amd_iommu_capable(enum iommu_cap cap)
3335 case IOMMU_CAP_CACHE_COHERENCY:
3337 case IOMMU_CAP_INTR_REMAP:
3338 return (irq_remapping_enabled == 1);
3339 case IOMMU_CAP_NOEXEC:
3346 static void amd_iommu_get_dm_regions(struct device *dev,
3347 struct list_head *head)
3349 struct unity_map_entry *entry;
3352 devid = get_device_id(dev);
3356 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3357 struct iommu_dm_region *region;
3359 if (devid < entry->devid_start || devid > entry->devid_end)
3362 region = kzalloc(sizeof(*region), GFP_KERNEL);
3364 pr_err("Out of memory allocating dm-regions for %s\n",
3369 region->start = entry->address_start;
3370 region->length = entry->address_end - entry->address_start;
3371 if (entry->prot & IOMMU_PROT_IR)
3372 region->prot |= IOMMU_READ;
3373 if (entry->prot & IOMMU_PROT_IW)
3374 region->prot |= IOMMU_WRITE;
3376 list_add_tail(®ion->list, head);
3380 static void amd_iommu_put_dm_regions(struct device *dev,
3381 struct list_head *head)
3383 struct iommu_dm_region *entry, *next;
3385 list_for_each_entry_safe(entry, next, head, list)
3389 static void amd_iommu_apply_dm_region(struct device *dev,
3390 struct iommu_domain *domain,
3391 struct iommu_dm_region *region)
3393 struct protection_domain *pdomain = to_pdomain(domain);
3394 struct dma_ops_domain *dma_dom = pdomain->priv;
3395 unsigned long start, end;
3397 start = IOVA_PFN(region->start);
3398 end = IOVA_PFN(region->start + region->length);
3400 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3403 static const struct iommu_ops amd_iommu_ops = {
3404 .capable = amd_iommu_capable,
3405 .domain_alloc = amd_iommu_domain_alloc,
3406 .domain_free = amd_iommu_domain_free,
3407 .attach_dev = amd_iommu_attach_device,
3408 .detach_dev = amd_iommu_detach_device,
3409 .map = amd_iommu_map,
3410 .unmap = amd_iommu_unmap,
3411 .map_sg = default_iommu_map_sg,
3412 .iova_to_phys = amd_iommu_iova_to_phys,
3413 .add_device = amd_iommu_add_device,
3414 .remove_device = amd_iommu_remove_device,
3415 .device_group = amd_iommu_device_group,
3416 .get_dm_regions = amd_iommu_get_dm_regions,
3417 .put_dm_regions = amd_iommu_put_dm_regions,
3418 .apply_dm_region = amd_iommu_apply_dm_region,
3419 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3422 /*****************************************************************************
3424 * The next functions do a basic initialization of IOMMU for pass through
3427 * In passthrough mode the IOMMU is initialized and enabled but not used for
3428 * DMA-API translation.
3430 *****************************************************************************/
3432 /* IOMMUv2 specific functions */
3433 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3435 return atomic_notifier_chain_register(&ppr_notifier, nb);
3437 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3439 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3441 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3443 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3445 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3447 struct protection_domain *domain = to_pdomain(dom);
3448 unsigned long flags;
3450 spin_lock_irqsave(&domain->lock, flags);
3452 /* Update data structure */
3453 domain->mode = PAGE_MODE_NONE;
3454 domain->updated = true;
3456 /* Make changes visible to IOMMUs */
3457 update_domain(domain);
3459 /* Page-table is not visible to IOMMU anymore, so free it */
3460 free_pagetable(domain);
3462 spin_unlock_irqrestore(&domain->lock, flags);
3464 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3466 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3468 struct protection_domain *domain = to_pdomain(dom);
3469 unsigned long flags;
3472 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3475 /* Number of GCR3 table levels required */
3476 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3479 if (levels > amd_iommu_max_glx_val)
3482 spin_lock_irqsave(&domain->lock, flags);
3485 * Save us all sanity checks whether devices already in the
3486 * domain support IOMMUv2. Just force that the domain has no
3487 * devices attached when it is switched into IOMMUv2 mode.
3490 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3494 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3495 if (domain->gcr3_tbl == NULL)
3498 domain->glx = levels;
3499 domain->flags |= PD_IOMMUV2_MASK;
3500 domain->updated = true;
3502 update_domain(domain);
3507 spin_unlock_irqrestore(&domain->lock, flags);
3511 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3513 static int __flush_pasid(struct protection_domain *domain, int pasid,
3514 u64 address, bool size)
3516 struct iommu_dev_data *dev_data;
3517 struct iommu_cmd cmd;
3520 if (!(domain->flags & PD_IOMMUV2_MASK))
3523 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3526 * IOMMU TLB needs to be flushed before Device TLB to
3527 * prevent device TLB refill from IOMMU TLB
3529 for (i = 0; i < amd_iommus_present; ++i) {
3530 if (domain->dev_iommu[i] == 0)
3533 ret = iommu_queue_command(amd_iommus[i], &cmd);
3538 /* Wait until IOMMU TLB flushes are complete */
3539 domain_flush_complete(domain);
3541 /* Now flush device TLBs */
3542 list_for_each_entry(dev_data, &domain->dev_list, list) {
3543 struct amd_iommu *iommu;
3547 There might be non-IOMMUv2 capable devices in an IOMMUv2
3550 if (!dev_data->ats.enabled)
3553 qdep = dev_data->ats.qdep;
3554 iommu = amd_iommu_rlookup_table[dev_data->devid];
3556 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3557 qdep, address, size);
3559 ret = iommu_queue_command(iommu, &cmd);
3564 /* Wait until all device TLBs are flushed */
3565 domain_flush_complete(domain);
3574 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3577 return __flush_pasid(domain, pasid, address, false);
3580 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3583 struct protection_domain *domain = to_pdomain(dom);
3584 unsigned long flags;
3587 spin_lock_irqsave(&domain->lock, flags);
3588 ret = __amd_iommu_flush_page(domain, pasid, address);
3589 spin_unlock_irqrestore(&domain->lock, flags);
3593 EXPORT_SYMBOL(amd_iommu_flush_page);
3595 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3597 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3601 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3603 struct protection_domain *domain = to_pdomain(dom);
3604 unsigned long flags;
3607 spin_lock_irqsave(&domain->lock, flags);
3608 ret = __amd_iommu_flush_tlb(domain, pasid);
3609 spin_unlock_irqrestore(&domain->lock, flags);
3613 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3615 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3622 index = (pasid >> (9 * level)) & 0x1ff;
3628 if (!(*pte & GCR3_VALID)) {
3632 root = (void *)get_zeroed_page(GFP_ATOMIC);
3636 *pte = __pa(root) | GCR3_VALID;
3639 root = __va(*pte & PAGE_MASK);
3647 static int __set_gcr3(struct protection_domain *domain, int pasid,
3652 if (domain->mode != PAGE_MODE_NONE)
3655 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3659 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3661 return __amd_iommu_flush_tlb(domain, pasid);
3664 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3668 if (domain->mode != PAGE_MODE_NONE)
3671 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3677 return __amd_iommu_flush_tlb(domain, pasid);
3680 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3683 struct protection_domain *domain = to_pdomain(dom);
3684 unsigned long flags;
3687 spin_lock_irqsave(&domain->lock, flags);
3688 ret = __set_gcr3(domain, pasid, cr3);
3689 spin_unlock_irqrestore(&domain->lock, flags);
3693 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3695 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3697 struct protection_domain *domain = to_pdomain(dom);
3698 unsigned long flags;
3701 spin_lock_irqsave(&domain->lock, flags);
3702 ret = __clear_gcr3(domain, pasid);
3703 spin_unlock_irqrestore(&domain->lock, flags);
3707 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3709 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3710 int status, int tag)
3712 struct iommu_dev_data *dev_data;
3713 struct amd_iommu *iommu;
3714 struct iommu_cmd cmd;
3716 dev_data = get_dev_data(&pdev->dev);
3717 iommu = amd_iommu_rlookup_table[dev_data->devid];
3719 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3720 tag, dev_data->pri_tlp);
3722 return iommu_queue_command(iommu, &cmd);
3724 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3726 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3728 struct protection_domain *pdomain;
3730 pdomain = get_domain(&pdev->dev);
3731 if (IS_ERR(pdomain))
3734 /* Only return IOMMUv2 domains */
3735 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3738 return &pdomain->domain;
3740 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3742 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3744 struct iommu_dev_data *dev_data;
3746 if (!amd_iommu_v2_supported())
3749 dev_data = get_dev_data(&pdev->dev);
3750 dev_data->errata |= (1 << erratum);
3752 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3754 int amd_iommu_device_info(struct pci_dev *pdev,
3755 struct amd_iommu_device_info *info)
3760 if (pdev == NULL || info == NULL)
3763 if (!amd_iommu_v2_supported())
3766 memset(info, 0, sizeof(*info));
3768 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3770 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3772 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3774 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3776 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3780 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3781 max_pasids = min(max_pasids, (1 << 20));
3783 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3784 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3786 features = pci_pasid_features(pdev);
3787 if (features & PCI_PASID_CAP_EXEC)
3788 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3789 if (features & PCI_PASID_CAP_PRIV)
3790 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3795 EXPORT_SYMBOL(amd_iommu_device_info);
3797 #ifdef CONFIG_IRQ_REMAP
3799 /*****************************************************************************
3801 * Interrupt Remapping Implementation
3803 *****************************************************************************/
3821 u16 devid; /* Device ID for IRTE table */
3822 u16 index; /* Index into IRTE table*/
3825 struct amd_ir_data {
3826 struct irq_2_irte irq_2_irte;
3827 union irte irte_entry;
3829 struct msi_msg msi_entry;
3833 static struct irq_chip amd_ir_chip;
3835 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3836 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3837 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3838 #define DTE_IRQ_REMAP_ENABLE 1ULL
3840 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3844 dte = amd_iommu_dev_table[devid].data[2];
3845 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3846 dte |= virt_to_phys(table->table);
3847 dte |= DTE_IRQ_REMAP_INTCTL;
3848 dte |= DTE_IRQ_TABLE_LEN;
3849 dte |= DTE_IRQ_REMAP_ENABLE;
3851 amd_iommu_dev_table[devid].data[2] = dte;
3854 #define IRTE_ALLOCATED (~1U)
3856 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3858 struct irq_remap_table *table = NULL;
3859 struct amd_iommu *iommu;
3860 unsigned long flags;
3863 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3865 iommu = amd_iommu_rlookup_table[devid];
3869 table = irq_lookup_table[devid];
3873 alias = amd_iommu_alias_table[devid];
3874 table = irq_lookup_table[alias];
3876 irq_lookup_table[devid] = table;
3877 set_dte_irq_entry(devid, table);
3878 iommu_flush_dte(iommu, devid);
3882 /* Nothing there yet, allocate new irq remapping table */
3883 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3887 /* Initialize table spin-lock */
3888 spin_lock_init(&table->lock);
3891 /* Keep the first 32 indexes free for IOAPIC interrupts */
3892 table->min_index = 32;
3894 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3895 if (!table->table) {
3901 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3906 for (i = 0; i < 32; ++i)
3907 table->table[i] = IRTE_ALLOCATED;
3910 irq_lookup_table[devid] = table;
3911 set_dte_irq_entry(devid, table);
3912 iommu_flush_dte(iommu, devid);
3913 if (devid != alias) {
3914 irq_lookup_table[alias] = table;
3915 set_dte_irq_entry(alias, table);
3916 iommu_flush_dte(iommu, alias);
3920 iommu_completion_wait(iommu);
3923 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3928 static int alloc_irq_index(u16 devid, int count)
3930 struct irq_remap_table *table;
3931 unsigned long flags;
3934 table = get_irq_table(devid, false);
3938 spin_lock_irqsave(&table->lock, flags);
3940 /* Scan table for free entries */
3941 for (c = 0, index = table->min_index;
3942 index < MAX_IRQS_PER_TABLE;
3944 if (table->table[index] == 0)
3951 table->table[index - c + 1] = IRTE_ALLOCATED;
3961 spin_unlock_irqrestore(&table->lock, flags);
3966 static int modify_irte(u16 devid, int index, union irte irte)
3968 struct irq_remap_table *table;
3969 struct amd_iommu *iommu;
3970 unsigned long flags;
3972 iommu = amd_iommu_rlookup_table[devid];
3976 table = get_irq_table(devid, false);
3980 spin_lock_irqsave(&table->lock, flags);
3981 table->table[index] = irte.val;
3982 spin_unlock_irqrestore(&table->lock, flags);
3984 iommu_flush_irt(iommu, devid);
3985 iommu_completion_wait(iommu);
3990 static void free_irte(u16 devid, int index)
3992 struct irq_remap_table *table;
3993 struct amd_iommu *iommu;
3994 unsigned long flags;
3996 iommu = amd_iommu_rlookup_table[devid];
4000 table = get_irq_table(devid, false);
4004 spin_lock_irqsave(&table->lock, flags);
4005 table->table[index] = 0;
4006 spin_unlock_irqrestore(&table->lock, flags);
4008 iommu_flush_irt(iommu, devid);
4009 iommu_completion_wait(iommu);
4012 static int get_devid(struct irq_alloc_info *info)
4016 switch (info->type) {
4017 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4018 devid = get_ioapic_devid(info->ioapic_id);
4020 case X86_IRQ_ALLOC_TYPE_HPET:
4021 devid = get_hpet_devid(info->hpet_id);
4023 case X86_IRQ_ALLOC_TYPE_MSI:
4024 case X86_IRQ_ALLOC_TYPE_MSIX:
4025 devid = get_device_id(&info->msi_dev->dev);
4035 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4037 struct amd_iommu *iommu;
4043 devid = get_devid(info);
4045 iommu = amd_iommu_rlookup_table[devid];
4047 return iommu->ir_domain;
4053 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4055 struct amd_iommu *iommu;
4061 switch (info->type) {
4062 case X86_IRQ_ALLOC_TYPE_MSI:
4063 case X86_IRQ_ALLOC_TYPE_MSIX:
4064 devid = get_device_id(&info->msi_dev->dev);
4068 iommu = amd_iommu_rlookup_table[devid];
4070 return iommu->msi_domain;
4079 struct irq_remap_ops amd_iommu_irq_ops = {
4080 .prepare = amd_iommu_prepare,
4081 .enable = amd_iommu_enable,
4082 .disable = amd_iommu_disable,
4083 .reenable = amd_iommu_reenable,
4084 .enable_faulting = amd_iommu_enable_faulting,
4085 .get_ir_irq_domain = get_ir_irq_domain,
4086 .get_irq_domain = get_irq_domain,
4089 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4090 struct irq_cfg *irq_cfg,
4091 struct irq_alloc_info *info,
4092 int devid, int index, int sub_handle)
4094 struct irq_2_irte *irte_info = &data->irq_2_irte;
4095 struct msi_msg *msg = &data->msi_entry;
4096 union irte *irte = &data->irte_entry;
4097 struct IO_APIC_route_entry *entry;
4099 data->irq_2_irte.devid = devid;
4100 data->irq_2_irte.index = index + sub_handle;
4102 /* Setup IRTE for IOMMU */
4104 irte->fields.vector = irq_cfg->vector;
4105 irte->fields.int_type = apic->irq_delivery_mode;
4106 irte->fields.destination = irq_cfg->dest_apicid;
4107 irte->fields.dm = apic->irq_dest_mode;
4108 irte->fields.valid = 1;
4110 switch (info->type) {
4111 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4112 /* Setup IOAPIC entry */
4113 entry = info->ioapic_entry;
4114 info->ioapic_entry = NULL;
4115 memset(entry, 0, sizeof(*entry));
4116 entry->vector = index;
4118 entry->trigger = info->ioapic_trigger;
4119 entry->polarity = info->ioapic_polarity;
4120 /* Mask level triggered irqs. */
4121 if (info->ioapic_trigger)
4125 case X86_IRQ_ALLOC_TYPE_HPET:
4126 case X86_IRQ_ALLOC_TYPE_MSI:
4127 case X86_IRQ_ALLOC_TYPE_MSIX:
4128 msg->address_hi = MSI_ADDR_BASE_HI;
4129 msg->address_lo = MSI_ADDR_BASE_LO;
4130 msg->data = irte_info->index;
4139 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4140 unsigned int nr_irqs, void *arg)
4142 struct irq_alloc_info *info = arg;
4143 struct irq_data *irq_data;
4144 struct amd_ir_data *data;
4145 struct irq_cfg *cfg;
4151 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4152 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4156 * With IRQ remapping enabled, don't need contiguous CPU vectors
4157 * to support multiple MSI interrupts.
4159 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4160 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4162 devid = get_devid(info);
4166 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4170 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4171 if (get_irq_table(devid, true))
4172 index = info->ioapic_pin;
4176 index = alloc_irq_index(devid, nr_irqs);
4179 pr_warn("Failed to allocate IRTE\n");
4180 goto out_free_parent;
4183 for (i = 0; i < nr_irqs; i++) {
4184 irq_data = irq_domain_get_irq_data(domain, virq + i);
4185 cfg = irqd_cfg(irq_data);
4186 if (!irq_data || !cfg) {
4192 data = kzalloc(sizeof(*data), GFP_KERNEL);
4196 irq_data->hwirq = (devid << 16) + i;
4197 irq_data->chip_data = data;
4198 irq_data->chip = &amd_ir_chip;
4199 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4200 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4206 for (i--; i >= 0; i--) {
4207 irq_data = irq_domain_get_irq_data(domain, virq + i);
4209 kfree(irq_data->chip_data);
4211 for (i = 0; i < nr_irqs; i++)
4212 free_irte(devid, index + i);
4214 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4218 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4219 unsigned int nr_irqs)
4221 struct irq_2_irte *irte_info;
4222 struct irq_data *irq_data;
4223 struct amd_ir_data *data;
4226 for (i = 0; i < nr_irqs; i++) {
4227 irq_data = irq_domain_get_irq_data(domain, virq + i);
4228 if (irq_data && irq_data->chip_data) {
4229 data = irq_data->chip_data;
4230 irte_info = &data->irq_2_irte;
4231 free_irte(irte_info->devid, irte_info->index);
4235 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4238 static void irq_remapping_activate(struct irq_domain *domain,
4239 struct irq_data *irq_data)
4241 struct amd_ir_data *data = irq_data->chip_data;
4242 struct irq_2_irte *irte_info = &data->irq_2_irte;
4244 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4247 static void irq_remapping_deactivate(struct irq_domain *domain,
4248 struct irq_data *irq_data)
4250 struct amd_ir_data *data = irq_data->chip_data;
4251 struct irq_2_irte *irte_info = &data->irq_2_irte;
4255 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4258 static struct irq_domain_ops amd_ir_domain_ops = {
4259 .alloc = irq_remapping_alloc,
4260 .free = irq_remapping_free,
4261 .activate = irq_remapping_activate,
4262 .deactivate = irq_remapping_deactivate,
4265 static int amd_ir_set_affinity(struct irq_data *data,
4266 const struct cpumask *mask, bool force)
4268 struct amd_ir_data *ir_data = data->chip_data;
4269 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4270 struct irq_cfg *cfg = irqd_cfg(data);
4271 struct irq_data *parent = data->parent_data;
4274 ret = parent->chip->irq_set_affinity(parent, mask, force);
4275 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4279 * Atomically updates the IRTE with the new destination, vector
4280 * and flushes the interrupt entry cache.
4282 ir_data->irte_entry.fields.vector = cfg->vector;
4283 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
4284 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
4287 * After this point, all the interrupts will start arriving
4288 * at the new destination. So, time to cleanup the previous
4289 * vector allocation.
4291 send_cleanup_vector(cfg);
4293 return IRQ_SET_MASK_OK_DONE;
4296 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4298 struct amd_ir_data *ir_data = irq_data->chip_data;
4300 *msg = ir_data->msi_entry;
4303 static struct irq_chip amd_ir_chip = {
4304 .irq_ack = ir_ack_apic_edge,
4305 .irq_set_affinity = amd_ir_set_affinity,
4306 .irq_compose_msi_msg = ir_compose_msi_msg,
4309 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4311 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4312 if (!iommu->ir_domain)
4315 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4316 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);