2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
59 #define LOOP_TIMEOUT 100000
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
78 * 512GB Pages are not supported due to a hardware bug
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
88 LIST_HEAD(ioapic_map);
90 LIST_HEAD(acpihid_map);
92 #define FLUSH_QUEUE_SIZE 256
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
97 struct dma_ops_domain *dma_dom;
103 struct flush_queue_entry *entries;
106 DEFINE_PER_CPU(struct flush_queue, flush_queue);
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
115 static const struct iommu_ops amd_iommu_ops;
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
120 static struct dma_map_ops amd_iommu_dma_ops;
123 * This struct contains device specific data for the IOMMU
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
139 u32 errata; /* Bitmap for errata to apply */
143 * general struct to manage commands send to an IOMMU
149 struct kmem_cache *amd_iommu_irq_cache;
151 static void update_domain(struct protection_domain *domain);
152 static int protection_domain_init(struct protection_domain *domain);
153 static void detach_device(struct device *dev);
156 * Data container for a dma_ops specific protection domain
158 struct dma_ops_domain {
159 /* generic protection domain information */
160 struct protection_domain domain;
163 struct iova_domain iovad;
166 static struct iova_domain reserved_iova_ranges;
167 static struct lock_class_key reserved_rbtree_key;
169 /****************************************************************************
173 ****************************************************************************/
175 static inline int match_hid_uid(struct device *dev,
176 struct acpihid_map_entry *entry)
178 const char *hid, *uid;
180 hid = acpi_device_hid(ACPI_COMPANION(dev));
181 uid = acpi_device_uid(ACPI_COMPANION(dev));
187 return strcmp(hid, entry->hid);
190 return strcmp(hid, entry->hid);
192 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
195 static inline u16 get_pci_device_id(struct device *dev)
197 struct pci_dev *pdev = to_pci_dev(dev);
199 return PCI_DEVID(pdev->bus->number, pdev->devfn);
202 static inline int get_acpihid_device_id(struct device *dev,
203 struct acpihid_map_entry **entry)
205 struct acpihid_map_entry *p;
207 list_for_each_entry(p, &acpihid_map, list) {
208 if (!match_hid_uid(dev, p)) {
217 static inline int get_device_id(struct device *dev)
222 devid = get_pci_device_id(dev);
224 devid = get_acpihid_device_id(dev, NULL);
229 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
231 return container_of(dom, struct protection_domain, domain);
234 static struct iommu_dev_data *alloc_dev_data(u16 devid)
236 struct iommu_dev_data *dev_data;
239 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
243 dev_data->devid = devid;
245 spin_lock_irqsave(&dev_data_list_lock, flags);
246 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
247 spin_unlock_irqrestore(&dev_data_list_lock, flags);
252 static struct iommu_dev_data *search_dev_data(u16 devid)
254 struct iommu_dev_data *dev_data;
257 spin_lock_irqsave(&dev_data_list_lock, flags);
258 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
259 if (dev_data->devid == devid)
266 spin_unlock_irqrestore(&dev_data_list_lock, flags);
271 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
273 *(u16 *)data = alias;
277 static u16 get_alias(struct device *dev)
279 struct pci_dev *pdev = to_pci_dev(dev);
280 u16 devid, ivrs_alias, pci_alias;
282 /* The callers make sure that get_device_id() does not fail here */
283 devid = get_device_id(dev);
284 ivrs_alias = amd_iommu_alias_table[devid];
285 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
287 if (ivrs_alias == pci_alias)
293 * The IVRS is fairly reliable in telling us about aliases, but it
294 * can't know about every screwy device. If we don't have an IVRS
295 * reported alias, use the PCI reported alias. In that case we may
296 * still need to initialize the rlookup and dev_table entries if the
297 * alias is to a non-existent device.
299 if (ivrs_alias == devid) {
300 if (!amd_iommu_rlookup_table[pci_alias]) {
301 amd_iommu_rlookup_table[pci_alias] =
302 amd_iommu_rlookup_table[devid];
303 memcpy(amd_iommu_dev_table[pci_alias].data,
304 amd_iommu_dev_table[devid].data,
305 sizeof(amd_iommu_dev_table[pci_alias].data));
311 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
312 "for device %s[%04x:%04x], kernel reported alias "
313 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
314 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
315 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
316 PCI_FUNC(pci_alias));
319 * If we don't have a PCI DMA alias and the IVRS alias is on the same
320 * bus, then the IVRS table may know about a quirk that we don't.
322 if (pci_alias == devid &&
323 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
324 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
325 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
326 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
333 static struct iommu_dev_data *find_dev_data(u16 devid)
335 struct iommu_dev_data *dev_data;
337 dev_data = search_dev_data(devid);
339 if (dev_data == NULL)
340 dev_data = alloc_dev_data(devid);
345 static struct iommu_dev_data *get_dev_data(struct device *dev)
347 return dev->archdata.iommu;
351 * Find or create an IOMMU group for a acpihid device.
353 static struct iommu_group *acpihid_device_group(struct device *dev)
355 struct acpihid_map_entry *p, *entry = NULL;
358 devid = get_acpihid_device_id(dev, &entry);
360 return ERR_PTR(devid);
362 list_for_each_entry(p, &acpihid_map, list) {
363 if ((devid == p->devid) && p->group)
364 entry->group = p->group;
368 entry->group = generic_device_group(dev);
373 static bool pci_iommuv2_capable(struct pci_dev *pdev)
375 static const int caps[] = {
378 PCI_EXT_CAP_ID_PASID,
382 for (i = 0; i < 3; ++i) {
383 pos = pci_find_ext_capability(pdev, caps[i]);
391 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
393 struct iommu_dev_data *dev_data;
395 dev_data = get_dev_data(&pdev->dev);
397 return dev_data->errata & (1 << erratum) ? true : false;
401 * This function checks if the driver got a valid device from the caller to
402 * avoid dereferencing invalid pointers.
404 static bool check_device(struct device *dev)
408 if (!dev || !dev->dma_mask)
411 devid = get_device_id(dev);
415 /* Out of our scope? */
416 if (devid > amd_iommu_last_bdf)
419 if (amd_iommu_rlookup_table[devid] == NULL)
425 static void init_iommu_group(struct device *dev)
427 struct iommu_group *group;
429 group = iommu_group_get_for_dev(dev);
433 iommu_group_put(group);
436 static int iommu_init_device(struct device *dev)
438 struct iommu_dev_data *dev_data;
441 if (dev->archdata.iommu)
444 devid = get_device_id(dev);
448 dev_data = find_dev_data(devid);
452 dev_data->alias = get_alias(dev);
454 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
455 struct amd_iommu *iommu;
457 iommu = amd_iommu_rlookup_table[dev_data->devid];
458 dev_data->iommu_v2 = iommu->is_iommu_v2;
461 dev->archdata.iommu = dev_data;
463 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
469 static void iommu_ignore_device(struct device *dev)
474 devid = get_device_id(dev);
478 alias = get_alias(dev);
480 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
481 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
483 amd_iommu_rlookup_table[devid] = NULL;
484 amd_iommu_rlookup_table[alias] = NULL;
487 static void iommu_uninit_device(struct device *dev)
490 struct iommu_dev_data *dev_data;
492 devid = get_device_id(dev);
496 dev_data = search_dev_data(devid);
500 if (dev_data->domain)
503 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
506 iommu_group_remove_device(dev);
509 dev->archdata.dma_ops = NULL;
512 * We keep dev_data around for unplugged devices and reuse it when the
513 * device is re-plugged - not doing so would introduce a ton of races.
517 /****************************************************************************
519 * Interrupt handling functions
521 ****************************************************************************/
523 static void dump_dte_entry(u16 devid)
527 for (i = 0; i < 4; ++i)
528 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
529 amd_iommu_dev_table[devid].data[i]);
532 static void dump_command(unsigned long phys_addr)
534 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
537 for (i = 0; i < 4; ++i)
538 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
541 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
543 int type, devid, domid, flags;
544 volatile u32 *event = __evt;
549 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
550 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
551 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
552 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
553 address = (u64)(((u64)event[3]) << 32) | event[2];
556 /* Did we hit the erratum? */
557 if (++count == LOOP_TIMEOUT) {
558 pr_err("AMD-Vi: No event written to event log\n");
565 printk(KERN_ERR "AMD-Vi: Event logged [");
568 case EVENT_TYPE_ILL_DEV:
569 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
570 "address=0x%016llx flags=0x%04x]\n",
571 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
573 dump_dte_entry(devid);
575 case EVENT_TYPE_IO_FAULT:
576 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
577 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
578 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
579 domid, address, flags);
581 case EVENT_TYPE_DEV_TAB_ERR:
582 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
583 "address=0x%016llx flags=0x%04x]\n",
584 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
587 case EVENT_TYPE_PAGE_TAB_ERR:
588 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
589 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
591 domid, address, flags);
593 case EVENT_TYPE_ILL_CMD:
594 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
595 dump_command(address);
597 case EVENT_TYPE_CMD_HARD_ERR:
598 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
599 "flags=0x%04x]\n", address, flags);
601 case EVENT_TYPE_IOTLB_INV_TO:
602 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
603 "address=0x%016llx]\n",
604 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
607 case EVENT_TYPE_INV_DEV_REQ:
608 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
609 "address=0x%016llx flags=0x%04x]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
617 memset(__evt, 0, 4 * sizeof(u32));
620 static void iommu_poll_events(struct amd_iommu *iommu)
624 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
625 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
627 while (head != tail) {
628 iommu_print_event(iommu, iommu->evt_buf + head);
629 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
632 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
635 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
637 struct amd_iommu_fault fault;
639 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
640 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
644 fault.address = raw[1];
645 fault.pasid = PPR_PASID(raw[0]);
646 fault.device_id = PPR_DEVID(raw[0]);
647 fault.tag = PPR_TAG(raw[0]);
648 fault.flags = PPR_FLAGS(raw[0]);
650 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
653 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
657 if (iommu->ppr_log == NULL)
660 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
661 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
663 while (head != tail) {
668 raw = (u64 *)(iommu->ppr_log + head);
671 * Hardware bug: Interrupt may arrive before the entry is
672 * written to memory. If this happens we need to wait for the
675 for (i = 0; i < LOOP_TIMEOUT; ++i) {
676 if (PPR_REQ_TYPE(raw[0]) != 0)
681 /* Avoid memcpy function-call overhead */
686 * To detect the hardware bug we need to clear the entry
689 raw[0] = raw[1] = 0UL;
691 /* Update head pointer of hardware ring-buffer */
692 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
693 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
695 /* Handle PPR entry */
696 iommu_handle_ppr_entry(iommu, entry);
698 /* Refresh ring-buffer information */
699 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
704 irqreturn_t amd_iommu_int_thread(int irq, void *data)
706 struct amd_iommu *iommu = (struct amd_iommu *) data;
707 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
709 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
710 /* Enable EVT and PPR interrupts again */
711 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
712 iommu->mmio_base + MMIO_STATUS_OFFSET);
714 if (status & MMIO_STATUS_EVT_INT_MASK) {
715 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
716 iommu_poll_events(iommu);
719 if (status & MMIO_STATUS_PPR_INT_MASK) {
720 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
721 iommu_poll_ppr_log(iommu);
725 * Hardware bug: ERBT1312
726 * When re-enabling interrupt (by writing 1
727 * to clear the bit), the hardware might also try to set
728 * the interrupt bit in the event status register.
729 * In this scenario, the bit will be set, and disable
730 * subsequent interrupts.
732 * Workaround: The IOMMU driver should read back the
733 * status register and check if the interrupt bits are cleared.
734 * If not, driver will need to go through the interrupt handler
735 * again and re-clear the bits
737 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
742 irqreturn_t amd_iommu_int_handler(int irq, void *data)
744 return IRQ_WAKE_THREAD;
747 /****************************************************************************
749 * IOMMU command queuing functions
751 ****************************************************************************/
753 static int wait_on_sem(volatile u64 *sem)
757 while (*sem == 0 && i < LOOP_TIMEOUT) {
762 if (i == LOOP_TIMEOUT) {
763 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
770 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
771 struct iommu_cmd *cmd,
776 target = iommu->cmd_buf + tail;
777 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
779 /* Copy command to buffer */
780 memcpy(target, cmd, sizeof(*cmd));
782 /* Tell the IOMMU about it */
783 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
786 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
788 WARN_ON(address & 0x7ULL);
790 memset(cmd, 0, sizeof(*cmd));
791 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
792 cmd->data[1] = upper_32_bits(__pa(address));
794 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
797 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
799 memset(cmd, 0, sizeof(*cmd));
800 cmd->data[0] = devid;
801 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
804 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
805 size_t size, u16 domid, int pde)
810 pages = iommu_num_pages(address, size, PAGE_SIZE);
815 * If we have to flush more than one page, flush all
816 * TLB entries for this domain
818 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
822 address &= PAGE_MASK;
824 memset(cmd, 0, sizeof(*cmd));
825 cmd->data[1] |= domid;
826 cmd->data[2] = lower_32_bits(address);
827 cmd->data[3] = upper_32_bits(address);
828 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
829 if (s) /* size bit - we flush more than one 4kb page */
830 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
831 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
832 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
835 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
836 u64 address, size_t size)
841 pages = iommu_num_pages(address, size, PAGE_SIZE);
846 * If we have to flush more than one page, flush all
847 * TLB entries for this domain
849 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
853 address &= PAGE_MASK;
855 memset(cmd, 0, sizeof(*cmd));
856 cmd->data[0] = devid;
857 cmd->data[0] |= (qdep & 0xff) << 24;
858 cmd->data[1] = devid;
859 cmd->data[2] = lower_32_bits(address);
860 cmd->data[3] = upper_32_bits(address);
861 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
863 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
866 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
867 u64 address, bool size)
869 memset(cmd, 0, sizeof(*cmd));
871 address &= ~(0xfffULL);
873 cmd->data[0] = pasid;
874 cmd->data[1] = domid;
875 cmd->data[2] = lower_32_bits(address);
876 cmd->data[3] = upper_32_bits(address);
877 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
878 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
880 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
881 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
884 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
885 int qdep, u64 address, bool size)
887 memset(cmd, 0, sizeof(*cmd));
889 address &= ~(0xfffULL);
891 cmd->data[0] = devid;
892 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
893 cmd->data[0] |= (qdep & 0xff) << 24;
894 cmd->data[1] = devid;
895 cmd->data[1] |= (pasid & 0xff) << 16;
896 cmd->data[2] = lower_32_bits(address);
897 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
898 cmd->data[3] = upper_32_bits(address);
900 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
901 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
904 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
905 int status, int tag, bool gn)
907 memset(cmd, 0, sizeof(*cmd));
909 cmd->data[0] = devid;
911 cmd->data[1] = pasid;
912 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
914 cmd->data[3] = tag & 0x1ff;
915 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
917 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
920 static void build_inv_all(struct iommu_cmd *cmd)
922 memset(cmd, 0, sizeof(*cmd));
923 CMD_SET_TYPE(cmd, CMD_INV_ALL);
926 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
928 memset(cmd, 0, sizeof(*cmd));
929 cmd->data[0] = devid;
930 CMD_SET_TYPE(cmd, CMD_INV_IRT);
934 * Writes the command to the IOMMUs command buffer and informs the
935 * hardware about the new command.
937 static int iommu_queue_command_sync(struct amd_iommu *iommu,
938 struct iommu_cmd *cmd,
941 u32 left, tail, head, next_tail;
945 spin_lock_irqsave(&iommu->lock, flags);
947 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
948 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
949 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
950 left = (head - next_tail) % CMD_BUFFER_SIZE;
953 struct iommu_cmd sync_cmd;
954 volatile u64 sem = 0;
957 build_completion_wait(&sync_cmd, (u64)&sem);
958 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
960 spin_unlock_irqrestore(&iommu->lock, flags);
962 if ((ret = wait_on_sem(&sem)) != 0)
968 copy_cmd_to_buffer(iommu, cmd, tail);
970 /* We need to sync now to make sure all commands are processed */
971 iommu->need_sync = sync;
973 spin_unlock_irqrestore(&iommu->lock, flags);
978 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
980 return iommu_queue_command_sync(iommu, cmd, true);
984 * This function queues a completion wait command into the command
987 static int iommu_completion_wait(struct amd_iommu *iommu)
989 struct iommu_cmd cmd;
990 volatile u64 sem = 0;
993 if (!iommu->need_sync)
996 build_completion_wait(&cmd, (u64)&sem);
998 ret = iommu_queue_command_sync(iommu, &cmd, false);
1002 return wait_on_sem(&sem);
1005 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1007 struct iommu_cmd cmd;
1009 build_inv_dte(&cmd, devid);
1011 return iommu_queue_command(iommu, &cmd);
1014 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1018 for (devid = 0; devid <= 0xffff; ++devid)
1019 iommu_flush_dte(iommu, devid);
1021 iommu_completion_wait(iommu);
1025 * This function uses heavy locking and may disable irqs for some time. But
1026 * this is no issue because it is only called during resume.
1028 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1032 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1033 struct iommu_cmd cmd;
1034 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1036 iommu_queue_command(iommu, &cmd);
1039 iommu_completion_wait(iommu);
1042 static void iommu_flush_all(struct amd_iommu *iommu)
1044 struct iommu_cmd cmd;
1046 build_inv_all(&cmd);
1048 iommu_queue_command(iommu, &cmd);
1049 iommu_completion_wait(iommu);
1052 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1054 struct iommu_cmd cmd;
1056 build_inv_irt(&cmd, devid);
1058 iommu_queue_command(iommu, &cmd);
1061 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1065 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1066 iommu_flush_irt(iommu, devid);
1068 iommu_completion_wait(iommu);
1071 void iommu_flush_all_caches(struct amd_iommu *iommu)
1073 if (iommu_feature(iommu, FEATURE_IA)) {
1074 iommu_flush_all(iommu);
1076 iommu_flush_dte_all(iommu);
1077 iommu_flush_irt_all(iommu);
1078 iommu_flush_tlb_all(iommu);
1083 * Command send function for flushing on-device TLB
1085 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1086 u64 address, size_t size)
1088 struct amd_iommu *iommu;
1089 struct iommu_cmd cmd;
1092 qdep = dev_data->ats.qdep;
1093 iommu = amd_iommu_rlookup_table[dev_data->devid];
1095 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1097 return iommu_queue_command(iommu, &cmd);
1101 * Command send function for invalidating a device table entry
1103 static int device_flush_dte(struct iommu_dev_data *dev_data)
1105 struct amd_iommu *iommu;
1109 iommu = amd_iommu_rlookup_table[dev_data->devid];
1110 alias = dev_data->alias;
1112 ret = iommu_flush_dte(iommu, dev_data->devid);
1113 if (!ret && alias != dev_data->devid)
1114 ret = iommu_flush_dte(iommu, alias);
1118 if (dev_data->ats.enabled)
1119 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1125 * TLB invalidation function which is called from the mapping functions.
1126 * It invalidates a single PTE if the range to flush is within a single
1127 * page. Otherwise it flushes the whole TLB of the IOMMU.
1129 static void __domain_flush_pages(struct protection_domain *domain,
1130 u64 address, size_t size, int pde)
1132 struct iommu_dev_data *dev_data;
1133 struct iommu_cmd cmd;
1136 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1138 for (i = 0; i < amd_iommus_present; ++i) {
1139 if (!domain->dev_iommu[i])
1143 * Devices of this domain are behind this IOMMU
1144 * We need a TLB flush
1146 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1149 list_for_each_entry(dev_data, &domain->dev_list, list) {
1151 if (!dev_data->ats.enabled)
1154 ret |= device_flush_iotlb(dev_data, address, size);
1160 static void domain_flush_pages(struct protection_domain *domain,
1161 u64 address, size_t size)
1163 __domain_flush_pages(domain, address, size, 0);
1166 /* Flush the whole IO/TLB for a given protection domain */
1167 static void domain_flush_tlb(struct protection_domain *domain)
1169 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1172 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1173 static void domain_flush_tlb_pde(struct protection_domain *domain)
1175 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1178 static void domain_flush_complete(struct protection_domain *domain)
1182 for (i = 0; i < amd_iommus_present; ++i) {
1183 if (domain && !domain->dev_iommu[i])
1187 * Devices of this domain are behind this IOMMU
1188 * We need to wait for completion of all commands.
1190 iommu_completion_wait(amd_iommus[i]);
1196 * This function flushes the DTEs for all devices in domain
1198 static void domain_flush_devices(struct protection_domain *domain)
1200 struct iommu_dev_data *dev_data;
1202 list_for_each_entry(dev_data, &domain->dev_list, list)
1203 device_flush_dte(dev_data);
1206 /****************************************************************************
1208 * The functions below are used the create the page table mappings for
1209 * unity mapped regions.
1211 ****************************************************************************/
1214 * This function is used to add another level to an IO page table. Adding
1215 * another level increases the size of the address space by 9 bits to a size up
1218 static bool increase_address_space(struct protection_domain *domain,
1223 if (domain->mode == PAGE_MODE_6_LEVEL)
1224 /* address space already 64 bit large */
1227 pte = (void *)get_zeroed_page(gfp);
1231 *pte = PM_LEVEL_PDE(domain->mode,
1232 virt_to_phys(domain->pt_root));
1233 domain->pt_root = pte;
1235 domain->updated = true;
1240 static u64 *alloc_pte(struct protection_domain *domain,
1241 unsigned long address,
1242 unsigned long page_size,
1249 BUG_ON(!is_power_of_2(page_size));
1251 while (address > PM_LEVEL_SIZE(domain->mode))
1252 increase_address_space(domain, gfp);
1254 level = domain->mode - 1;
1255 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1256 address = PAGE_SIZE_ALIGN(address, page_size);
1257 end_lvl = PAGE_SIZE_LEVEL(page_size);
1259 while (level > end_lvl) {
1264 if (!IOMMU_PTE_PRESENT(__pte)) {
1265 page = (u64 *)get_zeroed_page(gfp);
1269 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1271 if (cmpxchg64(pte, __pte, __npte)) {
1272 free_page((unsigned long)page);
1277 /* No level skipping support yet */
1278 if (PM_PTE_LEVEL(*pte) != level)
1283 pte = IOMMU_PTE_PAGE(*pte);
1285 if (pte_page && level == end_lvl)
1288 pte = &pte[PM_LEVEL_INDEX(level, address)];
1295 * This function checks if there is a PTE for a given dma address. If
1296 * there is one, it returns the pointer to it.
1298 static u64 *fetch_pte(struct protection_domain *domain,
1299 unsigned long address,
1300 unsigned long *page_size)
1305 if (address > PM_LEVEL_SIZE(domain->mode))
1308 level = domain->mode - 1;
1309 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1310 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1315 if (!IOMMU_PTE_PRESENT(*pte))
1319 if (PM_PTE_LEVEL(*pte) == 7 ||
1320 PM_PTE_LEVEL(*pte) == 0)
1323 /* No level skipping support yet */
1324 if (PM_PTE_LEVEL(*pte) != level)
1329 /* Walk to the next level */
1330 pte = IOMMU_PTE_PAGE(*pte);
1331 pte = &pte[PM_LEVEL_INDEX(level, address)];
1332 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1335 if (PM_PTE_LEVEL(*pte) == 0x07) {
1336 unsigned long pte_mask;
1339 * If we have a series of large PTEs, make
1340 * sure to return a pointer to the first one.
1342 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1343 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1344 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1351 * Generic mapping functions. It maps a physical address into a DMA
1352 * address space. It allocates the page table pages if necessary.
1353 * In the future it can be extended to a generic mapping function
1354 * supporting all features of AMD IOMMU page tables like level skipping
1355 * and full 64 bit address spaces.
1357 static int iommu_map_page(struct protection_domain *dom,
1358 unsigned long bus_addr,
1359 unsigned long phys_addr,
1360 unsigned long page_size,
1367 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1368 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1370 if (!(prot & IOMMU_PROT_MASK))
1373 count = PAGE_SIZE_PTE_COUNT(page_size);
1374 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1379 for (i = 0; i < count; ++i)
1380 if (IOMMU_PTE_PRESENT(pte[i]))
1384 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1385 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1387 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1389 if (prot & IOMMU_PROT_IR)
1390 __pte |= IOMMU_PTE_IR;
1391 if (prot & IOMMU_PROT_IW)
1392 __pte |= IOMMU_PTE_IW;
1394 for (i = 0; i < count; ++i)
1402 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1403 unsigned long bus_addr,
1404 unsigned long page_size)
1406 unsigned long long unmapped;
1407 unsigned long unmap_size;
1410 BUG_ON(!is_power_of_2(page_size));
1414 while (unmapped < page_size) {
1416 pte = fetch_pte(dom, bus_addr, &unmap_size);
1421 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1422 for (i = 0; i < count; i++)
1426 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1427 unmapped += unmap_size;
1430 BUG_ON(unmapped && !is_power_of_2(unmapped));
1435 /****************************************************************************
1437 * The next functions belong to the address allocator for the dma_ops
1438 * interface functions.
1440 ****************************************************************************/
1443 static unsigned long dma_ops_alloc_iova(struct device *dev,
1444 struct dma_ops_domain *dma_dom,
1445 unsigned int pages, u64 dma_mask)
1447 unsigned long pfn = 0;
1449 pages = __roundup_pow_of_two(pages);
1451 if (dma_mask > DMA_BIT_MASK(32))
1452 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1453 IOVA_PFN(DMA_BIT_MASK(32)));
1456 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1458 return (pfn << PAGE_SHIFT);
1461 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1462 unsigned long address,
1465 pages = __roundup_pow_of_two(pages);
1466 address >>= PAGE_SHIFT;
1468 free_iova_fast(&dma_dom->iovad, address, pages);
1471 /****************************************************************************
1473 * The next functions belong to the domain allocation. A domain is
1474 * allocated for every IOMMU as the default domain. If device isolation
1475 * is enabled, every device get its own domain. The most important thing
1476 * about domains is the page table mapping the DMA address space they
1479 ****************************************************************************/
1482 * This function adds a protection domain to the global protection domain list
1484 static void add_domain_to_list(struct protection_domain *domain)
1486 unsigned long flags;
1488 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1489 list_add(&domain->list, &amd_iommu_pd_list);
1490 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1494 * This function removes a protection domain to the global
1495 * protection domain list
1497 static void del_domain_from_list(struct protection_domain *domain)
1499 unsigned long flags;
1501 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1502 list_del(&domain->list);
1503 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1506 static u16 domain_id_alloc(void)
1508 unsigned long flags;
1511 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1512 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1514 if (id > 0 && id < MAX_DOMAIN_ID)
1515 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1518 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1523 static void domain_id_free(int id)
1525 unsigned long flags;
1527 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1528 if (id > 0 && id < MAX_DOMAIN_ID)
1529 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1530 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1533 #define DEFINE_FREE_PT_FN(LVL, FN) \
1534 static void free_pt_##LVL (unsigned long __pt) \
1542 for (i = 0; i < 512; ++i) { \
1543 /* PTE present? */ \
1544 if (!IOMMU_PTE_PRESENT(pt[i])) \
1548 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1549 PM_PTE_LEVEL(pt[i]) == 7) \
1552 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1555 free_page((unsigned long)pt); \
1558 DEFINE_FREE_PT_FN(l2, free_page)
1559 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1560 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1561 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1562 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1564 static void free_pagetable(struct protection_domain *domain)
1566 unsigned long root = (unsigned long)domain->pt_root;
1568 switch (domain->mode) {
1569 case PAGE_MODE_NONE:
1571 case PAGE_MODE_1_LEVEL:
1574 case PAGE_MODE_2_LEVEL:
1577 case PAGE_MODE_3_LEVEL:
1580 case PAGE_MODE_4_LEVEL:
1583 case PAGE_MODE_5_LEVEL:
1586 case PAGE_MODE_6_LEVEL:
1594 static void free_gcr3_tbl_level1(u64 *tbl)
1599 for (i = 0; i < 512; ++i) {
1600 if (!(tbl[i] & GCR3_VALID))
1603 ptr = __va(tbl[i] & PAGE_MASK);
1605 free_page((unsigned long)ptr);
1609 static void free_gcr3_tbl_level2(u64 *tbl)
1614 for (i = 0; i < 512; ++i) {
1615 if (!(tbl[i] & GCR3_VALID))
1618 ptr = __va(tbl[i] & PAGE_MASK);
1620 free_gcr3_tbl_level1(ptr);
1624 static void free_gcr3_table(struct protection_domain *domain)
1626 if (domain->glx == 2)
1627 free_gcr3_tbl_level2(domain->gcr3_tbl);
1628 else if (domain->glx == 1)
1629 free_gcr3_tbl_level1(domain->gcr3_tbl);
1631 BUG_ON(domain->glx != 0);
1633 free_page((unsigned long)domain->gcr3_tbl);
1637 * Free a domain, only used if something went wrong in the
1638 * allocation path and we need to free an already allocated page table
1640 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1645 del_domain_from_list(&dom->domain);
1647 put_iova_domain(&dom->iovad);
1649 free_pagetable(&dom->domain);
1655 * Allocates a new protection domain usable for the dma_ops functions.
1656 * It also initializes the page table and the address allocator data
1657 * structures required for the dma_ops interface
1659 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1661 struct dma_ops_domain *dma_dom;
1663 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1667 if (protection_domain_init(&dma_dom->domain))
1670 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1671 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1672 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1673 dma_dom->domain.priv = dma_dom;
1674 if (!dma_dom->domain.pt_root)
1677 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1678 IOVA_START_PFN, DMA_32BIT_PFN);
1680 /* Initialize reserved ranges */
1681 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1683 add_domain_to_list(&dma_dom->domain);
1688 dma_ops_domain_free(dma_dom);
1694 * little helper function to check whether a given protection domain is a
1697 static bool dma_ops_domain(struct protection_domain *domain)
1699 return domain->flags & PD_DMA_OPS_MASK;
1702 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1707 if (domain->mode != PAGE_MODE_NONE)
1708 pte_root = virt_to_phys(domain->pt_root);
1710 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1711 << DEV_ENTRY_MODE_SHIFT;
1712 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1714 flags = amd_iommu_dev_table[devid].data[1];
1717 flags |= DTE_FLAG_IOTLB;
1719 if (domain->flags & PD_IOMMUV2_MASK) {
1720 u64 gcr3 = __pa(domain->gcr3_tbl);
1721 u64 glx = domain->glx;
1724 pte_root |= DTE_FLAG_GV;
1725 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1727 /* First mask out possible old values for GCR3 table */
1728 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1731 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1734 /* Encode GCR3 table into DTE */
1735 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1738 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1741 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1745 flags &= ~(0xffffUL);
1746 flags |= domain->id;
1748 amd_iommu_dev_table[devid].data[1] = flags;
1749 amd_iommu_dev_table[devid].data[0] = pte_root;
1752 static void clear_dte_entry(u16 devid)
1754 /* remove entry from the device table seen by the hardware */
1755 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1756 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1758 amd_iommu_apply_erratum_63(devid);
1761 static void do_attach(struct iommu_dev_data *dev_data,
1762 struct protection_domain *domain)
1764 struct amd_iommu *iommu;
1768 iommu = amd_iommu_rlookup_table[dev_data->devid];
1769 alias = dev_data->alias;
1770 ats = dev_data->ats.enabled;
1772 /* Update data structures */
1773 dev_data->domain = domain;
1774 list_add(&dev_data->list, &domain->dev_list);
1776 /* Do reference counting */
1777 domain->dev_iommu[iommu->index] += 1;
1778 domain->dev_cnt += 1;
1780 /* Update device table */
1781 set_dte_entry(dev_data->devid, domain, ats);
1782 if (alias != dev_data->devid)
1783 set_dte_entry(alias, domain, ats);
1785 device_flush_dte(dev_data);
1788 static void do_detach(struct iommu_dev_data *dev_data)
1790 struct amd_iommu *iommu;
1794 * First check if the device is still attached. It might already
1795 * be detached from its domain because the generic
1796 * iommu_detach_group code detached it and we try again here in
1797 * our alias handling.
1799 if (!dev_data->domain)
1802 iommu = amd_iommu_rlookup_table[dev_data->devid];
1803 alias = dev_data->alias;
1805 /* decrease reference counters */
1806 dev_data->domain->dev_iommu[iommu->index] -= 1;
1807 dev_data->domain->dev_cnt -= 1;
1809 /* Update data structures */
1810 dev_data->domain = NULL;
1811 list_del(&dev_data->list);
1812 clear_dte_entry(dev_data->devid);
1813 if (alias != dev_data->devid)
1814 clear_dte_entry(alias);
1816 /* Flush the DTE entry */
1817 device_flush_dte(dev_data);
1821 * If a device is not yet associated with a domain, this function does
1822 * assigns it visible for the hardware
1824 static int __attach_device(struct iommu_dev_data *dev_data,
1825 struct protection_domain *domain)
1830 * Must be called with IRQs disabled. Warn here to detect early
1833 WARN_ON(!irqs_disabled());
1836 spin_lock(&domain->lock);
1839 if (dev_data->domain != NULL)
1842 /* Attach alias group root */
1843 do_attach(dev_data, domain);
1850 spin_unlock(&domain->lock);
1856 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1858 pci_disable_ats(pdev);
1859 pci_disable_pri(pdev);
1860 pci_disable_pasid(pdev);
1863 /* FIXME: Change generic reset-function to do the same */
1864 static int pri_reset_while_enabled(struct pci_dev *pdev)
1869 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1873 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1874 control |= PCI_PRI_CTRL_RESET;
1875 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1880 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1885 /* FIXME: Hardcode number of outstanding requests for now */
1887 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1889 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1891 /* Only allow access to user-accessible pages */
1892 ret = pci_enable_pasid(pdev, 0);
1896 /* First reset the PRI state of the device */
1897 ret = pci_reset_pri(pdev);
1902 ret = pci_enable_pri(pdev, reqs);
1907 ret = pri_reset_while_enabled(pdev);
1912 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1919 pci_disable_pri(pdev);
1920 pci_disable_pasid(pdev);
1925 /* FIXME: Move this to PCI code */
1926 #define PCI_PRI_TLP_OFF (1 << 15)
1928 static bool pci_pri_tlp_required(struct pci_dev *pdev)
1933 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1937 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
1939 return (status & PCI_PRI_TLP_OFF) ? true : false;
1943 * If a device is not yet associated with a domain, this function
1944 * assigns it visible for the hardware
1946 static int attach_device(struct device *dev,
1947 struct protection_domain *domain)
1949 struct pci_dev *pdev;
1950 struct iommu_dev_data *dev_data;
1951 unsigned long flags;
1954 dev_data = get_dev_data(dev);
1956 if (!dev_is_pci(dev))
1957 goto skip_ats_check;
1959 pdev = to_pci_dev(dev);
1960 if (domain->flags & PD_IOMMUV2_MASK) {
1961 if (!dev_data->passthrough)
1964 if (dev_data->iommu_v2) {
1965 if (pdev_iommuv2_enable(pdev) != 0)
1968 dev_data->ats.enabled = true;
1969 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1970 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
1972 } else if (amd_iommu_iotlb_sup &&
1973 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1974 dev_data->ats.enabled = true;
1975 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1979 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1980 ret = __attach_device(dev_data, domain);
1981 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1984 * We might boot into a crash-kernel here. The crashed kernel
1985 * left the caches in the IOMMU dirty. So we have to flush
1986 * here to evict all dirty stuff.
1988 domain_flush_tlb_pde(domain);
1994 * Removes a device from a protection domain (unlocked)
1996 static void __detach_device(struct iommu_dev_data *dev_data)
1998 struct protection_domain *domain;
2001 * Must be called with IRQs disabled. Warn here to detect early
2004 WARN_ON(!irqs_disabled());
2006 if (WARN_ON(!dev_data->domain))
2009 domain = dev_data->domain;
2011 spin_lock(&domain->lock);
2013 do_detach(dev_data);
2015 spin_unlock(&domain->lock);
2019 * Removes a device from a protection domain (with devtable_lock held)
2021 static void detach_device(struct device *dev)
2023 struct protection_domain *domain;
2024 struct iommu_dev_data *dev_data;
2025 unsigned long flags;
2027 dev_data = get_dev_data(dev);
2028 domain = dev_data->domain;
2030 /* lock device table */
2031 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2032 __detach_device(dev_data);
2033 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2035 if (!dev_is_pci(dev))
2038 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2039 pdev_iommuv2_disable(to_pci_dev(dev));
2040 else if (dev_data->ats.enabled)
2041 pci_disable_ats(to_pci_dev(dev));
2043 dev_data->ats.enabled = false;
2046 static int amd_iommu_add_device(struct device *dev)
2048 struct iommu_dev_data *dev_data;
2049 struct iommu_domain *domain;
2050 struct amd_iommu *iommu;
2053 if (!check_device(dev) || get_dev_data(dev))
2056 devid = get_device_id(dev);
2060 iommu = amd_iommu_rlookup_table[devid];
2062 ret = iommu_init_device(dev);
2064 if (ret != -ENOTSUPP)
2065 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2068 iommu_ignore_device(dev);
2069 dev->archdata.dma_ops = &nommu_dma_ops;
2072 init_iommu_group(dev);
2074 dev_data = get_dev_data(dev);
2078 if (iommu_pass_through || dev_data->iommu_v2)
2079 iommu_request_dm_for_dev(dev);
2081 /* Domains are initialized for this device - have a look what we ended up with */
2082 domain = iommu_get_domain_for_dev(dev);
2083 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2084 dev_data->passthrough = true;
2086 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2089 iommu_completion_wait(iommu);
2094 static void amd_iommu_remove_device(struct device *dev)
2096 struct amd_iommu *iommu;
2099 if (!check_device(dev))
2102 devid = get_device_id(dev);
2106 iommu = amd_iommu_rlookup_table[devid];
2108 iommu_uninit_device(dev);
2109 iommu_completion_wait(iommu);
2112 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2114 if (dev_is_pci(dev))
2115 return pci_device_group(dev);
2117 return acpihid_device_group(dev);
2120 /*****************************************************************************
2122 * The next functions belong to the dma_ops mapping/unmapping code.
2124 *****************************************************************************/
2126 static void __queue_flush(struct flush_queue *queue)
2128 struct protection_domain *domain;
2129 unsigned long flags;
2132 /* First flush TLB of all known domains */
2133 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2134 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2135 domain_flush_tlb(domain);
2136 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2138 /* Wait until flushes have completed */
2139 domain_flush_complete(NULL);
2141 for (idx = 0; idx < queue->next; ++idx) {
2142 struct flush_queue_entry *entry;
2144 entry = queue->entries + idx;
2146 free_iova_fast(&entry->dma_dom->iovad,
2150 /* Not really necessary, just to make sure we catch any bugs */
2151 entry->dma_dom = NULL;
2157 void queue_flush_timeout(unsigned long unsused)
2161 atomic_set(&queue_timer_on, 0);
2163 for_each_possible_cpu(cpu) {
2164 struct flush_queue *queue;
2165 unsigned long flags;
2167 queue = per_cpu_ptr(&flush_queue, cpu);
2168 spin_lock_irqsave(&queue->lock, flags);
2169 if (queue->next > 0)
2170 __queue_flush(queue);
2171 spin_unlock_irqrestore(&queue->lock, flags);
2175 static void queue_add(struct dma_ops_domain *dma_dom,
2176 unsigned long address, unsigned long pages)
2178 struct flush_queue_entry *entry;
2179 struct flush_queue *queue;
2180 unsigned long flags;
2183 pages = __roundup_pow_of_two(pages);
2184 address >>= PAGE_SHIFT;
2186 queue = get_cpu_ptr(&flush_queue);
2187 spin_lock_irqsave(&queue->lock, flags);
2189 if (queue->next == FLUSH_QUEUE_SIZE)
2190 __queue_flush(queue);
2192 idx = queue->next++;
2193 entry = queue->entries + idx;
2195 entry->iova_pfn = address;
2196 entry->pages = pages;
2197 entry->dma_dom = dma_dom;
2199 spin_unlock_irqrestore(&queue->lock, flags);
2201 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2202 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2204 put_cpu_ptr(&flush_queue);
2209 * In the dma_ops path we only have the struct device. This function
2210 * finds the corresponding IOMMU, the protection domain and the
2211 * requestor id for a given device.
2212 * If the device is not yet associated with a domain this is also done
2215 static struct protection_domain *get_domain(struct device *dev)
2217 struct protection_domain *domain;
2219 if (!check_device(dev))
2220 return ERR_PTR(-EINVAL);
2222 domain = get_dev_data(dev)->domain;
2223 if (!dma_ops_domain(domain))
2224 return ERR_PTR(-EBUSY);
2229 static void update_device_table(struct protection_domain *domain)
2231 struct iommu_dev_data *dev_data;
2233 list_for_each_entry(dev_data, &domain->dev_list, list)
2234 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2237 static void update_domain(struct protection_domain *domain)
2239 if (!domain->updated)
2242 update_device_table(domain);
2244 domain_flush_devices(domain);
2245 domain_flush_tlb_pde(domain);
2247 domain->updated = false;
2250 static int dir2prot(enum dma_data_direction direction)
2252 if (direction == DMA_TO_DEVICE)
2253 return IOMMU_PROT_IR;
2254 else if (direction == DMA_FROM_DEVICE)
2255 return IOMMU_PROT_IW;
2256 else if (direction == DMA_BIDIRECTIONAL)
2257 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2262 * This function contains common code for mapping of a physically
2263 * contiguous memory region into DMA address space. It is used by all
2264 * mapping functions provided with this IOMMU driver.
2265 * Must be called with the domain lock held.
2267 static dma_addr_t __map_single(struct device *dev,
2268 struct dma_ops_domain *dma_dom,
2271 enum dma_data_direction direction,
2274 dma_addr_t offset = paddr & ~PAGE_MASK;
2275 dma_addr_t address, start, ret;
2280 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2283 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2284 if (address == DMA_ERROR_CODE)
2287 prot = dir2prot(direction);
2290 for (i = 0; i < pages; ++i) {
2291 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2292 PAGE_SIZE, prot, GFP_ATOMIC);
2301 if (unlikely(amd_iommu_np_cache)) {
2302 domain_flush_pages(&dma_dom->domain, address, size);
2303 domain_flush_complete(&dma_dom->domain);
2311 for (--i; i >= 0; --i) {
2313 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2316 domain_flush_tlb(&dma_dom->domain);
2317 domain_flush_complete(&dma_dom->domain);
2319 dma_ops_free_iova(dma_dom, address, pages);
2321 return DMA_ERROR_CODE;
2325 * Does the reverse of the __map_single function. Must be called with
2326 * the domain lock held too
2328 static void __unmap_single(struct dma_ops_domain *dma_dom,
2329 dma_addr_t dma_addr,
2333 dma_addr_t flush_addr;
2334 dma_addr_t i, start;
2337 flush_addr = dma_addr;
2338 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2339 dma_addr &= PAGE_MASK;
2342 for (i = 0; i < pages; ++i) {
2343 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2347 if (amd_iommu_unmap_flush) {
2348 dma_ops_free_iova(dma_dom, dma_addr, pages);
2349 domain_flush_tlb(&dma_dom->domain);
2350 domain_flush_complete(&dma_dom->domain);
2352 queue_add(dma_dom, dma_addr, pages);
2357 * The exported map_single function for dma_ops.
2359 static dma_addr_t map_page(struct device *dev, struct page *page,
2360 unsigned long offset, size_t size,
2361 enum dma_data_direction dir,
2362 struct dma_attrs *attrs)
2364 phys_addr_t paddr = page_to_phys(page) + offset;
2365 struct protection_domain *domain;
2368 domain = get_domain(dev);
2369 if (PTR_ERR(domain) == -EINVAL)
2370 return (dma_addr_t)paddr;
2371 else if (IS_ERR(domain))
2372 return DMA_ERROR_CODE;
2374 dma_mask = *dev->dma_mask;
2376 return __map_single(dev, domain->priv, paddr, size, dir, dma_mask);
2380 * The exported unmap_single function for dma_ops.
2382 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2383 enum dma_data_direction dir, struct dma_attrs *attrs)
2385 struct protection_domain *domain;
2387 domain = get_domain(dev);
2391 __unmap_single(domain->priv, dma_addr, size, dir);
2394 static int sg_num_pages(struct device *dev,
2395 struct scatterlist *sglist,
2398 unsigned long mask, boundary_size;
2399 struct scatterlist *s;
2402 mask = dma_get_seg_boundary(dev);
2403 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2404 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2406 for_each_sg(sglist, s, nelems, i) {
2409 s->dma_address = npages << PAGE_SHIFT;
2410 p = npages % boundary_size;
2411 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2412 if (p + n > boundary_size)
2413 npages += boundary_size - p;
2421 * The exported map_sg function for dma_ops (handles scatter-gather
2424 static int map_sg(struct device *dev, struct scatterlist *sglist,
2425 int nelems, enum dma_data_direction direction,
2426 struct dma_attrs *attrs)
2428 int mapped_pages = 0, npages = 0, prot = 0, i;
2429 struct protection_domain *domain;
2430 struct dma_ops_domain *dma_dom;
2431 struct scatterlist *s;
2432 unsigned long address;
2435 domain = get_domain(dev);
2439 dma_dom = domain->priv;
2440 dma_mask = *dev->dma_mask;
2442 npages = sg_num_pages(dev, sglist, nelems);
2444 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2445 if (address == DMA_ERROR_CODE)
2448 prot = dir2prot(direction);
2450 /* Map all sg entries */
2451 for_each_sg(sglist, s, nelems, i) {
2452 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2454 for (j = 0; j < pages; ++j) {
2455 unsigned long bus_addr, phys_addr;
2458 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2459 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2460 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2468 /* Everything is mapped - write the right values into s->dma_address */
2469 for_each_sg(sglist, s, nelems, i) {
2470 s->dma_address += address + s->offset;
2471 s->dma_length = s->length;
2477 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2478 dev_name(dev), npages);
2480 for_each_sg(sglist, s, nelems, i) {
2481 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2483 for (j = 0; j < pages; ++j) {
2484 unsigned long bus_addr;
2486 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2487 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2495 free_iova_fast(&dma_dom->iovad, address, npages);
2502 * The exported map_sg function for dma_ops (handles scatter-gather
2505 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2506 int nelems, enum dma_data_direction dir,
2507 struct dma_attrs *attrs)
2509 struct protection_domain *domain;
2510 unsigned long startaddr;
2513 domain = get_domain(dev);
2517 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2518 npages = sg_num_pages(dev, sglist, nelems);
2520 __unmap_single(domain->priv, startaddr, npages << PAGE_SHIFT, dir);
2524 * The exported alloc_coherent function for dma_ops.
2526 static void *alloc_coherent(struct device *dev, size_t size,
2527 dma_addr_t *dma_addr, gfp_t flag,
2528 struct dma_attrs *attrs)
2530 u64 dma_mask = dev->coherent_dma_mask;
2531 struct protection_domain *domain;
2534 domain = get_domain(dev);
2535 if (PTR_ERR(domain) == -EINVAL) {
2536 page = alloc_pages(flag, get_order(size));
2537 *dma_addr = page_to_phys(page);
2538 return page_address(page);
2539 } else if (IS_ERR(domain))
2542 size = PAGE_ALIGN(size);
2543 dma_mask = dev->coherent_dma_mask;
2544 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2547 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2549 if (!gfpflags_allow_blocking(flag))
2552 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2559 dma_mask = *dev->dma_mask;
2561 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2562 size, DMA_BIDIRECTIONAL, dma_mask);
2564 if (*dma_addr == DMA_ERROR_CODE)
2567 return page_address(page);
2571 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2572 __free_pages(page, get_order(size));
2578 * The exported free_coherent function for dma_ops.
2580 static void free_coherent(struct device *dev, size_t size,
2581 void *virt_addr, dma_addr_t dma_addr,
2582 struct dma_attrs *attrs)
2584 struct protection_domain *domain;
2587 page = virt_to_page(virt_addr);
2588 size = PAGE_ALIGN(size);
2590 domain = get_domain(dev);
2594 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2597 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2598 __free_pages(page, get_order(size));
2602 * This function is called by the DMA layer to find out if we can handle a
2603 * particular device. It is part of the dma_ops.
2605 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2607 return check_device(dev);
2610 static struct dma_map_ops amd_iommu_dma_ops = {
2611 .alloc = alloc_coherent,
2612 .free = free_coherent,
2613 .map_page = map_page,
2614 .unmap_page = unmap_page,
2616 .unmap_sg = unmap_sg,
2617 .dma_supported = amd_iommu_dma_supported,
2620 static int init_reserved_iova_ranges(void)
2622 struct pci_dev *pdev = NULL;
2625 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2626 IOVA_START_PFN, DMA_32BIT_PFN);
2628 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2629 &reserved_rbtree_key);
2631 /* MSI memory range */
2632 val = reserve_iova(&reserved_iova_ranges,
2633 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2635 pr_err("Reserving MSI range failed\n");
2639 /* HT memory range */
2640 val = reserve_iova(&reserved_iova_ranges,
2641 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2643 pr_err("Reserving HT range failed\n");
2648 * Memory used for PCI resources
2649 * FIXME: Check whether we can reserve the PCI-hole completly
2651 for_each_pci_dev(pdev) {
2654 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2655 struct resource *r = &pdev->resource[i];
2657 if (!(r->flags & IORESOURCE_MEM))
2660 val = reserve_iova(&reserved_iova_ranges,
2664 pr_err("Reserve pci-resource range failed\n");
2673 int __init amd_iommu_init_api(void)
2675 int ret, cpu, err = 0;
2677 ret = iova_cache_get();
2681 ret = init_reserved_iova_ranges();
2685 for_each_possible_cpu(cpu) {
2686 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2688 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2689 sizeof(*queue->entries),
2691 if (!queue->entries)
2694 spin_lock_init(&queue->lock);
2697 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2700 #ifdef CONFIG_ARM_AMBA
2701 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2705 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2711 for_each_possible_cpu(cpu) {
2712 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2714 kfree(queue->entries);
2720 int __init amd_iommu_init_dma_ops(void)
2722 setup_timer(&queue_timer, queue_flush_timeout, 0);
2723 atomic_set(&queue_timer_on, 0);
2725 swiotlb = iommu_pass_through ? 1 : 0;
2729 * In case we don't initialize SWIOTLB (actually the common case
2730 * when AMD IOMMU is enabled), make sure there are global
2731 * dma_ops set as a fall-back for devices not handled by this
2732 * driver (for example non-PCI devices).
2735 dma_ops = &nommu_dma_ops;
2737 if (amd_iommu_unmap_flush)
2738 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2740 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2746 /*****************************************************************************
2748 * The following functions belong to the exported interface of AMD IOMMU
2750 * This interface allows access to lower level functions of the IOMMU
2751 * like protection domain handling and assignement of devices to domains
2752 * which is not possible with the dma_ops interface.
2754 *****************************************************************************/
2756 static void cleanup_domain(struct protection_domain *domain)
2758 struct iommu_dev_data *entry;
2759 unsigned long flags;
2761 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2763 while (!list_empty(&domain->dev_list)) {
2764 entry = list_first_entry(&domain->dev_list,
2765 struct iommu_dev_data, list);
2766 __detach_device(entry);
2769 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2772 static void protection_domain_free(struct protection_domain *domain)
2777 del_domain_from_list(domain);
2780 domain_id_free(domain->id);
2785 static int protection_domain_init(struct protection_domain *domain)
2787 spin_lock_init(&domain->lock);
2788 mutex_init(&domain->api_lock);
2789 domain->id = domain_id_alloc();
2792 INIT_LIST_HEAD(&domain->dev_list);
2797 static struct protection_domain *protection_domain_alloc(void)
2799 struct protection_domain *domain;
2801 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2805 if (protection_domain_init(domain))
2808 add_domain_to_list(domain);
2818 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2820 struct protection_domain *pdomain;
2821 struct dma_ops_domain *dma_domain;
2824 case IOMMU_DOMAIN_UNMANAGED:
2825 pdomain = protection_domain_alloc();
2829 pdomain->mode = PAGE_MODE_3_LEVEL;
2830 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2831 if (!pdomain->pt_root) {
2832 protection_domain_free(pdomain);
2836 pdomain->domain.geometry.aperture_start = 0;
2837 pdomain->domain.geometry.aperture_end = ~0ULL;
2838 pdomain->domain.geometry.force_aperture = true;
2841 case IOMMU_DOMAIN_DMA:
2842 dma_domain = dma_ops_domain_alloc();
2844 pr_err("AMD-Vi: Failed to allocate\n");
2847 pdomain = &dma_domain->domain;
2849 case IOMMU_DOMAIN_IDENTITY:
2850 pdomain = protection_domain_alloc();
2854 pdomain->mode = PAGE_MODE_NONE;
2860 return &pdomain->domain;
2863 static void amd_iommu_domain_free(struct iommu_domain *dom)
2865 struct protection_domain *domain;
2870 domain = to_pdomain(dom);
2872 if (domain->dev_cnt > 0)
2873 cleanup_domain(domain);
2875 BUG_ON(domain->dev_cnt != 0);
2877 if (domain->mode != PAGE_MODE_NONE)
2878 free_pagetable(domain);
2880 if (domain->flags & PD_IOMMUV2_MASK)
2881 free_gcr3_table(domain);
2883 protection_domain_free(domain);
2886 static void amd_iommu_detach_device(struct iommu_domain *dom,
2889 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2890 struct amd_iommu *iommu;
2893 if (!check_device(dev))
2896 devid = get_device_id(dev);
2900 if (dev_data->domain != NULL)
2903 iommu = amd_iommu_rlookup_table[devid];
2907 iommu_completion_wait(iommu);
2910 static int amd_iommu_attach_device(struct iommu_domain *dom,
2913 struct protection_domain *domain = to_pdomain(dom);
2914 struct iommu_dev_data *dev_data;
2915 struct amd_iommu *iommu;
2918 if (!check_device(dev))
2921 dev_data = dev->archdata.iommu;
2923 iommu = amd_iommu_rlookup_table[dev_data->devid];
2927 if (dev_data->domain)
2930 ret = attach_device(dev, domain);
2932 iommu_completion_wait(iommu);
2937 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2938 phys_addr_t paddr, size_t page_size, int iommu_prot)
2940 struct protection_domain *domain = to_pdomain(dom);
2944 if (domain->mode == PAGE_MODE_NONE)
2947 if (iommu_prot & IOMMU_READ)
2948 prot |= IOMMU_PROT_IR;
2949 if (iommu_prot & IOMMU_WRITE)
2950 prot |= IOMMU_PROT_IW;
2952 mutex_lock(&domain->api_lock);
2953 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
2954 mutex_unlock(&domain->api_lock);
2959 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2962 struct protection_domain *domain = to_pdomain(dom);
2965 if (domain->mode == PAGE_MODE_NONE)
2968 mutex_lock(&domain->api_lock);
2969 unmap_size = iommu_unmap_page(domain, iova, page_size);
2970 mutex_unlock(&domain->api_lock);
2972 domain_flush_tlb_pde(domain);
2977 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2980 struct protection_domain *domain = to_pdomain(dom);
2981 unsigned long offset_mask, pte_pgsize;
2984 if (domain->mode == PAGE_MODE_NONE)
2987 pte = fetch_pte(domain, iova, &pte_pgsize);
2989 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2992 offset_mask = pte_pgsize - 1;
2993 __pte = *pte & PM_ADDR_MASK;
2995 return (__pte & ~offset_mask) | (iova & offset_mask);
2998 static bool amd_iommu_capable(enum iommu_cap cap)
3001 case IOMMU_CAP_CACHE_COHERENCY:
3003 case IOMMU_CAP_INTR_REMAP:
3004 return (irq_remapping_enabled == 1);
3005 case IOMMU_CAP_NOEXEC:
3012 static void amd_iommu_get_dm_regions(struct device *dev,
3013 struct list_head *head)
3015 struct unity_map_entry *entry;
3018 devid = get_device_id(dev);
3022 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3023 struct iommu_dm_region *region;
3025 if (devid < entry->devid_start || devid > entry->devid_end)
3028 region = kzalloc(sizeof(*region), GFP_KERNEL);
3030 pr_err("Out of memory allocating dm-regions for %s\n",
3035 region->start = entry->address_start;
3036 region->length = entry->address_end - entry->address_start;
3037 if (entry->prot & IOMMU_PROT_IR)
3038 region->prot |= IOMMU_READ;
3039 if (entry->prot & IOMMU_PROT_IW)
3040 region->prot |= IOMMU_WRITE;
3042 list_add_tail(®ion->list, head);
3046 static void amd_iommu_put_dm_regions(struct device *dev,
3047 struct list_head *head)
3049 struct iommu_dm_region *entry, *next;
3051 list_for_each_entry_safe(entry, next, head, list)
3055 static void amd_iommu_apply_dm_region(struct device *dev,
3056 struct iommu_domain *domain,
3057 struct iommu_dm_region *region)
3059 struct protection_domain *pdomain = to_pdomain(domain);
3060 struct dma_ops_domain *dma_dom = pdomain->priv;
3061 unsigned long start, end;
3063 start = IOVA_PFN(region->start);
3064 end = IOVA_PFN(region->start + region->length);
3066 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3069 static const struct iommu_ops amd_iommu_ops = {
3070 .capable = amd_iommu_capable,
3071 .domain_alloc = amd_iommu_domain_alloc,
3072 .domain_free = amd_iommu_domain_free,
3073 .attach_dev = amd_iommu_attach_device,
3074 .detach_dev = amd_iommu_detach_device,
3075 .map = amd_iommu_map,
3076 .unmap = amd_iommu_unmap,
3077 .map_sg = default_iommu_map_sg,
3078 .iova_to_phys = amd_iommu_iova_to_phys,
3079 .add_device = amd_iommu_add_device,
3080 .remove_device = amd_iommu_remove_device,
3081 .device_group = amd_iommu_device_group,
3082 .get_dm_regions = amd_iommu_get_dm_regions,
3083 .put_dm_regions = amd_iommu_put_dm_regions,
3084 .apply_dm_region = amd_iommu_apply_dm_region,
3085 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3088 /*****************************************************************************
3090 * The next functions do a basic initialization of IOMMU for pass through
3093 * In passthrough mode the IOMMU is initialized and enabled but not used for
3094 * DMA-API translation.
3096 *****************************************************************************/
3098 /* IOMMUv2 specific functions */
3099 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3101 return atomic_notifier_chain_register(&ppr_notifier, nb);
3103 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3105 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3107 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3109 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3111 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3113 struct protection_domain *domain = to_pdomain(dom);
3114 unsigned long flags;
3116 spin_lock_irqsave(&domain->lock, flags);
3118 /* Update data structure */
3119 domain->mode = PAGE_MODE_NONE;
3120 domain->updated = true;
3122 /* Make changes visible to IOMMUs */
3123 update_domain(domain);
3125 /* Page-table is not visible to IOMMU anymore, so free it */
3126 free_pagetable(domain);
3128 spin_unlock_irqrestore(&domain->lock, flags);
3130 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3132 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3134 struct protection_domain *domain = to_pdomain(dom);
3135 unsigned long flags;
3138 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3141 /* Number of GCR3 table levels required */
3142 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3145 if (levels > amd_iommu_max_glx_val)
3148 spin_lock_irqsave(&domain->lock, flags);
3151 * Save us all sanity checks whether devices already in the
3152 * domain support IOMMUv2. Just force that the domain has no
3153 * devices attached when it is switched into IOMMUv2 mode.
3156 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3160 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3161 if (domain->gcr3_tbl == NULL)
3164 domain->glx = levels;
3165 domain->flags |= PD_IOMMUV2_MASK;
3166 domain->updated = true;
3168 update_domain(domain);
3173 spin_unlock_irqrestore(&domain->lock, flags);
3177 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3179 static int __flush_pasid(struct protection_domain *domain, int pasid,
3180 u64 address, bool size)
3182 struct iommu_dev_data *dev_data;
3183 struct iommu_cmd cmd;
3186 if (!(domain->flags & PD_IOMMUV2_MASK))
3189 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3192 * IOMMU TLB needs to be flushed before Device TLB to
3193 * prevent device TLB refill from IOMMU TLB
3195 for (i = 0; i < amd_iommus_present; ++i) {
3196 if (domain->dev_iommu[i] == 0)
3199 ret = iommu_queue_command(amd_iommus[i], &cmd);
3204 /* Wait until IOMMU TLB flushes are complete */
3205 domain_flush_complete(domain);
3207 /* Now flush device TLBs */
3208 list_for_each_entry(dev_data, &domain->dev_list, list) {
3209 struct amd_iommu *iommu;
3213 There might be non-IOMMUv2 capable devices in an IOMMUv2
3216 if (!dev_data->ats.enabled)
3219 qdep = dev_data->ats.qdep;
3220 iommu = amd_iommu_rlookup_table[dev_data->devid];
3222 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3223 qdep, address, size);
3225 ret = iommu_queue_command(iommu, &cmd);
3230 /* Wait until all device TLBs are flushed */
3231 domain_flush_complete(domain);
3240 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3243 return __flush_pasid(domain, pasid, address, false);
3246 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3249 struct protection_domain *domain = to_pdomain(dom);
3250 unsigned long flags;
3253 spin_lock_irqsave(&domain->lock, flags);
3254 ret = __amd_iommu_flush_page(domain, pasid, address);
3255 spin_unlock_irqrestore(&domain->lock, flags);
3259 EXPORT_SYMBOL(amd_iommu_flush_page);
3261 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3263 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3267 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3269 struct protection_domain *domain = to_pdomain(dom);
3270 unsigned long flags;
3273 spin_lock_irqsave(&domain->lock, flags);
3274 ret = __amd_iommu_flush_tlb(domain, pasid);
3275 spin_unlock_irqrestore(&domain->lock, flags);
3279 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3281 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3288 index = (pasid >> (9 * level)) & 0x1ff;
3294 if (!(*pte & GCR3_VALID)) {
3298 root = (void *)get_zeroed_page(GFP_ATOMIC);
3302 *pte = __pa(root) | GCR3_VALID;
3305 root = __va(*pte & PAGE_MASK);
3313 static int __set_gcr3(struct protection_domain *domain, int pasid,
3318 if (domain->mode != PAGE_MODE_NONE)
3321 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3325 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3327 return __amd_iommu_flush_tlb(domain, pasid);
3330 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3334 if (domain->mode != PAGE_MODE_NONE)
3337 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3343 return __amd_iommu_flush_tlb(domain, pasid);
3346 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3349 struct protection_domain *domain = to_pdomain(dom);
3350 unsigned long flags;
3353 spin_lock_irqsave(&domain->lock, flags);
3354 ret = __set_gcr3(domain, pasid, cr3);
3355 spin_unlock_irqrestore(&domain->lock, flags);
3359 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3361 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3363 struct protection_domain *domain = to_pdomain(dom);
3364 unsigned long flags;
3367 spin_lock_irqsave(&domain->lock, flags);
3368 ret = __clear_gcr3(domain, pasid);
3369 spin_unlock_irqrestore(&domain->lock, flags);
3373 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3375 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3376 int status, int tag)
3378 struct iommu_dev_data *dev_data;
3379 struct amd_iommu *iommu;
3380 struct iommu_cmd cmd;
3382 dev_data = get_dev_data(&pdev->dev);
3383 iommu = amd_iommu_rlookup_table[dev_data->devid];
3385 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3386 tag, dev_data->pri_tlp);
3388 return iommu_queue_command(iommu, &cmd);
3390 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3392 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3394 struct protection_domain *pdomain;
3396 pdomain = get_domain(&pdev->dev);
3397 if (IS_ERR(pdomain))
3400 /* Only return IOMMUv2 domains */
3401 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3404 return &pdomain->domain;
3406 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3408 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3410 struct iommu_dev_data *dev_data;
3412 if (!amd_iommu_v2_supported())
3415 dev_data = get_dev_data(&pdev->dev);
3416 dev_data->errata |= (1 << erratum);
3418 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3420 int amd_iommu_device_info(struct pci_dev *pdev,
3421 struct amd_iommu_device_info *info)
3426 if (pdev == NULL || info == NULL)
3429 if (!amd_iommu_v2_supported())
3432 memset(info, 0, sizeof(*info));
3434 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3436 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3438 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3440 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3442 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3446 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3447 max_pasids = min(max_pasids, (1 << 20));
3449 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3450 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3452 features = pci_pasid_features(pdev);
3453 if (features & PCI_PASID_CAP_EXEC)
3454 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3455 if (features & PCI_PASID_CAP_PRIV)
3456 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3461 EXPORT_SYMBOL(amd_iommu_device_info);
3463 #ifdef CONFIG_IRQ_REMAP
3465 /*****************************************************************************
3467 * Interrupt Remapping Implementation
3469 *****************************************************************************/
3487 u16 devid; /* Device ID for IRTE table */
3488 u16 index; /* Index into IRTE table*/
3491 struct amd_ir_data {
3492 struct irq_2_irte irq_2_irte;
3493 union irte irte_entry;
3495 struct msi_msg msi_entry;
3499 static struct irq_chip amd_ir_chip;
3501 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3502 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3503 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3504 #define DTE_IRQ_REMAP_ENABLE 1ULL
3506 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3510 dte = amd_iommu_dev_table[devid].data[2];
3511 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3512 dte |= virt_to_phys(table->table);
3513 dte |= DTE_IRQ_REMAP_INTCTL;
3514 dte |= DTE_IRQ_TABLE_LEN;
3515 dte |= DTE_IRQ_REMAP_ENABLE;
3517 amd_iommu_dev_table[devid].data[2] = dte;
3520 #define IRTE_ALLOCATED (~1U)
3522 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3524 struct irq_remap_table *table = NULL;
3525 struct amd_iommu *iommu;
3526 unsigned long flags;
3529 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3531 iommu = amd_iommu_rlookup_table[devid];
3535 table = irq_lookup_table[devid];
3539 alias = amd_iommu_alias_table[devid];
3540 table = irq_lookup_table[alias];
3542 irq_lookup_table[devid] = table;
3543 set_dte_irq_entry(devid, table);
3544 iommu_flush_dte(iommu, devid);
3548 /* Nothing there yet, allocate new irq remapping table */
3549 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3553 /* Initialize table spin-lock */
3554 spin_lock_init(&table->lock);
3557 /* Keep the first 32 indexes free for IOAPIC interrupts */
3558 table->min_index = 32;
3560 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3561 if (!table->table) {
3567 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3572 for (i = 0; i < 32; ++i)
3573 table->table[i] = IRTE_ALLOCATED;
3576 irq_lookup_table[devid] = table;
3577 set_dte_irq_entry(devid, table);
3578 iommu_flush_dte(iommu, devid);
3579 if (devid != alias) {
3580 irq_lookup_table[alias] = table;
3581 set_dte_irq_entry(alias, table);
3582 iommu_flush_dte(iommu, alias);
3586 iommu_completion_wait(iommu);
3589 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3594 static int alloc_irq_index(u16 devid, int count)
3596 struct irq_remap_table *table;
3597 unsigned long flags;
3600 table = get_irq_table(devid, false);
3604 spin_lock_irqsave(&table->lock, flags);
3606 /* Scan table for free entries */
3607 for (c = 0, index = table->min_index;
3608 index < MAX_IRQS_PER_TABLE;
3610 if (table->table[index] == 0)
3617 table->table[index - c + 1] = IRTE_ALLOCATED;
3627 spin_unlock_irqrestore(&table->lock, flags);
3632 static int modify_irte(u16 devid, int index, union irte irte)
3634 struct irq_remap_table *table;
3635 struct amd_iommu *iommu;
3636 unsigned long flags;
3638 iommu = amd_iommu_rlookup_table[devid];
3642 table = get_irq_table(devid, false);
3646 spin_lock_irqsave(&table->lock, flags);
3647 table->table[index] = irte.val;
3648 spin_unlock_irqrestore(&table->lock, flags);
3650 iommu_flush_irt(iommu, devid);
3651 iommu_completion_wait(iommu);
3656 static void free_irte(u16 devid, int index)
3658 struct irq_remap_table *table;
3659 struct amd_iommu *iommu;
3660 unsigned long flags;
3662 iommu = amd_iommu_rlookup_table[devid];
3666 table = get_irq_table(devid, false);
3670 spin_lock_irqsave(&table->lock, flags);
3671 table->table[index] = 0;
3672 spin_unlock_irqrestore(&table->lock, flags);
3674 iommu_flush_irt(iommu, devid);
3675 iommu_completion_wait(iommu);
3678 static int get_devid(struct irq_alloc_info *info)
3682 switch (info->type) {
3683 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3684 devid = get_ioapic_devid(info->ioapic_id);
3686 case X86_IRQ_ALLOC_TYPE_HPET:
3687 devid = get_hpet_devid(info->hpet_id);
3689 case X86_IRQ_ALLOC_TYPE_MSI:
3690 case X86_IRQ_ALLOC_TYPE_MSIX:
3691 devid = get_device_id(&info->msi_dev->dev);
3701 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3703 struct amd_iommu *iommu;
3709 devid = get_devid(info);
3711 iommu = amd_iommu_rlookup_table[devid];
3713 return iommu->ir_domain;
3719 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3721 struct amd_iommu *iommu;
3727 switch (info->type) {
3728 case X86_IRQ_ALLOC_TYPE_MSI:
3729 case X86_IRQ_ALLOC_TYPE_MSIX:
3730 devid = get_device_id(&info->msi_dev->dev);
3734 iommu = amd_iommu_rlookup_table[devid];
3736 return iommu->msi_domain;
3745 struct irq_remap_ops amd_iommu_irq_ops = {
3746 .prepare = amd_iommu_prepare,
3747 .enable = amd_iommu_enable,
3748 .disable = amd_iommu_disable,
3749 .reenable = amd_iommu_reenable,
3750 .enable_faulting = amd_iommu_enable_faulting,
3751 .get_ir_irq_domain = get_ir_irq_domain,
3752 .get_irq_domain = get_irq_domain,
3755 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3756 struct irq_cfg *irq_cfg,
3757 struct irq_alloc_info *info,
3758 int devid, int index, int sub_handle)
3760 struct irq_2_irte *irte_info = &data->irq_2_irte;
3761 struct msi_msg *msg = &data->msi_entry;
3762 union irte *irte = &data->irte_entry;
3763 struct IO_APIC_route_entry *entry;
3765 data->irq_2_irte.devid = devid;
3766 data->irq_2_irte.index = index + sub_handle;
3768 /* Setup IRTE for IOMMU */
3770 irte->fields.vector = irq_cfg->vector;
3771 irte->fields.int_type = apic->irq_delivery_mode;
3772 irte->fields.destination = irq_cfg->dest_apicid;
3773 irte->fields.dm = apic->irq_dest_mode;
3774 irte->fields.valid = 1;
3776 switch (info->type) {
3777 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3778 /* Setup IOAPIC entry */
3779 entry = info->ioapic_entry;
3780 info->ioapic_entry = NULL;
3781 memset(entry, 0, sizeof(*entry));
3782 entry->vector = index;
3784 entry->trigger = info->ioapic_trigger;
3785 entry->polarity = info->ioapic_polarity;
3786 /* Mask level triggered irqs. */
3787 if (info->ioapic_trigger)
3791 case X86_IRQ_ALLOC_TYPE_HPET:
3792 case X86_IRQ_ALLOC_TYPE_MSI:
3793 case X86_IRQ_ALLOC_TYPE_MSIX:
3794 msg->address_hi = MSI_ADDR_BASE_HI;
3795 msg->address_lo = MSI_ADDR_BASE_LO;
3796 msg->data = irte_info->index;
3805 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3806 unsigned int nr_irqs, void *arg)
3808 struct irq_alloc_info *info = arg;
3809 struct irq_data *irq_data;
3810 struct amd_ir_data *data;
3811 struct irq_cfg *cfg;
3817 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3818 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3822 * With IRQ remapping enabled, don't need contiguous CPU vectors
3823 * to support multiple MSI interrupts.
3825 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3826 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3828 devid = get_devid(info);
3832 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3836 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3837 if (get_irq_table(devid, true))
3838 index = info->ioapic_pin;
3842 index = alloc_irq_index(devid, nr_irqs);
3845 pr_warn("Failed to allocate IRTE\n");
3846 goto out_free_parent;
3849 for (i = 0; i < nr_irqs; i++) {
3850 irq_data = irq_domain_get_irq_data(domain, virq + i);
3851 cfg = irqd_cfg(irq_data);
3852 if (!irq_data || !cfg) {
3858 data = kzalloc(sizeof(*data), GFP_KERNEL);
3862 irq_data->hwirq = (devid << 16) + i;
3863 irq_data->chip_data = data;
3864 irq_data->chip = &amd_ir_chip;
3865 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3866 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3872 for (i--; i >= 0; i--) {
3873 irq_data = irq_domain_get_irq_data(domain, virq + i);
3875 kfree(irq_data->chip_data);
3877 for (i = 0; i < nr_irqs; i++)
3878 free_irte(devid, index + i);
3880 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3884 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3885 unsigned int nr_irqs)
3887 struct irq_2_irte *irte_info;
3888 struct irq_data *irq_data;
3889 struct amd_ir_data *data;
3892 for (i = 0; i < nr_irqs; i++) {
3893 irq_data = irq_domain_get_irq_data(domain, virq + i);
3894 if (irq_data && irq_data->chip_data) {
3895 data = irq_data->chip_data;
3896 irte_info = &data->irq_2_irte;
3897 free_irte(irte_info->devid, irte_info->index);
3901 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3904 static void irq_remapping_activate(struct irq_domain *domain,
3905 struct irq_data *irq_data)
3907 struct amd_ir_data *data = irq_data->chip_data;
3908 struct irq_2_irte *irte_info = &data->irq_2_irte;
3910 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
3913 static void irq_remapping_deactivate(struct irq_domain *domain,
3914 struct irq_data *irq_data)
3916 struct amd_ir_data *data = irq_data->chip_data;
3917 struct irq_2_irte *irte_info = &data->irq_2_irte;
3921 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
3924 static struct irq_domain_ops amd_ir_domain_ops = {
3925 .alloc = irq_remapping_alloc,
3926 .free = irq_remapping_free,
3927 .activate = irq_remapping_activate,
3928 .deactivate = irq_remapping_deactivate,
3931 static int amd_ir_set_affinity(struct irq_data *data,
3932 const struct cpumask *mask, bool force)
3934 struct amd_ir_data *ir_data = data->chip_data;
3935 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3936 struct irq_cfg *cfg = irqd_cfg(data);
3937 struct irq_data *parent = data->parent_data;
3940 ret = parent->chip->irq_set_affinity(parent, mask, force);
3941 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3945 * Atomically updates the IRTE with the new destination, vector
3946 * and flushes the interrupt entry cache.
3948 ir_data->irte_entry.fields.vector = cfg->vector;
3949 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
3950 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
3953 * After this point, all the interrupts will start arriving
3954 * at the new destination. So, time to cleanup the previous
3955 * vector allocation.
3957 send_cleanup_vector(cfg);
3959 return IRQ_SET_MASK_OK_DONE;
3962 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3964 struct amd_ir_data *ir_data = irq_data->chip_data;
3966 *msg = ir_data->msi_entry;
3969 static struct irq_chip amd_ir_chip = {
3970 .irq_ack = ir_ack_apic_edge,
3971 .irq_set_affinity = amd_ir_set_affinity,
3972 .irq_compose_msi_msg = ir_compose_msi_msg,
3975 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3977 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
3978 if (!iommu->ir_domain)
3981 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3982 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);