drivers/irqchip/irq-gic-v3-its.c

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/bitmap.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/log2.h>
  23 #include <linux/mm.h>
  24 #include <linux/msi.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/of_pci.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/percpu.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/irqchip.h>
  34 #include <linux/irqchip/arm-gic-v3.h>
  35
  36 #include <asm/cacheflush.h>
  37 #include <asm/cputype.h>
  38 #include <asm/exception.h>
  39
  40 #include "irq-gic-common.h"
  41
  42 #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING           (1ULL << 0)
  43 #define ITS_FLAGS_WORKAROUND_CAVIUM_22375       (1ULL << 1)
  44
  45 #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING     (1 << 0)
  46
  47 /*
  48  * Collection structure - just an ID, and a redistributor address to
  49  * ping. We use one per CPU as a bag of interrupts assigned to this
  50  * CPU.
  51  */
  52 struct its_collection {
  53         u64                     target_address;
  54         u16                     col_id;
  55 };
  56
  57 /*
  58  * The ITS structure - contains most of the infrastructure, with the
  59  * top-level MSI domain, the command queue, the collections, and the
  60  * list of devices writing to it.
  61  */
  62 struct its_node {
  63         raw_spinlock_t          lock;
  64         struct list_head        entry;
  65         void __iomem            *base;
  66         unsigned long           phys_base;
  67         struct its_cmd_block    *cmd_base;
  68         struct its_cmd_block    *cmd_write;
  69         struct {
  70                 void            *base;
  71                 u32             order;
  72         } tables[GITS_BASER_NR_REGS];
  73         struct its_collection   *collections;
  74         struct list_head        its_device_list;
  75         u64                     flags;
  76         u32                     ite_size;
  77 };
  78
  79 #define ITS_ITT_ALIGN           SZ_256
  80
  81 struct event_lpi_map {
  82         unsigned long           *lpi_map;
  83         u16                     *col_map;
  84         irq_hw_number_t         lpi_base;
  85         int                     nr_lpis;
  86 };
  87
  88 /*
  89  * The ITS view of a device - belongs to an ITS, a collection, owns an
  90  * interrupt translation table, and a list of interrupts.
  91  */
  92 struct its_device {
  93         struct list_head        entry;
  94         struct its_node         *its;
  95         struct event_lpi_map    event_map;
  96         void                    *itt;
  97         u32                     nr_ites;
  98         u32                     device_id;
  99 };
 100
 101 static LIST_HEAD(its_nodes);
 102 static DEFINE_SPINLOCK(its_lock);
 103 static struct device_node *gic_root_node;
 104 static struct rdists *gic_rdists;
 105
 106 #define gic_data_rdist()                (raw_cpu_ptr(gic_rdists->rdist))
 107 #define gic_data_rdist_rd_base()        (gic_data_rdist()->rd_base)
 108
 109 static struct its_collection *dev_event_to_col(struct its_device *its_dev,
 110                                                u32 event)
 111 {
 112         struct its_node *its = its_dev->its;
 113
 114         return its->collections + its_dev->event_map.col_map[event];
 115 }
 116
 117 /*
 118  * ITS command descriptors - parameters to be encoded in a command
 119  * block.
 120  */
 121 struct its_cmd_desc {
 122         union {
 123                 struct {
 124                         struct its_device *dev;
 125                         u32 event_id;
 126                 } its_inv_cmd;
 127
 128                 struct {
 129                         struct its_device *dev;
 130                         u32 event_id;
 131                 } its_int_cmd;
 132
 133                 struct {
 134                         struct its_device *dev;
 135                         int valid;
 136                 } its_mapd_cmd;
 137
 138                 struct {
 139                         struct its_collection *col;
 140                         int valid;
 141                 } its_mapc_cmd;
 142
 143                 struct {
 144                         struct its_device *dev;
 145                         u32 phys_id;
 146                         u32 event_id;
 147                 } its_mapvi_cmd;
 148
 149                 struct {
 150                         struct its_device *dev;
 151                         struct its_collection *col;
 152                         u32 event_id;
 153                 } its_movi_cmd;
 154
 155                 struct {
 156                         struct its_device *dev;
 157                         u32 event_id;
 158                 } its_discard_cmd;
 159
 160                 struct {
 161                         struct its_collection *col;
 162                 } its_invall_cmd;
 163         };
 164 };
 165
 166 /*
 167  * The ITS command block, which is what the ITS actually parses.
 168  */
 169 struct its_cmd_block {
 170         u64     raw_cmd[4];
 171 };
 172
 173 #define ITS_CMD_QUEUE_SZ                SZ_64K
 174 #define ITS_CMD_QUEUE_NR_ENTRIES        (ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))
 175
 176 typedef struct its_collection *(*its_cmd_builder_t)(struct its_cmd_block *,
 177                                                     struct its_cmd_desc *);
 178
 179 static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
 180 {
 181         cmd->raw_cmd[0] &= ~0xffUL;
 182         cmd->raw_cmd[0] |= cmd_nr;
 183 }
 184
 185 static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
 186 {
 187         cmd->raw_cmd[0] &= BIT_ULL(32) - 1;
 188         cmd->raw_cmd[0] |= ((u64)devid) << 32;
 189 }
 190
 191 static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
 192 {
 193         cmd->raw_cmd[1] &= ~0xffffffffUL;
 194         cmd->raw_cmd[1] |= id;
 195 }
 196
 197 static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
 198 {
 199         cmd->raw_cmd[1] &= 0xffffffffUL;
 200         cmd->raw_cmd[1] |= ((u64)phys_id) << 32;
 201 }
 202
 203 static void its_encode_size(struct its_cmd_block *cmd, u8 size)
 204 {
 205         cmd->raw_cmd[1] &= ~0x1fUL;
 206         cmd->raw_cmd[1] |= size & 0x1f;
 207 }
 208
 209 static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
 210 {
 211         cmd->raw_cmd[2] &= ~0xffffffffffffUL;
 212         cmd->raw_cmd[2] |= itt_addr & 0xffffffffff00UL;
 213 }
 214
 215 static void its_encode_valid(struct its_cmd_block *cmd, int valid)
 216 {
 217         cmd->raw_cmd[2] &= ~(1UL << 63);
 218         cmd->raw_cmd[2] |= ((u64)!!valid) << 63;
 219 }
 220
 221 static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
 222 {
 223         cmd->raw_cmd[2] &= ~(0xffffffffUL << 16);
 224         cmd->raw_cmd[2] |= (target_addr & (0xffffffffUL << 16));
 225 }
 226
 227 static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
 228 {
 229         cmd->raw_cmd[2] &= ~0xffffUL;
 230         cmd->raw_cmd[2] |= col;
 231 }
 232
 233 static inline void its_fixup_cmd(struct its_cmd_block *cmd)
 234 {
 235         /* Let's fixup BE commands */
 236         cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
 237         cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
 238         cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
 239         cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
 240 }
 241
 242 static struct its_collection *its_build_mapd_cmd(struct its_cmd_block *cmd,
 243                                                  struct its_cmd_desc *desc)
 244 {
 245         unsigned long itt_addr;
 246         u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
 247
 248         itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
 249         itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);
 250
 251         its_encode_cmd(cmd, GITS_CMD_MAPD);
 252         its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
 253         its_encode_size(cmd, size - 1);
 254         its_encode_itt(cmd, itt_addr);
 255         its_encode_valid(cmd, desc->its_mapd_cmd.valid);
 256
 257         its_fixup_cmd(cmd);
 258
 259         return NULL;
 260 }
 261
 262 static struct its_collection *its_build_mapc_cmd(struct its_cmd_block *cmd,
 263                                                  struct its_cmd_desc *desc)
 264 {
 265         its_encode_cmd(cmd, GITS_CMD_MAPC);
 266         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 267         its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
 268         its_encode_valid(cmd, desc->its_mapc_cmd.valid);
 269
 270         its_fixup_cmd(cmd);
 271
 272         return desc->its_mapc_cmd.col;
 273 }
 274
 275 static struct its_collection *its_build_mapvi_cmd(struct its_cmd_block *cmd,
 276                                                   struct its_cmd_desc *desc)
 277 {
 278         struct its_collection *col;
 279
 280         col = dev_event_to_col(desc->its_mapvi_cmd.dev,
 281                                desc->its_mapvi_cmd.event_id);
 282
 283         its_encode_cmd(cmd, GITS_CMD_MAPVI);
 284         its_encode_devid(cmd, desc->its_mapvi_cmd.dev->device_id);
 285         its_encode_event_id(cmd, desc->its_mapvi_cmd.event_id);
 286         its_encode_phys_id(cmd, desc->its_mapvi_cmd.phys_id);
 287         its_encode_collection(cmd, col->col_id);
 288
 289         its_fixup_cmd(cmd);
 290
 291         return col;
 292 }
 293
 294 static struct its_collection *its_build_movi_cmd(struct its_cmd_block *cmd,
 295                                                  struct its_cmd_desc *desc)
 296 {
 297         struct its_collection *col;
 298
 299         col = dev_event_to_col(desc->its_movi_cmd.dev,
 300                                desc->its_movi_cmd.event_id);
 301
 302         its_encode_cmd(cmd, GITS_CMD_MOVI);
 303         its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
 304         its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
 305         its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);
 306
 307         its_fixup_cmd(cmd);
 308
 309         return col;
 310 }
 311
 312 static struct its_collection *its_build_discard_cmd(struct its_cmd_block *cmd,
 313                                                     struct its_cmd_desc *desc)
 314 {
 315         struct its_collection *col;
 316
 317         col = dev_event_to_col(desc->its_discard_cmd.dev,
 318                                desc->its_discard_cmd.event_id);
 319
 320         its_encode_cmd(cmd, GITS_CMD_DISCARD);
 321         its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
 322         its_encode_event_id(cmd, desc->its_discard_cmd.event_id);
 323
 324         its_fixup_cmd(cmd);
 325
 326         return col;
 327 }
 328
 329 static struct its_collection *its_build_inv_cmd(struct its_cmd_block *cmd,
 330                                                 struct its_cmd_desc *desc)
 331 {
 332         struct its_collection *col;
 333
 334         col = dev_event_to_col(desc->its_inv_cmd.dev,
 335                                desc->its_inv_cmd.event_id);
 336
 337         its_encode_cmd(cmd, GITS_CMD_INV);
 338         its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
 339         its_encode_event_id(cmd, desc->its_inv_cmd.event_id);
 340
 341         its_fixup_cmd(cmd);
 342
 343         return col;
 344 }
 345
 346 static struct its_collection *its_build_invall_cmd(struct its_cmd_block *cmd,
 347                                                    struct its_cmd_desc *desc)
 348 {
 349         its_encode_cmd(cmd, GITS_CMD_INVALL);
 350         its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
 351
 352         its_fixup_cmd(cmd);
 353
 354         return NULL;
 355 }
 356
 357 static u64 its_cmd_ptr_to_offset(struct its_node *its,
 358                                  struct its_cmd_block *ptr)
 359 {
 360         return (ptr - its->cmd_base) * sizeof(*ptr);
 361 }
 362
 363 static int its_queue_full(struct its_node *its)
 364 {
 365         int widx;
 366         int ridx;
 367
 368         widx = its->cmd_write - its->cmd_base;
 369         ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);
 370
 371         /* This is incredibly unlikely to happen, unless the ITS locks up. */
 372         if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
 373                 return 1;
 374
 375         return 0;
 376 }
 377
 378 static struct its_cmd_block *its_allocate_entry(struct its_node *its)
 379 {
 380         struct its_cmd_block *cmd;
 381         u32 count = 1000000;    /* 1s! */
 382
 383         while (its_queue_full(its)) {
 384                 count--;
 385                 if (!count) {
 386                         pr_err_ratelimited("ITS queue not draining\n");
 387                         return NULL;
 388                 }
 389                 cpu_relax();
 390                 udelay(1);
 391         }
 392
 393         cmd = its->cmd_write++;
 394
 395         /* Handle queue wrapping */
 396         if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
 397                 its->cmd_write = its->cmd_base;
 398
 399         return cmd;
 400 }
 401
 402 static struct its_cmd_block *its_post_commands(struct its_node *its)
 403 {
 404         u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);
 405
 406         writel_relaxed(wr, its->base + GITS_CWRITER);
 407
 408         return its->cmd_write;
 409 }
 410
 411 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
 412 {
 413         /*
 414          * Make sure the commands written to memory are observable by
 415          * the ITS.
 416          */
 417         if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
 418                 __flush_dcache_area(cmd, sizeof(*cmd));
 419         else
 420                 dsb(ishst);
 421 }
 422
 423 static void its_wait_for_range_completion(struct its_node *its,
 424                                           struct its_cmd_block *from,
 425                                           struct its_cmd_block *to)
 426 {
 427         u64 rd_idx, from_idx, to_idx;
 428         u32 count = 1000000;    /* 1s! */
 429
 430         from_idx = its_cmd_ptr_to_offset(its, from);
 431         to_idx = its_cmd_ptr_to_offset(its, to);
 432
 433         while (1) {
 434                 rd_idx = readl_relaxed(its->base + GITS_CREADR);
 435                 if (rd_idx >= to_idx || rd_idx < from_idx)
 436                         break;
 437
 438                 count--;
 439                 if (!count) {
 440                         pr_err_ratelimited("ITS queue timeout\n");
 441                         return;
 442                 }
 443                 cpu_relax();
 444                 udelay(1);
 445         }
 446 }
 447
 448 static void its_send_single_command(struct its_node *its,
 449                                     its_cmd_builder_t builder,
 450                                     struct its_cmd_desc *desc)
 451 {
 452         struct its_cmd_block *cmd, *sync_cmd, *next_cmd;
 453         struct its_collection *sync_col;
 454         unsigned long flags;
 455
 456         raw_spin_lock_irqsave(&its->lock, flags);
 457
 458         cmd = its_allocate_entry(its);
 459         if (!cmd) {             /* We're soooooo screewed... */
 460                 pr_err_ratelimited("ITS can't allocate, dropping command\n");
 461                 raw_spin_unlock_irqrestore(&its->lock, flags);
 462                 return;
 463         }
 464         sync_col = builder(cmd, desc);
 465         its_flush_cmd(its, cmd);
 466
 467         if (sync_col) {
 468                 sync_cmd = its_allocate_entry(its);
 469                 if (!sync_cmd) {
 470                         pr_err_ratelimited("ITS can't SYNC, skipping\n");
 471                         goto post;
 472                 }
 473                 its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
 474                 its_encode_target(sync_cmd, sync_col->target_address);
 475                 its_fixup_cmd(sync_cmd);
 476                 its_flush_cmd(its, sync_cmd);
 477         }
 478
 479 post:
 480         next_cmd = its_post_commands(its);
 481         raw_spin_unlock_irqrestore(&its->lock, flags);
 482
 483         its_wait_for_range_completion(its, cmd, next_cmd);
 484 }
 485
 486 static void its_send_inv(struct its_device *dev, u32 event_id)
 487 {
 488         struct its_cmd_desc desc;
 489
 490         desc.its_inv_cmd.dev = dev;
 491         desc.its_inv_cmd.event_id = event_id;
 492
 493         its_send_single_command(dev->its, its_build_inv_cmd, &desc);
 494 }
 495
 496 static void its_send_mapd(struct its_device *dev, int valid)
 497 {
 498         struct its_cmd_desc desc;
 499
 500         desc.its_mapd_cmd.dev = dev;
 501         desc.its_mapd_cmd.valid = !!valid;
 502
 503         its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
 504 }
 505
 506 static void its_send_mapc(struct its_node *its, struct its_collection *col,
 507                           int valid)
 508 {
 509         struct its_cmd_desc desc;
 510
 511         desc.its_mapc_cmd.col = col;
 512         desc.its_mapc_cmd.valid = !!valid;
 513
 514         its_send_single_command(its, its_build_mapc_cmd, &desc);
 515 }
 516
 517 static void its_send_mapvi(struct its_device *dev, u32 irq_id, u32 id)
 518 {
 519         struct its_cmd_desc desc;
 520
 521         desc.its_mapvi_cmd.dev = dev;
 522         desc.its_mapvi_cmd.phys_id = irq_id;
 523         desc.its_mapvi_cmd.event_id = id;
 524
 525         its_send_single_command(dev->its, its_build_mapvi_cmd, &desc);
 526 }
 527
 528 static void its_send_movi(struct its_device *dev,
 529                           struct its_collection *col, u32 id)
 530 {
 531         struct its_cmd_desc desc;
 532
 533         desc.its_movi_cmd.dev = dev;
 534         desc.its_movi_cmd.col = col;
 535         desc.its_movi_cmd.event_id = id;
 536
 537         its_send_single_command(dev->its, its_build_movi_cmd, &desc);
 538 }
 539
 540 static void its_send_discard(struct its_device *dev, u32 id)
 541 {
 542         struct its_cmd_desc desc;
 543
 544         desc.its_discard_cmd.dev = dev;
 545         desc.its_discard_cmd.event_id = id;
 546
 547         its_send_single_command(dev->its, its_build_discard_cmd, &desc);
 548 }
 549
 550 static void its_send_invall(struct its_node *its, struct its_collection *col)
 551 {
 552         struct its_cmd_desc desc;
 553
 554         desc.its_invall_cmd.col = col;
 555
 556         its_send_single_command(its, its_build_invall_cmd, &desc);
 557 }
 558
 559 /*
 560  * irqchip functions - assumes MSI, mostly.
 561  */
 562
 563 static inline u32 its_get_event_id(struct irq_data *d)
 564 {
 565         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 566         return d->hwirq - its_dev->event_map.lpi_base;
 567 }
 568
 569 static void lpi_set_config(struct irq_data *d, bool enable)
 570 {
 571         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 572         irq_hw_number_t hwirq = d->hwirq;
 573         u32 id = its_get_event_id(d);
 574         u8 *cfg = page_address(gic_rdists->prop_page) + hwirq - 8192;
 575
 576         if (enable)
 577                 *cfg |= LPI_PROP_ENABLED;
 578         else
 579                 *cfg &= ~LPI_PROP_ENABLED;
 580
 581         /*
 582          * Make the above write visible to the redistributors.
 583          * And yes, we're flushing exactly: One. Single. Byte.
 584          * Humpf...
 585          */
 586         if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
 587                 __flush_dcache_area(cfg, sizeof(*cfg));
 588         else
 589                 dsb(ishst);
 590         its_send_inv(its_dev, id);
 591 }
 592
 593 static void its_mask_irq(struct irq_data *d)
 594 {
 595         lpi_set_config(d, false);
 596 }
 597
 598 static void its_unmask_irq(struct irq_data *d)
 599 {
 600         lpi_set_config(d, true);
 601 }
 602
 603 static void its_eoi_irq(struct irq_data *d)
 604 {
 605         gic_write_eoir(d->hwirq);
 606 }
 607
 608 static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
 609                             bool force)
 610 {
 611         unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
 612         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 613         struct its_collection *target_col;
 614         u32 id = its_get_event_id(d);
 615
 616         if (cpu >= nr_cpu_ids)
 617                 return -EINVAL;
 618
 619         target_col = &its_dev->its->collections[cpu];
 620         its_send_movi(its_dev, target_col, id);
 621         its_dev->event_map.col_map[id] = cpu;
 622
 623         return IRQ_SET_MASK_OK_DONE;
 624 }
 625
 626 static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 627 {
 628         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
 629         struct its_node *its;
 630         u64 addr;
 631
 632         its = its_dev->its;
 633         addr = its->phys_base + GITS_TRANSLATER;
 634
 635         msg->address_lo         = addr & ((1UL << 32) - 1);
 636         msg->address_hi         = addr >> 32;
 637         msg->data               = its_get_event_id(d);
 638 }
 639
 640 static struct irq_chip its_irq_chip = {
 641         .name                   = "ITS",
 642         .irq_mask               = its_mask_irq,
 643         .irq_unmask             = its_unmask_irq,
 644         .irq_eoi                = its_eoi_irq,
 645         .irq_set_affinity       = its_set_affinity,
 646         .irq_compose_msi_msg    = its_irq_compose_msi_msg,
 647 };
 648
 649 /*
 650  * How we allocate LPIs:
 651  *
 652  * The GIC has id_bits bits for interrupt identifiers. From there, we
 653  * must subtract 8192 which are reserved for SGIs/PPIs/SPIs. Then, as
 654  * we allocate LPIs by chunks of 32, we can shift the whole thing by 5
 655  * bits to the right.
 656  *
 657  * This gives us (((1UL << id_bits) - 8192) >> 5) possible allocations.
 658  */
 659 #define IRQS_PER_CHUNK_SHIFT    5
 660 #define IRQS_PER_CHUNK          (1 << IRQS_PER_CHUNK_SHIFT)
 661
 662 static unsigned long *lpi_bitmap;
 663 static u32 lpi_chunks;
 664 static DEFINE_SPINLOCK(lpi_lock);
 665
 666 static int its_lpi_to_chunk(int lpi)
 667 {
 668         return (lpi - 8192) >> IRQS_PER_CHUNK_SHIFT;
 669 }
 670
 671 static int its_chunk_to_lpi(int chunk)
 672 {
 673         return (chunk << IRQS_PER_CHUNK_SHIFT) + 8192;
 674 }
 675
 676 static int its_lpi_init(u32 id_bits)
 677 {
 678         lpi_chunks = its_lpi_to_chunk(1UL << id_bits);
 679
 680         lpi_bitmap = kzalloc(BITS_TO_LONGS(lpi_chunks) * sizeof(long),
 681                              GFP_KERNEL);
 682         if (!lpi_bitmap) {
 683                 lpi_chunks = 0;
 684                 return -ENOMEM;
 685         }
 686
 687         pr_info("ITS: Allocated %d chunks for LPIs\n", (int)lpi_chunks);
 688         return 0;
 689 }
 690
 691 static unsigned long *its_lpi_alloc_chunks(int nr_irqs, int *base, int *nr_ids)
 692 {
 693         unsigned long *bitmap = NULL;
 694         int chunk_id;
 695         int nr_chunks;
 696         int i;
 697
 698         nr_chunks = DIV_ROUND_UP(nr_irqs, IRQS_PER_CHUNK);
 699
 700         spin_lock(&lpi_lock);
 701
 702         do {
 703                 chunk_id = bitmap_find_next_zero_area(lpi_bitmap, lpi_chunks,
 704                                                       0, nr_chunks, 0);
 705                 if (chunk_id < lpi_chunks)
 706                         break;
 707
 708                 nr_chunks--;
 709         } while (nr_chunks > 0);
 710
 711         if (!nr_chunks)
 712                 goto out;
 713
 714         bitmap = kzalloc(BITS_TO_LONGS(nr_chunks * IRQS_PER_CHUNK) * sizeof (long),
 715                          GFP_ATOMIC);
 716         if (!bitmap)
 717                 goto out;
 718
 719         for (i = 0; i < nr_chunks; i++)
 720                 set_bit(chunk_id + i, lpi_bitmap);
 721
 722         *base = its_chunk_to_lpi(chunk_id);
 723         *nr_ids = nr_chunks * IRQS_PER_CHUNK;
 724
 725 out:
 726         spin_unlock(&lpi_lock);
 727
 728         if (!bitmap)
 729                 *base = *nr_ids = 0;
 730
 731         return bitmap;
 732 }
 733
 734 static void its_lpi_free(struct event_lpi_map *map)
 735 {
 736         int base = map->lpi_base;
 737         int nr_ids = map->nr_lpis;
 738         int lpi;
 739
 740         spin_lock(&lpi_lock);
 741
 742         for (lpi = base; lpi < (base + nr_ids); lpi += IRQS_PER_CHUNK) {
 743                 int chunk = its_lpi_to_chunk(lpi);
 744                 BUG_ON(chunk > lpi_chunks);
 745                 if (test_bit(chunk, lpi_bitmap)) {
 746                         clear_bit(chunk, lpi_bitmap);
 747                 } else {
 748                         pr_err("Bad LPI chunk %d\n", chunk);
 749                 }
 750         }
 751
 752         spin_unlock(&lpi_lock);
 753
 754         kfree(map->lpi_map);
 755         kfree(map->col_map);
 756 }
 757
 758 /*
 759  * We allocate 64kB for PROPBASE. That gives us at most 64K LPIs to
 760  * deal with (one configuration byte per interrupt). PENDBASE has to
 761  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 762  */
 763 #define LPI_PROPBASE_SZ         SZ_64K
 764 #define LPI_PENDBASE_SZ         (LPI_PROPBASE_SZ / 8 + SZ_1K)
 765
 766 /*
 767  * This is how many bits of ID we need, including the useless ones.
 768  */
 769 #define LPI_NRBITS              ilog2(LPI_PROPBASE_SZ + SZ_8K)
 770
 771 #define LPI_PROP_DEFAULT_PRIO   0xa0
 772
 773 static int __init its_alloc_lpi_tables(void)
 774 {
 775         phys_addr_t paddr;
 776
 777         gic_rdists->prop_page = alloc_pages(GFP_NOWAIT,
 778                                            get_order(LPI_PROPBASE_SZ));
 779         if (!gic_rdists->prop_page) {
 780                 pr_err("Failed to allocate PROPBASE\n");
 781                 return -ENOMEM;
 782         }
 783
 784         paddr = page_to_phys(gic_rdists->prop_page);
 785         pr_info("GIC: using LPI property table @%pa\n", &paddr);
 786
 787         /* Priority 0xa0, Group-1, disabled */
 788         memset(page_address(gic_rdists->prop_page),
 789                LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1,
 790                LPI_PROPBASE_SZ);
 791
 792         /* Make sure the GIC will observe the written configuration */
 793         __flush_dcache_area(page_address(gic_rdists->prop_page), LPI_PROPBASE_SZ);
 794
 795         return 0;
 796 }
 797
 798 static const char *its_base_type_string[] = {
 799         [GITS_BASER_TYPE_DEVICE]        = "Devices",
 800         [GITS_BASER_TYPE_VCPU]          = "Virtual CPUs",
 801         [GITS_BASER_TYPE_CPU]           = "Physical CPUs",
 802         [GITS_BASER_TYPE_COLLECTION]    = "Interrupt Collections",
 803         [GITS_BASER_TYPE_RESERVED5]     = "Reserved (5)",
 804         [GITS_BASER_TYPE_RESERVED6]     = "Reserved (6)",
 805         [GITS_BASER_TYPE_RESERVED7]     = "Reserved (7)",
 806 };
 807
 808 static void its_free_tables(struct its_node *its)
 809 {
 810         int i;
 811
 812         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 813                 if (its->tables[i].base) {
 814                         free_pages((unsigned long)its->tables[i].base,
 815                                    its->tables[i].order);
 816                         its->tables[i].base = NULL;
 817                 }
 818         }
 819 }
 820
 821 static int its_alloc_tables(const char *node_name, struct its_node *its)
 822 {
 823         int err;
 824         int i;
 825         int psz = SZ_64K;
 826         u64 shr = GITS_BASER_InnerShareable;
 827         u64 cache;
 828         u64 typer;
 829         u32 ids;
 830
 831         if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) {
 832                 /*
 833                  * erratum 22375: only alloc 8MB table size
 834                  * erratum 24313: ignore memory access type
 835                  */
 836                 cache   = 0;
 837                 ids     = 0x14;                 /* 20 bits, 8MB */
 838         } else {
 839                 cache   = GITS_BASER_WaWb;
 840                 typer   = readq_relaxed(its->base + GITS_TYPER);
 841                 ids     = GITS_TYPER_DEVBITS(typer);
 842         }
 843
 844         for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 845                 u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
 846                 u64 type = GITS_BASER_TYPE(val);
 847                 u64 entry_size = GITS_BASER_ENTRY_SIZE(val);
 848                 int order = get_order(psz);
 849                 int alloc_size;
 850                 int alloc_pages;
 851                 u64 tmp;
 852                 void *base;
 853
 854                 if (type == GITS_BASER_TYPE_NONE)
 855                         continue;
 856
 857                 /*
 858                  * Allocate as many entries as required to fit the
 859                  * range of device IDs that the ITS can grok... The ID
 860                  * space being incredibly sparse, this results in a
 861                  * massive waste of memory.
 862                  *
 863                  * For other tables, only allocate a single page.
 864                  */
 865                 if (type == GITS_BASER_TYPE_DEVICE) {
 866                         /*
 867                          * 'order' was initialized earlier to the default page
 868                          * granule of the the ITS.  We can't have an allocation
 869                          * smaller than that.  If the requested allocation
 870                          * is smaller, round up to the default page granule.
 871                          */
 872                         order = max(get_order((1UL << ids) * entry_size),
 873                                     order);
 874                         if (order >= MAX_ORDER) {
 875                                 order = MAX_ORDER - 1;
 876                                 pr_warn("%s: Device Table too large, reduce its page order to %u\n",
 877                                         node_name, order);
 878                         }
 879                 }
 880
 881                 alloc_size = (1 << order) * PAGE_SIZE;
 882 retry_alloc_baser:
 883                 alloc_pages = (alloc_size / psz);
 884                 if (alloc_pages > GITS_BASER_PAGES_MAX) {
 885                         alloc_pages = GITS_BASER_PAGES_MAX;
 886                         order = get_order(GITS_BASER_PAGES_MAX * psz);
 887                         pr_warn("%s: Device Table too large, reduce its page order to %u (%u pages)\n",
 888                                 node_name, order, alloc_pages);
 889                 }
 890
 891                 base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
 892                 if (!base) {
 893                         err = -ENOMEM;
 894                         goto out_free;
 895                 }
 896
 897                 its->tables[i].base = base;
 898                 its->tables[i].order = order;
 899
 900 retry_baser:
 901                 val = (virt_to_phys(base)                                |
 902                        (type << GITS_BASER_TYPE_SHIFT)                   |
 903                        ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) |
 904                        cache                                             |
 905                        shr                                               |
 906                        GITS_BASER_VALID);
 907
 908                 switch (psz) {
 909                 case SZ_4K:
 910                         val |= GITS_BASER_PAGE_SIZE_4K;
 911                         break;
 912                 case SZ_16K:
 913                         val |= GITS_BASER_PAGE_SIZE_16K;
 914                         break;
 915                 case SZ_64K:
 916                         val |= GITS_BASER_PAGE_SIZE_64K;
 917                         break;
 918                 }
 919
 920                 val |= alloc_pages - 1;
 921
 922                 writeq_relaxed(val, its->base + GITS_BASER + i * 8);
 923                 tmp = readq_relaxed(its->base + GITS_BASER + i * 8);
 924
 925                 if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
 926                         /*
 927                          * Shareability didn't stick. Just use
 928                          * whatever the read reported, which is likely
 929                          * to be the only thing this redistributor
 930                          * supports. If that's zero, make it
 931                          * non-cacheable as well.
 932                          */
 933                         shr = tmp & GITS_BASER_SHAREABILITY_MASK;
 934                         if (!shr) {
 935                                 cache = GITS_BASER_nC;
 936                                 __flush_dcache_area(base, alloc_size);
 937                         }
 938                         goto retry_baser;
 939                 }
 940
 941                 if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
 942                         /*
 943                          * Page size didn't stick. Let's try a smaller
 944                          * size and retry. If we reach 4K, then
 945                          * something is horribly wrong...
 946                          */
 947                         free_pages((unsigned long)base, order);
 948                         its->tables[i].base = NULL;
 949
 950                         switch (psz) {
 951                         case SZ_16K:
 952                                 psz = SZ_4K;
 953                                 goto retry_alloc_baser;
 954                         case SZ_64K:
 955                                 psz = SZ_16K;
 956                                 goto retry_alloc_baser;
 957                         }
 958                 }
 959
 960                 if (val != tmp) {
 961                         pr_err("ITS: %s: GITS_BASER%d doesn't stick: %lx %lx\n",
 962                                node_name, i,
 963                                (unsigned long) val, (unsigned long) tmp);
 964                         err = -ENXIO;
 965                         goto out_free;
 966                 }
 967
 968                 pr_info("ITS: allocated %d %s @%lx (psz %dK, shr %d)\n",
 969                         (int)(alloc_size / entry_size),
 970                         its_base_type_string[type],
 971                         (unsigned long)virt_to_phys(base),
 972                         psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);
 973         }
 974
 975         return 0;
 976
 977 out_free:
 978         its_free_tables(its);
 979
 980         return err;
 981 }
 982
 983 static int its_alloc_collections(struct its_node *its)
 984 {
 985         its->collections = kzalloc(nr_cpu_ids * sizeof(*its->collections),
 986                                    GFP_KERNEL);
 987         if (!its->collections)
 988                 return -ENOMEM;
 989
 990         return 0;
 991 }
 992
 993 static void its_cpu_init_lpis(void)
 994 {
 995         void __iomem *rbase = gic_data_rdist_rd_base();
 996         struct page *pend_page;
 997         u64 val, tmp;
 998
 999         /* If we didn't allocate the pending table yet, do it now */
1000         pend_page = gic_data_rdist()->pend_page;
1001         if (!pend_page) {
1002                 phys_addr_t paddr;
1003                 /*
1004                  * The pending pages have to be at least 64kB aligned,
1005                  * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
1006                  */
1007                 pend_page = alloc_pages(GFP_NOWAIT | __GFP_ZERO,
1008                                         get_order(max(LPI_PENDBASE_SZ, SZ_64K)));
1009                 if (!pend_page) {
1010                         pr_err("Failed to allocate PENDBASE for CPU%d\n",
1011                                smp_processor_id());
1012                         return;
1013                 }
1014
1015                 /* Make sure the GIC will observe the zero-ed page */
1016                 __flush_dcache_area(page_address(pend_page), LPI_PENDBASE_SZ);
1017
1018                 paddr = page_to_phys(pend_page);
1019                 pr_info("CPU%d: using LPI pending table @%pa\n",
1020                         smp_processor_id(), &paddr);
1021                 gic_data_rdist()->pend_page = pend_page;
1022         }
1023
1024         /* Disable LPIs */
1025         val = readl_relaxed(rbase + GICR_CTLR);
1026         val &= ~GICR_CTLR_ENABLE_LPIS;
1027         writel_relaxed(val, rbase + GICR_CTLR);
1028
1029         /*
1030          * Make sure any change to the table is observable by the GIC.
1031          */
1032         dsb(sy);
1033
1034         /* set PROPBASE */
1035         val = (page_to_phys(gic_rdists->prop_page) |
1036                GICR_PROPBASER_InnerShareable |
1037                GICR_PROPBASER_WaWb |
1038                ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));
1039
1040         writeq_relaxed(val, rbase + GICR_PROPBASER);
1041         tmp = readq_relaxed(rbase + GICR_PROPBASER);
1042
1043         if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
1044                 if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
1045                         /*
1046                          * The HW reports non-shareable, we must
1047                          * remove the cacheability attributes as
1048                          * well.
1049                          */
1050                         val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
1051                                  GICR_PROPBASER_CACHEABILITY_MASK);
1052                         val |= GICR_PROPBASER_nC;
1053                         writeq_relaxed(val, rbase + GICR_PROPBASER);
1054                 }
1055                 pr_info_once("GIC: using cache flushing for LPI property table\n");
1056                 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
1057         }
1058
1059         /* set PENDBASE */
1060         val = (page_to_phys(pend_page) |
1061                GICR_PENDBASER_InnerShareable |
1062                GICR_PENDBASER_WaWb);
1063
1064         writeq_relaxed(val, rbase + GICR_PENDBASER);
1065         tmp = readq_relaxed(rbase + GICR_PENDBASER);
1066
1067         if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
1068                 /*
1069                  * The HW reports non-shareable, we must remove the
1070                  * cacheability attributes as well.
1071                  */
1072                 val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
1073                          GICR_PENDBASER_CACHEABILITY_MASK);
1074                 val |= GICR_PENDBASER_nC;
1075                 writeq_relaxed(val, rbase + GICR_PENDBASER);
1076         }
1077
1078         /* Enable LPIs */
1079         val = readl_relaxed(rbase + GICR_CTLR);
1080         val |= GICR_CTLR_ENABLE_LPIS;
1081         writel_relaxed(val, rbase + GICR_CTLR);
1082
1083         /* Make sure the GIC has seen the above */
1084         dsb(sy);
1085 }
1086
1087 static void its_cpu_init_collection(void)
1088 {
1089         struct its_node *its;
1090         int cpu;
1091
1092         spin_lock(&its_lock);
1093         cpu = smp_processor_id();
1094
1095         list_for_each_entry(its, &its_nodes, entry) {
1096                 u64 target;
1097
1098                 /*
1099                  * We now have to bind each collection to its target
1100                  * redistributor.
1101                  */
1102                 if (readq_relaxed(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
1103                         /*
1104                          * This ITS wants the physical address of the
1105                          * redistributor.
1106                          */
1107                         target = gic_data_rdist()->phys_base;
1108                 } else {
1109                         /*
1110                          * This ITS wants a linear CPU number.
1111                          */
1112                         target = readq_relaxed(gic_data_rdist_rd_base() + GICR_TYPER);
1113                         target = GICR_TYPER_CPU_NUMBER(target) << 16;
1114                 }
1115
1116                 /* Perform collection mapping */
1117                 its->collections[cpu].target_address = target;
1118                 its->collections[cpu].col_id = cpu;
1119
1120                 its_send_mapc(its, &its->collections[cpu], 1);
1121                 its_send_invall(its, &its->collections[cpu]);
1122         }
1123
1124         spin_unlock(&its_lock);
1125 }
1126
1127 static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
1128 {
1129         struct its_device *its_dev = NULL, *tmp;
1130         unsigned long flags;
1131
1132         raw_spin_lock_irqsave(&its->lock, flags);
1133
1134         list_for_each_entry(tmp, &its->its_device_list, entry) {
1135                 if (tmp->device_id == dev_id) {
1136                         its_dev = tmp;
1137                         break;
1138                 }
1139         }
1140
1141         raw_spin_unlock_irqrestore(&its->lock, flags);
1142
1143         return its_dev;
1144 }
1145
1146 static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
1147                                             int nvecs)
1148 {
1149         struct its_device *dev;
1150         unsigned long *lpi_map;
1151         unsigned long flags;
1152         u16 *col_map = NULL;
1153         void *itt;
1154         int lpi_base;
1155         int nr_lpis;
1156         int nr_ites;
1157         int sz;
1158
1159         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1160         /*
1161          * At least one bit of EventID is being used, hence a minimum
1162          * of two entries. No, the architecture doesn't let you
1163          * express an ITT with a single entry.
1164          */
1165         nr_ites = max(2UL, roundup_pow_of_two(nvecs));
1166         sz = nr_ites * its->ite_size;
1167         sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
1168         itt = kzalloc(sz, GFP_KERNEL);
1169         lpi_map = its_lpi_alloc_chunks(nvecs, &lpi_base, &nr_lpis);
1170         if (lpi_map)
1171                 col_map = kzalloc(sizeof(*col_map) * nr_lpis, GFP_KERNEL);
1172
1173         if (!dev || !itt || !lpi_map || !col_map) {
1174                 kfree(dev);
1175                 kfree(itt);
1176                 kfree(lpi_map);
1177                 kfree(col_map);
1178                 return NULL;
1179         }
1180
1181         __flush_dcache_area(itt, sz);
1182
1183         dev->its = its;
1184         dev->itt = itt;
1185         dev->nr_ites = nr_ites;
1186         dev->event_map.lpi_map = lpi_map;
1187         dev->event_map.col_map = col_map;
1188         dev->event_map.lpi_base = lpi_base;
1189         dev->event_map.nr_lpis = nr_lpis;
1190         dev->device_id = dev_id;
1191         INIT_LIST_HEAD(&dev->entry);
1192
1193         raw_spin_lock_irqsave(&its->lock, flags);
1194         list_add(&dev->entry, &its->its_device_list);
1195         raw_spin_unlock_irqrestore(&its->lock, flags);
1196
1197         /* Map device to its ITT */
1198         its_send_mapd(dev, 1);
1199
1200         return dev;
1201 }
1202
1203 static void its_free_device(struct its_device *its_dev)
1204 {
1205         unsigned long flags;
1206
1207         raw_spin_lock_irqsave(&its_dev->its->lock, flags);
1208         list_del(&its_dev->entry);
1209         raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
1210         kfree(its_dev->itt);
1211         kfree(its_dev);
1212 }
1213
1214 static int its_alloc_device_irq(struct its_device *dev, irq_hw_number_t *hwirq)
1215 {
1216         int idx;
1217
1218         idx = find_first_zero_bit(dev->event_map.lpi_map,
1219                                   dev->event_map.nr_lpis);
1220         if (idx == dev->event_map.nr_lpis)
1221                 return -ENOSPC;
1222
1223         *hwirq = dev->event_map.lpi_base + idx;
1224         set_bit(idx, dev->event_map.lpi_map);
1225
1226         return 0;
1227 }
1228
1229 static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
1230                            int nvec, msi_alloc_info_t *info)
1231 {
1232         struct its_node *its;
1233         struct its_device *its_dev;
1234         struct msi_domain_info *msi_info;
1235         u32 dev_id;
1236
1237         /*
1238          * We ignore "dev" entierely, and rely on the dev_id that has
1239          * been passed via the scratchpad. This limits this domain's
1240          * usefulness to upper layers that definitely know that they
1241          * are built on top of the ITS.
1242          */
1243         dev_id = info->scratchpad[0].ul;
1244
1245         msi_info = msi_get_domain_info(domain);
1246         its = msi_info->data;
1247
1248         its_dev = its_find_device(its, dev_id);
1249         if (its_dev) {
1250                 /*
1251                  * We already have seen this ID, probably through
1252                  * another alias (PCI bridge of some sort). No need to
1253                  * create the device.
1254                  */
1255                 pr_debug("Reusing ITT for devID %x\n", dev_id);
1256                 goto out;
1257         }
1258
1259         its_dev = its_create_device(its, dev_id, nvec);
1260         if (!its_dev)
1261                 return -ENOMEM;
1262
1263         pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
1264 out:
1265         info->scratchpad[0].ptr = its_dev;
1266         return 0;
1267 }
1268
1269 static struct msi_domain_ops its_msi_domain_ops = {
1270         .msi_prepare    = its_msi_prepare,
1271 };
1272
1273 static int its_irq_gic_domain_alloc(struct irq_domain *domain,
1274                                     unsigned int virq,
1275                                     irq_hw_number_t hwirq)
1276 {
1277         struct irq_fwspec fwspec;
1278
1279         if (irq_domain_get_of_node(domain->parent)) {
1280                 fwspec.fwnode = domain->parent->fwnode;
1281                 fwspec.param_count = 3;
1282                 fwspec.param[0] = GIC_IRQ_TYPE_LPI;
1283                 fwspec.param[1] = hwirq;
1284                 fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
1285         } else {
1286                 return -EINVAL;
1287         }
1288
1289         return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
1290 }
1291
1292 static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1293                                 unsigned int nr_irqs, void *args)
1294 {
1295         msi_alloc_info_t *info = args;
1296         struct its_device *its_dev = info->scratchpad[0].ptr;
1297         irq_hw_number_t hwirq;
1298         int err;
1299         int i;
1300
1301         for (i = 0; i < nr_irqs; i++) {
1302                 err = its_alloc_device_irq(its_dev, &hwirq);
1303                 if (err)
1304                         return err;
1305
1306                 err = its_irq_gic_domain_alloc(domain, virq + i, hwirq);
1307                 if (err)
1308                         return err;
1309
1310                 irq_domain_set_hwirq_and_chip(domain, virq + i,
1311                                               hwirq, &its_irq_chip, its_dev);
1312                 pr_debug("ID:%d pID:%d vID:%d\n",
1313                          (int)(hwirq - its_dev->event_map.lpi_base),
1314                          (int) hwirq, virq + i);
1315         }
1316
1317         return 0;
1318 }
1319
1320 static void its_irq_domain_activate(struct irq_domain *domain,
1321                                     struct irq_data *d)
1322 {
1323         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1324         u32 event = its_get_event_id(d);
1325
1326         /* Bind the LPI to the first possible CPU */
1327         its_dev->event_map.col_map[event] = cpumask_first(cpu_online_mask);
1328
1329         /* Map the GIC IRQ and event to the device */
1330         its_send_mapvi(its_dev, d->hwirq, event);
1331 }
1332
1333 static void its_irq_domain_deactivate(struct irq_domain *domain,
1334                                       struct irq_data *d)
1335 {
1336         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1337         u32 event = its_get_event_id(d);
1338
1339         /* Stop the delivery of interrupts */
1340         its_send_discard(its_dev, event);
1341 }
1342
1343 static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
1344                                 unsigned int nr_irqs)
1345 {
1346         struct irq_data *d = irq_domain_get_irq_data(domain, virq);
1347         struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1348         int i;
1349
1350         for (i = 0; i < nr_irqs; i++) {
1351                 struct irq_data *data = irq_domain_get_irq_data(domain,
1352                                                                 virq + i);
1353                 u32 event = its_get_event_id(data);
1354
1355                 /* Mark interrupt index as unused */
1356                 clear_bit(event, its_dev->event_map.lpi_map);
1357
1358                 /* Nuke the entry in the domain */
1359                 irq_domain_reset_irq_data(data);
1360         }
1361
1362         /* If all interrupts have been freed, start mopping the floor */
1363         if (bitmap_empty(its_dev->event_map.lpi_map,
1364                          its_dev->event_map.nr_lpis)) {
1365                 its_lpi_free(&its_dev->event_map);
1366
1367                 /* Unmap device/itt */
1368                 its_send_mapd(its_dev, 0);
1369                 its_free_device(its_dev);
1370         }
1371
1372         irq_domain_free_irqs_parent(domain, virq, nr_irqs);
1373 }
1374
1375 static const struct irq_domain_ops its_domain_ops = {
1376         .alloc                  = its_irq_domain_alloc,
1377         .free                   = its_irq_domain_free,
1378         .activate               = its_irq_domain_activate,
1379         .deactivate             = its_irq_domain_deactivate,
1380 };
1381
1382 static int its_force_quiescent(void __iomem *base)
1383 {
1384         u32 count = 1000000;    /* 1s */
1385         u32 val;
1386
1387         val = readl_relaxed(base + GITS_CTLR);
1388         if (val & GITS_CTLR_QUIESCENT)
1389                 return 0;
1390
1391         /* Disable the generation of all interrupts to this ITS */
1392         val &= ~GITS_CTLR_ENABLE;
1393         writel_relaxed(val, base + GITS_CTLR);
1394
1395         /* Poll GITS_CTLR and wait until ITS becomes quiescent */
1396         while (1) {
1397                 val = readl_relaxed(base + GITS_CTLR);
1398                 if (val & GITS_CTLR_QUIESCENT)
1399                         return 0;
1400
1401                 count--;
1402                 if (!count)
1403                         return -EBUSY;
1404
1405                 cpu_relax();
1406                 udelay(1);
1407         }
1408 }
1409
1410 static void __maybe_unused its_enable_quirk_cavium_22375(void *data)
1411 {
1412         struct its_node *its = data;
1413
1414         its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
1415 }
1416
1417 static const struct gic_quirk its_quirks[] = {
1418 #ifdef CONFIG_CAVIUM_ERRATUM_22375
1419         {
1420                 .desc   = "ITS: Cavium errata 22375, 24313",
1421                 .iidr   = 0xa100034c,   /* ThunderX pass 1.x */
1422                 .mask   = 0xffff0fff,
1423                 .init   = its_enable_quirk_cavium_22375,
1424         },
1425 #endif
1426         {
1427         }
1428 };
1429
1430 static void its_enable_quirks(struct its_node *its)
1431 {
1432         u32 iidr = readl_relaxed(its->base + GITS_IIDR);
1433
1434         gic_enable_quirks(iidr, its_quirks, its);
1435 }
1436
1437 static int its_probe(struct device_node *node, struct irq_domain *parent)
1438 {
1439         struct resource res;
1440         struct its_node *its;
1441         void __iomem *its_base;
1442         struct irq_domain *inner_domain;
1443         u32 val;
1444         u64 baser, tmp;
1445         int err;
1446
1447         err = of_address_to_resource(node, 0, &res);
1448         if (err) {
1449                 pr_warn("%s: no regs?\n", node->full_name);
1450                 return -ENXIO;
1451         }
1452
1453         its_base = ioremap(res.start, resource_size(&res));
1454         if (!its_base) {
1455                 pr_warn("%s: unable to map registers\n", node->full_name);
1456                 return -ENOMEM;
1457         }
1458
1459         val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
1460         if (val != 0x30 && val != 0x40) {
1461                 pr_warn("%s: no ITS detected, giving up\n", node->full_name);
1462                 err = -ENODEV;
1463                 goto out_unmap;
1464         }
1465
1466         err = its_force_quiescent(its_base);
1467         if (err) {
1468                 pr_warn("%s: failed to quiesce, giving up\n",
1469                         node->full_name);
1470                 goto out_unmap;
1471         }
1472
1473         pr_info("ITS: %s\n", node->full_name);
1474
1475         its = kzalloc(sizeof(*its), GFP_KERNEL);
1476         if (!its) {
1477                 err = -ENOMEM;
1478                 goto out_unmap;
1479         }
1480
1481         raw_spin_lock_init(&its->lock);
1482         INIT_LIST_HEAD(&its->entry);
1483         INIT_LIST_HEAD(&its->its_device_list);
1484         its->base = its_base;
1485         its->phys_base = res.start;
1486         its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1;
1487
1488         its->cmd_base = kzalloc(ITS_CMD_QUEUE_SZ, GFP_KERNEL);
1489         if (!its->cmd_base) {
1490                 err = -ENOMEM;
1491                 goto out_free_its;
1492         }
1493         its->cmd_write = its->cmd_base;
1494
1495         its_enable_quirks(its);
1496
1497         err = its_alloc_tables(node->full_name, its);
1498         if (err)
1499                 goto out_free_cmd;
1500
1501         err = its_alloc_collections(its);
1502         if (err)
1503                 goto out_free_tables;
1504
1505         baser = (virt_to_phys(its->cmd_base)    |
1506                  GITS_CBASER_WaWb               |
1507                  GITS_CBASER_InnerShareable     |
1508                  (ITS_CMD_QUEUE_SZ / SZ_4K - 1) |
1509                  GITS_CBASER_VALID);
1510
1511         writeq_relaxed(baser, its->base + GITS_CBASER);
1512         tmp = readq_relaxed(its->base + GITS_CBASER);
1513
1514         if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
1515                 if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
1516                         /*
1517                          * The HW reports non-shareable, we must
1518                          * remove the cacheability attributes as
1519                          * well.
1520                          */
1521                         baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
1522                                    GITS_CBASER_CACHEABILITY_MASK);
1523                         baser |= GITS_CBASER_nC;
1524                         writeq_relaxed(baser, its->base + GITS_CBASER);
1525                 }
1526                 pr_info("ITS: using cache flushing for cmd queue\n");
1527                 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
1528         }
1529
1530         writeq_relaxed(0, its->base + GITS_CWRITER);
1531         writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);
1532
1533         if (of_property_read_bool(node, "msi-controller")) {
1534                 struct msi_domain_info *info;
1535
1536                 info = kzalloc(sizeof(*info), GFP_KERNEL);
1537                 if (!info) {
1538                         err = -ENOMEM;
1539                         goto out_free_tables;
1540                 }
1541
1542                 inner_domain = irq_domain_add_tree(node, &its_domain_ops, its);
1543                 if (!inner_domain) {
1544                         err = -ENOMEM;
1545                         kfree(info);
1546                         goto out_free_tables;
1547                 }
1548
1549                 inner_domain->parent = parent;
1550                 inner_domain->bus_token = DOMAIN_BUS_NEXUS;
1551                 info->ops = &its_msi_domain_ops;
1552                 info->data = its;
1553                 inner_domain->host_data = info;
1554         }
1555
1556         spin_lock(&its_lock);
1557         list_add(&its->entry, &its_nodes);
1558         spin_unlock(&its_lock);
1559
1560         return 0;
1561
1562 out_free_tables:
1563         its_free_tables(its);
1564 out_free_cmd:
1565         kfree(its->cmd_base);
1566 out_free_its:
1567         kfree(its);
1568 out_unmap:
1569         iounmap(its_base);
1570         pr_err("ITS: failed probing %s (%d)\n", node->full_name, err);
1571         return err;
1572 }
1573
1574 static bool gic_rdists_supports_plpis(void)
1575 {
1576         return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
1577 }
1578
1579 int its_cpu_init(void)
1580 {
1581         if (!list_empty(&its_nodes)) {
1582                 if (!gic_rdists_supports_plpis()) {
1583                         pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
1584                         return -ENXIO;
1585                 }
1586                 its_cpu_init_lpis();
1587                 its_cpu_init_collection();
1588         }
1589
1590         return 0;
1591 }
1592
1593 static struct of_device_id its_device_id[] = {
1594         {       .compatible     = "arm,gic-v3-its",     },
1595         {},
1596 };
1597
1598 int its_init(struct device_node *node, struct rdists *rdists,
1599              struct irq_domain *parent_domain)
1600 {
1601         struct device_node *np;
1602
1603         for (np = of_find_matching_node(node, its_device_id); np;
1604              np = of_find_matching_node(np, its_device_id)) {
1605                 its_probe(np, parent_domain);
1606         }
1607
1608         if (list_empty(&its_nodes)) {
1609                 pr_warn("ITS: No ITS available, not enabling LPIs\n");
1610                 return -ENXIO;
1611         }
1612
1613         gic_rdists = rdists;
1614         gic_root_node = node;
1615
1616         its_alloc_lpi_tables();
1617         its_lpi_init(rdists->id_bits);
1618
1619         return 0;
1620 }