drivers/irqchip/irq-mips-gic.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   8  */
   9 #include <linux/bitmap.h>
  10 #include <linux/clocksource.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/irqchip/mips-gic.h>
  15 #include <linux/sched.h>
  16 #include <linux/smp.h>
  17
  18 #include <asm/setup.h>
  19 #include <asm/traps.h>
  20
  21 unsigned int gic_frequency;
  22 unsigned int gic_present;
  23
  24 struct gic_pcpu_mask {
  25         DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
  26 };
  27
  28 static void __iomem *gic_base;
  29 static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  30 static DEFINE_SPINLOCK(gic_lock);
  31 static struct irq_domain *gic_irq_domain;
  32 static int gic_shared_intrs;
  33 static int gic_vpes;
  34 static unsigned int gic_cpu_pin;
  35 static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
  36
  37 static void __gic_irq_dispatch(void);
  38
  39 static inline unsigned int gic_read(unsigned int reg)
  40 {
  41         return __raw_readl(gic_base + reg);
  42 }
  43
  44 static inline void gic_write(unsigned int reg, unsigned int val)
  45 {
  46         __raw_writel(val, gic_base + reg);
  47 }
  48
  49 static inline void gic_update_bits(unsigned int reg, unsigned int mask,
  50                                    unsigned int val)
  51 {
  52         unsigned int regval;
  53
  54         regval = gic_read(reg);
  55         regval &= ~mask;
  56         regval |= val;
  57         gic_write(reg, regval);
  58 }
  59
  60 static inline void gic_reset_mask(unsigned int intr)
  61 {
  62         gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
  63                   1 << GIC_INTR_BIT(intr));
  64 }
  65
  66 static inline void gic_set_mask(unsigned int intr)
  67 {
  68         gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
  69                   1 << GIC_INTR_BIT(intr));
  70 }
  71
  72 static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
  73 {
  74         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
  75                         GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
  76                         pol << GIC_INTR_BIT(intr));
  77 }
  78
  79 static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
  80 {
  81         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
  82                         GIC_INTR_OFS(intr), 1 << GIC_INTR_BIT(intr),
  83                         trig << GIC_INTR_BIT(intr));
  84 }
  85
  86 static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
  87 {
  88         gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
  89                         1 << GIC_INTR_BIT(intr),
  90                         dual << GIC_INTR_BIT(intr));
  91 }
  92
  93 static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
  94 {
  95         gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
  96                   GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
  97 }
  98
  99 static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
 100 {
 101         gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
 102                   GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
 103                   GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
 104 }
 105
 106 #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
 107 cycle_t gic_read_count(void)
 108 {
 109         unsigned int hi, hi2, lo;
 110
 111         do {
 112                 hi = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
 113                 lo = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
 114                 hi2 = gic_read(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
 115         } while (hi2 != hi);
 116
 117         return (((cycle_t) hi) << 32) + lo;
 118 }
 119
 120 unsigned int gic_get_count_width(void)
 121 {
 122         unsigned int bits, config;
 123
 124         config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 125         bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
 126                          GIC_SH_CONFIG_COUNTBITS_SHF);
 127
 128         return bits;
 129 }
 130
 131 void gic_write_compare(cycle_t cnt)
 132 {
 133         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
 134                                 (int)(cnt >> 32));
 135         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
 136                                 (int)(cnt & 0xffffffff));
 137 }
 138
 139 void gic_write_cpu_compare(cycle_t cnt, int cpu)
 140 {
 141         unsigned long flags;
 142
 143         local_irq_save(flags);
 144
 145         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
 146         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
 147                                 (int)(cnt >> 32));
 148         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
 149                                 (int)(cnt & 0xffffffff));
 150
 151         local_irq_restore(flags);
 152 }
 153
 154 cycle_t gic_read_compare(void)
 155 {
 156         unsigned int hi, lo;
 157
 158         hi = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
 159         lo = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
 160
 161         return (((cycle_t) hi) << 32) + lo;
 162 }
 163 #endif
 164
 165 static bool gic_local_irq_is_routable(int intr)
 166 {
 167         u32 vpe_ctl;
 168
 169         /* All local interrupts are routable in EIC mode. */
 170         if (cpu_has_veic)
 171                 return true;
 172
 173         vpe_ctl = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
 174         switch (intr) {
 175         case GIC_LOCAL_INT_TIMER:
 176                 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
 177         case GIC_LOCAL_INT_PERFCTR:
 178                 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
 179         case GIC_LOCAL_INT_FDC:
 180                 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
 181         case GIC_LOCAL_INT_SWINT0:
 182         case GIC_LOCAL_INT_SWINT1:
 183                 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
 184         default:
 185                 return true;
 186         }
 187 }
 188
 189 unsigned int gic_get_timer_pending(void)
 190 {
 191         unsigned int vpe_pending;
 192
 193         vpe_pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
 194         return vpe_pending & GIC_VPE_PEND_TIMER_MSK;
 195 }
 196
 197 static void gic_bind_eic_interrupt(int irq, int set)
 198 {
 199         /* Convert irq vector # to hw int # */
 200         irq -= GIC_PIN_TO_VEC_OFFSET;
 201
 202         /* Set irq to use shadow set */
 203         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
 204                   GIC_VPE_EIC_SS(irq), set);
 205 }
 206
 207 void gic_send_ipi(unsigned int intr)
 208 {
 209         gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(intr));
 210 }
 211
 212 int gic_get_c0_compare_int(void)
 213 {
 214         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
 215                 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 216         return irq_create_mapping(gic_irq_domain,
 217                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
 218 }
 219
 220 int gic_get_c0_perfcount_int(void)
 221 {
 222         if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
 223                 /* Is the erformance counter shared with the timer? */
 224                 if (cp0_perfcount_irq < 0)
 225                         return -1;
 226                 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 227         }
 228         return irq_create_mapping(gic_irq_domain,
 229                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
 230 }
 231
 232 static unsigned int gic_get_int(void)
 233 {
 234         unsigned int i;
 235         unsigned long *pcpu_mask;
 236         unsigned long pending_reg, intrmask_reg;
 237         DECLARE_BITMAP(pending, GIC_MAX_INTRS);
 238         DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
 239
 240         /* Get per-cpu bitmaps */
 241         pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
 242
 243         pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
 244         intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
 245
 246         for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
 247                 pending[i] = gic_read(pending_reg);
 248                 intrmask[i] = gic_read(intrmask_reg);
 249                 pending_reg += 0x4;
 250                 intrmask_reg += 0x4;
 251         }
 252
 253         bitmap_and(pending, pending, intrmask, gic_shared_intrs);
 254         bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
 255
 256         return find_first_bit(pending, gic_shared_intrs);
 257 }
 258
 259 static void gic_mask_irq(struct irq_data *d)
 260 {
 261         gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
 262 }
 263
 264 static void gic_unmask_irq(struct irq_data *d)
 265 {
 266         gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
 267 }
 268
 269 static void gic_ack_irq(struct irq_data *d)
 270 {
 271         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 272
 273         gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
 274 }
 275
 276 static int gic_set_type(struct irq_data *d, unsigned int type)
 277 {
 278         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 279         unsigned long flags;
 280         bool is_edge;
 281
 282         spin_lock_irqsave(&gic_lock, flags);
 283         switch (type & IRQ_TYPE_SENSE_MASK) {
 284         case IRQ_TYPE_EDGE_FALLING:
 285                 gic_set_polarity(irq, GIC_POL_NEG);
 286                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 287                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 288                 is_edge = true;
 289                 break;
 290         case IRQ_TYPE_EDGE_RISING:
 291                 gic_set_polarity(irq, GIC_POL_POS);
 292                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 293                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 294                 is_edge = true;
 295                 break;
 296         case IRQ_TYPE_EDGE_BOTH:
 297                 /* polarity is irrelevant in this case */
 298                 gic_set_trigger(irq, GIC_TRIG_EDGE);
 299                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
 300                 is_edge = true;
 301                 break;
 302         case IRQ_TYPE_LEVEL_LOW:
 303                 gic_set_polarity(irq, GIC_POL_NEG);
 304                 gic_set_trigger(irq, GIC_TRIG_LEVEL);
 305                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 306                 is_edge = false;
 307                 break;
 308         case IRQ_TYPE_LEVEL_HIGH:
 309         default:
 310                 gic_set_polarity(irq, GIC_POL_POS);
 311                 gic_set_trigger(irq, GIC_TRIG_LEVEL);
 312                 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
 313                 is_edge = false;
 314                 break;
 315         }
 316
 317         if (is_edge) {
 318                 __irq_set_chip_handler_name_locked(d->irq,
 319                                                    &gic_edge_irq_controller,
 320                                                    handle_edge_irq, NULL);
 321         } else {
 322                 __irq_set_chip_handler_name_locked(d->irq,
 323                                                    &gic_level_irq_controller,
 324                                                    handle_level_irq, NULL);
 325         }
 326         spin_unlock_irqrestore(&gic_lock, flags);
 327
 328         return 0;
 329 }
 330
 331 #ifdef CONFIG_SMP
 332 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
 333                             bool force)
 334 {
 335         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 336         cpumask_t       tmp = CPU_MASK_NONE;
 337         unsigned long   flags;
 338         int             i;
 339
 340         cpumask_and(&tmp, cpumask, cpu_online_mask);
 341         if (cpus_empty(tmp))
 342                 return -EINVAL;
 343
 344         /* Assumption : cpumask refers to a single CPU */
 345         spin_lock_irqsave(&gic_lock, flags);
 346
 347         /* Re-route this IRQ */
 348         gic_map_to_vpe(irq, first_cpu(tmp));
 349
 350         /* Update the pcpu_masks */
 351         for (i = 0; i < NR_CPUS; i++)
 352                 clear_bit(irq, pcpu_masks[i].pcpu_mask);
 353         set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
 354
 355         cpumask_copy(d->affinity, cpumask);
 356         spin_unlock_irqrestore(&gic_lock, flags);
 357
 358         return IRQ_SET_MASK_OK_NOCOPY;
 359 }
 360 #endif
 361
 362 static struct irq_chip gic_level_irq_controller = {
 363         .name                   =       "MIPS GIC",
 364         .irq_mask               =       gic_mask_irq,
 365         .irq_unmask             =       gic_unmask_irq,
 366         .irq_set_type           =       gic_set_type,
 367 #ifdef CONFIG_SMP
 368         .irq_set_affinity       =       gic_set_affinity,
 369 #endif
 370 };
 371
 372 static struct irq_chip gic_edge_irq_controller = {
 373         .name                   =       "MIPS GIC",
 374         .irq_ack                =       gic_ack_irq,
 375         .irq_mask               =       gic_mask_irq,
 376         .irq_unmask             =       gic_unmask_irq,
 377         .irq_set_type           =       gic_set_type,
 378 #ifdef CONFIG_SMP
 379         .irq_set_affinity       =       gic_set_affinity,
 380 #endif
 381 };
 382
 383 static unsigned int gic_get_local_int(void)
 384 {
 385         unsigned long pending, masked;
 386
 387         pending = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
 388         masked = gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
 389
 390         bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
 391
 392         return find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
 393 }
 394
 395 static void gic_mask_local_irq(struct irq_data *d)
 396 {
 397         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 398
 399         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
 400 }
 401
 402 static void gic_unmask_local_irq(struct irq_data *d)
 403 {
 404         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 405
 406         gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
 407 }
 408
 409 static struct irq_chip gic_local_irq_controller = {
 410         .name                   =       "MIPS GIC Local",
 411         .irq_mask               =       gic_mask_local_irq,
 412         .irq_unmask             =       gic_unmask_local_irq,
 413 };
 414
 415 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 416 {
 417         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 418         int i;
 419         unsigned long flags;
 420
 421         spin_lock_irqsave(&gic_lock, flags);
 422         for (i = 0; i < gic_vpes; i++) {
 423                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 424                 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
 425         }
 426         spin_unlock_irqrestore(&gic_lock, flags);
 427 }
 428
 429 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 430 {
 431         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 432         int i;
 433         unsigned long flags;
 434
 435         spin_lock_irqsave(&gic_lock, flags);
 436         for (i = 0; i < gic_vpes; i++) {
 437                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 438                 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
 439         }
 440         spin_unlock_irqrestore(&gic_lock, flags);
 441 }
 442
 443 static struct irq_chip gic_all_vpes_local_irq_controller = {
 444         .name                   =       "MIPS GIC Local",
 445         .irq_mask               =       gic_mask_local_irq_all_vpes,
 446         .irq_unmask             =       gic_unmask_local_irq_all_vpes,
 447 };
 448
 449 static void __gic_irq_dispatch(void)
 450 {
 451         unsigned int intr, virq;
 452
 453         while ((intr = gic_get_local_int()) != GIC_NUM_LOCAL_INTRS) {
 454                 virq = irq_linear_revmap(gic_irq_domain,
 455                                          GIC_LOCAL_TO_HWIRQ(intr));
 456                 do_IRQ(virq);
 457         }
 458
 459         while ((intr = gic_get_int()) != gic_shared_intrs) {
 460                 virq = irq_linear_revmap(gic_irq_domain,
 461                                          GIC_SHARED_TO_HWIRQ(intr));
 462                 do_IRQ(virq);
 463         }
 464 }
 465
 466 static void gic_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 467 {
 468         __gic_irq_dispatch();
 469 }
 470
 471 #ifdef CONFIG_MIPS_GIC_IPI
 472 static int gic_resched_int_base;
 473 static int gic_call_int_base;
 474
 475 unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
 476 {
 477         return gic_resched_int_base + cpu;
 478 }
 479
 480 unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
 481 {
 482         return gic_call_int_base + cpu;
 483 }
 484
 485 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
 486 {
 487         scheduler_ipi();
 488
 489         return IRQ_HANDLED;
 490 }
 491
 492 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
 493 {
 494         smp_call_function_interrupt();
 495
 496         return IRQ_HANDLED;
 497 }
 498
 499 static struct irqaction irq_resched = {
 500         .handler        = ipi_resched_interrupt,
 501         .flags          = IRQF_PERCPU,
 502         .name           = "IPI resched"
 503 };
 504
 505 static struct irqaction irq_call = {
 506         .handler        = ipi_call_interrupt,
 507         .flags          = IRQF_PERCPU,
 508         .name           = "IPI call"
 509 };
 510
 511 static __init void gic_ipi_init_one(unsigned int intr, int cpu,
 512                                     struct irqaction *action)
 513 {
 514         int virq = irq_create_mapping(gic_irq_domain,
 515                                       GIC_SHARED_TO_HWIRQ(intr));
 516         int i;
 517
 518         gic_map_to_vpe(intr, cpu);
 519         for (i = 0; i < NR_CPUS; i++)
 520                 clear_bit(intr, pcpu_masks[i].pcpu_mask);
 521         set_bit(intr, pcpu_masks[cpu].pcpu_mask);
 522
 523         irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
 524
 525         irq_set_handler(virq, handle_percpu_irq);
 526         setup_irq(virq, action);
 527 }
 528
 529 static __init void gic_ipi_init(void)
 530 {
 531         int i;
 532
 533         /* Use last 2 * NR_CPUS interrupts as IPIs */
 534         gic_resched_int_base = gic_shared_intrs - nr_cpu_ids;
 535         gic_call_int_base = gic_resched_int_base - nr_cpu_ids;
 536
 537         for (i = 0; i < nr_cpu_ids; i++) {
 538                 gic_ipi_init_one(gic_call_int_base + i, i, &irq_call);
 539                 gic_ipi_init_one(gic_resched_int_base + i, i, &irq_resched);
 540         }
 541 }
 542 #else
 543 static inline void gic_ipi_init(void)
 544 {
 545 }
 546 #endif
 547
 548 static void __init gic_basic_init(void)
 549 {
 550         unsigned int i;
 551
 552         board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 553
 554         /* Setup defaults */
 555         for (i = 0; i < gic_shared_intrs; i++) {
 556                 gic_set_polarity(i, GIC_POL_POS);
 557                 gic_set_trigger(i, GIC_TRIG_LEVEL);
 558                 gic_reset_mask(i);
 559         }
 560
 561         for (i = 0; i < gic_vpes; i++) {
 562                 unsigned int j;
 563
 564                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 565                 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
 566                         if (!gic_local_irq_is_routable(j))
 567                                 continue;
 568                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
 569                 }
 570         }
 571 }
 572
 573 static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
 574                                     irq_hw_number_t hw)
 575 {
 576         int intr = GIC_HWIRQ_TO_LOCAL(hw);
 577         int ret = 0;
 578         int i;
 579         unsigned long flags;
 580
 581         if (!gic_local_irq_is_routable(intr))
 582                 return -EPERM;
 583
 584         /*
 585          * HACK: These are all really percpu interrupts, but the rest
 586          * of the MIPS kernel code does not use the percpu IRQ API for
 587          * the CP0 timer and performance counter interrupts.
 588          */
 589         if (intr != GIC_LOCAL_INT_TIMER && intr != GIC_LOCAL_INT_PERFCTR) {
 590                 irq_set_chip_and_handler(virq,
 591                                          &gic_local_irq_controller,
 592                                          handle_percpu_devid_irq);
 593                 irq_set_percpu_devid(virq);
 594         } else {
 595                 irq_set_chip_and_handler(virq,
 596                                          &gic_all_vpes_local_irq_controller,
 597                                          handle_percpu_irq);
 598         }
 599
 600         spin_lock_irqsave(&gic_lock, flags);
 601         for (i = 0; i < gic_vpes; i++) {
 602                 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
 603
 604                 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
 605
 606                 switch (intr) {
 607                 case GIC_LOCAL_INT_WD:
 608                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
 609                         break;
 610                 case GIC_LOCAL_INT_COMPARE:
 611                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP), val);
 612                         break;
 613                 case GIC_LOCAL_INT_TIMER:
 614                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP), val);
 615                         break;
 616                 case GIC_LOCAL_INT_PERFCTR:
 617                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP), val);
 618                         break;
 619                 case GIC_LOCAL_INT_SWINT0:
 620                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP), val);
 621                         break;
 622                 case GIC_LOCAL_INT_SWINT1:
 623                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP), val);
 624                         break;
 625                 case GIC_LOCAL_INT_FDC:
 626                         gic_write(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
 627                         break;
 628                 default:
 629                         pr_err("Invalid local IRQ %d\n", intr);
 630                         ret = -EINVAL;
 631                         break;
 632                 }
 633         }
 634         spin_unlock_irqrestore(&gic_lock, flags);
 635
 636         return ret;
 637 }
 638
 639 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
 640                                      irq_hw_number_t hw)
 641 {
 642         int intr = GIC_HWIRQ_TO_SHARED(hw);
 643         unsigned long flags;
 644
 645         irq_set_chip_and_handler(virq, &gic_level_irq_controller,
 646                                  handle_level_irq);
 647
 648         spin_lock_irqsave(&gic_lock, flags);
 649         gic_map_to_pin(intr, gic_cpu_pin);
 650         /* Map to VPE 0 by default */
 651         gic_map_to_vpe(intr, 0);
 652         set_bit(intr, pcpu_masks[0].pcpu_mask);
 653         spin_unlock_irqrestore(&gic_lock, flags);
 654
 655         return 0;
 656 }
 657
 658 static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 659                               irq_hw_number_t hw)
 660 {
 661         if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
 662                 return gic_local_irq_domain_map(d, virq, hw);
 663         return gic_shared_irq_domain_map(d, virq, hw);
 664 }
 665
 666 static struct irq_domain_ops gic_irq_domain_ops = {
 667         .map = gic_irq_domain_map,
 668         .xlate = irq_domain_xlate_twocell,
 669 };
 670
 671 void __init gic_init(unsigned long gic_base_addr,
 672                      unsigned long gic_addrspace_size, unsigned int cpu_vec,
 673                      unsigned int irqbase)
 674 {
 675         unsigned int gicconfig;
 676
 677         gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
 678
 679         gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
 680         gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
 681                    GIC_SH_CONFIG_NUMINTRS_SHF;
 682         gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
 683
 684         gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
 685                   GIC_SH_CONFIG_NUMVPES_SHF;
 686         gic_vpes = gic_vpes + 1;
 687
 688         if (cpu_has_veic) {
 689                 /* Always use vector 1 in EIC mode */
 690                 gic_cpu_pin = 0;
 691                 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
 692                                __gic_irq_dispatch);
 693         } else {
 694                 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
 695                 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
 696                                         gic_irq_dispatch);
 697         }
 698
 699         gic_irq_domain = irq_domain_add_simple(NULL, GIC_NUM_LOCAL_INTRS +
 700                                                gic_shared_intrs, irqbase,
 701                                                &gic_irq_domain_ops, NULL);
 702         if (!gic_irq_domain)
 703                 panic("Failed to add GIC IRQ domain");
 704
 705         gic_basic_init();
 706
 707         gic_ipi_init();
 708 }