2 * Allwinner A1X SoCs IRQ chip driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
18 #include <linux/irq.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
23 #include <asm/exception.h>
24 #include <asm/mach/irq.h>
28 #define SUN4I_IRQ_VECTOR_REG 0x00
29 #define SUN4I_IRQ_PROTECTION_REG 0x08
30 #define SUN4I_IRQ_NMI_CTRL_REG 0x0c
31 #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
32 #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
33 #define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
34 #define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
36 static void __iomem *sun4i_irq_base;
37 static struct irq_domain *sun4i_irq_domain;
39 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
41 static void sun4i_irq_ack(struct irq_data *irqd)
43 unsigned int irq = irqd_to_hwirq(irqd);
44 unsigned int irq_off = irq % 32;
49 return; /* Only IRQ 0 / the ENMI needs to be acked */
51 val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
52 writel(val | (1 << irq_off),
53 sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
56 static void sun4i_irq_mask(struct irq_data *irqd)
58 unsigned int irq = irqd_to_hwirq(irqd);
59 unsigned int irq_off = irq % 32;
63 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
64 writel(val & ~(1 << irq_off),
65 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
68 static void sun4i_irq_unmask(struct irq_data *irqd)
70 unsigned int irq = irqd_to_hwirq(irqd);
71 unsigned int irq_off = irq % 32;
75 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
76 writel(val | (1 << irq_off),
77 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
80 static struct irq_chip sun4i_irq_chip = {
82 .irq_eoi = sun4i_irq_ack,
83 .irq_mask = sun4i_irq_mask,
84 .irq_unmask = sun4i_irq_unmask,
85 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
88 static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
91 irq_set_chip_and_handler(virq, &sun4i_irq_chip, handle_fasteoi_irq);
92 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
97 static struct irq_domain_ops sun4i_irq_ops = {
99 .xlate = irq_domain_xlate_onecell,
102 static int __init sun4i_of_init(struct device_node *node,
103 struct device_node *parent)
105 sun4i_irq_base = of_iomap(node, 0);
107 panic("%s: unable to map IC registers\n",
110 /* Disable all interrupts */
111 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
112 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
113 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
115 /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
116 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
117 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
118 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
120 /* Clear all the pending interrupts */
121 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
122 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
123 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
125 /* Enable protection mode */
126 writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
128 /* Configure the external interrupt source type */
129 writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
131 sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
132 &sun4i_irq_ops, NULL);
133 if (!sun4i_irq_domain)
134 panic("%s: unable to create IRQ domain\n", node->full_name);
136 set_handle_irq(sun4i_handle_irq);
140 IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
142 static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
147 * hwirq == 0 can mean one of 3 things:
148 * 1) no more irqs pending
151 * So if we immediately get a reading of 0, check the irq-pending reg
152 * to differentiate between 2 and 3. We only do this once to avoid
153 * the extra check in the common case of 1 hapening after having
154 * read the vector-reg once.
156 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
158 !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
162 irq = irq_find_mapping(sun4i_irq_domain, hwirq);
163 handle_IRQ(irq, regs);
164 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
165 } while (hwirq != 0);