drivers/isdn/hisax/hfc4s8s_l1.c

   1 /*************************************************************************/
   2 /* $Id: hfc4s8s_l1.c,v 1.10 2005/02/09 16:31:09 martinb1 Exp $           */
   3 /* HFC-4S/8S low layer interface for Cologne Chip HFC-4S/8S isdn chips   */
   4 /* The low layer (L1) is implemented as a loadable module for usage with */
   5 /* the HiSax isdn driver for passive cards.                              */
   6 /*                                                                       */
   7 /* Author: Werner Cornelius                                              */
   8 /* (C) 2003 Cornelius Consult (werner@cornelius-consult.de)              */
   9 /*                                                                       */
  10 /* Driver maintained by Cologne Chip                                     */
  11 /*   - Martin Bachem, support@colognechip.com                            */
  12 /*                                                                       */
  13 /* This driver only works with chip revisions >= 1, older revision 0     */
  14 /* engineering samples (only first manufacturer sample cards) will not   */
  15 /* work and are rejected by the driver.                                  */
  16 /*                                                                       */
  17 /* This file distributed under the GNU GPL.                              */
  18 /*                                                                       */
  19 /* See Version History at the end of this file                           */
  20 /*                                                                       */
  21 /*************************************************************************/
  22
  23 #include <linux/module.h>
  24 #include <linux/init.h>
  25 #include <linux/pci.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/delay.h>
  28 #include <linux/slab.h>
  29 #include <linux/timer.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/wait.h>
  32 #include <asm/io.h>
  33 #include "hisax_if.h"
  34 #include "hfc4s8s_l1.h"
  35
  36 static const char hfc4s8s_rev[] = "Revision: 1.10";
  37
  38 /***************************************************************/
  39 /* adjustable transparent mode fifo threshold                  */
  40 /* The value defines the used fifo threshold with the equation */
  41 /*                                                             */
  42 /* notify number of bytes = 2 * 2 ^ TRANS_FIFO_THRES           */
  43 /*                                                             */
  44 /* The default value is 5 which results in a buffer size of 64 */
  45 /* and an interrupt rate of 8ms.                               */
  46 /* The maximum value is 7 due to fifo size restrictions.       */
  47 /* Values below 3-4 are not recommended due to high interrupt  */
  48 /* load of the processor. For non critical applications the    */
  49 /* value should be raised to 7 to reduce any interrupt overhead*/
  50 /***************************************************************/
  51 #define TRANS_FIFO_THRES 5
  52
  53 /*************/
  54 /* constants */
  55 /*************/
  56 #define CLOCKMODE_0     0       /* ext. 24.576 MhZ clk freq, int. single clock mode */
  57 #define CLOCKMODE_1     1       /* ext. 49.576 MhZ clk freq, int. single clock mode */
  58 #define CHIP_ID_SHIFT   4
  59 #define HFC_MAX_ST 8
  60 #define MAX_D_FRAME_SIZE 270
  61 #define MAX_B_FRAME_SIZE 1536
  62 #define TRANS_TIMER_MODE (TRANS_FIFO_THRES & 0xf)
  63 #define TRANS_FIFO_BYTES (2 << TRANS_FIFO_THRES)
  64 #define MAX_F_CNT 0x0f
  65
  66 #define CLKDEL_NT 0x6c
  67 #define CLKDEL_TE 0xf
  68 #define CTRL0_NT  4
  69 #define CTRL0_TE  0
  70
  71 #define L1_TIMER_T4 2           /* minimum in jiffies */
  72 #define L1_TIMER_T3 (7 * HZ)    /* activation timeout */
  73 #define L1_TIMER_T1 ((120 * HZ) / 1000) /* NT mode deactivation timeout */
  74
  75
  76 /******************/
  77 /* types and vars */
  78 /******************/
  79 static int card_cnt;
  80
  81 /* private driver_data */
  82 typedef struct {
  83         int chip_id;
  84         int clock_mode;
  85         int max_st_ports;
  86         char *device_name;
  87 } hfc4s8s_param;
  88
  89 static struct pci_device_id hfc4s8s_ids[] = {
  90         {.vendor = PCI_VENDOR_ID_CCD,
  91          .device = PCI_DEVICE_ID_4S,
  92          .subvendor = 0x1397,
  93          .subdevice = 0x08b4,
  94          .driver_data =
  95          (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_0, 4,
  96                                  "HFC-4S Evaluation Board"}),
  97         },
  98         {.vendor = PCI_VENDOR_ID_CCD,
  99          .device = PCI_DEVICE_ID_8S,
 100          .subvendor = 0x1397,
 101          .subdevice = 0x16b8,
 102          .driver_data =
 103          (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_0, 8,
 104                                  "HFC-8S Evaluation Board"}),
 105         },
 106         {.vendor = PCI_VENDOR_ID_CCD,
 107          .device = PCI_DEVICE_ID_4S,
 108          .subvendor = 0x1397,
 109          .subdevice = 0xb520,
 110          .driver_data =
 111          (unsigned long) &((hfc4s8s_param) {CHIP_ID_4S, CLOCKMODE_1, 4,
 112                                  "IOB4ST"}),
 113         },
 114         {.vendor = PCI_VENDOR_ID_CCD,
 115          .device = PCI_DEVICE_ID_8S,
 116          .subvendor = 0x1397,
 117          .subdevice = 0xb522,
 118          .driver_data =
 119          (unsigned long) &((hfc4s8s_param) {CHIP_ID_8S, CLOCKMODE_1, 8,
 120                                  "IOB8ST"}),
 121         },
 122         {}
 123 };
 124
 125 MODULE_DEVICE_TABLE(pci, hfc4s8s_ids);
 126
 127 MODULE_AUTHOR("Werner Cornelius, werner@cornelius-consult.de");
 128 MODULE_DESCRIPTION("ISDN layer 1 for Cologne Chip HFC-4S/8S chips");
 129 MODULE_LICENSE("GPL");
 130
 131 /***********/
 132 /* layer 1 */
 133 /***********/
 134 struct hfc4s8s_btype {
 135         spinlock_t lock;
 136         struct hisax_b_if b_if;
 137         struct hfc4s8s_l1 *l1p;
 138         struct sk_buff_head tx_queue;
 139         struct sk_buff *tx_skb;
 140         struct sk_buff *rx_skb;
 141         __u8 *rx_ptr;
 142         int tx_cnt;
 143         int bchan;
 144         int mode;
 145 };
 146
 147 struct _hfc4s8s_hw;
 148
 149 struct hfc4s8s_l1 {
 150         spinlock_t lock;
 151         struct _hfc4s8s_hw *hw; /* pointer to hardware area */
 152         int l1_state;           /* actual l1 state */
 153         struct timer_list l1_timer;     /* layer 1 timer structure */
 154         int nt_mode;            /* set to nt mode */
 155         int st_num;             /* own index */
 156         int enabled;            /* interface is enabled */
 157         struct sk_buff_head d_tx_queue; /* send queue */
 158         int tx_cnt;             /* bytes to send */
 159         struct hisax_d_if d_if; /* D-channel interface */
 160         struct hfc4s8s_btype b_ch[2];   /* B-channel data */
 161         struct hisax_b_if *b_table[2];
 162 };
 163
 164 /**********************/
 165 /* hardware structure */
 166 /**********************/
 167 typedef struct _hfc4s8s_hw {
 168         spinlock_t lock;
 169
 170         int cardnum;
 171         int ifnum;
 172         int iobase;
 173         int nt_mode;
 174         u_char *membase;
 175         u_char *hw_membase;
 176         void *pdev;
 177         int max_fifo;
 178         hfc4s8s_param driver_data;
 179         int irq;
 180         int fifo_sched_cnt;
 181         struct work_struct tqueue;
 182         struct hfc4s8s_l1 l1[HFC_MAX_ST];
 183         char card_name[60];
 184         struct {
 185                 u_char r_irq_ctrl;
 186                 u_char r_ctrl0;
 187                 volatile u_char r_irq_statech;  /* active isdn l1 status */
 188                 u_char r_irqmsk_statchg;        /* enabled isdn status ints */
 189                 u_char r_irq_fifo_blx[8];       /* fifo status registers */
 190                 u_char fifo_rx_trans_enables[8];        /* mask for enabled transparent rx fifos */
 191                 u_char fifo_slow_timer_service[8];      /* mask for fifos needing slower timer service */
 192                 volatile u_char r_irq_oview;    /* contents of overview register */
 193                 volatile u_char timer_irq;
 194                 int timer_usg_cnt;      /* number of channels using timer */
 195         } mr;
 196 } hfc4s8s_hw;
 197
 198
 199
 200 /* inline functions io mapped */
 201 static inline void
 202 SetRegAddr(hfc4s8s_hw *a, u_char b)
 203 {
 204         outb(b, (a->iobase) + 4);
 205 }
 206
 207 static inline u_char
 208 GetRegAddr(hfc4s8s_hw *a)
 209 {
 210         return (inb((volatile u_int) (a->iobase + 4)));
 211 }
 212
 213
 214 static inline void
 215 Write_hfc8(hfc4s8s_hw *a, u_char b, u_char c)
 216 {
 217         SetRegAddr(a, b);
 218         outb(c, a->iobase);
 219 }
 220
 221 static inline void
 222 fWrite_hfc8(hfc4s8s_hw *a, u_char c)
 223 {
 224         outb(c, a->iobase);
 225 }
 226
 227 static inline void
 228 Write_hfc16(hfc4s8s_hw *a, u_char b, u_short c)
 229 {
 230         SetRegAddr(a, b);
 231         outw(c, a->iobase);
 232 }
 233
 234 static inline void
 235 Write_hfc32(hfc4s8s_hw *a, u_char b, u_long c)
 236 {
 237         SetRegAddr(a, b);
 238         outl(c, a->iobase);
 239 }
 240
 241 static inline void
 242 fWrite_hfc32(hfc4s8s_hw *a, u_long c)
 243 {
 244         outl(c, a->iobase);
 245 }
 246
 247 static inline u_char
 248 Read_hfc8(hfc4s8s_hw *a, u_char b)
 249 {
 250         SetRegAddr(a, b);
 251         return (inb((volatile u_int) a->iobase));
 252 }
 253
 254 static inline u_char
 255 fRead_hfc8(hfc4s8s_hw *a)
 256 {
 257         return (inb((volatile u_int) a->iobase));
 258 }
 259
 260
 261 static inline u_short
 262 Read_hfc16(hfc4s8s_hw *a, u_char b)
 263 {
 264         SetRegAddr(a, b);
 265         return (inw((volatile u_int) a->iobase));
 266 }
 267
 268 static inline u_long
 269 Read_hfc32(hfc4s8s_hw *a, u_char b)
 270 {
 271         SetRegAddr(a, b);
 272         return (inl((volatile u_int) a->iobase));
 273 }
 274
 275 static inline u_long
 276 fRead_hfc32(hfc4s8s_hw *a)
 277 {
 278         return (inl((volatile u_int) a->iobase));
 279 }
 280
 281 static inline void
 282 wait_busy(hfc4s8s_hw *a)
 283 {
 284         SetRegAddr(a, R_STATUS);
 285         while (inb((volatile u_int) a->iobase) & M_BUSY);
 286 }
 287
 288 #define PCI_ENA_REGIO   0x01
 289
 290 /******************************************************/
 291 /* function to read critical counter registers that   */
 292 /* may be updated by the chip during read             */
 293 /******************************************************/
 294 static u_char
 295 Read_hfc8_stable(hfc4s8s_hw *hw, int reg)
 296 {
 297         u_char ref8;
 298         u_char in8;
 299         ref8 = Read_hfc8(hw, reg);
 300         while (((in8 = Read_hfc8(hw, reg)) != ref8)) {
 301                 ref8 = in8;
 302         }
 303         return in8;
 304 }
 305
 306 static int
 307 Read_hfc16_stable(hfc4s8s_hw *hw, int reg)
 308 {
 309         int ref16;
 310         int in16;
 311
 312         ref16 = Read_hfc16(hw, reg);
 313         while (((in16 = Read_hfc16(hw, reg)) != ref16)) {
 314                 ref16 = in16;
 315         }
 316         return in16;
 317 }
 318
 319 /*****************************/
 320 /* D-channel call from HiSax */
 321 /*****************************/
 322 static void
 323 dch_l2l1(struct hisax_d_if *iface, int pr, void *arg)
 324 {
 325         struct hfc4s8s_l1 *l1 = iface->ifc.priv;
 326         struct sk_buff *skb = (struct sk_buff *) arg;
 327         u_long flags;
 328
 329         switch (pr) {
 330
 331         case (PH_DATA | REQUEST):
 332                 if (!l1->enabled) {
 333                         dev_kfree_skb(skb);
 334                         break;
 335                 }
 336                 spin_lock_irqsave(&l1->lock, flags);
 337                 skb_queue_tail(&l1->d_tx_queue, skb);
 338                 if ((skb_queue_len(&l1->d_tx_queue) == 1) &&
 339                     (l1->tx_cnt <= 0)) {
 340                         l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
 341                                 0x10;
 342                         spin_unlock_irqrestore(&l1->lock, flags);
 343                         schedule_work(&l1->hw->tqueue);
 344                 } else
 345                         spin_unlock_irqrestore(&l1->lock, flags);
 346                 break;
 347
 348         case (PH_ACTIVATE | REQUEST):
 349                 if (!l1->enabled)
 350                         break;
 351                 if (!l1->nt_mode) {
 352                         if (l1->l1_state < 6) {
 353                                 spin_lock_irqsave(&l1->lock,
 354                                                   flags);
 355
 356                                 Write_hfc8(l1->hw, R_ST_SEL,
 357                                            l1->st_num);
 358                                 Write_hfc8(l1->hw, A_ST_WR_STA,
 359                                            0x60);
 360                                 mod_timer(&l1->l1_timer,
 361                                           jiffies + L1_TIMER_T3);
 362                                 spin_unlock_irqrestore(&l1->lock,
 363                                                        flags);
 364                         } else if (l1->l1_state == 7)
 365                                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 366                                                   PH_ACTIVATE |
 367                                                   INDICATION,
 368                                                   NULL);
 369                 } else {
 370                         if (l1->l1_state != 3) {
 371                                 spin_lock_irqsave(&l1->lock,
 372                                                   flags);
 373                                 Write_hfc8(l1->hw, R_ST_SEL,
 374                                            l1->st_num);
 375                                 Write_hfc8(l1->hw, A_ST_WR_STA,
 376                                            0x60);
 377                                 spin_unlock_irqrestore(&l1->lock,
 378                                                        flags);
 379                         } else if (l1->l1_state == 3)
 380                                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 381                                                   PH_ACTIVATE |
 382                                                   INDICATION,
 383                                                   NULL);
 384                 }
 385                 break;
 386
 387         default:
 388                 printk(KERN_INFO
 389                        "HFC-4S/8S: Unknown D-chan cmd 0x%x received, ignored\n",
 390                        pr);
 391                 break;
 392         }
 393         if (!l1->enabled)
 394                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 395                                   PH_DEACTIVATE | INDICATION, NULL);
 396 }                               /* dch_l2l1 */
 397
 398 /*****************************/
 399 /* B-channel call from HiSax */
 400 /*****************************/
 401 static void
 402 bch_l2l1(struct hisax_if *ifc, int pr, void *arg)
 403 {
 404         struct hfc4s8s_btype *bch = ifc->priv;
 405         struct hfc4s8s_l1 *l1 = bch->l1p;
 406         struct sk_buff *skb = (struct sk_buff *) arg;
 407         long mode = (long) arg;
 408         u_long flags;
 409
 410         switch (pr) {
 411
 412         case (PH_DATA | REQUEST):
 413                 if (!l1->enabled || (bch->mode == L1_MODE_NULL)) {
 414                         dev_kfree_skb(skb);
 415                         break;
 416                 }
 417                 spin_lock_irqsave(&l1->lock, flags);
 418                 skb_queue_tail(&bch->tx_queue, skb);
 419                 if (!bch->tx_skb && (bch->tx_cnt <= 0)) {
 420                         l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
 421                                 ((bch->bchan == 1) ? 1 : 4);
 422                         spin_unlock_irqrestore(&l1->lock, flags);
 423                         schedule_work(&l1->hw->tqueue);
 424                 } else
 425                         spin_unlock_irqrestore(&l1->lock, flags);
 426                 break;
 427
 428         case (PH_ACTIVATE | REQUEST):
 429         case (PH_DEACTIVATE | REQUEST):
 430                 if (!l1->enabled)
 431                         break;
 432                 if (pr == (PH_DEACTIVATE | REQUEST))
 433                         mode = L1_MODE_NULL;
 434
 435                 switch (mode) {
 436                 case L1_MODE_HDLC:
 437                         spin_lock_irqsave(&l1->lock,
 438                                           flags);
 439                         l1->hw->mr.timer_usg_cnt++;
 440                         l1->hw->mr.
 441                                 fifo_slow_timer_service[l1->
 442                                                         st_num]
 443                                 |=
 444                                 ((bch->bchan ==
 445                                   1) ? 0x2 : 0x8);
 446                         Write_hfc8(l1->hw, R_FIFO,
 447                                    (l1->st_num * 8 +
 448                                     ((bch->bchan ==
 449                                       1) ? 0 : 2)));
 450                         wait_busy(l1->hw);
 451                         Write_hfc8(l1->hw, A_CON_HDLC, 0xc);    /* HDLC mode, flag fill, connect ST */
 452                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 453                         Write_hfc8(l1->hw, A_IRQ_MSK, 1);       /* enable TX interrupts for hdlc */
 454                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 455                         wait_busy(l1->hw);
 456
 457                         Write_hfc8(l1->hw, R_FIFO,
 458                                    (l1->st_num * 8 +
 459                                     ((bch->bchan ==
 460                                       1) ? 1 : 3)));
 461                         wait_busy(l1->hw);
 462                         Write_hfc8(l1->hw, A_CON_HDLC, 0xc);    /* HDLC mode, flag fill, connect ST */
 463                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 464                         Write_hfc8(l1->hw, A_IRQ_MSK, 1);       /* enable RX interrupts for hdlc */
 465                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 466
 467                         Write_hfc8(l1->hw, R_ST_SEL,
 468                                    l1->st_num);
 469                         l1->hw->mr.r_ctrl0 |=
 470                                 (bch->bchan & 3);
 471                         Write_hfc8(l1->hw, A_ST_CTRL0,
 472                                    l1->hw->mr.r_ctrl0);
 473                         bch->mode = L1_MODE_HDLC;
 474                         spin_unlock_irqrestore(&l1->lock,
 475                                                flags);
 476
 477                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 478                                            PH_ACTIVATE |
 479                                            INDICATION,
 480                                            NULL);
 481                         break;
 482
 483                 case L1_MODE_TRANS:
 484                         spin_lock_irqsave(&l1->lock,
 485                                           flags);
 486                         l1->hw->mr.
 487                                 fifo_rx_trans_enables[l1->
 488                                                       st_num]
 489                                 |=
 490                                 ((bch->bchan ==
 491                                   1) ? 0x2 : 0x8);
 492                         l1->hw->mr.timer_usg_cnt++;
 493                         Write_hfc8(l1->hw, R_FIFO,
 494                                    (l1->st_num * 8 +
 495                                     ((bch->bchan ==
 496                                       1) ? 0 : 2)));
 497                         wait_busy(l1->hw);
 498                         Write_hfc8(l1->hw, A_CON_HDLC, 0xf);    /* Transparent mode, 1 fill, connect ST */
 499                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 500                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable TX interrupts */
 501                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 502                         wait_busy(l1->hw);
 503
 504                         Write_hfc8(l1->hw, R_FIFO,
 505                                    (l1->st_num * 8 +
 506                                     ((bch->bchan ==
 507                                       1) ? 1 : 3)));
 508                         wait_busy(l1->hw);
 509                         Write_hfc8(l1->hw, A_CON_HDLC, 0xf);    /* Transparent mode, 1 fill, connect ST */
 510                         Write_hfc8(l1->hw, A_SUBCH_CFG, 0);     /* 8 bits */
 511                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable RX interrupts */
 512                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 513
 514                         Write_hfc8(l1->hw, R_ST_SEL,
 515                                    l1->st_num);
 516                         l1->hw->mr.r_ctrl0 |=
 517                                 (bch->bchan & 3);
 518                         Write_hfc8(l1->hw, A_ST_CTRL0,
 519                                    l1->hw->mr.r_ctrl0);
 520                         bch->mode = L1_MODE_TRANS;
 521                         spin_unlock_irqrestore(&l1->lock,
 522                                                flags);
 523
 524                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 525                                            PH_ACTIVATE |
 526                                            INDICATION,
 527                                            NULL);
 528                         break;
 529
 530                 default:
 531                         if (bch->mode == L1_MODE_NULL)
 532                                 break;
 533                         spin_lock_irqsave(&l1->lock,
 534                                           flags);
 535                         l1->hw->mr.
 536                                 fifo_slow_timer_service[l1->
 537                                                         st_num]
 538                                 &=
 539                                 ~((bch->bchan ==
 540                                    1) ? 0x3 : 0xc);
 541                         l1->hw->mr.
 542                                 fifo_rx_trans_enables[l1->
 543                                                       st_num]
 544                                 &=
 545                                 ~((bch->bchan ==
 546                                    1) ? 0x3 : 0xc);
 547                         l1->hw->mr.timer_usg_cnt--;
 548                         Write_hfc8(l1->hw, R_FIFO,
 549                                    (l1->st_num * 8 +
 550                                     ((bch->bchan ==
 551                                       1) ? 0 : 2)));
 552                         wait_busy(l1->hw);
 553                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable TX interrupts */
 554                         wait_busy(l1->hw);
 555                         Write_hfc8(l1->hw, R_FIFO,
 556                                    (l1->st_num * 8 +
 557                                     ((bch->bchan ==
 558                                       1) ? 1 : 3)));
 559                         wait_busy(l1->hw);
 560                         Write_hfc8(l1->hw, A_IRQ_MSK, 0);       /* disable RX interrupts */
 561                         Write_hfc8(l1->hw, R_ST_SEL,
 562                                    l1->st_num);
 563                         l1->hw->mr.r_ctrl0 &=
 564                                 ~(bch->bchan & 3);
 565                         Write_hfc8(l1->hw, A_ST_CTRL0,
 566                                    l1->hw->mr.r_ctrl0);
 567                         spin_unlock_irqrestore(&l1->lock,
 568                                                flags);
 569
 570                         bch->mode = L1_MODE_NULL;
 571                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 572                                            PH_DEACTIVATE |
 573                                            INDICATION,
 574                                            NULL);
 575                         if (bch->tx_skb) {
 576                                 dev_kfree_skb(bch->tx_skb);
 577                                 bch->tx_skb = NULL;
 578                         }
 579                         if (bch->rx_skb) {
 580                                 dev_kfree_skb(bch->rx_skb);
 581                                 bch->rx_skb = NULL;
 582                         }
 583                         skb_queue_purge(&bch->tx_queue);
 584                         bch->tx_cnt = 0;
 585                         bch->rx_ptr = NULL;
 586                         break;
 587                 }
 588
 589                 /* timer is only used when at least one b channel */
 590                 /* is set up to transparent mode */
 591                 if (l1->hw->mr.timer_usg_cnt) {
 592                         Write_hfc8(l1->hw, R_IRQMSK_MISC,
 593                                    M_TI_IRQMSK);
 594                 } else {
 595                         Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
 596                 }
 597
 598                 break;
 599
 600         default:
 601                 printk(KERN_INFO
 602                        "HFC-4S/8S: Unknown B-chan cmd 0x%x received, ignored\n",
 603                        pr);
 604                 break;
 605         }
 606         if (!l1->enabled)
 607                 bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 608                                    PH_DEACTIVATE | INDICATION, NULL);
 609 }                               /* bch_l2l1 */
 610
 611 /**************************/
 612 /* layer 1 timer function */
 613 /**************************/
 614 static void
 615 hfc_l1_timer(struct hfc4s8s_l1 *l1)
 616 {
 617         u_long flags;
 618
 619         if (!l1->enabled)
 620                 return;
 621
 622         spin_lock_irqsave(&l1->lock, flags);
 623         if (l1->nt_mode) {
 624                 l1->l1_state = 1;
 625                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 626                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11);
 627                 spin_unlock_irqrestore(&l1->lock, flags);
 628                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 629                                   PH_DEACTIVATE | INDICATION, NULL);
 630                 spin_lock_irqsave(&l1->lock, flags);
 631                 l1->l1_state = 1;
 632                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1);
 633                 spin_unlock_irqrestore(&l1->lock, flags);
 634         } else {
 635                 /* activation timed out */
 636                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 637                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13);
 638                 spin_unlock_irqrestore(&l1->lock, flags);
 639                 l1->d_if.ifc.l1l2(&l1->d_if.ifc,
 640                                   PH_DEACTIVATE | INDICATION, NULL);
 641                 spin_lock_irqsave(&l1->lock, flags);
 642                 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
 643                 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3);
 644                 spin_unlock_irqrestore(&l1->lock, flags);
 645         }
 646 }                               /* hfc_l1_timer */
 647
 648 /****************************************/
 649 /* a complete D-frame has been received */
 650 /****************************************/
 651 static void
 652 rx_d_frame(struct hfc4s8s_l1 *l1p, int ech)
 653 {
 654         int z1, z2;
 655         u_char f1, f2, df;
 656         struct sk_buff *skb;
 657         u_char *cp;
 658
 659
 660         if (!l1p->enabled)
 661                 return;
 662         do {
 663                 /* E/D RX fifo */
 664                 Write_hfc8(l1p->hw, R_FIFO,
 665                            (l1p->st_num * 8 + ((ech) ? 7 : 5)));
 666                 wait_busy(l1p->hw);
 667
 668                 f1 = Read_hfc8_stable(l1p->hw, A_F1);
 669                 f2 = Read_hfc8(l1p->hw, A_F2);
 670                 df = f1 - f2;
 671                 if ((f1 - f2) < 0)
 672                         df = f1 - f2 + MAX_F_CNT + 1;
 673
 674
 675                 if (!df) {
 676                         return; /* no complete frame in fifo */
 677                 }
 678
 679                 z1 = Read_hfc16_stable(l1p->hw, A_Z1);
 680                 z2 = Read_hfc16(l1p->hw, A_Z2);
 681
 682                 z1 = z1 - z2 + 1;
 683                 if (z1 < 0)
 684                         z1 += 384;
 685
 686                 if (!(skb = dev_alloc_skb(MAX_D_FRAME_SIZE))) {
 687                         printk(KERN_INFO
 688                                "HFC-4S/8S: Could not allocate D/E "
 689                                "channel receive buffer");
 690                         Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
 691                         wait_busy(l1p->hw);
 692                         return;
 693                 }
 694
 695                 if (((z1 < 4) || (z1 > MAX_D_FRAME_SIZE))) {
 696                         if (skb)
 697                                 dev_kfree_skb(skb);
 698                         /* remove errornous D frame */
 699                         if (df == 1) {
 700                                 /* reset fifo */
 701                                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
 702                                 wait_busy(l1p->hw);
 703                                 return;
 704                         } else {
 705                                 /* read errornous D frame */
 706                                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 707
 708                                 while (z1 >= 4) {
 709                                         fRead_hfc32(l1p->hw);
 710                                         z1 -= 4;
 711                                 }
 712
 713                                 while (z1--)
 714                                         fRead_hfc8(l1p->hw);
 715
 716                                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
 717                                 wait_busy(l1p->hw);
 718                                 return;
 719                         }
 720                 }
 721
 722                 cp = skb->data;
 723
 724                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 725
 726                 while (z1 >= 4) {
 727                         *((unsigned long *) cp) = fRead_hfc32(l1p->hw);
 728                         cp += 4;
 729                         z1 -= 4;
 730                 }
 731
 732                 while (z1--)
 733                         *cp++ = fRead_hfc8(l1p->hw);
 734
 735                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
 736                 wait_busy(l1p->hw);
 737
 738                 if (*(--cp)) {
 739                         dev_kfree_skb(skb);
 740                 } else {
 741                         skb->len = (cp - skb->data) - 2;
 742                         if (ech)
 743                                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
 744                                                    PH_DATA_E | INDICATION,
 745                                                    skb);
 746                         else
 747                                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc,
 748                                                    PH_DATA | INDICATION,
 749                                                    skb);
 750                 }
 751         } while (1);
 752 }                               /* rx_d_frame */
 753
 754 /*************************************************************/
 755 /* a B-frame has been received (perhaps not fully completed) */
 756 /*************************************************************/
 757 static void
 758 rx_b_frame(struct hfc4s8s_btype *bch)
 759 {
 760         int z1, z2, hdlc_complete;
 761         u_char f1, f2;
 762         struct hfc4s8s_l1 *l1 = bch->l1p;
 763         struct sk_buff *skb;
 764
 765         if (!l1->enabled || (bch->mode == L1_MODE_NULL))
 766                 return;
 767
 768         do {
 769                 /* RX Fifo */
 770                 Write_hfc8(l1->hw, R_FIFO,
 771                            (l1->st_num * 8 + ((bch->bchan == 1) ? 1 : 3)));
 772                 wait_busy(l1->hw);
 773
 774                 if (bch->mode == L1_MODE_HDLC) {
 775                         f1 = Read_hfc8_stable(l1->hw, A_F1);
 776                         f2 = Read_hfc8(l1->hw, A_F2);
 777                         hdlc_complete = ((f1 ^ f2) & MAX_F_CNT);
 778                 } else
 779                         hdlc_complete = 0;
 780                 z1 = Read_hfc16_stable(l1->hw, A_Z1);
 781                 z2 = Read_hfc16(l1->hw, A_Z2);
 782                 z1 = (z1 - z2);
 783                 if (hdlc_complete)
 784                         z1++;
 785                 if (z1 < 0)
 786                         z1 += 384;
 787
 788                 if (!z1)
 789                         break;
 790
 791                 if (!(skb = bch->rx_skb)) {
 792                         if (!
 793                             (skb =
 794                              dev_alloc_skb((bch->mode ==
 795                                             L1_MODE_TRANS) ? z1
 796                                            : (MAX_B_FRAME_SIZE + 3)))) {
 797                                 printk(KERN_ERR
 798                                        "HFC-4S/8S: Could not allocate B "
 799                                        "channel receive buffer");
 800                                 return;
 801                         }
 802                         bch->rx_ptr = skb->data;
 803                         bch->rx_skb = skb;
 804                 }
 805
 806                 skb->len = (bch->rx_ptr - skb->data) + z1;
 807
 808                 /* HDLC length check */
 809                 if ((bch->mode == L1_MODE_HDLC) &&
 810                     ((hdlc_complete && (skb->len < 4)) ||
 811                      (skb->len > (MAX_B_FRAME_SIZE + 3)))) {
 812
 813                         skb->len = 0;
 814                         bch->rx_ptr = skb->data;
 815                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 2);  /* reset fifo */
 816                         wait_busy(l1->hw);
 817                         return;
 818                 }
 819                 SetRegAddr(l1->hw, A_FIFO_DATA0);
 820
 821                 while (z1 >= 4) {
 822                         *((unsigned long *) bch->rx_ptr) =
 823                                 fRead_hfc32(l1->hw);
 824                         bch->rx_ptr += 4;
 825                         z1 -= 4;
 826                 }
 827
 828                 while (z1--)
 829                         *(bch->rx_ptr++) = fRead_hfc8(l1->hw);
 830
 831                 if (hdlc_complete) {
 832                         /* increment f counter */
 833                         Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
 834                         wait_busy(l1->hw);
 835
 836                         /* hdlc crc check */
 837                         bch->rx_ptr--;
 838                         if (*bch->rx_ptr) {
 839                                 skb->len = 0;
 840                                 bch->rx_ptr = skb->data;
 841                                 continue;
 842                         }
 843                         skb->len -= 3;
 844                 }
 845                 if (hdlc_complete || (bch->mode == L1_MODE_TRANS)) {
 846                         bch->rx_skb = NULL;
 847                         bch->rx_ptr = NULL;
 848                         bch->b_if.ifc.l1l2(&bch->b_if.ifc,
 849                                            PH_DATA | INDICATION, skb);
 850                 }
 851
 852         } while (1);
 853 }                               /* rx_b_frame */
 854
 855 /********************************************/
 856 /* a D-frame has been/should be transmitted */
 857 /********************************************/
 858 static void
 859 tx_d_frame(struct hfc4s8s_l1 *l1p)
 860 {
 861         struct sk_buff *skb;
 862         u_char f1, f2;
 863         u_char *cp;
 864         long cnt;
 865
 866         if (l1p->l1_state != 7)
 867                 return;
 868
 869         /* TX fifo */
 870         Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4));
 871         wait_busy(l1p->hw);
 872
 873         f1 = Read_hfc8(l1p->hw, A_F1);
 874         f2 = Read_hfc8_stable(l1p->hw, A_F2);
 875
 876         if ((f1 ^ f2) & MAX_F_CNT)
 877                 return;         /* fifo is still filled */
 878
 879         if (l1p->tx_cnt > 0) {
 880                 cnt = l1p->tx_cnt;
 881                 l1p->tx_cnt = 0;
 882                 l1p->d_if.ifc.l1l2(&l1p->d_if.ifc, PH_DATA | CONFIRM,
 883                                    (void *) cnt);
 884         }
 885
 886         if ((skb = skb_dequeue(&l1p->d_tx_queue))) {
 887                 cp = skb->data;
 888                 cnt = skb->len;
 889                 SetRegAddr(l1p->hw, A_FIFO_DATA0);
 890
 891                 while (cnt >= 4) {
 892                         SetRegAddr(l1p->hw, A_FIFO_DATA0);
 893                         fWrite_hfc32(l1p->hw, *(unsigned long *) cp);
 894                         cp += 4;
 895                         cnt -= 4;
 896                 }
 897
 898                 while (cnt--)
 899                         fWrite_hfc8(l1p->hw, *cp++);
 900
 901                 l1p->tx_cnt = skb->truesize;
 902                 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
 903                 wait_busy(l1p->hw);
 904
 905                 dev_kfree_skb(skb);
 906         }
 907 }                               /* tx_d_frame */
 908
 909 /******************************************************/
 910 /* a B-frame may be transmitted (or is not completed) */
 911 /******************************************************/
 912 static void
 913 tx_b_frame(struct hfc4s8s_btype *bch)
 914 {
 915         struct sk_buff *skb;
 916         struct hfc4s8s_l1 *l1 = bch->l1p;
 917         u_char *cp;
 918         int cnt, max, hdlc_num;
 919         long ack_len = 0;
 920
 921         if (!l1->enabled || (bch->mode == L1_MODE_NULL))
 922                 return;
 923
 924         /* TX fifo */
 925         Write_hfc8(l1->hw, R_FIFO,
 926                    (l1->st_num * 8 + ((bch->bchan == 1) ? 0 : 2)));
 927         wait_busy(l1->hw);
 928         do {
 929
 930                 if (bch->mode == L1_MODE_HDLC) {
 931                         hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
 932                         hdlc_num -=
 933                                 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
 934                         if (hdlc_num < 0)
 935                                 hdlc_num += 16;
 936                         if (hdlc_num >= 15)
 937                                 break;  /* fifo still filled up with hdlc frames */
 938                 } else
 939                         hdlc_num = 0;
 940
 941                 if (!(skb = bch->tx_skb)) {
 942                         if (!(skb = skb_dequeue(&bch->tx_queue))) {
 943                                 l1->hw->mr.fifo_slow_timer_service[l1->
 944                                                                    st_num]
 945                                         &= ~((bch->bchan == 1) ? 1 : 4);
 946                                 break;  /* list empty */
 947                         }
 948                         bch->tx_skb = skb;
 949                         bch->tx_cnt = 0;
 950                 }
 951
 952                 if (!hdlc_num)
 953                         l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
 954                                 ((bch->bchan == 1) ? 1 : 4);
 955                 else
 956                         l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
 957                                 ~((bch->bchan == 1) ? 1 : 4);
 958
 959                 max = Read_hfc16_stable(l1->hw, A_Z2);
 960                 max -= Read_hfc16(l1->hw, A_Z1);
 961                 if (max <= 0)
 962                         max += 384;
 963                 max--;
 964
 965                 if (max < 16)
 966                         break;  /* don't write to small amounts of bytes */
 967
 968                 cnt = skb->len - bch->tx_cnt;
 969                 if (cnt > max)
 970                         cnt = max;
 971                 cp = skb->data + bch->tx_cnt;
 972                 bch->tx_cnt += cnt;
 973
 974                 SetRegAddr(l1->hw, A_FIFO_DATA0);
 975                 while (cnt >= 4) {
 976                         fWrite_hfc32(l1->hw, *(unsigned long *) cp);
 977                         cp += 4;
 978                         cnt -= 4;
 979                 }
 980
 981                 while (cnt--)
 982                         fWrite_hfc8(l1->hw, *cp++);
 983
 984                 if (bch->tx_cnt >= skb->len) {
 985                         if (bch->mode == L1_MODE_HDLC) {
 986                                 /* increment f counter */
 987                                 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
 988                         }
 989                         ack_len += skb->truesize;
 990                         bch->tx_skb = NULL;
 991                         bch->tx_cnt = 0;
 992                         dev_kfree_skb(skb);
 993                 } else
 994                         /* Re-Select */
 995                         Write_hfc8(l1->hw, R_FIFO,
 996                                    (l1->st_num * 8 +
 997                                     ((bch->bchan == 1) ? 0 : 2)));
 998                 wait_busy(l1->hw);
 999         } while (1);
1000
1001         if (ack_len)
1002                 bch->b_if.ifc.l1l2((struct hisax_if *) &bch->b_if,
1003                                    PH_DATA | CONFIRM, (void *) ack_len);
1004 }                               /* tx_b_frame */
1005
1006 /*************************************/
1007 /* bottom half handler for interrupt */
1008 /*************************************/
1009 static void
1010 hfc4s8s_bh(struct work_struct *work)
1011 {
1012         hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue);
1013         u_char b;
1014         struct hfc4s8s_l1 *l1p;
1015         volatile u_char *fifo_stat;
1016         int idx;
1017
1018         /* handle layer 1 state changes */
1019         b = 1;
1020         l1p = hw->l1;
1021         while (b) {
1022                 if ((b & hw->mr.r_irq_statech)) {
1023                         /* reset l1 event */
1024                         hw->mr.r_irq_statech &= ~b;
1025                         if (l1p->enabled) {
1026                                 if (l1p->nt_mode) {
1027                                         u_char oldstate = l1p->l1_state;
1028
1029                                         Write_hfc8(l1p->hw, R_ST_SEL,
1030                                                    l1p->st_num);
1031                                         l1p->l1_state =
1032                                                 Read_hfc8(l1p->hw,
1033                                                           A_ST_RD_STA) & 0xf;
1034
1035                                         if ((oldstate == 3)
1036                                             && (l1p->l1_state != 3))
1037                                                 l1p->d_if.ifc.l1l2(&l1p->
1038                                                                    d_if.
1039                                                                    ifc,
1040                                                                    PH_DEACTIVATE
1041                                                                    |
1042                                                                    INDICATION,
1043                                                                    NULL);
1044
1045                                         if (l1p->l1_state != 2) {
1046                                                 del_timer(&l1p->l1_timer);
1047                                                 if (l1p->l1_state == 3) {
1048                                                         l1p->d_if.ifc.
1049                                                                 l1l2(&l1p->
1050                                                                      d_if.ifc,
1051                                                                      PH_ACTIVATE
1052                                                                      |
1053                                                                      INDICATION,
1054                                                                      NULL);
1055                                                 }
1056                                         } else {
1057                                                 /* allow transition */
1058                                                 Write_hfc8(hw, A_ST_WR_STA,
1059                                                            M_SET_G2_G3);
1060                                                 mod_timer(&l1p->l1_timer,
1061                                                           jiffies +
1062                                                           L1_TIMER_T1);
1063                                         }
1064                                         printk(KERN_INFO
1065                                                "HFC-4S/8S: NT ch %d l1 state %d -> %d\n",
1066                                                l1p->st_num, oldstate,
1067                                                l1p->l1_state);
1068                                 } else {
1069                                         u_char oldstate = l1p->l1_state;
1070
1071                                         Write_hfc8(l1p->hw, R_ST_SEL,
1072                                                    l1p->st_num);
1073                                         l1p->l1_state =
1074                                                 Read_hfc8(l1p->hw,
1075                                                           A_ST_RD_STA) & 0xf;
1076
1077                                         if (((l1p->l1_state == 3) &&
1078                                              ((oldstate == 7) ||
1079                                               (oldstate == 8))) ||
1080                                             ((timer_pending
1081                                               (&l1p->l1_timer))
1082                                              && (l1p->l1_state == 8))) {
1083                                                 mod_timer(&l1p->l1_timer,
1084                                                           L1_TIMER_T4 +
1085                                                           jiffies);
1086                                         } else {
1087                                                 if (l1p->l1_state == 7) {
1088                                                         del_timer(&l1p->
1089                                                                   l1_timer);
1090                                                         l1p->d_if.ifc.
1091                                                                 l1l2(&l1p->
1092                                                                      d_if.ifc,
1093                                                                      PH_ACTIVATE
1094                                                                      |
1095                                                                      INDICATION,
1096                                                                      NULL);
1097                                                         tx_d_frame(l1p);
1098                                                 }
1099                                                 if (l1p->l1_state == 3) {
1100                                                         if (oldstate != 3)
1101                                                                 l1p->d_if.
1102                                                                         ifc.
1103                                                                         l1l2
1104                                                                         (&l1p->
1105                                                                          d_if.
1106                                                                          ifc,
1107                                                                          PH_DEACTIVATE
1108                                                                          |
1109                                                                          INDICATION,
1110                                                                          NULL);
1111                                                 }
1112                                         }
1113                                         printk(KERN_INFO
1114                                                "HFC-4S/8S: TE %d ch %d l1 state %d -> %d\n",
1115                                                l1p->hw->cardnum,
1116                                                l1p->st_num, oldstate,
1117                                                l1p->l1_state);
1118                                 }
1119                         }
1120                 }
1121                 b <<= 1;
1122                 l1p++;
1123         }
1124
1125         /* now handle the fifos */
1126         idx = 0;
1127         fifo_stat = hw->mr.r_irq_fifo_blx;
1128         l1p = hw->l1;
1129         while (idx < hw->driver_data.max_st_ports) {
1130
1131                 if (hw->mr.timer_irq) {
1132                         *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
1133                         if (hw->fifo_sched_cnt <= 0) {
1134                                 *fifo_stat |=
1135                                         hw->mr.fifo_slow_timer_service[l1p->
1136                                                                        st_num];
1137                         }
1138                 }
1139                 /* ignore fifo 6 (TX E fifo) */
1140                 *fifo_stat &= 0xff - 0x40;
1141
1142                 while (*fifo_stat) {
1143
1144                         if (!l1p->nt_mode) {
1145                                 /* RX Fifo has data to read */
1146                                 if ((*fifo_stat & 0x20)) {
1147                                         *fifo_stat &= ~0x20;
1148                                         rx_d_frame(l1p, 0);
1149                                 }
1150                                 /* E Fifo has data to read */
1151                                 if ((*fifo_stat & 0x80)) {
1152                                         *fifo_stat &= ~0x80;
1153                                         rx_d_frame(l1p, 1);
1154                                 }
1155                                 /* TX Fifo completed send */
1156                                 if ((*fifo_stat & 0x10)) {
1157                                         *fifo_stat &= ~0x10;
1158                                         tx_d_frame(l1p);
1159                                 }
1160                         }
1161                         /* B1 RX Fifo has data to read */
1162                         if ((*fifo_stat & 0x2)) {
1163                                 *fifo_stat &= ~0x2;
1164                                 rx_b_frame(l1p->b_ch);
1165                         }
1166                         /* B1 TX Fifo has send completed */
1167                         if ((*fifo_stat & 0x1)) {
1168                                 *fifo_stat &= ~0x1;
1169                                 tx_b_frame(l1p->b_ch);
1170                         }
1171                         /* B2 RX Fifo has data to read */
1172                         if ((*fifo_stat & 0x8)) {
1173                                 *fifo_stat &= ~0x8;
1174                                 rx_b_frame(l1p->b_ch + 1);
1175                         }
1176                         /* B2 TX Fifo has send completed */
1177                         if ((*fifo_stat & 0x4)) {
1178                                 *fifo_stat &= ~0x4;
1179                                 tx_b_frame(l1p->b_ch + 1);
1180                         }
1181                 }
1182                 fifo_stat++;
1183                 l1p++;
1184                 idx++;
1185         }
1186
1187         if (hw->fifo_sched_cnt <= 0)
1188                 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE));
1189         hw->mr.timer_irq = 0;   /* clear requested timer irq */
1190 }                               /* hfc4s8s_bh */
1191
1192 /*********************/
1193 /* interrupt handler */
1194 /*********************/
1195 static irqreturn_t
1196 hfc4s8s_interrupt(int intno, void *dev_id)
1197 {
1198         hfc4s8s_hw *hw = dev_id;
1199         u_char b, ovr;
1200         volatile u_char *ovp;
1201         int idx;
1202         u_char old_ioreg;
1203
1204         if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN))
1205                 return IRQ_NONE;
1206
1207         /* read current selected regsister */
1208         old_ioreg = GetRegAddr(hw);
1209
1210         /* Layer 1 State change */
1211         hw->mr.r_irq_statech |=
1212                 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
1213         if (!
1214             (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
1215             && !hw->mr.r_irq_statech) {
1216                 SetRegAddr(hw, old_ioreg);
1217                 return IRQ_NONE;
1218         }
1219
1220         /* timer event */
1221         if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) {
1222                 hw->mr.timer_irq = 1;
1223                 hw->fifo_sched_cnt--;
1224         }
1225
1226         /* FIFO event */
1227         if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) {
1228                 hw->mr.r_irq_oview |= ovr;
1229                 idx = R_IRQ_FIFO_BL0;
1230                 ovp = hw->mr.r_irq_fifo_blx;
1231                 while (ovr) {
1232                         if ((ovr & 1)) {
1233                                 *ovp |= Read_hfc8(hw, idx);
1234                         }
1235                         ovp++;
1236                         idx++;
1237                         ovr >>= 1;
1238                 }
1239         }
1240
1241         /* queue the request to allow other cards to interrupt */
1242         schedule_work(&hw->tqueue);
1243
1244         SetRegAddr(hw, old_ioreg);
1245         return IRQ_HANDLED;
1246 }                               /* hfc4s8s_interrupt */
1247
1248 /***********************************************************************/
1249 /* reset the complete chip, don't release the chips irq but disable it */
1250 /***********************************************************************/
1251 static void
1252 chipreset(hfc4s8s_hw *hw)
1253 {
1254         u_long flags;
1255
1256         spin_lock_irqsave(&hw->lock, flags);
1257         Write_hfc8(hw, R_CTRL, 0);      /* use internal RAM */
1258         Write_hfc8(hw, R_RAM_MISC, 0);  /* 32k*8 RAM */
1259         Write_hfc8(hw, R_FIFO_MD, 0);   /* fifo mode 386 byte/fifo simple mode */
1260         Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */
1261         hw->mr.r_irq_ctrl = 0;  /* interrupt is inactive */
1262         spin_unlock_irqrestore(&hw->lock, flags);
1263
1264         udelay(3);
1265         Write_hfc8(hw, R_CIRM, 0);      /* disable reset */
1266         wait_busy(hw);
1267
1268         Write_hfc8(hw, R_PCM_MD0, M_PCM_MD);    /* master mode */
1269         Write_hfc8(hw, R_RAM_MISC, M_FZ_MD);    /* transmit fifo option */
1270         if (hw->driver_data.clock_mode == 1)
1271                 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK);       /* PCM clk / 2 */
1272         Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE);      /* timer interval */
1273
1274         memset(&hw->mr, 0, sizeof(hw->mr));
1275 }                               /* chipreset */
1276
1277 /********************************************/
1278 /* disable/enable hardware in nt or te mode */
1279 /********************************************/
1280 static void
1281 hfc_hardware_enable(hfc4s8s_hw *hw, int enable, int nt_mode)
1282 {
1283         u_long flags;
1284         char if_name[40];
1285         int i;
1286
1287         if (enable) {
1288                 /* save system vars */
1289                 hw->nt_mode = nt_mode;
1290
1291                 /* enable fifo and state irqs, but not global irq enable */
1292                 hw->mr.r_irq_ctrl = M_FIFO_IRQ;
1293                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1294                 hw->mr.r_irqmsk_statchg = 0;
1295                 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1296                 Write_hfc8(hw, R_PWM_MD, 0x80);
1297                 Write_hfc8(hw, R_PWM1, 26);
1298                 if (!nt_mode)
1299                         Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC);
1300
1301                 /* enable the line interfaces and fifos */
1302                 for (i = 0; i < hw->driver_data.max_st_ports; i++) {
1303                         hw->mr.r_irqmsk_statchg |= (1 << i);
1304                         Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1305                         Write_hfc8(hw, R_ST_SEL, i);
1306                         Write_hfc8(hw, A_ST_CLK_DLY,
1307                                    ((nt_mode) ? CLKDEL_NT : CLKDEL_TE));
1308                         hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE);
1309                         Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0);
1310                         Write_hfc8(hw, A_ST_CTRL2, 3);
1311                         Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */
1312
1313                         hw->l1[i].enabled = 1;
1314                         hw->l1[i].nt_mode = nt_mode;
1315
1316                         if (!nt_mode) {
1317                                 /* setup E-fifo */
1318                                 Write_hfc8(hw, R_FIFO, i * 8 + 7);      /* E fifo */
1319                                 wait_busy(hw);
1320                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1321                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1322                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1323                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1324                                 wait_busy(hw);
1325
1326                                 /* setup D RX-fifo */
1327                                 Write_hfc8(hw, R_FIFO, i * 8 + 5);      /* RX fifo */
1328                                 wait_busy(hw);
1329                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1330                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1331                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1332                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1333                                 wait_busy(hw);
1334
1335                                 /* setup D TX-fifo */
1336                                 Write_hfc8(hw, R_FIFO, i * 8 + 4);      /* TX fifo */
1337                                 wait_busy(hw);
1338                                 Write_hfc8(hw, A_CON_HDLC, 0x11);       /* HDLC mode, 1 fill, connect ST */
1339                                 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1340                                 Write_hfc8(hw, A_IRQ_MSK, 1);   /* enable interrupt */
1341                                 Write_hfc8(hw, A_INC_RES_FIFO, 2);      /* reset fifo */
1342                                 wait_busy(hw);
1343                         }
1344
1345                         sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i);
1346
1347                         if (hisax_register
1348                             (&hw->l1[i].d_if, hw->l1[i].b_table, if_name,
1349                              ((nt_mode) ? 3 : 2))) {
1350
1351                                 hw->l1[i].enabled = 0;
1352                                 hw->mr.r_irqmsk_statchg &= ~(1 << i);
1353                                 Write_hfc8(hw, R_SCI_MSK,
1354                                            hw->mr.r_irqmsk_statchg);
1355                                 printk(KERN_INFO
1356                                        "HFC-4S/8S: Unable to register S/T device %s, break\n",
1357                                        if_name);
1358                                 break;
1359                         }
1360                 }
1361                 spin_lock_irqsave(&hw->lock, flags);
1362                 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN;
1363                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1364                 spin_unlock_irqrestore(&hw->lock, flags);
1365         } else {
1366                 /* disable hardware */
1367                 spin_lock_irqsave(&hw->lock, flags);
1368                 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN;
1369                 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1370                 spin_unlock_irqrestore(&hw->lock, flags);
1371
1372                 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) {
1373                         hw->l1[i].enabled = 0;
1374                         hisax_unregister(&hw->l1[i].d_if);
1375                         del_timer(&hw->l1[i].l1_timer);
1376                         skb_queue_purge(&hw->l1[i].d_tx_queue);
1377                         skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue);
1378                         skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue);
1379                 }
1380                 chipreset(hw);
1381         }
1382 }                               /* hfc_hardware_enable */
1383
1384 /******************************************/
1385 /* disable memory mapped ports / io ports */
1386 /******************************************/
1387 static void
1388 release_pci_ports(hfc4s8s_hw *hw)
1389 {
1390         pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
1391         if (hw->iobase)
1392                 release_region(hw->iobase, 8);
1393 }
1394
1395 /*****************************************/
1396 /* enable memory mapped ports / io ports */
1397 /*****************************************/
1398 static void
1399 enable_pci_ports(hfc4s8s_hw *hw)
1400 {
1401         pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO);
1402 }
1403
1404 /*************************************/
1405 /* initialise the HFC-4s/8s hardware */
1406 /* return 0 on success.              */
1407 /*************************************/
1408 static int
1409 setup_instance(hfc4s8s_hw *hw)
1410 {
1411         int err = -EIO;
1412         int i;
1413
1414         for (i = 0; i < HFC_MAX_ST; i++) {
1415                 struct hfc4s8s_l1 *l1p;
1416
1417                 l1p = hw->l1 + i;
1418                 spin_lock_init(&l1p->lock);
1419                 l1p->hw = hw;
1420                 l1p->l1_timer.function = (void *) hfc_l1_timer;
1421                 l1p->l1_timer.data = (long) (l1p);
1422                 init_timer(&l1p->l1_timer);
1423                 l1p->st_num = i;
1424                 skb_queue_head_init(&l1p->d_tx_queue);
1425                 l1p->d_if.ifc.priv = hw->l1 + i;
1426                 l1p->d_if.ifc.l2l1 = (void *) dch_l2l1;
1427
1428                 spin_lock_init(&l1p->b_ch[0].lock);
1429                 l1p->b_ch[0].b_if.ifc.l2l1 = (void *) bch_l2l1;
1430                 l1p->b_ch[0].b_if.ifc.priv = (void *) &l1p->b_ch[0];
1431                 l1p->b_ch[0].l1p = hw->l1 + i;
1432                 l1p->b_ch[0].bchan = 1;
1433                 l1p->b_table[0] = &l1p->b_ch[0].b_if;
1434                 skb_queue_head_init(&l1p->b_ch[0].tx_queue);
1435
1436                 spin_lock_init(&l1p->b_ch[1].lock);
1437                 l1p->b_ch[1].b_if.ifc.l2l1 = (void *) bch_l2l1;
1438                 l1p->b_ch[1].b_if.ifc.priv = (void *) &l1p->b_ch[1];
1439                 l1p->b_ch[1].l1p = hw->l1 + i;
1440                 l1p->b_ch[1].bchan = 2;
1441                 l1p->b_table[1] = &l1p->b_ch[1].b_if;
1442                 skb_queue_head_init(&l1p->b_ch[1].tx_queue);
1443         }
1444
1445         enable_pci_ports(hw);
1446         chipreset(hw);
1447
1448         i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT;
1449         if (i != hw->driver_data.chip_id) {
1450                 printk(KERN_INFO
1451                        "HFC-4S/8S: invalid chip id 0x%x instead of 0x%x, card ignored\n",
1452                        i, hw->driver_data.chip_id);
1453                 goto out;
1454         }
1455
1456         i = Read_hfc8(hw, R_CHIP_RV) & 0xf;
1457         if (!i) {
1458                 printk(KERN_INFO
1459                        "HFC-4S/8S: chip revision 0 not supported, card ignored\n");
1460                 goto out;
1461         }
1462
1463         INIT_WORK(&hw->tqueue, hfc4s8s_bh);
1464
1465         if (request_irq
1466             (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) {
1467                 printk(KERN_INFO
1468                        "HFC-4S/8S: unable to alloc irq %d, card ignored\n",
1469                        hw->irq);
1470                 goto out;
1471         }
1472         printk(KERN_INFO
1473                "HFC-4S/8S: found PCI card at iobase 0x%x, irq %d\n",
1474                hw->iobase, hw->irq);
1475
1476         hfc_hardware_enable(hw, 1, 0);
1477
1478         return (0);
1479
1480 out:
1481         hw->irq = 0;
1482         release_pci_ports(hw);
1483         kfree(hw);
1484         return (err);
1485 }
1486
1487 /*****************************************/
1488 /* PCI hotplug interface: probe new card */
1489 /*****************************************/
1490 static int
1491 hfc4s8s_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1492 {
1493         int err = -ENOMEM;
1494         hfc4s8s_param *driver_data = (hfc4s8s_param *) ent->driver_data;
1495         hfc4s8s_hw *hw;
1496
1497         if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) {
1498                 printk(KERN_ERR "No kmem for HFC-4S/8S card\n");
1499                 return (err);
1500         }
1501
1502         hw->pdev = pdev;
1503         err = pci_enable_device(pdev);
1504
1505         if (err)
1506                 goto out;
1507
1508         hw->cardnum = card_cnt;
1509         sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum);
1510         printk(KERN_INFO "HFC-4S/8S: found adapter %s (%s) at %s\n",
1511                driver_data->device_name, hw->card_name, pci_name(pdev));
1512
1513         spin_lock_init(&hw->lock);
1514
1515         hw->driver_data = *driver_data;
1516         hw->irq = pdev->irq;
1517         hw->iobase = pci_resource_start(pdev, 0);
1518
1519         if (!request_region(hw->iobase, 8, hw->card_name)) {
1520                 printk(KERN_INFO
1521                        "HFC-4S/8S: failed to request address space at 0x%04x\n",
1522                        hw->iobase);
1523                 goto out;
1524         }
1525
1526         pci_set_drvdata(pdev, hw);
1527         err = setup_instance(hw);
1528         if (!err)
1529                 card_cnt++;
1530         return (err);
1531
1532 out:
1533         kfree(hw);
1534         return (err);
1535 }
1536
1537 /**************************************/
1538 /* PCI hotplug interface: remove card */
1539 /**************************************/
1540 static void
1541 hfc4s8s_remove(struct pci_dev *pdev)
1542 {
1543         hfc4s8s_hw *hw = pci_get_drvdata(pdev);
1544
1545         printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum);
1546         hfc_hardware_enable(hw, 0, 0);
1547
1548         if (hw->irq)
1549                 free_irq(hw->irq, hw);
1550         hw->irq = 0;
1551         release_pci_ports(hw);
1552
1553         card_cnt--;
1554         pci_disable_device(pdev);
1555         kfree(hw);
1556         return;
1557 }
1558
1559 static struct pci_driver hfc4s8s_driver = {
1560         .name   = "hfc4s8s_l1",
1561         .probe  = hfc4s8s_probe,
1562         .remove = hfc4s8s_remove,
1563         .id_table       = hfc4s8s_ids,
1564 };
1565
1566 /**********************/
1567 /* driver Module init */
1568 /**********************/
1569 static int __init
1570 hfc4s8s_module_init(void)
1571 {
1572         int err;
1573
1574         printk(KERN_INFO
1575                "HFC-4S/8S: Layer 1 driver module for HFC-4S/8S isdn chips, %s\n",
1576                hfc4s8s_rev);
1577         printk(KERN_INFO
1578                "HFC-4S/8S: (C) 2003 Cornelius Consult, www.cornelius-consult.de\n");
1579
1580         card_cnt = 0;
1581
1582         err = pci_register_driver(&hfc4s8s_driver);
1583         if (err < 0) {
1584                 goto out;
1585         }
1586         printk(KERN_INFO "HFC-4S/8S: found %d cards\n", card_cnt);
1587
1588         return 0;
1589 out:
1590         return (err);
1591 }                               /* hfc4s8s_init_hw */
1592
1593 /*************************************/
1594 /* driver module exit :              */
1595 /* release the HFC-4s/8s hardware    */
1596 /*************************************/
1597 static void __exit
1598 hfc4s8s_module_exit(void)
1599 {
1600         pci_unregister_driver(&hfc4s8s_driver);
1601         printk(KERN_INFO "HFC-4S/8S: module removed\n");
1602 }                               /* hfc4s8s_release_hw */
1603
1604 module_init(hfc4s8s_module_init);
1605 module_exit(hfc4s8s_module_exit);