4 #include "dvb_frontend.h"
6 #define DVBFE_TUNER_OPEN 99
7 #define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100
8 #define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101
10 #define MT2063_ERROR (1 << 31)
11 #define MT2063_USER_ERROR (1 << 30)
13 /* Macro to be used to check for errors */
14 #define MT2063_IS_ERROR(s) (((s) >> 30) != 0)
15 #define MT2063_NO_ERROR(s) (((s) >> 30) == 0)
17 #define MT2063_OK (0x00000000)
20 #define MT2063_UNKNOWN (0x80000001)
22 /* Error: Upconverter PLL is not locked */
23 #define MT2063_UPC_UNLOCK (0x80000002)
25 /* Error: Downconverter PLL is not locked */
26 #define MT2063_DNC_UNLOCK (0x80000004)
28 /* Error: Two-wire serial bus communications error */
29 #define MT2063_COMM_ERR (0x80000008)
31 /* Error: Tuner handle passed to function was invalid */
32 #define MT2063_INV_HANDLE (0x80000010)
34 /* Error: Function argument is invalid (out of range) */
35 #define MT2063_ARG_RANGE (0x80000020)
37 /* Error: Function argument (ptr to return value) was NULL */
38 #define MT2063_ARG_NULL (0x80000040)
40 /* Error: Attempt to open more than MT_TUNER_CNT tuners */
41 #define MT2063_TUNER_CNT_ERR (0x80000080)
43 /* Error: Tuner Part Code / Rev Code mismatches expected value */
44 #define MT2063_TUNER_ID_ERR (0x80000100)
46 /* Error: Tuner Initialization failure */
47 #define MT2063_TUNER_INIT_ERR (0x80000200)
49 #define MT2063_TUNER_OPEN_ERR (0x80000400)
51 /* User-definable fields (see mt_userdef.h) */
52 #define MT2063_USER_DEFINED1 (0x00001000)
53 #define MT2063_USER_DEFINED2 (0x00002000)
54 #define MT2063_USER_DEFINED3 (0x00004000)
55 #define MT2063_USER_DEFINED4 (0x00008000)
56 #define MT2063_USER_MASK (0x4000f000)
57 #define MT2063_USER_SHIFT (12)
59 /* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
60 #define MT2063_SPUR_CNT_MASK (0x001f0000)
61 #define MT2063_SPUR_SHIFT (16)
63 /* Info: Tuner timeout waiting for condition */
64 #define MT2063_TUNER_TIMEOUT (0x00400000)
66 /* Info: Unavoidable LO-related spur may be present in the output */
67 #define MT2063_SPUR_PRESENT_ERR (0x00800000)
69 /* Info: Tuner input frequency is out of range */
70 #define MT2063_FIN_RANGE (0x01000000)
72 /* Info: Tuner output frequency is out of range */
73 #define MT2063_FOUT_RANGE (0x02000000)
75 /* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
76 #define MT2063_UPC_RANGE (0x04000000)
78 /* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
79 #define MT2063_DNC_RANGE (0x08000000)
85 #define MAX_UDATA (4294967295) /* max value storable in u32 */
88 * Define an MTxxxx_CNT macro for each type of tuner that will be built
89 * into your application (e.g., MT2121, MT2060). MT_TUNER_CNT
90 * must be set to the SUM of all of the MTxxxx_CNT macros.
92 * #define MT2050_CNT (1)
93 * #define MT2060_CNT (1)
94 * #define MT2111_CNT (1)
95 * #define MT2121_CNT (3)
99 #define MT2063_TUNER_CNT (1) /* total num of MicroTuner tuners */
100 #define MT2063_I2C (0xC0)
103 * Constant defining the version of the following structure
104 * and therefore the API for this code.
106 * When compiling the tuner driver, the preprocessor will
107 * check against this version number to make sure that
108 * it matches the version that the tuner driver knows about.
110 /* Version 010201 => 1.21 */
111 #define MT2063_AVOID_SPURS_INFO_VERSION 010201
113 /* DECT Frequency Avoidance */
114 #define MT2063_DECT_AVOID_US_FREQS 0x00000001
116 #define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
118 #define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
120 #define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
122 enum MT2063_DECT_Avoid_Type {
123 MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
124 MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS, /* Avoid US DECT frequencies. */
125 MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS, /* Avoid European DECT frequencies. */
126 MT2063_AVOID_BOTH /* Avoid both regions. Not typically used. */
129 #define MT2063_MAX_ZONES 48
131 struct MT2063_ExclZone_t;
133 struct MT2063_ExclZone_t {
136 struct MT2063_ExclZone_t *next_;
140 * Structure of data needed for Spur Avoidance
142 struct MT2063_AvoidSpursData_t {
155 u32 f_LO1_FracN_Avoid;
156 u32 f_LO2_FracN_Avoid;
158 u32 f_min_LO_Separation;
161 enum MT2063_DECT_Avoid_Type avoidDECT;
166 struct MT2063_ExclZone_t *freeZones;
167 struct MT2063_ExclZone_t *usedZones;
168 struct MT2063_ExclZone_t MT2063_ExclZones[MT2063_MAX_ZONES];
172 * Values returned by the MT2063's on-chip temperature sensor
173 * to be read/written.
175 enum MT2063_Temperature {
176 MT2063_T_0C = 0, /* Temperature approx 0C */
177 MT2063_T_10C, /* Temperature approx 10C */
178 MT2063_T_20C, /* Temperature approx 20C */
179 MT2063_T_30C, /* Temperature approx 30C */
180 MT2063_T_40C, /* Temperature approx 40C */
181 MT2063_T_50C, /* Temperature approx 50C */
182 MT2063_T_60C, /* Temperature approx 60C */
183 MT2063_T_70C, /* Temperature approx 70C */
184 MT2063_T_80C, /* Temperature approx 80C */
185 MT2063_T_90C, /* Temperature approx 90C */
186 MT2063_T_100C, /* Temperature approx 100C */
187 MT2063_T_110C, /* Temperature approx 110C */
188 MT2063_T_120C, /* Temperature approx 120C */
189 MT2063_T_130C, /* Temperature approx 130C */
190 MT2063_T_140C, /* Temperature approx 140C */
191 MT2063_T_150C, /* Temperature approx 150C */
195 * Parameters for selecting GPIO bits
197 enum MT2063_GPIO_Attr {
203 enum MT2063_GPIO_ID {
210 * Parameter for function MT2063_SetExtSRO that specifies the external
211 * SRO drive frequency.
213 * MT2063_EXT_SRO_OFF is the power-up default value.
215 enum MT2063_Ext_SRO {
216 MT2063_EXT_SRO_OFF, /* External SRO drive off */
217 MT2063_EXT_SRO_BY_4, /* External SRO drive divide by 4 */
218 MT2063_EXT_SRO_BY_2, /* External SRO drive divide by 2 */
219 MT2063_EXT_SRO_BY_1 /* External SRO drive divide by 1 */
223 * Parameter for function MT2063_SetPowerMask that specifies the power down
224 * of various sections of the MT2063.
226 enum MT2063_Mask_Bits {
227 MT2063_REG_SD = 0x0040, /* Shutdown regulator */
228 MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
229 MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
230 MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
231 MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
232 MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
233 MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
234 MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
235 MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
236 MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
237 MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
238 MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
239 MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
240 MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
241 MT2063_NONE_SD = 0x0000 /* No shutdown bits */
245 * Parameter for function MT2063_GetParam & MT2063_SetParam that
246 * specifies the tuning algorithm parameter to be read/written.
249 /* tuner address set by MT2063_Open() */
252 /* max number of MT2063 tuners set by MT_TUNER_CNT in mt_userdef.h */
255 /* current number of open MT2063 tuners set by MT2063_Open() */
258 /* crystal frequency (default: 16000000 Hz) */
261 /* min tuning step size (default: 50000 Hz) */
264 /* input center frequency set by MT2063_Tune() */
267 /* LO1 Frequency set by MT2063_Tune() */
270 /* LO1 minimum step size (default: 250000 Hz) */
273 /* LO1 FracN keep-out region (default: 999999 Hz) */
274 MT2063_LO1_FRACN_AVOID_PARAM,
276 /* Current 1st IF in use set by MT2063_Tune() */
279 /* Requested 1st IF set by MT2063_Tune() */
282 /* Center of 1st IF SAW filter (default: 1218000000 Hz) */
285 /* Bandwidth of 1st IF SAW filter (default: 20000000 Hz) */
288 /* zero-IF bandwidth (default: 2000000 Hz) */
291 /* LO2 Frequency set by MT2063_Tune() */
294 /* LO2 minimum step size (default: 50000 Hz) */
297 /* LO2 FracN keep-out region (default: 374999 Hz) */
298 MT2063_LO2_FRACN_AVOID,
300 /* output center frequency set by MT2063_Tune() */
303 /* output bandwidth set by MT2063_Tune() */
306 /* min inter-tuner LO separation (default: 1000000 Hz) */
307 MT2063_LO_SEPARATION,
309 /* ID of avoid-spurs algorithm in use compile-time constant */
312 /* max # of intra-tuner harmonics (default: 15) */
315 /* max # of inter-tuner harmonics (default: 7) */
318 /* # of 1st IF exclusion zones used set by MT2063_Tune() */
321 /* # of spurs found/avoided set by MT2063_Tune() */
324 /* >0 spurs avoided set by MT2063_Tune() */
327 /* >0 spurs in output (mathematically) set by MT2063_Tune() */
330 /* Receiver Mode for some parameters. 1 is DVB-T */
333 /* directly set LNA attenuation, parameter is value to set */
336 /* maximum LNA attenuation, parameter is value to set */
339 /* directly set ATN attenuation. Paremeter is value to set. */
342 /* maxium ATN attenuation. Paremeter is value to set. */
345 /* directly set FIF attenuation. Paremeter is value to set. */
348 /* maxium FIF attenuation. Paremeter is value to set. */
354 /* Power Detector LNA level target */
357 /* Power Detector 1 level */
360 /* Power Detector 1 level target */
363 /* Power Detector 2 level */
366 /* Power Detector 2 level target */
369 /* Selects, which DNC is activ */
370 MT2063_DNC_OUTPUT_ENABLE,
375 /* VGA bias current */
378 /* TAGC, determins the speed of the AGC */
384 /* Control setting to avoid DECT freqs (default: MT_AVOID_BOTH) */
387 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
390 MT2063_EOP /* last entry in enumerated list */
394 * Parameter for selecting tuner mode
396 enum MT2063_RCVR_MODES {
397 MT2063_CABLE_QAM = 0, /* Digital cable */
398 MT2063_CABLE_ANALOG, /* Analog cable */
399 MT2063_OFFAIR_COFDM, /* Digital offair */
400 MT2063_OFFAIR_COFDM_SAWLESS, /* Digital offair without SAW */
401 MT2063_OFFAIR_ANALOG, /* Analog offair */
402 MT2063_OFFAIR_8VSB, /* Analog offair */
403 MT2063_NUM_RCVR_MODES
407 * Possible values for MT2063_DNC_OUTPUT
409 enum MT2063_DNC_Output_Enable {
417 ** Two-wire serial bus subaddresses of the tuner registers.
418 ** Also known as the tuner's register addresses.
420 enum MT2063_Register_Offsets {
421 MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
422 MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
423 MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
424 MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
425 MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
426 MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
427 MT2063_REG_RSVD_06, /* 0x06: Reserved */
428 MT2063_REG_LO_STATUS, /* 0x07: LO Status */
429 MT2063_REG_FIFFC, /* 0x08: FIFF Center */
430 MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
431 MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
432 MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
433 MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
434 MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
435 MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
436 MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
437 MT2063_REG_RSVD_10, /* 0x10: Reserved */
438 MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
439 MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
440 MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
441 MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
442 MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
443 MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
444 MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
445 MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
446 MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
447 MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
448 MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
449 MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
450 MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
451 MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
452 MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
453 MT2063_REG_RSVD_20, /* 0x20: Reserved */
454 MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
455 MT2063_REG_RSVD_22, /* 0x22: Reserved */
456 MT2063_REG_RSVD_23, /* 0x23: Reserved */
457 MT2063_REG_RSVD_24, /* 0x24: Reserved */
458 MT2063_REG_RSVD_25, /* 0x25: Reserved */
459 MT2063_REG_RSVD_26, /* 0x26: Reserved */
460 MT2063_REG_RSVD_27, /* 0x27: Reserved */
461 MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
462 MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
463 MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
464 MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
465 MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
466 MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
467 MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
468 MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
469 MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
470 MT2063_REG_RSVD_31, /* 0x31: Reserved */
471 MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
472 MT2063_REG_RSVD_33, /* 0x33: Reserved */
473 MT2063_REG_RSVD_34, /* 0x34: Reserved */
474 MT2063_REG_RSVD_35, /* 0x35: Reserved */
475 MT2063_REG_RSVD_36, /* 0x36: Reserved */
476 MT2063_REG_RSVD_37, /* 0x37: Reserved */
477 MT2063_REG_RSVD_38, /* 0x38: Reserved */
478 MT2063_REG_RSVD_39, /* 0x39: Reserved */
479 MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
480 MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
481 MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
485 struct MT2063_Info_t {
491 struct MT2063_AvoidSpursData_t AS_Data;
497 u8 reg[MT2063_REG_END_REGS];
499 typedef struct MT2063_Info_t *pMT2063_Info_t;
501 enum MTTune_atv_standard {
515 struct mt2063_config {
520 struct mt2063_state {
521 struct i2c_adapter *i2c;
523 const struct mt2063_config *config;
524 struct dvb_tuner_ops ops;
525 struct dvb_frontend *frontend;
526 struct tuner_state status;
527 const struct MT2063_Info_t *MT2063_ht;
530 enum MTTune_atv_standard tv_type;
537 #if defined(CONFIG_MEDIA_TUNER_MT2063) || (defined(CONFIG_MEDIA_TUNER_MT2063_MODULE) && defined(MODULE))
538 struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
539 struct mt2063_config *config,
540 struct i2c_adapter *i2c);
544 static inline struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
545 struct mt2063_config *config,
546 struct i2c_adapter *i2c)
548 printk(KERN_WARNING "%s: Driver disabled by Kconfig\n", __func__);
552 #endif /* CONFIG_DVB_MT2063 */
554 #endif /* __MT2063_H__ */