drivers/media/common/tuners/tda18271-common.c

   1 /*
   2     tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
   3
   4     Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include "tda18271-priv.h"
  22
  23 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  24 {
  25         struct tda18271_priv *priv = fe->tuner_priv;
  26         enum tda18271_i2c_gate gate;
  27         int ret = 0;
  28
  29         switch (priv->gate) {
  30         case TDA18271_GATE_DIGITAL:
  31         case TDA18271_GATE_ANALOG:
  32                 gate = priv->gate;
  33                 break;
  34         case TDA18271_GATE_AUTO:
  35         default:
  36                 switch (priv->mode) {
  37                 case TDA18271_DIGITAL:
  38                         gate = TDA18271_GATE_DIGITAL;
  39                         break;
  40                 case TDA18271_ANALOG:
  41                 default:
  42                         gate = TDA18271_GATE_ANALOG;
  43                         break;
  44                 }
  45         }
  46
  47         switch (gate) {
  48         case TDA18271_GATE_ANALOG:
  49                 if (fe->ops.analog_ops.i2c_gate_ctrl)
  50                         ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
  51                 break;
  52         case TDA18271_GATE_DIGITAL:
  53                 if (fe->ops.i2c_gate_ctrl)
  54                         ret = fe->ops.i2c_gate_ctrl(fe, enable);
  55                 break;
  56         default:
  57                 ret = -EINVAL;
  58                 break;
  59         }
  60
  61         return ret;
  62 };
  63
  64 /*---------------------------------------------------------------------*/
  65
  66 static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
  67 {
  68         struct tda18271_priv *priv = fe->tuner_priv;
  69         unsigned char *regs = priv->tda18271_regs;
  70
  71         tda_reg("=== TDA18271 REG DUMP ===\n");
  72         tda_reg("ID_BYTE            = 0x%02x\n", 0xff & regs[R_ID]);
  73         tda_reg("THERMO_BYTE        = 0x%02x\n", 0xff & regs[R_TM]);
  74         tda_reg("POWER_LEVEL_BYTE   = 0x%02x\n", 0xff & regs[R_PL]);
  75         tda_reg("EASY_PROG_BYTE_1   = 0x%02x\n", 0xff & regs[R_EP1]);
  76         tda_reg("EASY_PROG_BYTE_2   = 0x%02x\n", 0xff & regs[R_EP2]);
  77         tda_reg("EASY_PROG_BYTE_3   = 0x%02x\n", 0xff & regs[R_EP3]);
  78         tda_reg("EASY_PROG_BYTE_4   = 0x%02x\n", 0xff & regs[R_EP4]);
  79         tda_reg("EASY_PROG_BYTE_5   = 0x%02x\n", 0xff & regs[R_EP5]);
  80         tda_reg("CAL_POST_DIV_BYTE  = 0x%02x\n", 0xff & regs[R_CPD]);
  81         tda_reg("CAL_DIV_BYTE_1     = 0x%02x\n", 0xff & regs[R_CD1]);
  82         tda_reg("CAL_DIV_BYTE_2     = 0x%02x\n", 0xff & regs[R_CD2]);
  83         tda_reg("CAL_DIV_BYTE_3     = 0x%02x\n", 0xff & regs[R_CD3]);
  84         tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
  85         tda_reg("MAIN_DIV_BYTE_1    = 0x%02x\n", 0xff & regs[R_MD1]);
  86         tda_reg("MAIN_DIV_BYTE_2    = 0x%02x\n", 0xff & regs[R_MD2]);
  87         tda_reg("MAIN_DIV_BYTE_3    = 0x%02x\n", 0xff & regs[R_MD3]);
  88
  89         /* only dump extended regs if DBG_ADV is set */
  90         if (!(tda18271_debug & DBG_ADV))
  91                 return;
  92
  93         /* W indicates write-only registers.
  94          * Register dump for write-only registers shows last value written. */
  95
  96         tda_reg("EXTENDED_BYTE_1    = 0x%02x\n", 0xff & regs[R_EB1]);
  97         tda_reg("EXTENDED_BYTE_2    = 0x%02x\n", 0xff & regs[R_EB2]);
  98         tda_reg("EXTENDED_BYTE_3    = 0x%02x\n", 0xff & regs[R_EB3]);
  99         tda_reg("EXTENDED_BYTE_4    = 0x%02x\n", 0xff & regs[R_EB4]);
 100         tda_reg("EXTENDED_BYTE_5    = 0x%02x\n", 0xff & regs[R_EB5]);
 101         tda_reg("EXTENDED_BYTE_6    = 0x%02x\n", 0xff & regs[R_EB6]);
 102         tda_reg("EXTENDED_BYTE_7    = 0x%02x\n", 0xff & regs[R_EB7]);
 103         tda_reg("EXTENDED_BYTE_8    = 0x%02x\n", 0xff & regs[R_EB8]);
 104         tda_reg("EXTENDED_BYTE_9  W = 0x%02x\n", 0xff & regs[R_EB9]);
 105         tda_reg("EXTENDED_BYTE_10   = 0x%02x\n", 0xff & regs[R_EB10]);
 106         tda_reg("EXTENDED_BYTE_11   = 0x%02x\n", 0xff & regs[R_EB11]);
 107         tda_reg("EXTENDED_BYTE_12   = 0x%02x\n", 0xff & regs[R_EB12]);
 108         tda_reg("EXTENDED_BYTE_13   = 0x%02x\n", 0xff & regs[R_EB13]);
 109         tda_reg("EXTENDED_BYTE_14   = 0x%02x\n", 0xff & regs[R_EB14]);
 110         tda_reg("EXTENDED_BYTE_15   = 0x%02x\n", 0xff & regs[R_EB15]);
 111         tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
 112         tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
 113         tda_reg("EXTENDED_BYTE_18   = 0x%02x\n", 0xff & regs[R_EB18]);
 114         tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
 115         tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
 116         tda_reg("EXTENDED_BYTE_21   = 0x%02x\n", 0xff & regs[R_EB21]);
 117         tda_reg("EXTENDED_BYTE_22   = 0x%02x\n", 0xff & regs[R_EB22]);
 118         tda_reg("EXTENDED_BYTE_23   = 0x%02x\n", 0xff & regs[R_EB23]);
 119 }
 120
 121 int tda18271_read_regs(struct dvb_frontend *fe)
 122 {
 123         struct tda18271_priv *priv = fe->tuner_priv;
 124         unsigned char *regs = priv->tda18271_regs;
 125         unsigned char buf = 0x00;
 126         int ret;
 127         struct i2c_msg msg[] = {
 128                 { .addr = priv->i2c_props.addr, .flags = 0,
 129                   .buf = &buf, .len = 1 },
 130                 { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
 131                   .buf = regs, .len = 16 }
 132         };
 133
 134         tda18271_i2c_gate_ctrl(fe, 1);
 135
 136         /* read all registers */
 137         ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
 138
 139         tda18271_i2c_gate_ctrl(fe, 0);
 140
 141         if (ret != 2)
 142                 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
 143
 144         if (tda18271_debug & DBG_REG)
 145                 tda18271_dump_regs(fe, 0);
 146
 147         return (ret == 2 ? 0 : ret);
 148 }
 149
 150 int tda18271_read_extended(struct dvb_frontend *fe)
 151 {
 152         struct tda18271_priv *priv = fe->tuner_priv;
 153         unsigned char *regs = priv->tda18271_regs;
 154         unsigned char regdump[TDA18271_NUM_REGS];
 155         unsigned char buf = 0x00;
 156         int ret, i;
 157         struct i2c_msg msg[] = {
 158                 { .addr = priv->i2c_props.addr, .flags = 0,
 159                   .buf = &buf, .len = 1 },
 160                 { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
 161                   .buf = regdump, .len = TDA18271_NUM_REGS }
 162         };
 163
 164         tda18271_i2c_gate_ctrl(fe, 1);
 165
 166         /* read all registers */
 167         ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
 168
 169         tda18271_i2c_gate_ctrl(fe, 0);
 170
 171         if (ret != 2)
 172                 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
 173
 174         for (i = 0; i < TDA18271_NUM_REGS; i++) {
 175                 /* don't update write-only registers */
 176                 if ((i != R_EB9)  &&
 177                     (i != R_EB16) &&
 178                     (i != R_EB17) &&
 179                     (i != R_EB19) &&
 180                     (i != R_EB20))
 181                 regs[i] = regdump[i];
 182         }
 183
 184         if (tda18271_debug & DBG_REG)
 185                 tda18271_dump_regs(fe, 1);
 186
 187         return (ret == 2 ? 0 : ret);
 188 }
 189
 190 int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
 191 {
 192         struct tda18271_priv *priv = fe->tuner_priv;
 193         unsigned char *regs = priv->tda18271_regs;
 194         unsigned char buf[TDA18271_NUM_REGS + 1];
 195         struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0,
 196                                .buf = buf, .len = len + 1 };
 197         int i, ret;
 198
 199         BUG_ON((len == 0) || (idx + len > sizeof(buf)));
 200
 201         buf[0] = idx;
 202         for (i = 1; i <= len; i++)
 203                 buf[i] = regs[idx - 1 + i];
 204
 205         tda18271_i2c_gate_ctrl(fe, 1);
 206
 207         /* write registers */
 208         ret = i2c_transfer(priv->i2c_props.adap, &msg, 1);
 209
 210         tda18271_i2c_gate_ctrl(fe, 0);
 211
 212         if (ret != 1)
 213                 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
 214
 215         return (ret == 1 ? 0 : ret);
 216 }
 217
 218 /*---------------------------------------------------------------------*/
 219
 220 int tda18271_charge_pump_source(struct dvb_frontend *fe,
 221                                 enum tda18271_pll pll, int force)
 222 {
 223         struct tda18271_priv *priv = fe->tuner_priv;
 224         unsigned char *regs = priv->tda18271_regs;
 225
 226         int r_cp = (pll == TDA18271_CAL_PLL) ? R_EB7 : R_EB4;
 227
 228         regs[r_cp] &= ~0x20;
 229         regs[r_cp] |= ((force & 1) << 5);
 230         tda18271_write_regs(fe, r_cp, 1);
 231
 232         return 0;
 233 }
 234
 235 int tda18271_init_regs(struct dvb_frontend *fe)
 236 {
 237         struct tda18271_priv *priv = fe->tuner_priv;
 238         unsigned char *regs = priv->tda18271_regs;
 239
 240         tda_dbg("initializing registers for device @ %d-%04x\n",
 241                 i2c_adapter_id(priv->i2c_props.adap),
 242                 priv->i2c_props.addr);
 243
 244         /* initialize registers */
 245         switch (priv->id) {
 246         case TDA18271HDC1:
 247                 regs[R_ID]   = 0x83;
 248                 break;
 249         case TDA18271HDC2:
 250                 regs[R_ID]   = 0x84;
 251                 break;
 252         };
 253
 254         regs[R_TM]   = 0x08;
 255         regs[R_PL]   = 0x80;
 256         regs[R_EP1]  = 0xc6;
 257         regs[R_EP2]  = 0xdf;
 258         regs[R_EP3]  = 0x16;
 259         regs[R_EP4]  = 0x60;
 260         regs[R_EP5]  = 0x80;
 261         regs[R_CPD]  = 0x80;
 262         regs[R_CD1]  = 0x00;
 263         regs[R_CD2]  = 0x00;
 264         regs[R_CD3]  = 0x00;
 265         regs[R_MPD]  = 0x00;
 266         regs[R_MD1]  = 0x00;
 267         regs[R_MD2]  = 0x00;
 268         regs[R_MD3]  = 0x00;
 269
 270         switch (priv->id) {
 271         case TDA18271HDC1:
 272                 regs[R_EB1]  = 0xff;
 273                 break;
 274         case TDA18271HDC2:
 275                 regs[R_EB1]  = 0xfc;
 276                 break;
 277         };
 278
 279         regs[R_EB2]  = 0x01;
 280         regs[R_EB3]  = 0x84;
 281         regs[R_EB4]  = 0x41;
 282         regs[R_EB5]  = 0x01;
 283         regs[R_EB6]  = 0x84;
 284         regs[R_EB7]  = 0x40;
 285         regs[R_EB8]  = 0x07;
 286         regs[R_EB9]  = 0x00;
 287         regs[R_EB10] = 0x00;
 288         regs[R_EB11] = 0x96;
 289
 290         switch (priv->id) {
 291         case TDA18271HDC1:
 292                 regs[R_EB12] = 0x0f;
 293                 break;
 294         case TDA18271HDC2:
 295                 regs[R_EB12] = 0x33;
 296                 break;
 297         };
 298
 299         regs[R_EB13] = 0xc1;
 300         regs[R_EB14] = 0x00;
 301         regs[R_EB15] = 0x8f;
 302         regs[R_EB16] = 0x00;
 303         regs[R_EB17] = 0x00;
 304
 305         switch (priv->id) {
 306         case TDA18271HDC1:
 307                 regs[R_EB18] = 0x00;
 308                 break;
 309         case TDA18271HDC2:
 310                 regs[R_EB18] = 0x8c;
 311                 break;
 312         };
 313
 314         regs[R_EB19] = 0x00;
 315         regs[R_EB20] = 0x20;
 316
 317         switch (priv->id) {
 318         case TDA18271HDC1:
 319                 regs[R_EB21] = 0x33;
 320                 break;
 321         case TDA18271HDC2:
 322                 regs[R_EB21] = 0xb3;
 323                 break;
 324         };
 325
 326         regs[R_EB22] = 0x48;
 327         regs[R_EB23] = 0xb0;
 328
 329         if (priv->small_i2c) {
 330                 tda18271_write_regs(fe, 0x00, 0x10);
 331                 tda18271_write_regs(fe, 0x10, 0x10);
 332                 tda18271_write_regs(fe, 0x20, 0x07);
 333         } else
 334                 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
 335
 336         /* setup agc1 gain */
 337         regs[R_EB17] = 0x00;
 338         tda18271_write_regs(fe, R_EB17, 1);
 339         regs[R_EB17] = 0x03;
 340         tda18271_write_regs(fe, R_EB17, 1);
 341         regs[R_EB17] = 0x43;
 342         tda18271_write_regs(fe, R_EB17, 1);
 343         regs[R_EB17] = 0x4c;
 344         tda18271_write_regs(fe, R_EB17, 1);
 345
 346         /* setup agc2 gain */
 347         if ((priv->id) == TDA18271HDC1) {
 348                 regs[R_EB20] = 0xa0;
 349                 tda18271_write_regs(fe, R_EB20, 1);
 350                 regs[R_EB20] = 0xa7;
 351                 tda18271_write_regs(fe, R_EB20, 1);
 352                 regs[R_EB20] = 0xe7;
 353                 tda18271_write_regs(fe, R_EB20, 1);
 354                 regs[R_EB20] = 0xec;
 355                 tda18271_write_regs(fe, R_EB20, 1);
 356         }
 357
 358         /* image rejection calibration */
 359
 360         /* low-band */
 361         regs[R_EP3] = 0x1f;
 362         regs[R_EP4] = 0x66;
 363         regs[R_EP5] = 0x81;
 364         regs[R_CPD] = 0xcc;
 365         regs[R_CD1] = 0x6c;
 366         regs[R_CD2] = 0x00;
 367         regs[R_CD3] = 0x00;
 368         regs[R_MPD] = 0xcd;
 369         regs[R_MD1] = 0x77;
 370         regs[R_MD2] = 0x08;
 371         regs[R_MD3] = 0x00;
 372
 373         tda18271_write_regs(fe, R_EP3, 11);
 374
 375         if ((priv->id) == TDA18271HDC2) {
 376                 /* main pll cp source on */
 377                 tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 1);
 378                 msleep(1);
 379
 380                 /* main pll cp source off */
 381                 tda18271_charge_pump_source(fe, TDA18271_MAIN_PLL, 0);
 382         }
 383
 384         msleep(5); /* pll locking */
 385
 386         /* launch detector */
 387         tda18271_write_regs(fe, R_EP1, 1);
 388         msleep(5); /* wanted low measurement */
 389
 390         regs[R_EP5] = 0x85;
 391         regs[R_CPD] = 0xcb;
 392         regs[R_CD1] = 0x66;
 393         regs[R_CD2] = 0x70;
 394
 395         tda18271_write_regs(fe, R_EP3, 7);
 396         msleep(5); /* pll locking */
 397
 398         /* launch optimization algorithm */
 399         tda18271_write_regs(fe, R_EP2, 1);
 400         msleep(30); /* image low optimization completion */
 401
 402         /* mid-band */
 403         regs[R_EP5] = 0x82;
 404         regs[R_CPD] = 0xa8;
 405         regs[R_CD2] = 0x00;
 406         regs[R_MPD] = 0xa9;
 407         regs[R_MD1] = 0x73;
 408         regs[R_MD2] = 0x1a;
 409
 410         tda18271_write_regs(fe, R_EP3, 11);
 411         msleep(5); /* pll locking */
 412
 413         /* launch detector */
 414         tda18271_write_regs(fe, R_EP1, 1);
 415         msleep(5); /* wanted mid measurement */
 416
 417         regs[R_EP5] = 0x86;
 418         regs[R_CPD] = 0xa8;
 419         regs[R_CD1] = 0x66;
 420         regs[R_CD2] = 0xa0;
 421
 422         tda18271_write_regs(fe, R_EP3, 7);
 423         msleep(5); /* pll locking */
 424
 425         /* launch optimization algorithm */
 426         tda18271_write_regs(fe, R_EP2, 1);
 427         msleep(30); /* image mid optimization completion */
 428
 429         /* high-band */
 430         regs[R_EP5] = 0x83;
 431         regs[R_CPD] = 0x98;
 432         regs[R_CD1] = 0x65;
 433         regs[R_CD2] = 0x00;
 434         regs[R_MPD] = 0x99;
 435         regs[R_MD1] = 0x71;
 436         regs[R_MD2] = 0xcd;
 437
 438         tda18271_write_regs(fe, R_EP3, 11);
 439         msleep(5); /* pll locking */
 440
 441         /* launch detector */
 442         tda18271_write_regs(fe, R_EP1, 1);
 443         msleep(5); /* wanted high measurement */
 444
 445         regs[R_EP5] = 0x87;
 446         regs[R_CD1] = 0x65;
 447         regs[R_CD2] = 0x50;
 448
 449         tda18271_write_regs(fe, R_EP3, 7);
 450         msleep(5); /* pll locking */
 451
 452         /* launch optimization algorithm */
 453         tda18271_write_regs(fe, R_EP2, 1);
 454         msleep(30); /* image high optimization completion */
 455
 456         /* return to normal mode */
 457         regs[R_EP4] = 0x64;
 458         tda18271_write_regs(fe, R_EP4, 1);
 459
 460         /* synchronize */
 461         tda18271_write_regs(fe, R_EP1, 1);
 462
 463         return 0;
 464 }
 465
 466 /*---------------------------------------------------------------------*/
 467
 468 /*
 469  *  Standby modes, EP3 [7:5]
 470  *
 471  *  | SM  || SM_LT || SM_XT || mode description
 472  *  |=====\\=======\\=======\\===================================
 473  *  |  0  ||   0   ||   0   || normal mode
 474  *  |-----||-------||-------||-----------------------------------
 475  *  |     ||       ||       || standby mode w/ slave tuner output
 476  *  |  1  ||   0   ||   0   || & loop thru & xtal oscillator on
 477  *  |-----||-------||-------||-----------------------------------
 478  *  |  1  ||   1   ||   0   || standby mode w/ xtal oscillator on
 479  *  |-----||-------||-------||-----------------------------------
 480  *  |  1  ||   1   ||   1   || power off
 481  *
 482  */
 483
 484 int tda18271_set_standby_mode(struct dvb_frontend *fe,
 485                               int sm, int sm_lt, int sm_xt)
 486 {
 487         struct tda18271_priv *priv = fe->tuner_priv;
 488         unsigned char *regs = priv->tda18271_regs;
 489
 490         tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
 491
 492         regs[R_EP3]  &= ~0xe0; /* clear sm, sm_lt, sm_xt */
 493         regs[R_EP3]  |= sm    ? (1 << 7) : 0 |
 494                         sm_lt ? (1 << 6) : 0 |
 495                         sm_xt ? (1 << 5) : 0;
 496
 497         tda18271_write_regs(fe, R_EP3, 1);
 498
 499         return 0;
 500 }
 501
 502 /*---------------------------------------------------------------------*/
 503
 504 int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
 505 {
 506         /* sets main post divider & divider bytes, but does not write them */
 507         struct tda18271_priv *priv = fe->tuner_priv;
 508         unsigned char *regs = priv->tda18271_regs;
 509         u8 d, pd;
 510         u32 div;
 511
 512         int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
 513         if (ret < 0)
 514                 goto fail;
 515
 516         regs[R_MPD]   = (0x77 & pd);
 517
 518         switch (priv->mode) {
 519         case TDA18271_ANALOG:
 520                 regs[R_MPD]  &= ~0x08;
 521                 break;
 522         case TDA18271_DIGITAL:
 523                 regs[R_MPD]  |=  0x08;
 524                 break;
 525         }
 526
 527         div =  ((d * (freq / 1000)) << 7) / 125;
 528
 529         regs[R_MD1]   = 0x7f & (div >> 16);
 530         regs[R_MD2]   = 0xff & (div >> 8);
 531         regs[R_MD3]   = 0xff & div;
 532 fail:
 533         return ret;
 534 }
 535
 536 int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
 537 {
 538         /* sets cal post divider & divider bytes, but does not write them */
 539         struct tda18271_priv *priv = fe->tuner_priv;
 540         unsigned char *regs = priv->tda18271_regs;
 541         u8 d, pd;
 542         u32 div;
 543
 544         int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
 545         if (ret < 0)
 546                 goto fail;
 547
 548         regs[R_CPD]   = pd;
 549
 550         div =  ((d * (freq / 1000)) << 7) / 125;
 551
 552         regs[R_CD1]   = 0x7f & (div >> 16);
 553         regs[R_CD2]   = 0xff & (div >> 8);
 554         regs[R_CD3]   = 0xff & div;
 555 fail:
 556         return ret;
 557 }
 558
 559 /*---------------------------------------------------------------------*/
 560
 561 int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
 562 {
 563         /* sets bp filter bits, but does not write them */
 564         struct tda18271_priv *priv = fe->tuner_priv;
 565         unsigned char *regs = priv->tda18271_regs;
 566         u8 val;
 567
 568         int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
 569         if (ret < 0)
 570                 goto fail;
 571
 572         regs[R_EP1]  &= ~0x07; /* clear bp filter bits */
 573         regs[R_EP1]  |= (0x07 & val);
 574 fail:
 575         return ret;
 576 }
 577
 578 int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
 579 {
 580         /* sets K & M bits, but does not write them */
 581         struct tda18271_priv *priv = fe->tuner_priv;
 582         unsigned char *regs = priv->tda18271_regs;
 583         u8 val;
 584
 585         int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
 586         if (ret < 0)
 587                 goto fail;
 588
 589         regs[R_EB13] &= ~0x7c; /* clear k & m bits */
 590         regs[R_EB13] |= (0x7c & val);
 591 fail:
 592         return ret;
 593 }
 594
 595 int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
 596 {
 597         /* sets rf band bits, but does not write them */
 598         struct tda18271_priv *priv = fe->tuner_priv;
 599         unsigned char *regs = priv->tda18271_regs;
 600         u8 val;
 601
 602         int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
 603         if (ret < 0)
 604                 goto fail;
 605
 606         regs[R_EP2]  &= ~0xe0; /* clear rf band bits */
 607         regs[R_EP2]  |= (0xe0 & (val << 5));
 608 fail:
 609         return ret;
 610 }
 611
 612 int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
 613 {
 614         /* sets gain taper bits, but does not write them */
 615         struct tda18271_priv *priv = fe->tuner_priv;
 616         unsigned char *regs = priv->tda18271_regs;
 617         u8 val;
 618
 619         int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
 620         if (ret < 0)
 621                 goto fail;
 622
 623         regs[R_EP2]  &= ~0x1f; /* clear gain taper bits */
 624         regs[R_EP2]  |= (0x1f & val);
 625 fail:
 626         return ret;
 627 }
 628
 629 int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
 630 {
 631         /* sets IR Meas bits, but does not write them */
 632         struct tda18271_priv *priv = fe->tuner_priv;
 633         unsigned char *regs = priv->tda18271_regs;
 634         u8 val;
 635
 636         int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
 637         if (ret < 0)
 638                 goto fail;
 639
 640         regs[R_EP5] &= ~0x07;
 641         regs[R_EP5] |= (0x07 & val);
 642 fail:
 643         return ret;
 644 }
 645
 646 int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
 647 {
 648         /* sets rf cal byte (RFC_Cprog), but does not write it */
 649         struct tda18271_priv *priv = fe->tuner_priv;
 650         unsigned char *regs = priv->tda18271_regs;
 651         u8 val;
 652
 653         tda18271_lookup_map(fe, RF_CAL, freq, &val);
 654
 655         regs[R_EB14] = val;
 656
 657         return 0;
 658 }
 659
 660 /*
 661  * Overrides for Emacs so that we follow Linus's tabbing style.
 662  * ---------------------------------------------------------------------------
 663  * Local variables:
 664  * c-basic-offset: 8
 665  * End:
 666  */