drivers/media/dvb/frontends/lgdt3305.c

   1 /*
   2  *    Support for LG Electronics LGDT3304 and LGDT3305 - VSB/QAM
   3  *
   4  *    Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License
  17  *    along with this program; if not, write to the Free Software
  18  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  */
  21
  22 #include <asm/div64.h>
  23 #include <linux/dvb/frontend.h>
  24 #include <linux/slab.h>
  25 #include "dvb_math.h"
  26 #include "lgdt3305.h"
  27
  28 static int debug;
  29 module_param(debug, int, 0644);
  30 MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
  31
  32 #define DBG_INFO 1
  33 #define DBG_REG  2
  34
  35 #define lg_printk(kern, fmt, arg...)                                    \
  36         printk(kern "%s: " fmt, __func__, ##arg)
  37
  38 #define lg_info(fmt, arg...)    printk(KERN_INFO "lgdt3305: " fmt, ##arg)
  39 #define lg_warn(fmt, arg...)    lg_printk(KERN_WARNING,       fmt, ##arg)
  40 #define lg_err(fmt, arg...)     lg_printk(KERN_ERR,           fmt, ##arg)
  41 #define lg_dbg(fmt, arg...) if (debug & DBG_INFO)                       \
  42                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  43 #define lg_reg(fmt, arg...) if (debug & DBG_REG)                        \
  44                                 lg_printk(KERN_DEBUG,         fmt, ##arg)
  45
  46 #define lg_fail(ret)                                                    \
  47 ({                                                                      \
  48         int __ret;                                                      \
  49         __ret = (ret < 0);                                              \
  50         if (__ret)                                                      \
  51                 lg_err("error %d on line %d\n", ret, __LINE__);         \
  52         __ret;                                                          \
  53 })
  54
  55 struct lgdt3305_state {
  56         struct i2c_adapter *i2c_adap;
  57         const struct lgdt3305_config *cfg;
  58
  59         struct dvb_frontend frontend;
  60
  61         fe_modulation_t current_modulation;
  62         u32 current_frequency;
  63         u32 snr;
  64 };
  65
  66 /* ------------------------------------------------------------------------ */
  67
  68 #define LGDT3305_GEN_CTRL_1                   0x0000
  69 #define LGDT3305_GEN_CTRL_2                   0x0001
  70 #define LGDT3305_GEN_CTRL_3                   0x0002
  71 #define LGDT3305_GEN_STATUS                   0x0003
  72 #define LGDT3305_GEN_CONTROL                  0x0007
  73 #define LGDT3305_GEN_CTRL_4                   0x000a
  74 #define LGDT3305_DGTL_AGC_REF_1               0x0012
  75 #define LGDT3305_DGTL_AGC_REF_2               0x0013
  76 #define LGDT3305_CR_CTR_FREQ_1                0x0106
  77 #define LGDT3305_CR_CTR_FREQ_2                0x0107
  78 #define LGDT3305_CR_CTR_FREQ_3                0x0108
  79 #define LGDT3305_CR_CTR_FREQ_4                0x0109
  80 #define LGDT3305_CR_MSE_1                     0x011b
  81 #define LGDT3305_CR_MSE_2                     0x011c
  82 #define LGDT3305_CR_LOCK_STATUS               0x011d
  83 #define LGDT3305_CR_CTRL_7                    0x0126
  84 #define LGDT3305_AGC_POWER_REF_1              0x0300
  85 #define LGDT3305_AGC_POWER_REF_2              0x0301
  86 #define LGDT3305_AGC_DELAY_PT_1               0x0302
  87 #define LGDT3305_AGC_DELAY_PT_2               0x0303
  88 #define LGDT3305_RFAGC_LOOP_FLTR_BW_1         0x0306
  89 #define LGDT3305_RFAGC_LOOP_FLTR_BW_2         0x0307
  90 #define LGDT3305_IFBW_1                       0x0308
  91 #define LGDT3305_IFBW_2                       0x0309
  92 #define LGDT3305_AGC_CTRL_1                   0x030c
  93 #define LGDT3305_AGC_CTRL_4                   0x0314
  94 #define LGDT3305_EQ_MSE_1                     0x0413
  95 #define LGDT3305_EQ_MSE_2                     0x0414
  96 #define LGDT3305_EQ_MSE_3                     0x0415
  97 #define LGDT3305_PT_MSE_1                     0x0417
  98 #define LGDT3305_PT_MSE_2                     0x0418
  99 #define LGDT3305_PT_MSE_3                     0x0419
 100 #define LGDT3305_FEC_BLOCK_CTRL               0x0504
 101 #define LGDT3305_FEC_LOCK_STATUS              0x050a
 102 #define LGDT3305_FEC_PKT_ERR_1                0x050c
 103 #define LGDT3305_FEC_PKT_ERR_2                0x050d
 104 #define LGDT3305_TP_CTRL_1                    0x050e
 105 #define LGDT3305_BERT_PERIOD                  0x0801
 106 #define LGDT3305_BERT_ERROR_COUNT_1           0x080a
 107 #define LGDT3305_BERT_ERROR_COUNT_2           0x080b
 108 #define LGDT3305_BERT_ERROR_COUNT_3           0x080c
 109 #define LGDT3305_BERT_ERROR_COUNT_4           0x080d
 110
 111 static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
 112 {
 113         int ret;
 114         u8 buf[] = { reg >> 8, reg & 0xff, val };
 115         struct i2c_msg msg = {
 116                 .addr = state->cfg->i2c_addr, .flags = 0,
 117                 .buf = buf, .len = 3,
 118         };
 119
 120         lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
 121
 122         ret = i2c_transfer(state->i2c_adap, &msg, 1);
 123
 124         if (ret != 1) {
 125                 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
 126                        msg.buf[0], msg.buf[1], msg.buf[2], ret);
 127                 if (ret < 0)
 128                         return ret;
 129                 else
 130                         return -EREMOTEIO;
 131         }
 132         return 0;
 133 }
 134
 135 static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
 136 {
 137         int ret;
 138         u8 reg_buf[] = { reg >> 8, reg & 0xff };
 139         struct i2c_msg msg[] = {
 140                 { .addr = state->cfg->i2c_addr,
 141                   .flags = 0, .buf = reg_buf, .len = 2 },
 142                 { .addr = state->cfg->i2c_addr,
 143                   .flags = I2C_M_RD, .buf = val, .len = 1 },
 144         };
 145
 146         lg_reg("reg: 0x%04x\n", reg);
 147
 148         ret = i2c_transfer(state->i2c_adap, msg, 2);
 149
 150         if (ret != 2) {
 151                 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
 152                        state->cfg->i2c_addr, reg, ret);
 153                 if (ret < 0)
 154                         return ret;
 155                 else
 156                         return -EREMOTEIO;
 157         }
 158         return 0;
 159 }
 160
 161 #define read_reg(state, reg)                                            \
 162 ({                                                                      \
 163         u8 __val;                                                       \
 164         int ret = lgdt3305_read_reg(state, reg, &__val);                \
 165         if (lg_fail(ret))                                               \
 166                 __val = 0;                                              \
 167         __val;                                                          \
 168 })
 169
 170 static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
 171                                 u16 reg, int bit, int onoff)
 172 {
 173         u8 val;
 174         int ret;
 175
 176         lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
 177
 178         ret = lgdt3305_read_reg(state, reg, &val);
 179         if (lg_fail(ret))
 180                 goto fail;
 181
 182         val &= ~(1 << bit);
 183         val |= (onoff & 1) << bit;
 184
 185         ret = lgdt3305_write_reg(state, reg, val);
 186 fail:
 187         return ret;
 188 }
 189
 190 struct lgdt3305_reg {
 191         u16 reg;
 192         u8 val;
 193 };
 194
 195 static int lgdt3305_write_regs(struct lgdt3305_state *state,
 196                                struct lgdt3305_reg *regs, int len)
 197 {
 198         int i, ret;
 199
 200         lg_reg("writing %d registers...\n", len);
 201
 202         for (i = 0; i < len - 1; i++) {
 203                 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
 204                 if (lg_fail(ret))
 205                         return ret;
 206         }
 207         return 0;
 208 }
 209
 210 /* ------------------------------------------------------------------------ */
 211
 212 static int lgdt3305_soft_reset(struct lgdt3305_state *state)
 213 {
 214         int ret;
 215
 216         lg_dbg("\n");
 217
 218         ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
 219         if (lg_fail(ret))
 220                 goto fail;
 221
 222         msleep(20);
 223         ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
 224 fail:
 225         return ret;
 226 }
 227
 228 static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
 229                                      enum lgdt3305_mpeg_mode mode)
 230 {
 231         lg_dbg("(%d)\n", mode);
 232         return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
 233 }
 234
 235 static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state,
 236                                        enum lgdt3305_tp_clock_edge edge,
 237                                        enum lgdt3305_tp_valid_polarity valid)
 238 {
 239         u8 val;
 240         int ret;
 241
 242         lg_dbg("edge = %d, valid = %d\n", edge, valid);
 243
 244         ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
 245         if (lg_fail(ret))
 246                 goto fail;
 247
 248         val &= ~0x09;
 249
 250         if (edge)
 251                 val |= 0x08;
 252         if (valid)
 253                 val |= 0x01;
 254
 255         ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
 256         if (lg_fail(ret))
 257                 goto fail;
 258
 259         ret = lgdt3305_soft_reset(state);
 260 fail:
 261         return ret;
 262 }
 263
 264 static int lgdt3305_set_modulation(struct lgdt3305_state *state,
 265                                    struct dvb_frontend_parameters *param)
 266 {
 267         u8 opermode;
 268         int ret;
 269
 270         lg_dbg("\n");
 271
 272         ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
 273         if (lg_fail(ret))
 274                 goto fail;
 275
 276         opermode &= ~0x03;
 277
 278         switch (param->u.vsb.modulation) {
 279         case VSB_8:
 280                 opermode |= 0x03;
 281                 break;
 282         case QAM_64:
 283                 opermode |= 0x00;
 284                 break;
 285         case QAM_256:
 286                 opermode |= 0x01;
 287                 break;
 288         default:
 289                 return -EINVAL;
 290         }
 291         ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
 292 fail:
 293         return ret;
 294 }
 295
 296 static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
 297                                          struct dvb_frontend_parameters *param)
 298 {
 299         int val;
 300
 301         switch (param->u.vsb.modulation) {
 302         case VSB_8:
 303                 val = 0;
 304                 break;
 305         case QAM_64:
 306         case QAM_256:
 307                 val = 1;
 308                 break;
 309         default:
 310                 return -EINVAL;
 311         }
 312         lg_dbg("val = %d\n", val);
 313
 314         return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
 315 }
 316
 317 /* ------------------------------------------------------------------------ */
 318
 319 static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
 320                                          struct dvb_frontend_parameters *param)
 321 {
 322         u16 agc_ref;
 323
 324         switch (param->u.vsb.modulation) {
 325         case VSB_8:
 326                 agc_ref = 0x32c4;
 327                 break;
 328         case QAM_64:
 329                 agc_ref = 0x2a00;
 330                 break;
 331         case QAM_256:
 332                 agc_ref = 0x2a80;
 333                 break;
 334         default:
 335                 return -EINVAL;
 336         }
 337
 338         lg_dbg("agc ref: 0x%04x\n", agc_ref);
 339
 340         lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
 341         lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
 342
 343         return 0;
 344 }
 345
 346 static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
 347                                struct dvb_frontend_parameters *param)
 348 {
 349         u16 ifbw, rfbw, agcdelay;
 350
 351         switch (param->u.vsb.modulation) {
 352         case VSB_8:
 353                 agcdelay = 0x04c0;
 354                 rfbw     = 0x8000;
 355                 ifbw     = 0x8000;
 356                 break;
 357         case QAM_64:
 358         case QAM_256:
 359                 agcdelay = 0x046b;
 360                 rfbw     = 0x8889;
 361                 if (state->cfg->demod_chip == LGDT3305)
 362                         ifbw = 0x8888;
 363                 else
 364                         ifbw = 0x6666;
 365                 break;
 366         default:
 367                 return -EINVAL;
 368         }
 369
 370         if (state->cfg->rf_agc_loop) {
 371                 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
 372
 373                 /* rf agc loop filter bandwidth */
 374                 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
 375                                    agcdelay >> 8);
 376                 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
 377                                    agcdelay & 0xff);
 378
 379                 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
 380                                    rfbw >> 8);
 381                 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
 382                                    rfbw & 0xff);
 383         } else {
 384                 lg_dbg("ifbw: 0x%04x\n", ifbw);
 385
 386                 /* if agc loop filter bandwidth */
 387                 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
 388                 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
 389         }
 390
 391         return 0;
 392 }
 393
 394 static int lgdt3305_agc_setup(struct lgdt3305_state *state,
 395                               struct dvb_frontend_parameters *param)
 396 {
 397         int lockdten, acqen;
 398
 399         switch (param->u.vsb.modulation) {
 400         case VSB_8:
 401                 lockdten = 0;
 402                 acqen = 0;
 403                 break;
 404         case QAM_64:
 405         case QAM_256:
 406                 lockdten = 1;
 407                 acqen = 1;
 408                 break;
 409         default:
 410                 return -EINVAL;
 411         }
 412
 413         lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
 414
 415         /* control agc function */
 416         switch (state->cfg->demod_chip) {
 417         case LGDT3304:
 418                 lgdt3305_write_reg(state, 0x0314, 0xe1 | lockdten << 1);
 419                 lgdt3305_set_reg_bit(state, 0x030e, 2, acqen);
 420                 break;
 421         case LGDT3305:
 422                 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
 423                 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
 424                 break;
 425         default:
 426                 return -EINVAL;
 427         }
 428
 429         return lgdt3305_rfagc_loop(state, param);
 430 }
 431
 432 static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
 433                                       struct dvb_frontend_parameters *param)
 434 {
 435         u16 usref = 0;
 436
 437         switch (param->u.vsb.modulation) {
 438         case VSB_8:
 439                 if (state->cfg->usref_8vsb)
 440                         usref = state->cfg->usref_8vsb;
 441                 break;
 442         case QAM_64:
 443                 if (state->cfg->usref_qam64)
 444                         usref = state->cfg->usref_qam64;
 445                 break;
 446         case QAM_256:
 447                 if (state->cfg->usref_qam256)
 448                         usref = state->cfg->usref_qam256;
 449                 break;
 450         default:
 451                 return -EINVAL;
 452         }
 453
 454         if (usref) {
 455                 lg_dbg("set manual mode: 0x%04x\n", usref);
 456
 457                 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
 458
 459                 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
 460                                    0xff & (usref >> 8));
 461                 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
 462                                    0xff & (usref >> 0));
 463         }
 464         return 0;
 465 }
 466
 467 /* ------------------------------------------------------------------------ */
 468
 469 static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
 470                                        struct dvb_frontend_parameters *param,
 471                                        int inversion)
 472 {
 473         int ret;
 474
 475         lg_dbg("(%d)\n", inversion);
 476
 477         switch (param->u.vsb.modulation) {
 478         case VSB_8:
 479                 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
 480                                          inversion ? 0xf9 : 0x79);
 481                 break;
 482         case QAM_64:
 483         case QAM_256:
 484                 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
 485                                          inversion ? 0xfd : 0xff);
 486                 break;
 487         default:
 488                 ret = -EINVAL;
 489         }
 490         return ret;
 491 }
 492
 493 static int lgdt3305_set_if(struct lgdt3305_state *state,
 494                            struct dvb_frontend_parameters *param)
 495 {
 496         u16 if_freq_khz;
 497         u8 nco1, nco2, nco3, nco4;
 498         u64 nco;
 499
 500         switch (param->u.vsb.modulation) {
 501         case VSB_8:
 502                 if_freq_khz = state->cfg->vsb_if_khz;
 503                 break;
 504         case QAM_64:
 505         case QAM_256:
 506                 if_freq_khz = state->cfg->qam_if_khz;
 507                 break;
 508         default:
 509                 return -EINVAL;
 510         }
 511
 512         nco = if_freq_khz / 10;
 513
 514         switch (param->u.vsb.modulation) {
 515         case VSB_8:
 516                 nco <<= 24;
 517                 do_div(nco, 625);
 518                 break;
 519         case QAM_64:
 520         case QAM_256:
 521                 nco <<= 28;
 522                 do_div(nco, 625);
 523                 break;
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         nco1 = (nco >> 24) & 0x3f;
 529         nco1 |= 0x40;
 530         nco2 = (nco >> 16) & 0xff;
 531         nco3 = (nco >> 8) & 0xff;
 532         nco4 = nco & 0xff;
 533
 534         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
 535         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
 536         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
 537         lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
 538
 539         lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
 540                if_freq_khz, nco1, nco2, nco3, nco4);
 541
 542         return 0;
 543 }
 544
 545 /* ------------------------------------------------------------------------ */
 546
 547 static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 548 {
 549         struct lgdt3305_state *state = fe->demodulator_priv;
 550
 551         if (state->cfg->deny_i2c_rptr)
 552                 return 0;
 553
 554         lg_dbg("(%d)\n", enable);
 555
 556         return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
 557                                     enable ? 0 : 1);
 558 }
 559
 560 static int lgdt3304_sleep(struct dvb_frontend *fe)
 561 {
 562         return 0;
 563 }
 564
 565 static int lgdt3305_sleep(struct dvb_frontend *fe)
 566 {
 567         struct lgdt3305_state *state = fe->demodulator_priv;
 568         u8 gen_ctrl_3, gen_ctrl_4;
 569
 570         lg_dbg("\n");
 571
 572         gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
 573         gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
 574
 575         /* hold in software reset while sleeping */
 576         gen_ctrl_3 &= ~0x01;
 577         /* tristate the IF-AGC pin */
 578         gen_ctrl_3 |=  0x02;
 579         /* tristate the RF-AGC pin */
 580         gen_ctrl_3 |=  0x04;
 581
 582         /* disable vsb/qam module */
 583         gen_ctrl_4 &= ~0x01;
 584         /* disable adc module */
 585         gen_ctrl_4 &= ~0x02;
 586
 587         lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
 588         lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
 589
 590         return 0;
 591 }
 592
 593 static int lgdt3304_init(struct dvb_frontend *fe)
 594 {
 595         struct lgdt3305_state *state = fe->demodulator_priv;
 596         int ret;
 597
 598         static struct lgdt3305_reg lgdt3304_init_data[] = {
 599                 { .reg = LGDT3305_GEN_CTRL_1,     .val = 0x03, },
 600                 { .reg = 0x000d,                  .val = 0x02, },
 601                 { .reg = 0x000e,                  .val = 0x02, },
 602                 { .reg = LGDT3305_DGTL_AGC_REF_1, .val = 0x32, },
 603                 { .reg = LGDT3305_DGTL_AGC_REF_2, .val = 0xc4, },
 604                 { .reg = LGDT3305_CR_CTR_FREQ_1,  .val = 0x00, },
 605                 { .reg = LGDT3305_CR_CTR_FREQ_2,  .val = 0x00, },
 606                 { .reg = LGDT3305_CR_CTR_FREQ_3,  .val = 0x00, },
 607                 { .reg = LGDT3305_CR_CTR_FREQ_4,  .val = 0x00, },
 608                 { .reg = LGDT3305_CR_CTRL_7,      .val = 0xf9, },
 609                 { .reg = 0x0112,                  .val = 0x17, },
 610                 { .reg = 0x0113,                  .val = 0x15, },
 611                 { .reg = 0x0114,                  .val = 0x18, },
 612                 { .reg = 0x0115,                  .val = 0xff, },
 613                 { .reg = 0x0116,                  .val = 0x3c, },
 614                 { .reg = 0x0214,                  .val = 0x67, },
 615                 { .reg = 0x0424,                  .val = 0x8d, },
 616                 { .reg = 0x0427,                  .val = 0x12, },
 617                 { .reg = 0x0428,                  .val = 0x4f, },
 618                 { .reg = LGDT3305_IFBW_1,         .val = 0x80, },
 619                 { .reg = LGDT3305_IFBW_2,         .val = 0x00, },
 620                 { .reg = 0x030a,                  .val = 0x08, },
 621                 { .reg = 0x030b,                  .val = 0x9b, },
 622                 { .reg = 0x030d,                  .val = 0x00, },
 623                 { .reg = 0x030e,                  .val = 0x1c, },
 624                 { .reg = 0x0314,                  .val = 0xe1, },
 625                 { .reg = 0x000d,                  .val = 0x82, },
 626                 { .reg = LGDT3305_TP_CTRL_1,      .val = 0x5b, },
 627                 { .reg = LGDT3305_TP_CTRL_1,      .val = 0x5b, },
 628         };
 629
 630         lg_dbg("\n");
 631
 632         ret = lgdt3305_write_regs(state, lgdt3304_init_data,
 633                                   ARRAY_SIZE(lgdt3304_init_data));
 634         if (lg_fail(ret))
 635                 goto fail;
 636
 637         ret = lgdt3305_soft_reset(state);
 638 fail:
 639         return ret;
 640 }
 641
 642 static int lgdt3305_init(struct dvb_frontend *fe)
 643 {
 644         struct lgdt3305_state *state = fe->demodulator_priv;
 645         int ret;
 646
 647         static struct lgdt3305_reg lgdt3305_init_data[] = {
 648                 { .reg = LGDT3305_GEN_CTRL_1,
 649                   .val = 0x03, },
 650                 { .reg = LGDT3305_GEN_CTRL_2,
 651                   .val = 0xb0, },
 652                 { .reg = LGDT3305_GEN_CTRL_3,
 653                   .val = 0x01, },
 654                 { .reg = LGDT3305_GEN_CONTROL,
 655                   .val = 0x6f, },
 656                 { .reg = LGDT3305_GEN_CTRL_4,
 657                   .val = 0x03, },
 658                 { .reg = LGDT3305_DGTL_AGC_REF_1,
 659                   .val = 0x32, },
 660                 { .reg = LGDT3305_DGTL_AGC_REF_2,
 661                   .val = 0xc4, },
 662                 { .reg = LGDT3305_CR_CTR_FREQ_1,
 663                   .val = 0x00, },
 664                 { .reg = LGDT3305_CR_CTR_FREQ_2,
 665                   .val = 0x00, },
 666                 { .reg = LGDT3305_CR_CTR_FREQ_3,
 667                   .val = 0x00, },
 668                 { .reg = LGDT3305_CR_CTR_FREQ_4,
 669                   .val = 0x00, },
 670                 { .reg = LGDT3305_CR_CTRL_7,
 671                   .val = 0x79, },
 672                 { .reg = LGDT3305_AGC_POWER_REF_1,
 673                   .val = 0x32, },
 674                 { .reg = LGDT3305_AGC_POWER_REF_2,
 675                   .val = 0xc4, },
 676                 { .reg = LGDT3305_AGC_DELAY_PT_1,
 677                   .val = 0x0d, },
 678                 { .reg = LGDT3305_AGC_DELAY_PT_2,
 679                   .val = 0x30, },
 680                 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1,
 681                   .val = 0x80, },
 682                 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2,
 683                   .val = 0x00, },
 684                 { .reg = LGDT3305_IFBW_1,
 685                   .val = 0x80, },
 686                 { .reg = LGDT3305_IFBW_2,
 687                   .val = 0x00, },
 688                 { .reg = LGDT3305_AGC_CTRL_1,
 689                   .val = 0x30, },
 690                 { .reg = LGDT3305_AGC_CTRL_4,
 691                   .val = 0x61, },
 692                 { .reg = LGDT3305_FEC_BLOCK_CTRL,
 693                   .val = 0xff, },
 694                 { .reg = LGDT3305_TP_CTRL_1,
 695                   .val = 0x1b, },
 696         };
 697
 698         lg_dbg("\n");
 699
 700         ret = lgdt3305_write_regs(state, lgdt3305_init_data,
 701                                   ARRAY_SIZE(lgdt3305_init_data));
 702         if (lg_fail(ret))
 703                 goto fail;
 704
 705         ret = lgdt3305_soft_reset(state);
 706 fail:
 707         return ret;
 708 }
 709
 710 static int lgdt3304_set_parameters(struct dvb_frontend *fe,
 711                                    struct dvb_frontend_parameters *param)
 712 {
 713         struct lgdt3305_state *state = fe->demodulator_priv;
 714         int ret;
 715
 716         lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation);
 717
 718         if (fe->ops.tuner_ops.set_params) {
 719                 ret = fe->ops.tuner_ops.set_params(fe, param);
 720                 if (fe->ops.i2c_gate_ctrl)
 721                         fe->ops.i2c_gate_ctrl(fe, 0);
 722                 if (lg_fail(ret))
 723                         goto fail;
 724                 state->current_frequency = param->frequency;
 725         }
 726
 727         ret = lgdt3305_set_modulation(state, param);
 728         if (lg_fail(ret))
 729                 goto fail;
 730
 731         ret = lgdt3305_passband_digital_agc(state, param);
 732         if (lg_fail(ret))
 733                 goto fail;
 734
 735         ret = lgdt3305_agc_setup(state, param);
 736         if (lg_fail(ret))
 737                 goto fail;
 738
 739         /* reg 0x030d is 3304-only... seen in vsb and qam usbsnoops... */
 740         switch (param->u.vsb.modulation) {
 741         case VSB_8:
 742                 lgdt3305_write_reg(state, 0x030d, 0x00);
 743                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, 0x4f);
 744                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, 0x0c);
 745                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, 0xac);
 746                 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, 0xba);
 747                 break;
 748         case QAM_64:
 749         case QAM_256:
 750                 lgdt3305_write_reg(state, 0x030d, 0x14);
 751                 ret = lgdt3305_set_if(state, param);
 752                 if (lg_fail(ret))
 753                         goto fail;
 754                 break;
 755         default:
 756                 return -EINVAL;
 757         }
 758
 759
 760         ret = lgdt3305_spectral_inversion(state, param,
 761                                           state->cfg->spectral_inversion
 762                                           ? 1 : 0);
 763         if (lg_fail(ret))
 764                 goto fail;
 765
 766         state->current_modulation = param->u.vsb.modulation;
 767
 768         ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
 769         if (lg_fail(ret))
 770                 goto fail;
 771
 772         /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
 773         ret = lgdt3305_mpeg_mode_polarity(state,
 774                                           state->cfg->tpclk_edge,
 775                                           state->cfg->tpvalid_polarity);
 776 fail:
 777         return ret;
 778 }
 779
 780 static int lgdt3305_set_parameters(struct dvb_frontend *fe,
 781                                    struct dvb_frontend_parameters *param)
 782 {
 783         struct lgdt3305_state *state = fe->demodulator_priv;
 784         int ret;
 785
 786         lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation);
 787
 788         if (fe->ops.tuner_ops.set_params) {
 789                 ret = fe->ops.tuner_ops.set_params(fe, param);
 790                 if (fe->ops.i2c_gate_ctrl)
 791                         fe->ops.i2c_gate_ctrl(fe, 0);
 792                 if (lg_fail(ret))
 793                         goto fail;
 794                 state->current_frequency = param->frequency;
 795         }
 796
 797         ret = lgdt3305_set_modulation(state, param);
 798         if (lg_fail(ret))
 799                 goto fail;
 800
 801         ret = lgdt3305_passband_digital_agc(state, param);
 802         if (lg_fail(ret))
 803                 goto fail;
 804         ret = lgdt3305_set_agc_power_ref(state, param);
 805         if (lg_fail(ret))
 806                 goto fail;
 807         ret = lgdt3305_agc_setup(state, param);
 808         if (lg_fail(ret))
 809                 goto fail;
 810
 811         /* low if */
 812         ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
 813         if (lg_fail(ret))
 814                 goto fail;
 815         ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
 816         if (lg_fail(ret))
 817                 goto fail;
 818
 819         ret = lgdt3305_set_if(state, param);
 820         if (lg_fail(ret))
 821                 goto fail;
 822         ret = lgdt3305_spectral_inversion(state, param,
 823                                           state->cfg->spectral_inversion
 824                                           ? 1 : 0);
 825         if (lg_fail(ret))
 826                 goto fail;
 827
 828         ret = lgdt3305_set_filter_extension(state, param);
 829         if (lg_fail(ret))
 830                 goto fail;
 831
 832         state->current_modulation = param->u.vsb.modulation;
 833
 834         ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
 835         if (lg_fail(ret))
 836                 goto fail;
 837
 838         /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
 839         ret = lgdt3305_mpeg_mode_polarity(state,
 840                                           state->cfg->tpclk_edge,
 841                                           state->cfg->tpvalid_polarity);
 842 fail:
 843         return ret;
 844 }
 845
 846 static int lgdt3305_get_frontend(struct dvb_frontend *fe,
 847                                  struct dvb_frontend_parameters *param)
 848 {
 849         struct lgdt3305_state *state = fe->demodulator_priv;
 850
 851         lg_dbg("\n");
 852
 853         param->u.vsb.modulation = state->current_modulation;
 854         param->frequency = state->current_frequency;
 855         return 0;
 856 }
 857
 858 /* ------------------------------------------------------------------------ */
 859
 860 static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
 861                                         int *locked)
 862 {
 863         u8 val;
 864         int ret;
 865         char *cr_lock_state = "";
 866
 867         *locked = 0;
 868
 869         ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
 870         if (lg_fail(ret))
 871                 goto fail;
 872
 873         switch (state->current_modulation) {
 874         case QAM_256:
 875         case QAM_64:
 876                 if (val & (1 << 1))
 877                         *locked = 1;
 878
 879                 switch (val & 0x07) {
 880                 case 0:
 881                         cr_lock_state = "QAM UNLOCK";
 882                         break;
 883                 case 4:
 884                         cr_lock_state = "QAM 1stLock";
 885                         break;
 886                 case 6:
 887                         cr_lock_state = "QAM 2ndLock";
 888                         break;
 889                 case 7:
 890                         cr_lock_state = "QAM FinalLock";
 891                         break;
 892                 default:
 893                         cr_lock_state = "CLOCKQAM-INVALID!";
 894                         break;
 895                 }
 896                 break;
 897         case VSB_8:
 898                 if (val & (1 << 7)) {
 899                         *locked = 1;
 900                         cr_lock_state = "CLOCKVSB";
 901                 }
 902                 break;
 903         default:
 904                 ret = -EINVAL;
 905         }
 906         lg_dbg("(%d) %s\n", *locked, cr_lock_state);
 907 fail:
 908         return ret;
 909 }
 910
 911 static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
 912                                          int *locked)
 913 {
 914         u8 val;
 915         int ret, mpeg_lock, fec_lock, viterbi_lock;
 916
 917         *locked = 0;
 918
 919         switch (state->current_modulation) {
 920         case QAM_256:
 921         case QAM_64:
 922                 ret = lgdt3305_read_reg(state,
 923                                         LGDT3305_FEC_LOCK_STATUS, &val);
 924                 if (lg_fail(ret))
 925                         goto fail;
 926
 927                 mpeg_lock    = (val & (1 << 0)) ? 1 : 0;
 928                 fec_lock     = (val & (1 << 2)) ? 1 : 0;
 929                 viterbi_lock = (val & (1 << 3)) ? 1 : 0;
 930
 931                 *locked = mpeg_lock && fec_lock && viterbi_lock;
 932
 933                 lg_dbg("(%d) %s%s%s\n", *locked,
 934                        mpeg_lock    ? "mpeg lock  "  : "",
 935                        fec_lock     ? "fec lock  "   : "",
 936                        viterbi_lock ? "viterbi lock" : "");
 937                 break;
 938         case VSB_8:
 939         default:
 940                 ret = -EINVAL;
 941         }
 942 fail:
 943         return ret;
 944 }
 945
 946 static int lgdt3305_read_status(struct dvb_frontend *fe, fe_status_t *status)
 947 {
 948         struct lgdt3305_state *state = fe->demodulator_priv;
 949         u8 val;
 950         int ret, signal, inlock, nofecerr, snrgood,
 951                 cr_lock, fec_lock, sync_lock;
 952
 953         *status = 0;
 954
 955         ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
 956         if (lg_fail(ret))
 957                 goto fail;
 958
 959         signal    = (val & (1 << 4)) ? 1 : 0;
 960         inlock    = (val & (1 << 3)) ? 0 : 1;
 961         sync_lock = (val & (1 << 2)) ? 1 : 0;
 962         nofecerr  = (val & (1 << 1)) ? 1 : 0;
 963         snrgood   = (val & (1 << 0)) ? 1 : 0;
 964
 965         lg_dbg("%s%s%s%s%s\n",
 966                signal    ? "SIGNALEXIST " : "",
 967                inlock    ? "INLOCK "      : "",
 968                sync_lock ? "SYNCLOCK "    : "",
 969                nofecerr  ? "NOFECERR "    : "",
 970                snrgood   ? "SNRGOOD "     : "");
 971
 972         ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
 973         if (lg_fail(ret))
 974                 goto fail;
 975
 976         if (signal)
 977                 *status |= FE_HAS_SIGNAL;
 978         if (cr_lock)
 979                 *status |= FE_HAS_CARRIER;
 980         if (nofecerr)
 981                 *status |= FE_HAS_VITERBI;
 982         if (sync_lock)
 983                 *status |= FE_HAS_SYNC;
 984
 985         switch (state->current_modulation) {
 986         case QAM_256:
 987         case QAM_64:
 988                 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
 989                 if (lg_fail(ret))
 990                         goto fail;
 991
 992                 if (fec_lock)
 993                         *status |= FE_HAS_LOCK;
 994                 break;
 995         case VSB_8:
 996                 if (inlock)
 997                         *status |= FE_HAS_LOCK;
 998                 break;
 999         default:
1000                 ret = -EINVAL;
1001         }
1002 fail:
1003         return ret;
1004 }
1005
1006 /* ------------------------------------------------------------------------ */
1007
1008 /* borrowed from lgdt330x.c */
1009 static u32 calculate_snr(u32 mse, u32 c)
1010 {
1011         if (mse == 0) /* no signal */
1012                 return 0;
1013
1014         mse = intlog10(mse);
1015         if (mse > c) {
1016                 /* Negative SNR, which is possible, but realisticly the
1017                 demod will lose lock before the signal gets this bad.  The
1018                 API only allows for unsigned values, so just return 0 */
1019                 return 0;
1020         }
1021         return 10*(c - mse);
1022 }
1023
1024 static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
1025 {
1026         struct lgdt3305_state *state = fe->demodulator_priv;
1027         u32 noise;      /* noise value */
1028         u32 c;          /* per-modulation SNR calculation constant */
1029
1030         switch (state->current_modulation) {
1031         case VSB_8:
1032 #ifdef USE_PTMSE
1033                 /* Use Phase Tracker Mean-Square Error Register */
1034                 /* SNR for ranges from -13.11 to +44.08 */
1035                 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
1036                         (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
1037                         (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
1038                 c = 73957994; /* log10(25*32^2)*2^24 */
1039 #else
1040                 /* Use Equalizer Mean-Square Error Register */
1041                 /* SNR for ranges from -16.12 to +44.08 */
1042                 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
1043                         (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
1044                         (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
1045                 c = 73957994; /* log10(25*32^2)*2^24 */
1046 #endif
1047                 break;
1048         case QAM_64:
1049         case QAM_256:
1050                 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
1051                         (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
1052
1053                 c = (state->current_modulation == QAM_64) ?
1054                         97939837 : 98026066;
1055                 /* log10(688128)*2^24 and log10(696320)*2^24 */
1056                 break;
1057         default:
1058                 return -EINVAL;
1059         }
1060         state->snr = calculate_snr(noise, c);
1061         /* report SNR in dB * 10 */
1062         *snr = (state->snr / ((1 << 24) / 10));
1063         lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
1064                state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
1065
1066         return 0;
1067 }
1068
1069 static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
1070                                          u16 *strength)
1071 {
1072         /* borrowed from lgdt330x.c
1073          *
1074          * Calculate strength from SNR up to 35dB
1075          * Even though the SNR can go higher than 35dB,
1076          * there is some comfort factor in having a range of
1077          * strong signals that can show at 100%
1078          */
1079         struct lgdt3305_state *state = fe->demodulator_priv;
1080         u16 snr;
1081         int ret;
1082
1083         *strength = 0;
1084
1085         ret = fe->ops.read_snr(fe, &snr);
1086         if (lg_fail(ret))
1087                 goto fail;
1088         /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
1089         /* scale the range 0 - 35*2^24 into 0 - 65535 */
1090         if (state->snr >= 8960 * 0x10000)
1091                 *strength = 0xffff;
1092         else
1093                 *strength = state->snr / 8960;
1094 fail:
1095         return ret;
1096 }
1097
1098 /* ------------------------------------------------------------------------ */
1099
1100 static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
1101 {
1102         *ber = 0;
1103         return 0;
1104 }
1105
1106 static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1107 {
1108         struct lgdt3305_state *state = fe->demodulator_priv;
1109
1110         *ucblocks =
1111                 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
1112                 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
1113
1114         return 0;
1115 }
1116
1117 static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
1118                                       struct dvb_frontend_tune_settings
1119                                         *fe_tune_settings)
1120 {
1121         fe_tune_settings->min_delay_ms = 500;
1122         lg_dbg("\n");
1123         return 0;
1124 }
1125
1126 static void lgdt3305_release(struct dvb_frontend *fe)
1127 {
1128         struct lgdt3305_state *state = fe->demodulator_priv;
1129         lg_dbg("\n");
1130         kfree(state);
1131 }
1132
1133 static struct dvb_frontend_ops lgdt3304_ops;
1134 static struct dvb_frontend_ops lgdt3305_ops;
1135
1136 struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
1137                                      struct i2c_adapter *i2c_adap)
1138 {
1139         struct lgdt3305_state *state = NULL;
1140         int ret;
1141         u8 val;
1142
1143         lg_dbg("(%d-%04x)\n",
1144                i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1145                config ? config->i2c_addr : 0);
1146
1147         state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1148         if (state == NULL)
1149                 goto fail;
1150
1151         state->cfg = config;
1152         state->i2c_adap = i2c_adap;
1153
1154         switch (config->demod_chip) {
1155         case LGDT3304:
1156                 memcpy(&state->frontend.ops, &lgdt3304_ops,
1157                        sizeof(struct dvb_frontend_ops));
1158                 break;
1159         case LGDT3305:
1160                 memcpy(&state->frontend.ops, &lgdt3305_ops,
1161                        sizeof(struct dvb_frontend_ops));
1162                 break;
1163         default:
1164                 goto fail;
1165         }
1166         state->frontend.demodulator_priv = state;
1167
1168         /* verify that we're talking to a lg dt3304/5 */
1169         ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1170         if ((lg_fail(ret)) | (val == 0))
1171                 goto fail;
1172         ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1173         if (lg_fail(ret))
1174                 goto fail;
1175         ret = lgdt3305_read_reg(state, 0x0808, &val);
1176         if ((lg_fail(ret)) | (val != 0x80))
1177                 goto fail;
1178         ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1179         if (lg_fail(ret))
1180                 goto fail;
1181
1182         state->current_frequency = -1;
1183         state->current_modulation = -1;
1184
1185         return &state->frontend;
1186 fail:
1187         lg_warn("unable to detect %s hardware\n",
1188                 config->demod_chip ? "LGDT3304" : "LGDT3305");
1189         kfree(state);
1190         return NULL;
1191 }
1192 EXPORT_SYMBOL(lgdt3305_attach);
1193
1194 static struct dvb_frontend_ops lgdt3304_ops = {
1195         .info = {
1196                 .name = "LG Electronics LGDT3304 VSB/QAM Frontend",
1197                 .type               = FE_ATSC,
1198                 .frequency_min      = 54000000,
1199                 .frequency_max      = 858000000,
1200                 .frequency_stepsize = 62500,
1201                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1202         },
1203         .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1204         .init                 = lgdt3304_init,
1205         .sleep                = lgdt3304_sleep,
1206         .set_frontend         = lgdt3304_set_parameters,
1207         .get_frontend         = lgdt3305_get_frontend,
1208         .get_tune_settings    = lgdt3305_get_tune_settings,
1209         .read_status          = lgdt3305_read_status,
1210         .read_ber             = lgdt3305_read_ber,
1211         .read_signal_strength = lgdt3305_read_signal_strength,
1212         .read_snr             = lgdt3305_read_snr,
1213         .read_ucblocks        = lgdt3305_read_ucblocks,
1214         .release              = lgdt3305_release,
1215 };
1216
1217 static struct dvb_frontend_ops lgdt3305_ops = {
1218         .info = {
1219                 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1220                 .type               = FE_ATSC,
1221                 .frequency_min      = 54000000,
1222                 .frequency_max      = 858000000,
1223                 .frequency_stepsize = 62500,
1224                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1225         },
1226         .i2c_gate_ctrl        = lgdt3305_i2c_gate_ctrl,
1227         .init                 = lgdt3305_init,
1228         .sleep                = lgdt3305_sleep,
1229         .set_frontend         = lgdt3305_set_parameters,
1230         .get_frontend         = lgdt3305_get_frontend,
1231         .get_tune_settings    = lgdt3305_get_tune_settings,
1232         .read_status          = lgdt3305_read_status,
1233         .read_ber             = lgdt3305_read_ber,
1234         .read_signal_strength = lgdt3305_read_signal_strength,
1235         .read_snr             = lgdt3305_read_snr,
1236         .read_ucblocks        = lgdt3305_read_ucblocks,
1237         .release              = lgdt3305_release,
1238 };
1239
1240 MODULE_DESCRIPTION("LG Electronics LGDT3304/5 ATSC/QAM-B Demodulator Driver");
1241 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
1242 MODULE_LICENSE("GPL");
1243 MODULE_VERSION("0.1");
1244
1245 /*
1246  * Local variables:
1247  * c-basic-offset: 8
1248  * End:
1249  */