drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware
  27  * or /lib/firmware (depending on configuration of firmware hotplug).
  28  */
  29 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  30 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  31
  32 #include <linux/init.h>
  33 #include <linux/module.h>
  34 #include <linux/device.h>
  35 #include <linux/jiffies.h>
  36 #include <linux/string.h>
  37 #include <linux/slab.h>
  38
  39 #include "dvb_frontend.h"
  40 #include "tda1004x.h"
  41
  42 static int debug;
  43 #define dprintk(args...) \
  44         do { \
  45                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  46         } while (0)
  47
  48 #define TDA1004X_CHIPID          0x00
  49 #define TDA1004X_AUTO            0x01
  50 #define TDA1004X_IN_CONF1        0x02
  51 #define TDA1004X_IN_CONF2        0x03
  52 #define TDA1004X_OUT_CONF1       0x04
  53 #define TDA1004X_OUT_CONF2       0x05
  54 #define TDA1004X_STATUS_CD       0x06
  55 #define TDA1004X_CONFC4          0x07
  56 #define TDA1004X_DSSPARE2        0x0C
  57 #define TDA10045H_CODE_IN        0x0D
  58 #define TDA10045H_FWPAGE         0x0E
  59 #define TDA1004X_SCAN_CPT        0x10
  60 #define TDA1004X_DSP_CMD         0x11
  61 #define TDA1004X_DSP_ARG         0x12
  62 #define TDA1004X_DSP_DATA1       0x13
  63 #define TDA1004X_DSP_DATA2       0x14
  64 #define TDA1004X_CONFADC1        0x15
  65 #define TDA1004X_CONFC1          0x16
  66 #define TDA10045H_S_AGC          0x1a
  67 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  68 #define TDA1004X_SNR             0x1c
  69 #define TDA1004X_CONF_TS1        0x1e
  70 #define TDA1004X_CONF_TS2        0x1f
  71 #define TDA1004X_CBER_RESET      0x20
  72 #define TDA1004X_CBER_MSB        0x21
  73 #define TDA1004X_CBER_LSB        0x22
  74 #define TDA1004X_CVBER_LUT       0x23
  75 #define TDA1004X_VBER_MSB        0x24
  76 #define TDA1004X_VBER_MID        0x25
  77 #define TDA1004X_VBER_LSB        0x26
  78 #define TDA1004X_UNCOR           0x27
  79
  80 #define TDA10045H_CONFPLL_P      0x2D
  81 #define TDA10045H_CONFPLL_M_MSB  0x2E
  82 #define TDA10045H_CONFPLL_M_LSB  0x2F
  83 #define TDA10045H_CONFPLL_N      0x30
  84
  85 #define TDA10046H_CONFPLL1       0x2D
  86 #define TDA10046H_CONFPLL2       0x2F
  87 #define TDA10046H_CONFPLL3       0x30
  88 #define TDA10046H_TIME_WREF1     0x31
  89 #define TDA10046H_TIME_WREF2     0x32
  90 #define TDA10046H_TIME_WREF3     0x33
  91 #define TDA10046H_TIME_WREF4     0x34
  92 #define TDA10046H_TIME_WREF5     0x35
  93
  94 #define TDA10045H_UNSURW_MSB     0x31
  95 #define TDA10045H_UNSURW_LSB     0x32
  96 #define TDA10045H_WREF_MSB       0x33
  97 #define TDA10045H_WREF_MID       0x34
  98 #define TDA10045H_WREF_LSB       0x35
  99 #define TDA10045H_MUXOUT         0x36
 100 #define TDA1004X_CONFADC2        0x37
 101
 102 #define TDA10045H_IOFFSET        0x38
 103
 104 #define TDA10046H_CONF_TRISTATE1 0x3B
 105 #define TDA10046H_CONF_TRISTATE2 0x3C
 106 #define TDA10046H_CONF_POLARITY  0x3D
 107 #define TDA10046H_FREQ_OFFSET    0x3E
 108 #define TDA10046H_GPIO_OUT_SEL   0x41
 109 #define TDA10046H_GPIO_SELECT    0x42
 110 #define TDA10046H_AGC_CONF       0x43
 111 #define TDA10046H_AGC_THR        0x44
 112 #define TDA10046H_AGC_RENORM     0x45
 113 #define TDA10046H_AGC_GAINS      0x46
 114 #define TDA10046H_AGC_TUN_MIN    0x47
 115 #define TDA10046H_AGC_TUN_MAX    0x48
 116 #define TDA10046H_AGC_IF_MIN     0x49
 117 #define TDA10046H_AGC_IF_MAX     0x4A
 118
 119 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 120 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 121
 122 #define TDA10046H_CVBER_CTRL     0x4F
 123 #define TDA10046H_AGC_IF_LEVEL   0x52
 124 #define TDA10046H_CODE_CPT       0x57
 125 #define TDA10046H_CODE_IN        0x58
 126
 127
 128 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 129 {
 130         int ret;
 131         u8 buf[] = { reg, data };
 132         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 133
 134         dprintk("%s: reg=0x%x, data=0x%x\n", __func__, reg, data);
 135
 136         msg.addr = state->config->demod_address;
 137         ret = i2c_transfer(state->i2c, &msg, 1);
 138
 139         if (ret != 1)
 140                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 141                         __func__, reg, data, ret);
 142
 143         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
 144                 reg, data, ret);
 145         return (ret != 1) ? -1 : 0;
 146 }
 147
 148 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 149 {
 150         int ret;
 151         u8 b0[] = { reg };
 152         u8 b1[] = { 0 };
 153         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 154                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 155
 156         dprintk("%s: reg=0x%x\n", __func__, reg);
 157
 158         msg[0].addr = state->config->demod_address;
 159         msg[1].addr = state->config->demod_address;
 160         ret = i2c_transfer(state->i2c, msg, 2);
 161
 162         if (ret != 2) {
 163                 dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg,
 164                         ret);
 165                 return -1;
 166         }
 167
 168         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __func__,
 169                 reg, b1[0], ret);
 170         return b1[0];
 171 }
 172
 173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 174 {
 175         int val;
 176         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __func__, reg,
 177                 mask, data);
 178
 179         // read a byte and check
 180         val = tda1004x_read_byte(state, reg);
 181         if (val < 0)
 182                 return val;
 183
 184         // mask if off
 185         val = val & ~mask;
 186         val |= data & 0xff;
 187
 188         // write it out again
 189         return tda1004x_write_byteI(state, reg, val);
 190 }
 191
 192 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 193 {
 194         int i;
 195         int result;
 196
 197         dprintk("%s: reg=0x%x, len=0x%x\n", __func__, reg, len);
 198
 199         result = 0;
 200         for (i = 0; i < len; i++) {
 201                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 202                 if (result != 0)
 203                         break;
 204         }
 205
 206         return result;
 207 }
 208
 209 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 210 {
 211         int result;
 212         dprintk("%s\n", __func__);
 213
 214         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 215         msleep(20);
 216         return result;
 217 }
 218
 219 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 220 {
 221         dprintk("%s\n", __func__);
 222
 223         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 224 }
 225
 226 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 227                                    fe_bandwidth_t bandwidth)
 228 {
 229         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 230         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 231         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 232
 233         switch (bandwidth) {
 234         case BANDWIDTH_6_MHZ:
 235                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 236                 break;
 237
 238         case BANDWIDTH_7_MHZ:
 239                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 240                 break;
 241
 242         case BANDWIDTH_8_MHZ:
 243                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 244                 break;
 245
 246         default:
 247                 return -EINVAL;
 248         }
 249
 250         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 251
 252         return 0;
 253 }
 254
 255 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 256                                    fe_bandwidth_t bandwidth)
 257 {
 258         static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 };
 259         static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f };
 260         static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d };
 261
 262         static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 };
 263         static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab };
 264         static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 };
 265         int tda10046_clk53m;
 266
 267         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 268             (state->config->if_freq == TDA10046_FREQ_052))
 269                 tda10046_clk53m = 0;
 270         else
 271                 tda10046_clk53m = 1;
 272         switch (bandwidth) {
 273         case BANDWIDTH_6_MHZ:
 274                 if (tda10046_clk53m)
 275                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M,
 276                                                   sizeof(bandwidth_6mhz_53M));
 277                 else
 278                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M,
 279                                                   sizeof(bandwidth_6mhz_48M));
 280                 if (state->config->if_freq == TDA10046_FREQ_045) {
 281                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
 282                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
 283                 }
 284                 break;
 285
 286         case BANDWIDTH_7_MHZ:
 287                 if (tda10046_clk53m)
 288                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M,
 289                                                   sizeof(bandwidth_7mhz_53M));
 290                 else
 291                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M,
 292                                                   sizeof(bandwidth_7mhz_48M));
 293                 if (state->config->if_freq == TDA10046_FREQ_045) {
 294                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 295                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 296                 }
 297                 break;
 298
 299         case BANDWIDTH_8_MHZ:
 300                 if (tda10046_clk53m)
 301                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M,
 302                                                   sizeof(bandwidth_8mhz_53M));
 303                 else
 304                         tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M,
 305                                                   sizeof(bandwidth_8mhz_48M));
 306                 if (state->config->if_freq == TDA10046_FREQ_045) {
 307                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 308                         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
 309                 }
 310                 break;
 311
 312         default:
 313                 return -EINVAL;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static int tda1004x_do_upload(struct tda1004x_state *state,
 320                               const unsigned char *mem, unsigned int len,
 321                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 322 {
 323         u8 buf[65];
 324         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 325         int tx_size;
 326         int pos = 0;
 327
 328         /* clear code counter */
 329         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 330         fw_msg.addr = state->config->demod_address;
 331
 332         buf[0] = dspCodeInReg;
 333         while (pos != len) {
 334                 // work out how much to send this time
 335                 tx_size = len - pos;
 336                 if (tx_size > 0x10)
 337                         tx_size = 0x10;
 338
 339                 // send the chunk
 340                 memcpy(buf + 1, mem + pos, tx_size);
 341                 fw_msg.len = tx_size + 1;
 342                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 343                         printk(KERN_ERR "tda1004x: Error during firmware upload\n");
 344                         return -EIO;
 345                 }
 346                 pos += tx_size;
 347
 348                 dprintk("%s: fw_pos=0x%x\n", __func__, pos);
 349         }
 350         // give the DSP a chance to settle 03/10/05 Hac
 351         msleep(100);
 352
 353         return 0;
 354 }
 355
 356 static int tda1004x_check_upload_ok(struct tda1004x_state *state)
 357 {
 358         u8 data1, data2;
 359         unsigned long timeout;
 360
 361         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 362                 timeout = jiffies + 2 * HZ;
 363                 while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 364                         if (time_after(jiffies, timeout)) {
 365                                 printk(KERN_ERR "tda1004x: timeout waiting for DSP ready\n");
 366                                 break;
 367                         }
 368                         msleep(1);
 369                 }
 370         } else
 371                 msleep(100);
 372
 373         // check upload was OK
 374         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 375         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 376
 377         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 378         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 379         if (data1 != 0x67 || data2 < 0x20 || data2 > 0x2e) {
 380                 printk(KERN_INFO "tda1004x: found firmware revision %x -- invalid\n", data2);
 381                 return -EIO;
 382         }
 383         printk(KERN_INFO "tda1004x: found firmware revision %x -- ok\n", data2);
 384         return 0;
 385 }
 386
 387 static int tda10045_fwupload(struct dvb_frontend* fe)
 388 {
 389         struct tda1004x_state* state = fe->demodulator_priv;
 390         int ret;
 391         const struct firmware *fw;
 392
 393         /* don't re-upload unless necessary */
 394         if (tda1004x_check_upload_ok(state) == 0)
 395                 return 0;
 396
 397         /* request the firmware, this will block until someone uploads it */
 398         printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 399         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 400         if (ret) {
 401                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 402                 return ret;
 403         }
 404
 405         /* reset chip */
 406         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 407         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 408         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 409         msleep(10);
 410
 411         /* set parameters */
 412         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 413
 414         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 415         release_firmware(fw);
 416         if (ret)
 417                 return ret;
 418         printk(KERN_INFO "tda1004x: firmware upload complete\n");
 419
 420         /* wait for DSP to initialise */
 421         /* DSPREADY doesn't seem to work on the TDA10045H */
 422         msleep(100);
 423
 424         return tda1004x_check_upload_ok(state);
 425 }
 426
 427 static void tda10046_init_plls(struct dvb_frontend* fe)
 428 {
 429         struct tda1004x_state* state = fe->demodulator_priv;
 430         int tda10046_clk53m;
 431
 432         if ((state->config->if_freq == TDA10046_FREQ_045) ||
 433             (state->config->if_freq == TDA10046_FREQ_052))
 434                 tda10046_clk53m = 0;
 435         else
 436                 tda10046_clk53m = 1;
 437
 438         tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
 439         if(tda10046_clk53m) {
 440                 printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n");
 441                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
 442         } else {
 443                 printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n");
 444                 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
 445         }
 446         if (state->config->xtal_freq == TDA10046_XTAL_4M ) {
 447                 dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __func__);
 448                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 449         } else {
 450                 dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __func__);
 451                 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
 452         }
 453         if(tda10046_clk53m)
 454                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
 455         else
 456                 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
 457         /* Note clock frequency is handled implicitly */
 458         switch (state->config->if_freq) {
 459         case TDA10046_FREQ_045:
 460                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
 461                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
 462                 break;
 463         case TDA10046_FREQ_052:
 464                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
 465                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
 466                 break;
 467         case TDA10046_FREQ_3617:
 468                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 469                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
 470                 break;
 471         case TDA10046_FREQ_3613:
 472                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
 473                 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
 474                 break;
 475         }
 476         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 477         /* let the PLLs settle */
 478         msleep(120);
 479 }
 480
 481 static int tda10046_fwupload(struct dvb_frontend* fe)
 482 {
 483         struct tda1004x_state* state = fe->demodulator_priv;
 484         int ret;
 485         const struct firmware *fw;
 486
 487         /* reset + wake up chip */
 488         if (state->config->xtal_freq == TDA10046_XTAL_4M) {
 489                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0);
 490         } else {
 491                 dprintk("%s: 16MHz Xtal, reducing I2C speed\n", __func__);
 492                 tda1004x_write_byteI(state, TDA1004X_CONFC4, 0x80);
 493         }
 494         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 495         /* set GPIO 1 and 3 */
 496         if (state->config->gpio_config != TDA10046_GPTRI) {
 497                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
 498                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
 499         }
 500         /* let the clocks recover from sleep */
 501         msleep(10);
 502
 503         /* The PLLs need to be reprogrammed after sleep */
 504         tda10046_init_plls(fe);
 505         tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
 506
 507         /* don't re-upload unless necessary */
 508         if (tda1004x_check_upload_ok(state) == 0)
 509                 return 0;
 510
 511         printk(KERN_INFO "tda1004x: trying to boot from eeprom\n");
 512         tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4);
 513         msleep(300);
 514         /* don't re-upload unless necessary */
 515         if (tda1004x_check_upload_ok(state) == 0)
 516                 return 0;
 517
 518         if (state->config->request_firmware != NULL) {
 519                 /* request the firmware, this will block until someone uploads it */
 520                 printk(KERN_INFO "tda1004x: waiting for firmware upload...\n");
 521                 ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 522                 if (ret) {
 523                         /* remain compatible to old bug: try to load with tda10045 image name */
 524                         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 525                         if (ret) {
 526                                 printk(KERN_ERR "tda1004x: no firmware upload (timeout or file not found?)\n");
 527                                 return ret;
 528                         } else {
 529                                 printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n",
 530                                                   TDA10046_DEFAULT_FIRMWARE);
 531                         }
 532                 }
 533         } else {
 534                 printk(KERN_ERR "tda1004x: no request function defined, can't upload from file\n");
 535                 return -EIO;
 536         }
 537         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 538         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 539         release_firmware(fw);
 540         return tda1004x_check_upload_ok(state);
 541 }
 542
 543 static int tda1004x_encode_fec(int fec)
 544 {
 545         // convert known FEC values
 546         switch (fec) {
 547         case FEC_1_2:
 548                 return 0;
 549         case FEC_2_3:
 550                 return 1;
 551         case FEC_3_4:
 552                 return 2;
 553         case FEC_5_6:
 554                 return 3;
 555         case FEC_7_8:
 556                 return 4;
 557         }
 558
 559         // unsupported
 560         return -EINVAL;
 561 }
 562
 563 static int tda1004x_decode_fec(int tdafec)
 564 {
 565         // convert known FEC values
 566         switch (tdafec) {
 567         case 0:
 568                 return FEC_1_2;
 569         case 1:
 570                 return FEC_2_3;
 571         case 2:
 572                 return FEC_3_4;
 573         case 3:
 574                 return FEC_5_6;
 575         case 4:
 576                 return FEC_7_8;
 577         }
 578
 579         // unsupported
 580         return -1;
 581 }
 582
 583 static int tda1004x_write(struct dvb_frontend* fe, u8 *buf, int len)
 584 {
 585         struct tda1004x_state* state = fe->demodulator_priv;
 586
 587         if (len != 2)
 588                 return -EINVAL;
 589
 590         return tda1004x_write_byteI(state, buf[0], buf[1]);
 591 }
 592
 593 static int tda10045_init(struct dvb_frontend* fe)
 594 {
 595         struct tda1004x_state* state = fe->demodulator_priv;
 596
 597         dprintk("%s\n", __func__);
 598
 599         if (tda10045_fwupload(fe)) {
 600                 printk("tda1004x: firmware upload failed\n");
 601                 return -EIO;
 602         }
 603
 604         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 605
 606         // tda setup
 607         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 608         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 609         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 610         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 611         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 612         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 613         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 614         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 615         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 616         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 617         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 618
 619         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 620
 621         return 0;
 622 }
 623
 624 static int tda10046_init(struct dvb_frontend* fe)
 625 {
 626         struct tda1004x_state* state = fe->demodulator_priv;
 627         dprintk("%s\n", __func__);
 628
 629         if (tda10046_fwupload(fe)) {
 630                 printk("tda1004x: firmware upload failed\n");
 631                         return -EIO;
 632         }
 633
 634         // tda setup
 635         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 636         tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87);    // 100 ppm crystal, select HP stream
 637         tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88);      // enable pulse killer
 638
 639         switch (state->config->agc_config) {
 640         case TDA10046_AGC_DEFAULT:
 641                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
 642                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 643                 break;
 644         case TDA10046_AGC_IFO_AUTO_NEG:
 645                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 646                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 647                 break;
 648         case TDA10046_AGC_IFO_AUTO_POS:
 649                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
 650                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00);  // set AGC polarities
 651                 break;
 652         case TDA10046_AGC_TDA827X:
 653                 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02);   // AGC setup
 654                 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70);    // AGC Threshold
 655                 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
 656                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60);  // set AGC polarities
 657                 break;
 658         }
 659         if (state->config->ts_mode == 0) {
 660                 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
 661                 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 662         } else {
 663                 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
 664                 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
 665                                                         state->config->invert_oclk << 4);
 666         }
 667         tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
 668         tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
 669         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 670         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 671         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 672         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 673         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
 674         tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
 675         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 676         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
 677         // tda1004x_write_mask(state, 0x50, 0x80, 0x80);         // handle out of guard echoes
 678
 679         return 0;
 680 }
 681
 682 static int tda1004x_set_fe(struct dvb_frontend* fe,
 683                            struct dvb_frontend_parameters *fe_params)
 684 {
 685         struct tda1004x_state* state = fe->demodulator_priv;
 686         int tmp;
 687         int inversion;
 688
 689         dprintk("%s\n", __func__);
 690
 691         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 692                 // setup auto offset
 693                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 694                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 695                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 696
 697                 // disable agc_conf[2]
 698                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 699         }
 700
 701         // set frequency
 702         if (fe->ops.tuner_ops.set_params) {
 703                 fe->ops.tuner_ops.set_params(fe, fe_params);
 704                 if (fe->ops.i2c_gate_ctrl)
 705                         fe->ops.i2c_gate_ctrl(fe, 0);
 706         }
 707
 708         // Hardcoded to use auto as much as possible on the TDA10045 as it
 709         // is very unreliable if AUTO mode is _not_ used.
 710         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 711                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 712                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 713                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 714         }
 715
 716         // Set standard params.. or put them to auto
 717         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 718                 (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 719                 (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 720                 (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 721                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 722                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 723                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 724                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 725         } else {
 726                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 727
 728                 // set HP FEC
 729                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 730                 if (tmp < 0)
 731                         return tmp;
 732                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 733
 734                 // set LP FEC
 735                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 736                 if (tmp < 0)
 737                         return tmp;
 738                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 739
 740                 // set constellation
 741                 switch (fe_params->u.ofdm.constellation) {
 742                 case QPSK:
 743                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 744                         break;
 745
 746                 case QAM_16:
 747                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 748                         break;
 749
 750                 case QAM_64:
 751                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 752                         break;
 753
 754                 default:
 755                         return -EINVAL;
 756                 }
 757
 758                 // set hierarchy
 759                 switch (fe_params->u.ofdm.hierarchy_information) {
 760                 case HIERARCHY_NONE:
 761                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 762                         break;
 763
 764                 case HIERARCHY_1:
 765                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 766                         break;
 767
 768                 case HIERARCHY_2:
 769                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 770                         break;
 771
 772                 case HIERARCHY_4:
 773                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 774                         break;
 775
 776                 default:
 777                         return -EINVAL;
 778                 }
 779         }
 780
 781         // set bandwidth
 782         switch (state->demod_type) {
 783         case TDA1004X_DEMOD_TDA10045:
 784                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 785                 break;
 786
 787         case TDA1004X_DEMOD_TDA10046:
 788                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 789                 break;
 790         }
 791
 792         // set inversion
 793         inversion = fe_params->inversion;
 794         if (state->config->invert)
 795                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 796         switch (inversion) {
 797         case INVERSION_OFF:
 798                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 799                 break;
 800
 801         case INVERSION_ON:
 802                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 803                 break;
 804
 805         default:
 806                 return -EINVAL;
 807         }
 808
 809         // set guard interval
 810         switch (fe_params->u.ofdm.guard_interval) {
 811         case GUARD_INTERVAL_1_32:
 812                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 813                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 814                 break;
 815
 816         case GUARD_INTERVAL_1_16:
 817                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 818                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 819                 break;
 820
 821         case GUARD_INTERVAL_1_8:
 822                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 823                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 824                 break;
 825
 826         case GUARD_INTERVAL_1_4:
 827                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 828                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 829                 break;
 830
 831         case GUARD_INTERVAL_AUTO:
 832                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 833                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 834                 break;
 835
 836         default:
 837                 return -EINVAL;
 838         }
 839
 840         // set transmission mode
 841         switch (fe_params->u.ofdm.transmission_mode) {
 842         case TRANSMISSION_MODE_2K:
 843                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 844                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 845                 break;
 846
 847         case TRANSMISSION_MODE_8K:
 848                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 849                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 850                 break;
 851
 852         case TRANSMISSION_MODE_AUTO:
 853                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 854                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 855                 break;
 856
 857         default:
 858                 return -EINVAL;
 859         }
 860
 861         // start the lock
 862         switch (state->demod_type) {
 863         case TDA1004X_DEMOD_TDA10045:
 864                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 865                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 866                 break;
 867
 868         case TDA1004X_DEMOD_TDA10046:
 869                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 870                 msleep(1);
 871                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
 872                 break;
 873         }
 874
 875         msleep(10);
 876
 877         return 0;
 878 }
 879
 880 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 881 {
 882         struct tda1004x_state* state = fe->demodulator_priv;
 883
 884         dprintk("%s\n", __func__);
 885
 886         // inversion status
 887         fe_params->inversion = INVERSION_OFF;
 888         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 889                 fe_params->inversion = INVERSION_ON;
 890         if (state->config->invert)
 891                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 892
 893         // bandwidth
 894         switch (state->demod_type) {
 895         case TDA1004X_DEMOD_TDA10045:
 896                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 897                 case 0x14:
 898                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 899                         break;
 900                 case 0xdb:
 901                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 902                         break;
 903                 case 0x4f:
 904                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 905                         break;
 906                 }
 907                 break;
 908         case TDA1004X_DEMOD_TDA10046:
 909                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 910                 case 0x5c:
 911                 case 0x54:
 912                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 913                         break;
 914                 case 0x6a:
 915                 case 0x60:
 916                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 917                         break;
 918                 case 0x7b:
 919                 case 0x70:
 920                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 921                         break;
 922                 }
 923                 break;
 924         }
 925
 926         // FEC
 927         fe_params->u.ofdm.code_rate_HP =
 928             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 929         fe_params->u.ofdm.code_rate_LP =
 930             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 931
 932         // constellation
 933         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 934         case 0:
 935                 fe_params->u.ofdm.constellation = QPSK;
 936                 break;
 937         case 1:
 938                 fe_params->u.ofdm.constellation = QAM_16;
 939                 break;
 940         case 2:
 941                 fe_params->u.ofdm.constellation = QAM_64;
 942                 break;
 943         }
 944
 945         // transmission mode
 946         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 947         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 948                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 949
 950         // guard interval
 951         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 952         case 0:
 953                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 954                 break;
 955         case 1:
 956                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 957                 break;
 958         case 2:
 959                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 960                 break;
 961         case 3:
 962                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 963                 break;
 964         }
 965
 966         // hierarchy
 967         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 968         case 0:
 969                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 970                 break;
 971         case 1:
 972                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 973                 break;
 974         case 2:
 975                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 976                 break;
 977         case 3:
 978                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 979                 break;
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 986 {
 987         struct tda1004x_state* state = fe->demodulator_priv;
 988         int status;
 989         int cber;
 990         int vber;
 991
 992         dprintk("%s\n", __func__);
 993
 994         // read status
 995         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 996         if (status == -1)
 997                 return -EIO;
 998
 999         // decode
1000         *fe_status = 0;
1001         if (status & 4)
1002                 *fe_status |= FE_HAS_SIGNAL;
1003         if (status & 2)
1004                 *fe_status |= FE_HAS_CARRIER;
1005         if (status & 8)
1006                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1007
1008         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1009         // is getting anything valid
1010         if (!(*fe_status & FE_HAS_VITERBI)) {
1011                 // read the CBER
1012                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1013                 if (cber == -1)
1014                         return -EIO;
1015                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1016                 if (status == -1)
1017                         return -EIO;
1018                 cber |= (status << 8);
1019                 // The address 0x20 should be read to cope with a TDA10046 bug
1020                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1021
1022                 if (cber != 65535)
1023                         *fe_status |= FE_HAS_VITERBI;
1024         }
1025
1026         // if we DO have some valid VITERBI output, but don't already have SYNC
1027         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1028         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1029                 // read the VBER
1030                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
1031                 if (vber == -1)
1032                         return -EIO;
1033                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
1034                 if (status == -1)
1035                         return -EIO;
1036                 vber |= (status << 8);
1037                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
1038                 if (status == -1)
1039                         return -EIO;
1040                 vber |= (status & 0x0f) << 16;
1041                 // The CVBER_LUT should be read to cope with TDA10046 hardware bug
1042                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
1043
1044                 // if RS has passed some valid TS packets, then we must be
1045                 // getting some SYNC bytes
1046                 if (vber < 16632)
1047                         *fe_status |= FE_HAS_SYNC;
1048         }
1049
1050         // success
1051         dprintk("%s: fe_status=0x%x\n", __func__, *fe_status);
1052         return 0;
1053 }
1054
1055 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
1056 {
1057         struct tda1004x_state* state = fe->demodulator_priv;
1058         int tmp;
1059         int reg = 0;
1060
1061         dprintk("%s\n", __func__);
1062
1063         // determine the register to use
1064         switch (state->demod_type) {
1065         case TDA1004X_DEMOD_TDA10045:
1066                 reg = TDA10045H_S_AGC;
1067                 break;
1068
1069         case TDA1004X_DEMOD_TDA10046:
1070                 reg = TDA10046H_AGC_IF_LEVEL;
1071                 break;
1072         }
1073
1074         // read it
1075         tmp = tda1004x_read_byte(state, reg);
1076         if (tmp < 0)
1077                 return -EIO;
1078
1079         *signal = (tmp << 8) | tmp;
1080         dprintk("%s: signal=0x%x\n", __func__, *signal);
1081         return 0;
1082 }
1083
1084 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1085 {
1086         struct tda1004x_state* state = fe->demodulator_priv;
1087         int tmp;
1088
1089         dprintk("%s\n", __func__);
1090
1091         // read it
1092         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1093         if (tmp < 0)
1094                 return -EIO;
1095         tmp = 255 - tmp;
1096
1097         *snr = ((tmp << 8) | tmp);
1098         dprintk("%s: snr=0x%x\n", __func__, *snr);
1099         return 0;
1100 }
1101
1102 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1103 {
1104         struct tda1004x_state* state = fe->demodulator_priv;
1105         int tmp;
1106         int tmp2;
1107         int counter;
1108
1109         dprintk("%s\n", __func__);
1110
1111         // read the UCBLOCKS and reset
1112         counter = 0;
1113         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1114         if (tmp < 0)
1115                 return -EIO;
1116         tmp &= 0x7f;
1117         while (counter++ < 5) {
1118                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1119                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1120                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1121
1122                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1123                 if (tmp2 < 0)
1124                         return -EIO;
1125                 tmp2 &= 0x7f;
1126                 if ((tmp2 < tmp) || (tmp2 == 0))
1127                         break;
1128         }
1129
1130         if (tmp != 0x7f)
1131                 *ucblocks = tmp;
1132         else
1133                 *ucblocks = 0xffffffff;
1134
1135         dprintk("%s: ucblocks=0x%x\n", __func__, *ucblocks);
1136         return 0;
1137 }
1138
1139 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1140 {
1141         struct tda1004x_state* state = fe->demodulator_priv;
1142         int tmp;
1143
1144         dprintk("%s\n", __func__);
1145
1146         // read it in
1147         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1148         if (tmp < 0)
1149                 return -EIO;
1150         *ber = tmp << 1;
1151         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1152         if (tmp < 0)
1153                 return -EIO;
1154         *ber |= (tmp << 9);
1155         // The address 0x20 should be read to cope with a TDA10046 bug
1156         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1157
1158         dprintk("%s: ber=0x%x\n", __func__, *ber);
1159         return 0;
1160 }
1161
1162 static int tda1004x_sleep(struct dvb_frontend* fe)
1163 {
1164         struct tda1004x_state* state = fe->demodulator_priv;
1165         int gpio_conf;
1166
1167         switch (state->demod_type) {
1168         case TDA1004X_DEMOD_TDA10045:
1169                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1170                 break;
1171
1172         case TDA1004X_DEMOD_TDA10046:
1173                 /* set outputs to tristate */
1174                 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);
1175                 /* invert GPIO 1 and 3 if desired*/
1176                 gpio_conf = state->config->gpio_config;
1177                 if (gpio_conf >= TDA10046_GP00_I)
1178                         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1179                                                         (gpio_conf & 0x0f) ^ 0x0a);
1180
1181                 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1182                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1183                 break;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int tda1004x_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
1190 {
1191         struct tda1004x_state* state = fe->demodulator_priv;
1192
1193         if (enable) {
1194                 return tda1004x_enable_tuner_i2c(state);
1195         } else {
1196                 return tda1004x_disable_tuner_i2c(state);
1197         }
1198 }
1199
1200 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1201 {
1202         fesettings->min_delay_ms = 800;
1203         /* Drift compensation makes no sense for DVB-T */
1204         fesettings->step_size = 0;
1205         fesettings->max_drift = 0;
1206         return 0;
1207 }
1208
1209 static void tda1004x_release(struct dvb_frontend* fe)
1210 {
1211         struct tda1004x_state *state = fe->demodulator_priv;
1212         kfree(state);
1213 }
1214
1215 static struct dvb_frontend_ops tda10045_ops = {
1216         .info = {
1217                 .name = "Philips TDA10045H DVB-T",
1218                 .type = FE_OFDM,
1219                 .frequency_min = 51000000,
1220                 .frequency_max = 858000000,
1221                 .frequency_stepsize = 166667,
1222                 .caps =
1223                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1224                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1225                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1226                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1227         },
1228
1229         .release = tda1004x_release,
1230
1231         .init = tda10045_init,
1232         .sleep = tda1004x_sleep,
1233         .write = tda1004x_write,
1234         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1235
1236         .set_frontend = tda1004x_set_fe,
1237         .get_frontend = tda1004x_get_fe,
1238         .get_tune_settings = tda1004x_get_tune_settings,
1239
1240         .read_status = tda1004x_read_status,
1241         .read_ber = tda1004x_read_ber,
1242         .read_signal_strength = tda1004x_read_signal_strength,
1243         .read_snr = tda1004x_read_snr,
1244         .read_ucblocks = tda1004x_read_ucblocks,
1245 };
1246
1247 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1248                                      struct i2c_adapter* i2c)
1249 {
1250         struct tda1004x_state *state;
1251         int id;
1252
1253         /* allocate memory for the internal state */
1254         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1255         if (!state) {
1256                 printk(KERN_ERR "Can't alocate memory for tda10045 state\n");
1257                 return NULL;
1258         }
1259
1260         /* setup the state */
1261         state->config = config;
1262         state->i2c = i2c;
1263         state->demod_type = TDA1004X_DEMOD_TDA10045;
1264
1265         /* check if the demod is there */
1266         id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1267         if (id < 0) {
1268                 printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n");
1269                 kfree(state);
1270                 return NULL;
1271         }
1272
1273         if (id != 0x25) {
1274                 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1275                 kfree(state);
1276                 return NULL;
1277         }
1278
1279         /* create dvb_frontend */
1280         memcpy(&state->frontend.ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1281         state->frontend.demodulator_priv = state;
1282         return &state->frontend;
1283 }
1284
1285 static struct dvb_frontend_ops tda10046_ops = {
1286         .info = {
1287                 .name = "Philips TDA10046H DVB-T",
1288                 .type = FE_OFDM,
1289                 .frequency_min = 51000000,
1290                 .frequency_max = 858000000,
1291                 .frequency_stepsize = 166667,
1292                 .caps =
1293                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1294                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1295                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1296                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1297         },
1298
1299         .release = tda1004x_release,
1300
1301         .init = tda10046_init,
1302         .sleep = tda1004x_sleep,
1303         .write = tda1004x_write,
1304         .i2c_gate_ctrl = tda1004x_i2c_gate_ctrl,
1305
1306         .set_frontend = tda1004x_set_fe,
1307         .get_frontend = tda1004x_get_fe,
1308         .get_tune_settings = tda1004x_get_tune_settings,
1309
1310         .read_status = tda1004x_read_status,
1311         .read_ber = tda1004x_read_ber,
1312         .read_signal_strength = tda1004x_read_signal_strength,
1313         .read_snr = tda1004x_read_snr,
1314         .read_ucblocks = tda1004x_read_ucblocks,
1315 };
1316
1317 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1318                                      struct i2c_adapter* i2c)
1319 {
1320         struct tda1004x_state *state;
1321         int id;
1322
1323         /* allocate memory for the internal state */
1324         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1325         if (!state) {
1326                 printk(KERN_ERR "Can't alocate memory for tda10046 state\n");
1327                 return NULL;
1328         }
1329
1330         /* setup the state */
1331         state->config = config;
1332         state->i2c = i2c;
1333         state->demod_type = TDA1004X_DEMOD_TDA10046;
1334
1335         /* check if the demod is there */
1336         id = tda1004x_read_byte(state, TDA1004X_CHIPID);
1337         if (id < 0) {
1338                 printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n");
1339                 kfree(state);
1340                 return NULL;
1341         }
1342         if (id != 0x46) {
1343                 printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id);
1344                 kfree(state);
1345                 return NULL;
1346         }
1347
1348         /* create dvb_frontend */
1349         memcpy(&state->frontend.ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1350         state->frontend.demodulator_priv = state;
1351         return &state->frontend;
1352 }
1353
1354 module_param(debug, int, 0644);
1355 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1356
1357 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1358 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1359 MODULE_LICENSE("GPL");
1360
1361 EXPORT_SYMBOL(tda10045_attach);
1362 EXPORT_SYMBOL(tda10046_attach);