drivers/media/dvb-frontends/drxk_hard.c

   1 /*
   2  * drxk_hard: DRX-K DVB-C/T demodulator driver
   3  *
   4  * Copyright (C) 2010-2011 Digital Devices GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <linux/hardirq.h>
  32 #include <asm/div64.h>
  33
  34 #include "dvb_frontend.h"
  35 #include "drxk.h"
  36 #include "drxk_hard.h"
  37 #include "dvb_math.h"
  38
  39 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
  40 static int power_down_qam(struct drxk_state *state);
  41 static int set_dvbt_standard(struct drxk_state *state,
  42                            enum operation_mode o_mode);
  43 static int set_qam_standard(struct drxk_state *state,
  44                           enum operation_mode o_mode);
  45 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
  46                   s32 tuner_freq_offset);
  47 static int set_dvbt_standard(struct drxk_state *state,
  48                            enum operation_mode o_mode);
  49 static int dvbt_start(struct drxk_state *state);
  50 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
  51                    s32 tuner_freq_offset);
  52 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
  53 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
  54 static int switch_antenna_to_qam(struct drxk_state *state);
  55 static int switch_antenna_to_dvbt(struct drxk_state *state);
  56
  57 static bool is_dvbt(struct drxk_state *state)
  58 {
  59         return state->m_operation_mode == OM_DVBT;
  60 }
  61
  62 static bool is_qam(struct drxk_state *state)
  63 {
  64         return state->m_operation_mode == OM_QAM_ITU_A ||
  65             state->m_operation_mode == OM_QAM_ITU_B ||
  66             state->m_operation_mode == OM_QAM_ITU_C;
  67 }
  68
  69 #define NOA1ROM 0
  70
  71 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
  72 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
  73
  74 #define DEFAULT_MER_83  165
  75 #define DEFAULT_MER_93  250
  76
  77 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
  78 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
  79 #endif
  80
  81 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
  82 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
  83 #endif
  84
  85 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
  86 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
  87
  88 #ifndef DRXK_KI_RAGC_ATV
  89 #define DRXK_KI_RAGC_ATV   4
  90 #endif
  91 #ifndef DRXK_KI_IAGC_ATV
  92 #define DRXK_KI_IAGC_ATV   6
  93 #endif
  94 #ifndef DRXK_KI_DAGC_ATV
  95 #define DRXK_KI_DAGC_ATV   7
  96 #endif
  97
  98 #ifndef DRXK_KI_RAGC_QAM
  99 #define DRXK_KI_RAGC_QAM   3
 100 #endif
 101 #ifndef DRXK_KI_IAGC_QAM
 102 #define DRXK_KI_IAGC_QAM   4
 103 #endif
 104 #ifndef DRXK_KI_DAGC_QAM
 105 #define DRXK_KI_DAGC_QAM   7
 106 #endif
 107 #ifndef DRXK_KI_RAGC_DVBT
 108 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
 109 #endif
 110 #ifndef DRXK_KI_IAGC_DVBT
 111 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
 112 #endif
 113 #ifndef DRXK_KI_DAGC_DVBT
 114 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
 115 #endif
 116
 117 #ifndef DRXK_AGC_DAC_OFFSET
 118 #define DRXK_AGC_DAC_OFFSET (0x800)
 119 #endif
 120
 121 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
 122 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
 123 #endif
 124
 125 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
 126 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
 127 #endif
 128
 129 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
 130 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
 131 #endif
 132
 133 #ifndef DRXK_QAM_SYMBOLRATE_MAX
 134 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
 135 #endif
 136
 137 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
 138 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
 139 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
 140 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
 141 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
 142 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
 143 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
 144 #define DRXK_BL_ROM_OFFSET_UCODE        0
 145
 146 #define DRXK_BLC_TIMEOUT                100
 147
 148 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
 149 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
 150
 151 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
 152
 153 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
 154 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
 155 #endif
 156
 157 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
 158 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
 159 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
 160 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
 161 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
 162
 163 static unsigned int debug;
 164 module_param(debug, int, 0644);
 165 MODULE_PARM_DESC(debug, "enable debug messages");
 166
 167 #define dprintk(level, fmt, arg...) do {                        \
 168 if (debug >= level)                                             \
 169         printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg);    \
 170 } while (0)
 171
 172
 173 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 174 {
 175         u64 tmp64;
 176
 177         tmp64 = (u64) a * (u64) b;
 178         do_div(tmp64, c);
 179
 180         return (u32) tmp64;
 181 }
 182
 183 static inline u32 Frac28a(u32 a, u32 c)
 184 {
 185         int i = 0;
 186         u32 Q1 = 0;
 187         u32 R0 = 0;
 188
 189         R0 = (a % c) << 4;      /* 32-28 == 4 shifts possible at max */
 190         Q1 = a / c;             /* integer part, only the 4 least significant bits
 191                                    will be visible in the result */
 192
 193         /* division using radix 16, 7 nibbles in the result */
 194         for (i = 0; i < 7; i++) {
 195                 Q1 = (Q1 << 4) | (R0 / c);
 196                 R0 = (R0 % c) << 4;
 197         }
 198         /* rounding */
 199         if ((R0 >> 3) >= c)
 200                 Q1++;
 201
 202         return Q1;
 203 }
 204
 205 static inline u32 log10times100(u32 value)
 206 {
 207         return (100L * intlog10(value)) >> 24;
 208 }
 209
 210 /****************************************************************************/
 211 /* I2C **********************************************************************/
 212 /****************************************************************************/
 213
 214 static int drxk_i2c_lock(struct drxk_state *state)
 215 {
 216         i2c_lock_adapter(state->i2c);
 217         state->drxk_i2c_exclusive_lock = true;
 218
 219         return 0;
 220 }
 221
 222 static void drxk_i2c_unlock(struct drxk_state *state)
 223 {
 224         if (!state->drxk_i2c_exclusive_lock)
 225                 return;
 226
 227         i2c_unlock_adapter(state->i2c);
 228         state->drxk_i2c_exclusive_lock = false;
 229 }
 230
 231 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
 232                              unsigned len)
 233 {
 234         if (state->drxk_i2c_exclusive_lock)
 235                 return __i2c_transfer(state->i2c, msgs, len);
 236         else
 237                 return i2c_transfer(state->i2c, msgs, len);
 238 }
 239
 240 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
 241 {
 242         struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
 243                                     .buf = val, .len = 1}
 244         };
 245
 246         return drxk_i2c_transfer(state, msgs, 1);
 247 }
 248
 249 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
 250 {
 251         int status;
 252         struct i2c_msg msg = {
 253             .addr = adr, .flags = 0, .buf = data, .len = len };
 254
 255         dprintk(3, ":");
 256         if (debug > 2) {
 257                 int i;
 258                 for (i = 0; i < len; i++)
 259                         printk(KERN_CONT " %02x", data[i]);
 260                 printk(KERN_CONT "\n");
 261         }
 262         status = drxk_i2c_transfer(state, &msg, 1);
 263         if (status >= 0 && status != 1)
 264                 status = -EIO;
 265
 266         if (status < 0)
 267                 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
 268
 269         return status;
 270 }
 271
 272 static int i2c_read(struct drxk_state *state,
 273                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 274 {
 275         int status;
 276         struct i2c_msg msgs[2] = {
 277                 {.addr = adr, .flags = 0,
 278                                     .buf = msg, .len = len},
 279                 {.addr = adr, .flags = I2C_M_RD,
 280                  .buf = answ, .len = alen}
 281         };
 282
 283         status = drxk_i2c_transfer(state, msgs, 2);
 284         if (status != 2) {
 285                 if (debug > 2)
 286                         printk(KERN_CONT ": ERROR!\n");
 287                 if (status >= 0)
 288                         status = -EIO;
 289
 290                 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
 291                 return status;
 292         }
 293         if (debug > 2) {
 294                 int i;
 295                 dprintk(2, ": read from");
 296                 for (i = 0; i < len; i++)
 297                         printk(KERN_CONT " %02x", msg[i]);
 298                 printk(KERN_CONT ", value = ");
 299                 for (i = 0; i < alen; i++)
 300                         printk(KERN_CONT " %02x", answ[i]);
 301                 printk(KERN_CONT "\n");
 302         }
 303         return 0;
 304 }
 305
 306 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
 307 {
 308         int status;
 309         u8 adr = state->demod_address, mm1[4], mm2[2], len;
 310
 311         if (state->single_master)
 312                 flags |= 0xC0;
 313
 314         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 315                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 316                 mm1[1] = ((reg >> 16) & 0xFF);
 317                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 318                 mm1[3] = ((reg >> 7) & 0xFF);
 319                 len = 4;
 320         } else {
 321                 mm1[0] = ((reg << 1) & 0xFF);
 322                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 323                 len = 2;
 324         }
 325         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 326         status = i2c_read(state, adr, mm1, len, mm2, 2);
 327         if (status < 0)
 328                 return status;
 329         if (data)
 330                 *data = mm2[0] | (mm2[1] << 8);
 331
 332         return 0;
 333 }
 334
 335 static int read16(struct drxk_state *state, u32 reg, u16 *data)
 336 {
 337         return read16_flags(state, reg, data, 0);
 338 }
 339
 340 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
 341 {
 342         int status;
 343         u8 adr = state->demod_address, mm1[4], mm2[4], len;
 344
 345         if (state->single_master)
 346                 flags |= 0xC0;
 347
 348         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 349                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 350                 mm1[1] = ((reg >> 16) & 0xFF);
 351                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 352                 mm1[3] = ((reg >> 7) & 0xFF);
 353                 len = 4;
 354         } else {
 355                 mm1[0] = ((reg << 1) & 0xFF);
 356                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 357                 len = 2;
 358         }
 359         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 360         status = i2c_read(state, adr, mm1, len, mm2, 4);
 361         if (status < 0)
 362                 return status;
 363         if (data)
 364                 *data = mm2[0] | (mm2[1] << 8) |
 365                     (mm2[2] << 16) | (mm2[3] << 24);
 366
 367         return 0;
 368 }
 369
 370 static int read32(struct drxk_state *state, u32 reg, u32 *data)
 371 {
 372         return read32_flags(state, reg, data, 0);
 373 }
 374
 375 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
 376 {
 377         u8 adr = state->demod_address, mm[6], len;
 378
 379         if (state->single_master)
 380                 flags |= 0xC0;
 381         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 382                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 383                 mm[1] = ((reg >> 16) & 0xFF);
 384                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 385                 mm[3] = ((reg >> 7) & 0xFF);
 386                 len = 4;
 387         } else {
 388                 mm[0] = ((reg << 1) & 0xFF);
 389                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 390                 len = 2;
 391         }
 392         mm[len] = data & 0xff;
 393         mm[len + 1] = (data >> 8) & 0xff;
 394
 395         dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
 396         return i2c_write(state, adr, mm, len + 2);
 397 }
 398
 399 static int write16(struct drxk_state *state, u32 reg, u16 data)
 400 {
 401         return write16_flags(state, reg, data, 0);
 402 }
 403
 404 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
 405 {
 406         u8 adr = state->demod_address, mm[8], len;
 407
 408         if (state->single_master)
 409                 flags |= 0xC0;
 410         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 411                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 412                 mm[1] = ((reg >> 16) & 0xFF);
 413                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 414                 mm[3] = ((reg >> 7) & 0xFF);
 415                 len = 4;
 416         } else {
 417                 mm[0] = ((reg << 1) & 0xFF);
 418                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 419                 len = 2;
 420         }
 421         mm[len] = data & 0xff;
 422         mm[len + 1] = (data >> 8) & 0xff;
 423         mm[len + 2] = (data >> 16) & 0xff;
 424         mm[len + 3] = (data >> 24) & 0xff;
 425         dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
 426
 427         return i2c_write(state, adr, mm, len + 4);
 428 }
 429
 430 static int write32(struct drxk_state *state, u32 reg, u32 data)
 431 {
 432         return write32_flags(state, reg, data, 0);
 433 }
 434
 435 static int write_block(struct drxk_state *state, u32 address,
 436                       const int block_size, const u8 p_block[])
 437 {
 438         int status = 0, blk_size = block_size;
 439         u8 flags = 0;
 440
 441         if (state->single_master)
 442                 flags |= 0xC0;
 443
 444         while (blk_size > 0) {
 445                 int chunk = blk_size > state->m_chunk_size ?
 446                     state->m_chunk_size : blk_size;
 447                 u8 *adr_buf = &state->chunk[0];
 448                 u32 adr_length = 0;
 449
 450                 if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) {
 451                         adr_buf[0] = (((address << 1) & 0xFF) | 0x01);
 452                         adr_buf[1] = ((address >> 16) & 0xFF);
 453                         adr_buf[2] = ((address >> 24) & 0xFF);
 454                         adr_buf[3] = ((address >> 7) & 0xFF);
 455                         adr_buf[2] |= flags;
 456                         adr_length = 4;
 457                         if (chunk == state->m_chunk_size)
 458                                 chunk -= 2;
 459                 } else {
 460                         adr_buf[0] = ((address << 1) & 0xFF);
 461                         adr_buf[1] = (((address >> 16) & 0x0F) |
 462                                      ((address >> 18) & 0xF0));
 463                         adr_length = 2;
 464                 }
 465                 memcpy(&state->chunk[adr_length], p_block, chunk);
 466                 dprintk(2, "(0x%08x, 0x%02x)\n", address, flags);
 467                 if (debug > 1) {
 468                         int i;
 469                         if (p_block)
 470                                 for (i = 0; i < chunk; i++)
 471                                         printk(KERN_CONT " %02x", p_block[i]);
 472                         printk(KERN_CONT "\n");
 473                 }
 474                 status = i2c_write(state, state->demod_address,
 475                                    &state->chunk[0], chunk + adr_length);
 476                 if (status < 0) {
 477                         printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
 478                                __func__, address);
 479                         break;
 480                 }
 481                 p_block += chunk;
 482                 address += (chunk >> 1);
 483                 blk_size -= chunk;
 484         }
 485         return status;
 486 }
 487
 488 #ifndef DRXK_MAX_RETRIES_POWERUP
 489 #define DRXK_MAX_RETRIES_POWERUP 20
 490 #endif
 491
 492 static int power_up_device(struct drxk_state *state)
 493 {
 494         int status;
 495         u8 data = 0;
 496         u16 retry_count = 0;
 497
 498         dprintk(1, "\n");
 499
 500         status = i2c_read1(state, state->demod_address, &data);
 501         if (status < 0) {
 502                 do {
 503                         data = 0;
 504                         status = i2c_write(state, state->demod_address,
 505                                            &data, 1);
 506                         msleep(10);
 507                         retry_count++;
 508                         if (status < 0)
 509                                 continue;
 510                         status = i2c_read1(state, state->demod_address,
 511                                            &data);
 512                 } while (status < 0 &&
 513                          (retry_count < DRXK_MAX_RETRIES_POWERUP));
 514                 if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)
 515                         goto error;
 516         }
 517
 518         /* Make sure all clk domains are active */
 519         status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
 520         if (status < 0)
 521                 goto error;
 522         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
 523         if (status < 0)
 524                 goto error;
 525         /* Enable pll lock tests */
 526         status = write16(state, SIO_CC_PLL_LOCK__A, 1);
 527         if (status < 0)
 528                 goto error;
 529
 530         state->m_current_power_mode = DRX_POWER_UP;
 531
 532 error:
 533         if (status < 0)
 534                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
 535
 536         return status;
 537 }
 538
 539
 540 static int init_state(struct drxk_state *state)
 541 {
 542         /*
 543          * FIXME: most (all?) of the values bellow should be moved into
 544          * struct drxk_config, as they are probably board-specific
 545          */
 546         u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO;
 547         u32 ul_vsb_if_agc_output_level = 0;
 548         u32 ul_vsb_if_agc_min_level = 0;
 549         u32 ul_vsb_if_agc_max_level = 0x7FFF;
 550         u32 ul_vsb_if_agc_speed = 3;
 551
 552         u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO;
 553         u32 ul_vsb_rf_agc_output_level = 0;
 554         u32 ul_vsb_rf_agc_min_level = 0;
 555         u32 ul_vsb_rf_agc_max_level = 0x7FFF;
 556         u32 ul_vsb_rf_agc_speed = 3;
 557         u32 ul_vsb_rf_agc_top = 9500;
 558         u32 ul_vsb_rf_agc_cut_off_current = 4000;
 559
 560         u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO;
 561         u32 ul_atv_if_agc_output_level = 0;
 562         u32 ul_atv_if_agc_min_level = 0;
 563         u32 ul_atv_if_agc_max_level = 0;
 564         u32 ul_atv_if_agc_speed = 3;
 565
 566         u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF;
 567         u32 ul_atv_rf_agc_output_level = 0;
 568         u32 ul_atv_rf_agc_min_level = 0;
 569         u32 ul_atv_rf_agc_max_level = 0;
 570         u32 ul_atv_rf_agc_top = 9500;
 571         u32 ul_atv_rf_agc_cut_off_current = 4000;
 572         u32 ul_atv_rf_agc_speed = 3;
 573
 574         u32 ulQual83 = DEFAULT_MER_83;
 575         u32 ulQual93 = DEFAULT_MER_93;
 576
 577         u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 578         u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 579
 580         /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
 581         /* io_pad_cfg_mode output mode is drive always */
 582         /* io_pad_cfg_drive is set to power 2 (23 mA) */
 583         u32 ul_gpio_cfg = 0x0113;
 584         u32 ul_invert_ts_clock = 0;
 585         u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
 586         u32 ul_dvbt_bitrate = 50000000;
 587         u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
 588
 589         u32 ul_insert_rs_byte = 0;
 590
 591         u32 ul_rf_mirror = 1;
 592         u32 ul_power_down = 0;
 593
 594         dprintk(1, "\n");
 595
 596         state->m_has_lna = false;
 597         state->m_has_dvbt = false;
 598         state->m_has_dvbc = false;
 599         state->m_has_atv = false;
 600         state->m_has_oob = false;
 601         state->m_has_audio = false;
 602
 603         if (!state->m_chunk_size)
 604                 state->m_chunk_size = 124;
 605
 606         state->m_osc_clock_freq = 0;
 607         state->m_smart_ant_inverted = false;
 608         state->m_b_p_down_open_bridge = false;
 609
 610         /* real system clock frequency in kHz */
 611         state->m_sys_clock_freq = 151875;
 612         /* Timing div, 250ns/Psys */
 613         /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
 614         state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
 615                                    HI_I2C_DELAY) / 1000;
 616         /* Clipping */
 617         if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
 618                 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
 619         state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
 620         /* port/bridge/power down ctrl */
 621         state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
 622
 623         state->m_b_power_down = (ul_power_down != 0);
 624
 625         state->m_drxk_a3_patch_code = false;
 626
 627         /* Init AGC and PGA parameters */
 628         /* VSB IF */
 629         state->m_vsb_if_agc_cfg.ctrl_mode = (ul_vsb_if_agc_mode);
 630         state->m_vsb_if_agc_cfg.output_level = (ul_vsb_if_agc_output_level);
 631         state->m_vsb_if_agc_cfg.min_output_level = (ul_vsb_if_agc_min_level);
 632         state->m_vsb_if_agc_cfg.max_output_level = (ul_vsb_if_agc_max_level);
 633         state->m_vsb_if_agc_cfg.speed = (ul_vsb_if_agc_speed);
 634         state->m_vsb_pga_cfg = 140;
 635
 636         /* VSB RF */
 637         state->m_vsb_rf_agc_cfg.ctrl_mode = (ul_vsb_rf_agc_mode);
 638         state->m_vsb_rf_agc_cfg.output_level = (ul_vsb_rf_agc_output_level);
 639         state->m_vsb_rf_agc_cfg.min_output_level = (ul_vsb_rf_agc_min_level);
 640         state->m_vsb_rf_agc_cfg.max_output_level = (ul_vsb_rf_agc_max_level);
 641         state->m_vsb_rf_agc_cfg.speed = (ul_vsb_rf_agc_speed);
 642         state->m_vsb_rf_agc_cfg.top = (ul_vsb_rf_agc_top);
 643         state->m_vsb_rf_agc_cfg.cut_off_current = (ul_vsb_rf_agc_cut_off_current);
 644         state->m_vsb_pre_saw_cfg.reference = 0x07;
 645         state->m_vsb_pre_saw_cfg.use_pre_saw = true;
 646
 647         state->m_Quality83percent = DEFAULT_MER_83;
 648         state->m_Quality93percent = DEFAULT_MER_93;
 649         if (ulQual93 <= 500 && ulQual83 < ulQual93) {
 650                 state->m_Quality83percent = ulQual83;
 651                 state->m_Quality93percent = ulQual93;
 652         }
 653
 654         /* ATV IF */
 655         state->m_atv_if_agc_cfg.ctrl_mode = (ul_atv_if_agc_mode);
 656         state->m_atv_if_agc_cfg.output_level = (ul_atv_if_agc_output_level);
 657         state->m_atv_if_agc_cfg.min_output_level = (ul_atv_if_agc_min_level);
 658         state->m_atv_if_agc_cfg.max_output_level = (ul_atv_if_agc_max_level);
 659         state->m_atv_if_agc_cfg.speed = (ul_atv_if_agc_speed);
 660
 661         /* ATV RF */
 662         state->m_atv_rf_agc_cfg.ctrl_mode = (ul_atv_rf_agc_mode);
 663         state->m_atv_rf_agc_cfg.output_level = (ul_atv_rf_agc_output_level);
 664         state->m_atv_rf_agc_cfg.min_output_level = (ul_atv_rf_agc_min_level);
 665         state->m_atv_rf_agc_cfg.max_output_level = (ul_atv_rf_agc_max_level);
 666         state->m_atv_rf_agc_cfg.speed = (ul_atv_rf_agc_speed);
 667         state->m_atv_rf_agc_cfg.top = (ul_atv_rf_agc_top);
 668         state->m_atv_rf_agc_cfg.cut_off_current = (ul_atv_rf_agc_cut_off_current);
 669         state->m_atv_pre_saw_cfg.reference = 0x04;
 670         state->m_atv_pre_saw_cfg.use_pre_saw = true;
 671
 672
 673         /* DVBT RF */
 674         state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
 675         state->m_dvbt_rf_agc_cfg.output_level = 0;
 676         state->m_dvbt_rf_agc_cfg.min_output_level = 0;
 677         state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
 678         state->m_dvbt_rf_agc_cfg.top = 0x2100;
 679         state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
 680         state->m_dvbt_rf_agc_cfg.speed = 1;
 681
 682
 683         /* DVBT IF */
 684         state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
 685         state->m_dvbt_if_agc_cfg.output_level = 0;
 686         state->m_dvbt_if_agc_cfg.min_output_level = 0;
 687         state->m_dvbt_if_agc_cfg.max_output_level = 9000;
 688         state->m_dvbt_if_agc_cfg.top = 13424;
 689         state->m_dvbt_if_agc_cfg.cut_off_current = 0;
 690         state->m_dvbt_if_agc_cfg.speed = 3;
 691         state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
 692         state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
 693         /* state->m_dvbtPgaCfg = 140; */
 694
 695         state->m_dvbt_pre_saw_cfg.reference = 4;
 696         state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
 697
 698         /* QAM RF */
 699         state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
 700         state->m_qam_rf_agc_cfg.output_level = 0;
 701         state->m_qam_rf_agc_cfg.min_output_level = 6023;
 702         state->m_qam_rf_agc_cfg.max_output_level = 27000;
 703         state->m_qam_rf_agc_cfg.top = 0x2380;
 704         state->m_qam_rf_agc_cfg.cut_off_current = 4000;
 705         state->m_qam_rf_agc_cfg.speed = 3;
 706
 707         /* QAM IF */
 708         state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
 709         state->m_qam_if_agc_cfg.output_level = 0;
 710         state->m_qam_if_agc_cfg.min_output_level = 0;
 711         state->m_qam_if_agc_cfg.max_output_level = 9000;
 712         state->m_qam_if_agc_cfg.top = 0x0511;
 713         state->m_qam_if_agc_cfg.cut_off_current = 0;
 714         state->m_qam_if_agc_cfg.speed = 3;
 715         state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
 716         state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
 717
 718         state->m_qam_pga_cfg = 140;
 719         state->m_qam_pre_saw_cfg.reference = 4;
 720         state->m_qam_pre_saw_cfg.use_pre_saw = false;
 721
 722         state->m_operation_mode = OM_NONE;
 723         state->m_drxk_state = DRXK_UNINITIALIZED;
 724
 725         /* MPEG output configuration */
 726         state->m_enable_mpeg_output = true;     /* If TRUE; enable MPEG ouput */
 727         state->m_insert_rs_byte = false;        /* If TRUE; insert RS byte */
 728         state->m_invert_data = false;   /* If TRUE; invert DATA signals */
 729         state->m_invert_err = false;    /* If TRUE; invert ERR signal */
 730         state->m_invert_str = false;    /* If TRUE; invert STR signals */
 731         state->m_invert_val = false;    /* If TRUE; invert VAL signals */
 732         state->m_invert_clk = (ul_invert_ts_clock != 0);        /* If TRUE; invert CLK signals */
 733
 734         /* If TRUE; static MPEG clockrate will be used;
 735            otherwise clockrate will adapt to the bitrate of the TS */
 736
 737         state->m_dvbt_bitrate = ul_dvbt_bitrate;
 738         state->m_dvbc_bitrate = ul_dvbc_bitrate;
 739
 740         state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
 741
 742         /* Maximum bitrate in b/s in case static clockrate is selected */
 743         state->m_mpeg_ts_static_bitrate = 19392658;
 744         state->m_disable_te_ihandling = false;
 745
 746         if (ul_insert_rs_byte)
 747                 state->m_insert_rs_byte = true;
 748
 749         state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 750         if (ul_mpeg_lock_time_out < 10000)
 751                 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
 752         state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 753         if (ul_demod_lock_time_out < 10000)
 754                 state->m_demod_lock_time_out = ul_demod_lock_time_out;
 755
 756         /* QAM defaults */
 757         state->m_constellation = DRX_CONSTELLATION_AUTO;
 758         state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
 759         state->m_fec_rs_plen = 204 * 8; /* fecRsPlen  annex A */
 760         state->m_fec_rs_prescale = 1;
 761
 762         state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
 763         state->m_agcfast_clip_ctrl_delay = 0;
 764
 765         state->m_gpio_cfg = (ul_gpio_cfg);
 766
 767         state->m_b_power_down = false;
 768         state->m_current_power_mode = DRX_POWER_DOWN;
 769
 770         state->m_rfmirror = (ul_rf_mirror == 0);
 771         state->m_if_agc_pol = false;
 772         return 0;
 773 }
 774
 775 static int drxx_open(struct drxk_state *state)
 776 {
 777         int status = 0;
 778         u32 jtag = 0;
 779         u16 bid = 0;
 780         u16 key = 0;
 781
 782         dprintk(1, "\n");
 783         /* stop lock indicator process */
 784         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 785         if (status < 0)
 786                 goto error;
 787         /* Check device id */
 788         status = read16(state, SIO_TOP_COMM_KEY__A, &key);
 789         if (status < 0)
 790                 goto error;
 791         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 792         if (status < 0)
 793                 goto error;
 794         status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
 795         if (status < 0)
 796                 goto error;
 797         status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
 798         if (status < 0)
 799                 goto error;
 800         status = write16(state, SIO_TOP_COMM_KEY__A, key);
 801 error:
 802         if (status < 0)
 803                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
 804         return status;
 805 }
 806
 807 static int get_device_capabilities(struct drxk_state *state)
 808 {
 809         u16 sio_pdr_ohw_cfg = 0;
 810         u32 sio_top_jtagid_lo = 0;
 811         int status;
 812         const char *spin = "";
 813
 814         dprintk(1, "\n");
 815
 816         /* driver 0.9.0 */
 817         /* stop lock indicator process */
 818         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 819         if (status < 0)
 820                 goto error;
 821         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 822         if (status < 0)
 823                 goto error;
 824         status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
 825         if (status < 0)
 826                 goto error;
 827         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
 828         if (status < 0)
 829                 goto error;
 830
 831         switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
 832         case 0:
 833                 /* ignore (bypass ?) */
 834                 break;
 835         case 1:
 836                 /* 27 MHz */
 837                 state->m_osc_clock_freq = 27000;
 838                 break;
 839         case 2:
 840                 /* 20.25 MHz */
 841                 state->m_osc_clock_freq = 20250;
 842                 break;
 843         case 3:
 844                 /* 4 MHz */
 845                 state->m_osc_clock_freq = 20250;
 846                 break;
 847         default:
 848                 printk(KERN_ERR "drxk: Clock Frequency is unknown\n");
 849                 return -EINVAL;
 850         }
 851         /*
 852                 Determine device capabilities
 853                 Based on pinning v14
 854                 */
 855         status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
 856         if (status < 0)
 857                 goto error;
 858
 859         printk(KERN_INFO "drxk: status = 0x%08x\n", sio_top_jtagid_lo);
 860
 861         /* driver 0.9.0 */
 862         switch ((sio_top_jtagid_lo >> 29) & 0xF) {
 863         case 0:
 864                 state->m_device_spin = DRXK_SPIN_A1;
 865                 spin = "A1";
 866                 break;
 867         case 2:
 868                 state->m_device_spin = DRXK_SPIN_A2;
 869                 spin = "A2";
 870                 break;
 871         case 3:
 872                 state->m_device_spin = DRXK_SPIN_A3;
 873                 spin = "A3";
 874                 break;
 875         default:
 876                 state->m_device_spin = DRXK_SPIN_UNKNOWN;
 877                 status = -EINVAL;
 878                 printk(KERN_ERR "drxk: Spin %d unknown\n",
 879                        (sio_top_jtagid_lo >> 29) & 0xF);
 880                 goto error2;
 881         }
 882         switch ((sio_top_jtagid_lo >> 12) & 0xFF) {
 883         case 0x13:
 884                 /* typeId = DRX3913K_TYPE_ID */
 885                 state->m_has_lna = false;
 886                 state->m_has_oob = false;
 887                 state->m_has_atv = false;
 888                 state->m_has_audio = false;
 889                 state->m_has_dvbt = true;
 890                 state->m_has_dvbc = true;
 891                 state->m_has_sawsw = true;
 892                 state->m_has_gpio2 = false;
 893                 state->m_has_gpio1 = false;
 894                 state->m_has_irqn = false;
 895                 break;
 896         case 0x15:
 897                 /* typeId = DRX3915K_TYPE_ID */
 898                 state->m_has_lna = false;
 899                 state->m_has_oob = false;
 900                 state->m_has_atv = true;
 901                 state->m_has_audio = false;
 902                 state->m_has_dvbt = true;
 903                 state->m_has_dvbc = false;
 904                 state->m_has_sawsw = true;
 905                 state->m_has_gpio2 = true;
 906                 state->m_has_gpio1 = true;
 907                 state->m_has_irqn = false;
 908                 break;
 909         case 0x16:
 910                 /* typeId = DRX3916K_TYPE_ID */
 911                 state->m_has_lna = false;
 912                 state->m_has_oob = false;
 913                 state->m_has_atv = true;
 914                 state->m_has_audio = false;
 915                 state->m_has_dvbt = true;
 916                 state->m_has_dvbc = false;
 917                 state->m_has_sawsw = true;
 918                 state->m_has_gpio2 = true;
 919                 state->m_has_gpio1 = true;
 920                 state->m_has_irqn = false;
 921                 break;
 922         case 0x18:
 923                 /* typeId = DRX3918K_TYPE_ID */
 924                 state->m_has_lna = false;
 925                 state->m_has_oob = false;
 926                 state->m_has_atv = true;
 927                 state->m_has_audio = true;
 928                 state->m_has_dvbt = true;
 929                 state->m_has_dvbc = false;
 930                 state->m_has_sawsw = true;
 931                 state->m_has_gpio2 = true;
 932                 state->m_has_gpio1 = true;
 933                 state->m_has_irqn = false;
 934                 break;
 935         case 0x21:
 936                 /* typeId = DRX3921K_TYPE_ID */
 937                 state->m_has_lna = false;
 938                 state->m_has_oob = false;
 939                 state->m_has_atv = true;
 940                 state->m_has_audio = true;
 941                 state->m_has_dvbt = true;
 942                 state->m_has_dvbc = true;
 943                 state->m_has_sawsw = true;
 944                 state->m_has_gpio2 = true;
 945                 state->m_has_gpio1 = true;
 946                 state->m_has_irqn = false;
 947                 break;
 948         case 0x23:
 949                 /* typeId = DRX3923K_TYPE_ID */
 950                 state->m_has_lna = false;
 951                 state->m_has_oob = false;
 952                 state->m_has_atv = true;
 953                 state->m_has_audio = true;
 954                 state->m_has_dvbt = true;
 955                 state->m_has_dvbc = true;
 956                 state->m_has_sawsw = true;
 957                 state->m_has_gpio2 = true;
 958                 state->m_has_gpio1 = true;
 959                 state->m_has_irqn = false;
 960                 break;
 961         case 0x25:
 962                 /* typeId = DRX3925K_TYPE_ID */
 963                 state->m_has_lna = false;
 964                 state->m_has_oob = false;
 965                 state->m_has_atv = true;
 966                 state->m_has_audio = true;
 967                 state->m_has_dvbt = true;
 968                 state->m_has_dvbc = true;
 969                 state->m_has_sawsw = true;
 970                 state->m_has_gpio2 = true;
 971                 state->m_has_gpio1 = true;
 972                 state->m_has_irqn = false;
 973                 break;
 974         case 0x26:
 975                 /* typeId = DRX3926K_TYPE_ID */
 976                 state->m_has_lna = false;
 977                 state->m_has_oob = false;
 978                 state->m_has_atv = true;
 979                 state->m_has_audio = false;
 980                 state->m_has_dvbt = true;
 981                 state->m_has_dvbc = true;
 982                 state->m_has_sawsw = true;
 983                 state->m_has_gpio2 = true;
 984                 state->m_has_gpio1 = true;
 985                 state->m_has_irqn = false;
 986                 break;
 987         default:
 988                 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
 989                         ((sio_top_jtagid_lo >> 12) & 0xFF));
 990                 status = -EINVAL;
 991                 goto error2;
 992         }
 993
 994         printk(KERN_INFO
 995                "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
 996                ((sio_top_jtagid_lo >> 12) & 0xFF), spin,
 997                state->m_osc_clock_freq / 1000,
 998                state->m_osc_clock_freq % 1000);
 999
1000 error:
1001         if (status < 0)
1002                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1003
1004 error2:
1005         return status;
1006 }
1007
1008 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
1009 {
1010         int status;
1011         bool powerdown_cmd;
1012
1013         dprintk(1, "\n");
1014
1015         /* Write command */
1016         status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1017         if (status < 0)
1018                 goto error;
1019         if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1020                 msleep(1);
1021
1022         powerdown_cmd =
1023             (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1024                     ((state->m_hi_cfg_ctrl) &
1025                      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1026                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1027         if (powerdown_cmd == false) {
1028                 /* Wait until command rdy */
1029                 u32 retry_count = 0;
1030                 u16 wait_cmd;
1031
1032                 do {
1033                         msleep(1);
1034                         retry_count += 1;
1035                         status = read16(state, SIO_HI_RA_RAM_CMD__A,
1036                                           &wait_cmd);
1037                 } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES)
1038                          && (wait_cmd != 0));
1039                 if (status < 0)
1040                         goto error;
1041                 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1042         }
1043 error:
1044         if (status < 0)
1045                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1046
1047         return status;
1048 }
1049
1050 static int hi_cfg_command(struct drxk_state *state)
1051 {
1052         int status;
1053
1054         dprintk(1, "\n");
1055
1056         mutex_lock(&state->mutex);
1057
1058         status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_hi_cfg_timeout);
1059         if (status < 0)
1060                 goto error;
1061         status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_hi_cfg_ctrl);
1062         if (status < 0)
1063                 goto error;
1064         status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_hi_cfg_wake_up_key);
1065         if (status < 0)
1066                 goto error;
1067         status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_hi_cfg_bridge_delay);
1068         if (status < 0)
1069                 goto error;
1070         status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_hi_cfg_timing_div);
1071         if (status < 0)
1072                 goto error;
1073         status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1074         if (status < 0)
1075                 goto error;
1076         status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1077         if (status < 0)
1078                 goto error;
1079
1080         state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1081 error:
1082         mutex_unlock(&state->mutex);
1083         if (status < 0)
1084                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1085         return status;
1086 }
1087
1088 static int init_hi(struct drxk_state *state)
1089 {
1090         dprintk(1, "\n");
1091
1092         state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1093         state->m_hi_cfg_timeout = 0x96FF;
1094         /* port/bridge/power down ctrl */
1095         state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1096
1097         return hi_cfg_command(state);
1098 }
1099
1100 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1101 {
1102         int status = -1;
1103         u16 sio_pdr_mclk_cfg = 0;
1104         u16 sio_pdr_mdx_cfg = 0;
1105         u16 err_cfg = 0;
1106
1107         dprintk(1, ": mpeg %s, %s mode\n",
1108                 mpeg_enable ? "enable" : "disable",
1109                 state->m_enable_parallel ? "parallel" : "serial");
1110
1111         /* stop lock indicator process */
1112         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1113         if (status < 0)
1114                 goto error;
1115
1116         /*  MPEG TS pad configuration */
1117         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1118         if (status < 0)
1119                 goto error;
1120
1121         if (mpeg_enable == false) {
1122                 /*  Set MPEG TS pads to inputmode */
1123                 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1124                 if (status < 0)
1125                         goto error;
1126                 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1127                 if (status < 0)
1128                         goto error;
1129                 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1130                 if (status < 0)
1131                         goto error;
1132                 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1133                 if (status < 0)
1134                         goto error;
1135                 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1136                 if (status < 0)
1137                         goto error;
1138                 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1139                 if (status < 0)
1140                         goto error;
1141                 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1142                 if (status < 0)
1143                         goto error;
1144                 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1145                 if (status < 0)
1146                         goto error;
1147                 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1148                 if (status < 0)
1149                         goto error;
1150                 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1151                 if (status < 0)
1152                         goto error;
1153                 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1154                 if (status < 0)
1155                         goto error;
1156                 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1157                 if (status < 0)
1158                         goto error;
1159         } else {
1160                 /* Enable MPEG output */
1161                 sio_pdr_mdx_cfg =
1162                         ((state->m_ts_data_strength <<
1163                         SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1164                 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1165                                         SIO_PDR_MCLK_CFG_DRIVE__B) |
1166                                         0x0003);
1167
1168                 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1169                 if (status < 0)
1170                         goto error;
1171
1172                 if (state->enable_merr_cfg)
1173                         err_cfg = sio_pdr_mdx_cfg;
1174
1175                 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1176                 if (status < 0)
1177                         goto error;
1178                 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1179                 if (status < 0)
1180                         goto error;
1181
1182                 if (state->m_enable_parallel == true) {
1183                         /* paralel -> enable MD1 to MD7 */
1184                         status = write16(state, SIO_PDR_MD1_CFG__A, sio_pdr_mdx_cfg);
1185                         if (status < 0)
1186                                 goto error;
1187                         status = write16(state, SIO_PDR_MD2_CFG__A, sio_pdr_mdx_cfg);
1188                         if (status < 0)
1189                                 goto error;
1190                         status = write16(state, SIO_PDR_MD3_CFG__A, sio_pdr_mdx_cfg);
1191                         if (status < 0)
1192                                 goto error;
1193                         status = write16(state, SIO_PDR_MD4_CFG__A, sio_pdr_mdx_cfg);
1194                         if (status < 0)
1195                                 goto error;
1196                         status = write16(state, SIO_PDR_MD5_CFG__A, sio_pdr_mdx_cfg);
1197                         if (status < 0)
1198                                 goto error;
1199                         status = write16(state, SIO_PDR_MD6_CFG__A, sio_pdr_mdx_cfg);
1200                         if (status < 0)
1201                                 goto error;
1202                         status = write16(state, SIO_PDR_MD7_CFG__A, sio_pdr_mdx_cfg);
1203                         if (status < 0)
1204                                 goto error;
1205                 } else {
1206                         sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1207                                                 SIO_PDR_MD0_CFG_DRIVE__B)
1208                                         | 0x0003);
1209                         /* serial -> disable MD1 to MD7 */
1210                         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1211                         if (status < 0)
1212                                 goto error;
1213                         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1214                         if (status < 0)
1215                                 goto error;
1216                         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1217                         if (status < 0)
1218                                 goto error;
1219                         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1220                         if (status < 0)
1221                                 goto error;
1222                         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1223                         if (status < 0)
1224                                 goto error;
1225                         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1226                         if (status < 0)
1227                                 goto error;
1228                         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1229                         if (status < 0)
1230                                 goto error;
1231                 }
1232                 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1233                 if (status < 0)
1234                         goto error;
1235                 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1236                 if (status < 0)
1237                         goto error;
1238         }
1239         /*  Enable MB output over MPEG pads and ctl input */
1240         status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1241         if (status < 0)
1242                 goto error;
1243         /*  Write nomagic word to enable pdr reg write */
1244         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1245 error:
1246         if (status < 0)
1247                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1248         return status;
1249 }
1250
1251 static int mpegts_disable(struct drxk_state *state)
1252 {
1253         dprintk(1, "\n");
1254
1255         return mpegts_configure_pins(state, false);
1256 }
1257
1258 static int bl_chain_cmd(struct drxk_state *state,
1259                       u16 rom_offset, u16 nr_of_elements, u32 time_out)
1260 {
1261         u16 bl_status = 0;
1262         int status;
1263         unsigned long end;
1264
1265         dprintk(1, "\n");
1266         mutex_lock(&state->mutex);
1267         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1268         if (status < 0)
1269                 goto error;
1270         status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1271         if (status < 0)
1272                 goto error;
1273         status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1274         if (status < 0)
1275                 goto error;
1276         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1277         if (status < 0)
1278                 goto error;
1279
1280         end = jiffies + msecs_to_jiffies(time_out);
1281         do {
1282                 msleep(1);
1283                 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1284                 if (status < 0)
1285                         goto error;
1286         } while ((bl_status == 0x1) &&
1287                         ((time_is_after_jiffies(end))));
1288
1289         if (bl_status == 0x1) {
1290                 printk(KERN_ERR "drxk: SIO not ready\n");
1291                 status = -EINVAL;
1292                 goto error2;
1293         }
1294 error:
1295         if (status < 0)
1296                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1297 error2:
1298         mutex_unlock(&state->mutex);
1299         return status;
1300 }
1301
1302
1303 static int download_microcode(struct drxk_state *state,
1304                              const u8 p_mc_image[], u32 length)
1305 {
1306         const u8 *p_src = p_mc_image;
1307         u32 address;
1308         u16 n_blocks;
1309         u16 block_size;
1310         u32 offset = 0;
1311         u32 i;
1312         int status = 0;
1313
1314         dprintk(1, "\n");
1315
1316         /* down the drain (we don't care about MAGIC_WORD) */
1317 #if 0
1318         /* For future reference */
1319         drain = (p_src[0] << 8) | p_src[1];
1320 #endif
1321         p_src += sizeof(u16);
1322         offset += sizeof(u16);
1323         n_blocks = (p_src[0] << 8) | p_src[1];
1324         p_src += sizeof(u16);
1325         offset += sizeof(u16);
1326
1327         for (i = 0; i < n_blocks; i += 1) {
1328                 address = (p_src[0] << 24) | (p_src[1] << 16) |
1329                     (p_src[2] << 8) | p_src[3];
1330                 p_src += sizeof(u32);
1331                 offset += sizeof(u32);
1332
1333                 block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16);
1334                 p_src += sizeof(u16);
1335                 offset += sizeof(u16);
1336
1337 #if 0
1338                 /* For future reference */
1339                 flags = (p_src[0] << 8) | p_src[1];
1340 #endif
1341                 p_src += sizeof(u16);
1342                 offset += sizeof(u16);
1343
1344 #if 0
1345                 /* For future reference */
1346                 block_crc = (p_src[0] << 8) | p_src[1];
1347 #endif
1348                 p_src += sizeof(u16);
1349                 offset += sizeof(u16);
1350
1351                 if (offset + block_size > length) {
1352                         printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1353                         return -EINVAL;
1354                 }
1355
1356                 status = write_block(state, address, block_size, p_src);
1357                 if (status < 0) {
1358                         printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1359                         break;
1360                 }
1361                 p_src += block_size;
1362                 offset += block_size;
1363         }
1364         return status;
1365 }
1366
1367 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1368 {
1369         int status;
1370         u16 data = 0;
1371         u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1372         u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1373         unsigned long end;
1374
1375         dprintk(1, "\n");
1376
1377         if (enable == false) {
1378                 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1379                 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1380         }
1381
1382         status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1383         if (status >= 0 && data == desired_status) {
1384                 /* tokenring already has correct status */
1385                 return status;
1386         }
1387         /* Disable/enable dvbt tokenring bridge   */
1388         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1389
1390         end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1391         do {
1392                 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1393                 if ((status >= 0 && data == desired_status) || time_is_after_jiffies(end))
1394                         break;
1395                 msleep(1);
1396         } while (1);
1397         if (data != desired_status) {
1398                 printk(KERN_ERR "drxk: SIO not ready\n");
1399                 return -EINVAL;
1400         }
1401         return status;
1402 }
1403
1404 static int mpegts_stop(struct drxk_state *state)
1405 {
1406         int status = 0;
1407         u16 fec_oc_snc_mode = 0;
1408         u16 fec_oc_ipr_mode = 0;
1409
1410         dprintk(1, "\n");
1411
1412         /* Gracefull shutdown (byte boundaries) */
1413         status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1414         if (status < 0)
1415                 goto error;
1416         fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1417         status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1418         if (status < 0)
1419                 goto error;
1420
1421         /* Suppress MCLK during absence of data */
1422         status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1423         if (status < 0)
1424                 goto error;
1425         fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1426         status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1427
1428 error:
1429         if (status < 0)
1430                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1431
1432         return status;
1433 }
1434
1435 static int scu_command(struct drxk_state *state,
1436                        u16 cmd, u8 parameter_len,
1437                        u16 *parameter, u8 result_len, u16 *result)
1438 {
1439 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1440 #error DRXK register mapping no longer compatible with this routine!
1441 #endif
1442         u16 cur_cmd = 0;
1443         int status = -EINVAL;
1444         unsigned long end;
1445         u8 buffer[34];
1446         int cnt = 0, ii;
1447         const char *p;
1448         char errname[30];
1449
1450         dprintk(1, "\n");
1451
1452         if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) ||
1453             ((result_len > 0) && (result == NULL))) {
1454                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1455                 return status;
1456         }
1457
1458         mutex_lock(&state->mutex);
1459
1460         /* assume that the command register is ready
1461                 since it is checked afterwards */
1462         for (ii = parameter_len - 1; ii >= 0; ii -= 1) {
1463                 buffer[cnt++] = (parameter[ii] & 0xFF);
1464                 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1465         }
1466         buffer[cnt++] = (cmd & 0xFF);
1467         buffer[cnt++] = ((cmd >> 8) & 0xFF);
1468
1469         write_block(state, SCU_RAM_PARAM_0__A -
1470                         (parameter_len - 1), cnt, buffer);
1471         /* Wait until SCU has processed command */
1472         end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1473         do {
1474                 msleep(1);
1475                 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1476                 if (status < 0)
1477                         goto error;
1478         } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1479         if (cur_cmd != DRX_SCU_READY) {
1480                 printk(KERN_ERR "drxk: SCU not ready\n");
1481                 status = -EIO;
1482                 goto error2;
1483         }
1484         /* read results */
1485         if ((result_len > 0) && (result != NULL)) {
1486                 s16 err;
1487                 int ii;
1488
1489                 for (ii = result_len - 1; ii >= 0; ii -= 1) {
1490                         status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1491                         if (status < 0)
1492                                 goto error;
1493                 }
1494
1495                 /* Check if an error was reported by SCU */
1496                 err = (s16)result[0];
1497                 if (err >= 0)
1498                         goto error;
1499
1500                 /* check for the known error codes */
1501                 switch (err) {
1502                 case SCU_RESULT_UNKCMD:
1503                         p = "SCU_RESULT_UNKCMD";
1504                         break;
1505                 case SCU_RESULT_UNKSTD:
1506                         p = "SCU_RESULT_UNKSTD";
1507                         break;
1508                 case SCU_RESULT_SIZE:
1509                         p = "SCU_RESULT_SIZE";
1510                         break;
1511                 case SCU_RESULT_INVPAR:
1512                         p = "SCU_RESULT_INVPAR";
1513                         break;
1514                 default: /* Other negative values are errors */
1515                         sprintf(errname, "ERROR: %d\n", err);
1516                         p = errname;
1517                 }
1518                 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1519                 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1520                 status = -EINVAL;
1521                 goto error2;
1522         }
1523
1524 error:
1525         if (status < 0)
1526                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1527 error2:
1528         mutex_unlock(&state->mutex);
1529         return status;
1530 }
1531
1532 static int set_iqm_af(struct drxk_state *state, bool active)
1533 {
1534         u16 data = 0;
1535         int status;
1536
1537         dprintk(1, "\n");
1538
1539         /* Configure IQM */
1540         status = read16(state, IQM_AF_STDBY__A, &data);
1541         if (status < 0)
1542                 goto error;
1543
1544         if (!active) {
1545                 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1546                                 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1547                                 | IQM_AF_STDBY_STDBY_PD_STANDBY
1548                                 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1549                                 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1550         } else {
1551                 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1552                                 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1553                                 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1554                                 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1555                                 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1556                         );
1557         }
1558         status = write16(state, IQM_AF_STDBY__A, data);
1559
1560 error:
1561         if (status < 0)
1562                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1563         return status;
1564 }
1565
1566 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1567 {
1568         int status = 0;
1569         u16 sio_cc_pwd_mode = 0;
1570
1571         dprintk(1, "\n");
1572
1573         /* Check arguments */
1574         if (mode == NULL)
1575                 return -EINVAL;
1576
1577         switch (*mode) {
1578         case DRX_POWER_UP:
1579                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE;
1580                 break;
1581         case DRXK_POWER_DOWN_OFDM:
1582                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1583                 break;
1584         case DRXK_POWER_DOWN_CORE:
1585                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1586                 break;
1587         case DRXK_POWER_DOWN_PLL:
1588                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL;
1589                 break;
1590         case DRX_POWER_DOWN:
1591                 sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC;
1592                 break;
1593         default:
1594                 /* Unknow sleep mode */
1595                 return -EINVAL;
1596         }
1597
1598         /* If already in requested power mode, do nothing */
1599         if (state->m_current_power_mode == *mode)
1600                 return 0;
1601
1602         /* For next steps make sure to start from DRX_POWER_UP mode */
1603         if (state->m_current_power_mode != DRX_POWER_UP) {
1604                 status = power_up_device(state);
1605                 if (status < 0)
1606                         goto error;
1607                 status = dvbt_enable_ofdm_token_ring(state, true);
1608                 if (status < 0)
1609                         goto error;
1610         }
1611
1612         if (*mode == DRX_POWER_UP) {
1613                 /* Restore analog & pin configuartion */
1614         } else {
1615                 /* Power down to requested mode */
1616                 /* Backup some register settings */
1617                 /* Set pins with possible pull-ups connected
1618                    to them in input mode */
1619                 /* Analog power down */
1620                 /* ADC power down */
1621                 /* Power down device */
1622                 /* stop all comm_exec */
1623                 /* Stop and power down previous standard */
1624                 switch (state->m_operation_mode) {
1625                 case OM_DVBT:
1626                         status = mpegts_stop(state);
1627                         if (status < 0)
1628                                 goto error;
1629                         status = power_down_dvbt(state, false);
1630                         if (status < 0)
1631                                 goto error;
1632                         break;
1633                 case OM_QAM_ITU_A:
1634                 case OM_QAM_ITU_C:
1635                         status = mpegts_stop(state);
1636                         if (status < 0)
1637                                 goto error;
1638                         status = power_down_qam(state);
1639                         if (status < 0)
1640                                 goto error;
1641                         break;
1642                 default:
1643                         break;
1644                 }
1645                 status = dvbt_enable_ofdm_token_ring(state, false);
1646                 if (status < 0)
1647                         goto error;
1648                 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1649                 if (status < 0)
1650                         goto error;
1651                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1652                 if (status < 0)
1653                         goto error;
1654
1655                 if (*mode != DRXK_POWER_DOWN_OFDM) {
1656                         state->m_hi_cfg_ctrl |=
1657                                 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1658                         status = hi_cfg_command(state);
1659                         if (status < 0)
1660                                 goto error;
1661                 }
1662         }
1663         state->m_current_power_mode = *mode;
1664
1665 error:
1666         if (status < 0)
1667                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1668
1669         return status;
1670 }
1671
1672 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1673 {
1674         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
1675         u16 cmd_result = 0;
1676         u16 data = 0;
1677         int status;
1678
1679         dprintk(1, "\n");
1680
1681         status = read16(state, SCU_COMM_EXEC__A, &data);
1682         if (status < 0)
1683                 goto error;
1684         if (data == SCU_COMM_EXEC_ACTIVE) {
1685                 /* Send OFDM stop command */
1686                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
1687                 if (status < 0)
1688                         goto error;
1689                 /* Send OFDM reset command */
1690                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
1691                 if (status < 0)
1692                         goto error;
1693         }
1694
1695         /* Reset datapath for OFDM, processors first */
1696         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1697         if (status < 0)
1698                 goto error;
1699         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1700         if (status < 0)
1701                 goto error;
1702         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1703         if (status < 0)
1704                 goto error;
1705
1706         /* powerdown AFE                   */
1707         status = set_iqm_af(state, false);
1708         if (status < 0)
1709                 goto error;
1710
1711         /* powerdown to OFDM mode          */
1712         if (set_power_mode) {
1713                 status = ctrl_power_mode(state, &power_mode);
1714                 if (status < 0)
1715                         goto error;
1716         }
1717 error:
1718         if (status < 0)
1719                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1720         return status;
1721 }
1722
1723 static int setoperation_mode(struct drxk_state *state,
1724                             enum operation_mode o_mode)
1725 {
1726         int status = 0;
1727
1728         dprintk(1, "\n");
1729         /*
1730            Stop and power down previous standard
1731            TODO investigate total power down instead of partial
1732            power down depending on "previous" standard.
1733          */
1734
1735         /* disable HW lock indicator */
1736         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1737         if (status < 0)
1738                 goto error;
1739
1740         /* Device is already at the required mode */
1741         if (state->m_operation_mode == o_mode)
1742                 return 0;
1743
1744         switch (state->m_operation_mode) {
1745                 /* OM_NONE was added for start up */
1746         case OM_NONE:
1747                 break;
1748         case OM_DVBT:
1749                 status = mpegts_stop(state);
1750                 if (status < 0)
1751                         goto error;
1752                 status = power_down_dvbt(state, true);
1753                 if (status < 0)
1754                         goto error;
1755                 state->m_operation_mode = OM_NONE;
1756                 break;
1757         case OM_QAM_ITU_A:      /* fallthrough */
1758         case OM_QAM_ITU_C:
1759                 status = mpegts_stop(state);
1760                 if (status < 0)
1761                         goto error;
1762                 status = power_down_qam(state);
1763                 if (status < 0)
1764                         goto error;
1765                 state->m_operation_mode = OM_NONE;
1766                 break;
1767         case OM_QAM_ITU_B:
1768         default:
1769                 status = -EINVAL;
1770                 goto error;
1771         }
1772
1773         /*
1774                 Power up new standard
1775                 */
1776         switch (o_mode) {
1777         case OM_DVBT:
1778                 dprintk(1, ": DVB-T\n");
1779                 state->m_operation_mode = o_mode;
1780                 status = set_dvbt_standard(state, o_mode);
1781                 if (status < 0)
1782                         goto error;
1783                 break;
1784         case OM_QAM_ITU_A:      /* fallthrough */
1785         case OM_QAM_ITU_C:
1786                 dprintk(1, ": DVB-C Annex %c\n",
1787                         (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1788                 state->m_operation_mode = o_mode;
1789                 status = set_qam_standard(state, o_mode);
1790                 if (status < 0)
1791                         goto error;
1792                 break;
1793         case OM_QAM_ITU_B:
1794         default:
1795                 status = -EINVAL;
1796         }
1797 error:
1798         if (status < 0)
1799                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1800         return status;
1801 }
1802
1803 static int start(struct drxk_state *state, s32 offset_freq,
1804                  s32 intermediate_frequency)
1805 {
1806         int status = -EINVAL;
1807
1808         u16 i_freqk_hz;
1809         s32 offsetk_hz = offset_freq / 1000;
1810
1811         dprintk(1, "\n");
1812         if (state->m_drxk_state != DRXK_STOPPED &&
1813                 state->m_drxk_state != DRXK_DTV_STARTED)
1814                 goto error;
1815
1816         state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1817
1818         if (intermediate_frequency < 0) {
1819                 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1820                 intermediate_frequency = -intermediate_frequency;
1821         }
1822
1823         switch (state->m_operation_mode) {
1824         case OM_QAM_ITU_A:
1825         case OM_QAM_ITU_C:
1826                 i_freqk_hz = (intermediate_frequency / 1000);
1827                 status = set_qam(state, i_freqk_hz, offsetk_hz);
1828                 if (status < 0)
1829                         goto error;
1830                 state->m_drxk_state = DRXK_DTV_STARTED;
1831                 break;
1832         case OM_DVBT:
1833                 i_freqk_hz = (intermediate_frequency / 1000);
1834                 status = mpegts_stop(state);
1835                 if (status < 0)
1836                         goto error;
1837                 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1838                 if (status < 0)
1839                         goto error;
1840                 status = dvbt_start(state);
1841                 if (status < 0)
1842                         goto error;
1843                 state->m_drxk_state = DRXK_DTV_STARTED;
1844                 break;
1845         default:
1846                 break;
1847         }
1848 error:
1849         if (status < 0)
1850                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1851         return status;
1852 }
1853
1854 static int shut_down(struct drxk_state *state)
1855 {
1856         dprintk(1, "\n");
1857
1858         mpegts_stop(state);
1859         return 0;
1860 }
1861
1862 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1863 {
1864         int status = -EINVAL;
1865
1866         dprintk(1, "\n");
1867
1868         if (p_lock_status == NULL)
1869                 goto error;
1870
1871         *p_lock_status = NOT_LOCKED;
1872
1873         /* define the SCU command code */
1874         switch (state->m_operation_mode) {
1875         case OM_QAM_ITU_A:
1876         case OM_QAM_ITU_B:
1877         case OM_QAM_ITU_C:
1878                 status = get_qam_lock_status(state, p_lock_status);
1879                 break;
1880         case OM_DVBT:
1881                 status = get_dvbt_lock_status(state, p_lock_status);
1882                 break;
1883         default:
1884                 break;
1885         }
1886 error:
1887         if (status < 0)
1888                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1889         return status;
1890 }
1891
1892 static int mpegts_start(struct drxk_state *state)
1893 {
1894         int status;
1895
1896         u16 fec_oc_snc_mode = 0;
1897
1898         /* Allow OC to sync again */
1899         status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1900         if (status < 0)
1901                 goto error;
1902         fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1903         status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1904         if (status < 0)
1905                 goto error;
1906         status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1907 error:
1908         if (status < 0)
1909                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1910         return status;
1911 }
1912
1913 static int mpegts_dto_init(struct drxk_state *state)
1914 {
1915         int status;
1916
1917         dprintk(1, "\n");
1918
1919         /* Rate integration settings */
1920         status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1921         if (status < 0)
1922                 goto error;
1923         status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1924         if (status < 0)
1925                 goto error;
1926         status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1927         if (status < 0)
1928                 goto error;
1929         status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1930         if (status < 0)
1931                 goto error;
1932         status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1933         if (status < 0)
1934                 goto error;
1935         status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1936         if (status < 0)
1937                 goto error;
1938         status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1939         if (status < 0)
1940                 goto error;
1941         status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1942         if (status < 0)
1943                 goto error;
1944
1945         /* Additional configuration */
1946         status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1947         if (status < 0)
1948                 goto error;
1949         status = write16(state, FEC_OC_SNC_LWM__A, 2);
1950         if (status < 0)
1951                 goto error;
1952         status = write16(state, FEC_OC_SNC_HWM__A, 12);
1953 error:
1954         if (status < 0)
1955                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1956
1957         return status;
1958 }
1959
1960 static int mpegts_dto_setup(struct drxk_state *state,
1961                           enum operation_mode o_mode)
1962 {
1963         int status;
1964
1965         u16 fec_oc_reg_mode = 0;        /* FEC_OC_MODE       register value */
1966         u16 fec_oc_reg_ipr_mode = 0;    /* FEC_OC_IPR_MODE   register value */
1967         u16 fec_oc_dto_mode = 0;        /* FEC_OC_IPR_INVERT register value */
1968         u16 fec_oc_fct_mode = 0;        /* FEC_OC_IPR_INVERT register value */
1969         u16 fec_oc_dto_period = 2;      /* FEC_OC_IPR_INVERT register value */
1970         u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */
1971         u32 fec_oc_rcn_ctl_rate = 0;    /* FEC_OC_IPR_INVERT register value */
1972         u16 fec_oc_tmd_mode = 0;
1973         u16 fec_oc_tmd_int_upd_rate = 0;
1974         u32 max_bit_rate = 0;
1975         bool static_clk = false;
1976
1977         dprintk(1, "\n");
1978
1979         /* Check insertion of the Reed-Solomon parity bytes */
1980         status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1981         if (status < 0)
1982                 goto error;
1983         status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1984         if (status < 0)
1985                 goto error;
1986         fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M);
1987         fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
1988         if (state->m_insert_rs_byte == true) {
1989                 /* enable parity symbol forward */
1990                 fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M;
1991                 /* MVAL disable during parity bytes */
1992                 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
1993                 /* TS burst length to 204 */
1994                 fec_oc_dto_burst_len = 204;
1995         }
1996
1997         /* Check serial or parrallel output */
1998         fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
1999         if (state->m_enable_parallel == false) {
2000                 /* MPEG data output is serial -> set ipr_mode[0] */
2001                 fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M;
2002         }
2003
2004         switch (o_mode) {
2005         case OM_DVBT:
2006                 max_bit_rate = state->m_dvbt_bitrate;
2007                 fec_oc_tmd_mode = 3;
2008                 fec_oc_rcn_ctl_rate = 0xC00000;
2009                 static_clk = state->m_dvbt_static_clk;
2010                 break;
2011         case OM_QAM_ITU_A:      /* fallthrough */
2012         case OM_QAM_ITU_C:
2013                 fec_oc_tmd_mode = 0x0004;
2014                 fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */
2015                 max_bit_rate = state->m_dvbc_bitrate;
2016                 static_clk = state->m_dvbc_static_clk;
2017                 break;
2018         default:
2019                 status = -EINVAL;
2020         }               /* switch (standard) */
2021         if (status < 0)
2022                 goto error;
2023
2024         /* Configure DTO's */
2025         if (static_clk) {
2026                 u32 bit_rate = 0;
2027
2028                 /* Rational DTO for MCLK source (static MCLK rate),
2029                         Dynamic DTO for optimal grouping
2030                         (avoid intra-packet gaps),
2031                         DTO offset enable to sync TS burst with MSTRT */
2032                 fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2033                                 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2034                 fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2035                                 FEC_OC_FCT_MODE_VIRT_ENA__M);
2036
2037                 /* Check user defined bitrate */
2038                 bit_rate = max_bit_rate;
2039                 if (bit_rate > 75900000UL) {    /* max is 75.9 Mb/s */
2040                         bit_rate = 75900000UL;
2041                 }
2042                 /* Rational DTO period:
2043                         dto_period = (Fsys / bitrate) - 2
2044
2045                         result should be floored,
2046                         to make sure >= requested bitrate
2047                         */
2048                 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2049                                                 * 1000) / bit_rate);
2050                 if (fec_oc_dto_period <= 2)
2051                         fec_oc_dto_period = 0;
2052                 else
2053                         fec_oc_dto_period -= 2;
2054                 fec_oc_tmd_int_upd_rate = 8;
2055         } else {
2056                 /* (commonAttr->static_clk == false) => dynamic mode */
2057                 fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M;
2058                 fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE;
2059                 fec_oc_tmd_int_upd_rate = 5;
2060         }
2061
2062         /* Write appropriate registers with requested configuration */
2063         status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2064         if (status < 0)
2065                 goto error;
2066         status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2067         if (status < 0)
2068                 goto error;
2069         status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2070         if (status < 0)
2071                 goto error;
2072         status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2073         if (status < 0)
2074                 goto error;
2075         status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2076         if (status < 0)
2077                 goto error;
2078         status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2079         if (status < 0)
2080                 goto error;
2081
2082         /* Rate integration settings */
2083         status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2084         if (status < 0)
2085                 goto error;
2086         status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fec_oc_tmd_int_upd_rate);
2087         if (status < 0)
2088                 goto error;
2089         status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2090 error:
2091         if (status < 0)
2092                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2093         return status;
2094 }
2095
2096 static int mpegts_configure_polarity(struct drxk_state *state)
2097 {
2098         u16 fec_oc_reg_ipr_invert = 0;
2099
2100         /* Data mask for the output data byte */
2101         u16 invert_data_mask =
2102             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2103             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2104             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2105             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2106
2107         dprintk(1, "\n");
2108
2109         /* Control selective inversion of output bits */
2110         fec_oc_reg_ipr_invert &= (~(invert_data_mask));
2111         if (state->m_invert_data == true)
2112                 fec_oc_reg_ipr_invert |= invert_data_mask;
2113         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2114         if (state->m_invert_err == true)
2115                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M;
2116         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2117         if (state->m_invert_str == true)
2118                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M;
2119         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2120         if (state->m_invert_val == true)
2121                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M;
2122         fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2123         if (state->m_invert_clk == true)
2124                 fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M;
2125
2126         return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2127 }
2128
2129 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2130
2131 static int set_agc_rf(struct drxk_state *state,
2132                     struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2133 {
2134         int status = -EINVAL;
2135         u16 data = 0;
2136         struct s_cfg_agc *p_if_agc_settings;
2137
2138         dprintk(1, "\n");
2139
2140         if (p_agc_cfg == NULL)
2141                 goto error;
2142
2143         switch (p_agc_cfg->ctrl_mode) {
2144         case DRXK_AGC_CTRL_AUTO:
2145                 /* Enable RF AGC DAC */
2146                 status = read16(state, IQM_AF_STDBY__A, &data);
2147                 if (status < 0)
2148                         goto error;
2149                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2150                 status = write16(state, IQM_AF_STDBY__A, data);
2151                 if (status < 0)
2152                         goto error;
2153                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2154                 if (status < 0)
2155                         goto error;
2156
2157                 /* Enable SCU RF AGC loop */
2158                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2159
2160                 /* Polarity */
2161                 if (state->m_rf_agc_pol)
2162                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2163                 else
2164                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2165                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2166                 if (status < 0)
2167                         goto error;
2168
2169                 /* Set speed (using complementary reduction value) */
2170                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2171                 if (status < 0)
2172                         goto error;
2173
2174                 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2175                 data |= (~(p_agc_cfg->speed <<
2176                                 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2177                                 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2178
2179                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2180                 if (status < 0)
2181                         goto error;
2182
2183                 if (is_dvbt(state))
2184                         p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2185                 else if (is_qam(state))
2186                         p_if_agc_settings = &state->m_qam_if_agc_cfg;
2187                 else
2188                         p_if_agc_settings = &state->m_atv_if_agc_cfg;
2189                 if (p_if_agc_settings == NULL) {
2190                         status = -EINVAL;
2191                         goto error;
2192                 }
2193
2194                 /* Set TOP, only if IF-AGC is in AUTO mode */
2195                 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO)
2196                         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->top);
2197                         if (status < 0)
2198                                 goto error;
2199
2200                 /* Cut-Off current */
2201                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, p_agc_cfg->cut_off_current);
2202                 if (status < 0)
2203                         goto error;
2204
2205                 /* Max. output level */
2206                 status = write16(state, SCU_RAM_AGC_RF_MAX__A, p_agc_cfg->max_output_level);
2207                 if (status < 0)
2208                         goto error;
2209
2210                 break;
2211
2212         case DRXK_AGC_CTRL_USER:
2213                 /* Enable RF AGC DAC */
2214                 status = read16(state, IQM_AF_STDBY__A, &data);
2215                 if (status < 0)
2216                         goto error;
2217                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2218                 status = write16(state, IQM_AF_STDBY__A, data);
2219                 if (status < 0)
2220                         goto error;
2221
2222                 /* Disable SCU RF AGC loop */
2223                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2224                 if (status < 0)
2225                         goto error;
2226                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2227                 if (state->m_rf_agc_pol)
2228                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2229                 else
2230                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2231                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2232                 if (status < 0)
2233                         goto error;
2234
2235                 /* SCU c.o.c. to 0, enabling full control range */
2236                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2237                 if (status < 0)
2238                         goto error;
2239
2240                 /* Write value to output pin */
2241                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, p_agc_cfg->output_level);
2242                 if (status < 0)
2243                         goto error;
2244                 break;
2245
2246         case DRXK_AGC_CTRL_OFF:
2247                 /* Disable RF AGC DAC */
2248                 status = read16(state, IQM_AF_STDBY__A, &data);
2249                 if (status < 0)
2250                         goto error;
2251                 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2252                 status = write16(state, IQM_AF_STDBY__A, data);
2253                 if (status < 0)
2254                         goto error;
2255
2256                 /* Disable SCU RF AGC loop */
2257                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2258                 if (status < 0)
2259                         goto error;
2260                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2261                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2262                 if (status < 0)
2263                         goto error;
2264                 break;
2265
2266         default:
2267                 status = -EINVAL;
2268
2269         }
2270 error:
2271         if (status < 0)
2272                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2273         return status;
2274 }
2275
2276 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2277
2278 static int set_agc_if(struct drxk_state *state,
2279                     struct s_cfg_agc *p_agc_cfg, bool is_dtv)
2280 {
2281         u16 data = 0;
2282         int status = 0;
2283         struct s_cfg_agc *p_rf_agc_settings;
2284
2285         dprintk(1, "\n");
2286
2287         switch (p_agc_cfg->ctrl_mode) {
2288         case DRXK_AGC_CTRL_AUTO:
2289
2290                 /* Enable IF AGC DAC */
2291                 status = read16(state, IQM_AF_STDBY__A, &data);
2292                 if (status < 0)
2293                         goto error;
2294                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2295                 status = write16(state, IQM_AF_STDBY__A, data);
2296                 if (status < 0)
2297                         goto error;
2298
2299                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2300                 if (status < 0)
2301                         goto error;
2302
2303                 /* Enable SCU IF AGC loop */
2304                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2305
2306                 /* Polarity */
2307                 if (state->m_if_agc_pol)
2308                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2309                 else
2310                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2311                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2312                 if (status < 0)
2313                         goto error;
2314
2315                 /* Set speed (using complementary reduction value) */
2316                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2317                 if (status < 0)
2318                         goto error;
2319                 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2320                 data |= (~(p_agc_cfg->speed <<
2321                                 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2322                                 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2323
2324                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2325                 if (status < 0)
2326                         goto error;
2327
2328                 if (is_qam(state))
2329                         p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2330                 else
2331                         p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2332                 if (p_rf_agc_settings == NULL)
2333                         return -1;
2334                 /* Restore TOP */
2335                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_rf_agc_settings->top);
2336                 if (status < 0)
2337                         goto error;
2338                 break;
2339
2340         case DRXK_AGC_CTRL_USER:
2341
2342                 /* Enable IF AGC DAC */
2343                 status = read16(state, IQM_AF_STDBY__A, &data);
2344                 if (status < 0)
2345                         goto error;
2346                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2347                 status = write16(state, IQM_AF_STDBY__A, data);
2348                 if (status < 0)
2349                         goto error;
2350
2351                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2352                 if (status < 0)
2353                         goto error;
2354
2355                 /* Disable SCU IF AGC loop */
2356                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2357
2358                 /* Polarity */
2359                 if (state->m_if_agc_pol)
2360                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2361                 else
2362                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2363                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2364                 if (status < 0)
2365                         goto error;
2366
2367                 /* Write value to output pin */
2368                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->output_level);
2369                 if (status < 0)
2370                         goto error;
2371                 break;
2372
2373         case DRXK_AGC_CTRL_OFF:
2374
2375                 /* Disable If AGC DAC */
2376                 status = read16(state, IQM_AF_STDBY__A, &data);
2377                 if (status < 0)
2378                         goto error;
2379                 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2380                 status = write16(state, IQM_AF_STDBY__A, data);
2381                 if (status < 0)
2382                         goto error;
2383
2384                 /* Disable SCU IF AGC loop */
2385                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2386                 if (status < 0)
2387                         goto error;
2388                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2389                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2390                 if (status < 0)
2391                         goto error;
2392                 break;
2393         }               /* switch (agcSettingsIf->ctrl_mode) */
2394
2395         /* always set the top to support
2396                 configurations without if-loop */
2397         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2398 error:
2399         if (status < 0)
2400                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2401         return status;
2402 }
2403
2404 static int get_qam_signal_to_noise(struct drxk_state *state,
2405                                s32 *p_signal_to_noise)
2406 {
2407         int status = 0;
2408         u16 qam_sl_err_power = 0;       /* accum. error between
2409                                         raw and sliced symbols */
2410         u32 qam_sl_sig_power = 0;       /* used for MER, depends of
2411                                         QAM modulation */
2412         u32 qam_sl_mer = 0;     /* QAM MER */
2413
2414         dprintk(1, "\n");
2415
2416         /* MER calculation */
2417
2418         /* get the register value needed for MER */
2419         status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2420         if (status < 0) {
2421                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2422                 return -EINVAL;
2423         }
2424
2425         switch (state->props.modulation) {
2426         case QAM_16:
2427                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2428                 break;
2429         case QAM_32:
2430                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2431                 break;
2432         case QAM_64:
2433                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2434                 break;
2435         case QAM_128:
2436                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2437                 break;
2438         default:
2439         case QAM_256:
2440                 qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2441                 break;
2442         }
2443
2444         if (qam_sl_err_power > 0) {
2445                 qam_sl_mer = log10times100(qam_sl_sig_power) -
2446                         log10times100((u32) qam_sl_err_power);
2447         }
2448         *p_signal_to_noise = qam_sl_mer;
2449
2450         return status;
2451 }
2452
2453 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2454                                 s32 *p_signal_to_noise)
2455 {
2456         int status;
2457         u16 reg_data = 0;
2458         u32 eq_reg_td_sqr_err_i = 0;
2459         u32 eq_reg_td_sqr_err_q = 0;
2460         u16 eq_reg_td_sqr_err_exp = 0;
2461         u16 eq_reg_td_tps_pwr_ofs = 0;
2462         u16 eq_reg_td_req_smb_cnt = 0;
2463         u32 tps_cnt = 0;
2464         u32 sqr_err_iq = 0;
2465         u32 a = 0;
2466         u32 b = 0;
2467         u32 c = 0;
2468         u32 i_mer = 0;
2469         u16 transmission_params = 0;
2470
2471         dprintk(1, "\n");
2472
2473         status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &eq_reg_td_tps_pwr_ofs);
2474         if (status < 0)
2475                 goto error;
2476         status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &eq_reg_td_req_smb_cnt);
2477         if (status < 0)
2478                 goto error;
2479         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &eq_reg_td_sqr_err_exp);
2480         if (status < 0)
2481                 goto error;
2482         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &reg_data);
2483         if (status < 0)
2484                 goto error;
2485         /* Extend SQR_ERR_I operational range */
2486         eq_reg_td_sqr_err_i = (u32) reg_data;
2487         if ((eq_reg_td_sqr_err_exp > 11) &&
2488                 (eq_reg_td_sqr_err_i < 0x00000FFFUL)) {
2489                 eq_reg_td_sqr_err_i += 0x00010000UL;
2490         }
2491         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);
2492         if (status < 0)
2493                 goto error;
2494         /* Extend SQR_ERR_Q operational range */
2495         eq_reg_td_sqr_err_q = (u32) reg_data;
2496         if ((eq_reg_td_sqr_err_exp > 11) &&
2497                 (eq_reg_td_sqr_err_q < 0x00000FFFUL))
2498                 eq_reg_td_sqr_err_q += 0x00010000UL;
2499
2500         status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmission_params);
2501         if (status < 0)
2502                 goto error;
2503
2504         /* Check input data for MER */
2505
2506         /* MER calculation (in 0.1 dB) without math.h */
2507         if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0))
2508                 i_mer = 0;
2509         else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) {
2510                 /* No error at all, this must be the HW reset value
2511                         * Apparently no first measurement yet
2512                         * Set MER to 0.0 */
2513                 i_mer = 0;
2514         } else {
2515                 sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) <<
2516                         eq_reg_td_sqr_err_exp;
2517                 if ((transmission_params &
2518                         OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2519                         == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2520                         tps_cnt = 17;
2521                 else
2522                         tps_cnt = 68;
2523
2524                 /* IMER = 100 * log10 (x)
2525                         where x = (eq_reg_td_tps_pwr_ofs^2 *
2526                         eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq
2527
2528                         => IMER = a + b -c
2529                         where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2)
2530                         b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt)
2531                         c = 100 * log10 (sqr_err_iq)
2532                         */
2533
2534                 /* log(x) x = 9bits * 9bits->18 bits  */
2535                 a = log10times100(eq_reg_td_tps_pwr_ofs *
2536                                         eq_reg_td_tps_pwr_ofs);
2537                 /* log(x) x = 16bits * 7bits->23 bits  */
2538                 b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt);
2539                 /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2540                 c = log10times100(sqr_err_iq);
2541
2542                 i_mer = a + b - c;
2543         }
2544         *p_signal_to_noise = i_mer;
2545
2546 error:
2547         if (status < 0)
2548                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2549         return status;
2550 }
2551
2552 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2553 {
2554         dprintk(1, "\n");
2555
2556         *p_signal_to_noise = 0;
2557         switch (state->m_operation_mode) {
2558         case OM_DVBT:
2559                 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2560         case OM_QAM_ITU_A:
2561         case OM_QAM_ITU_C:
2562                 return get_qam_signal_to_noise(state, p_signal_to_noise);
2563         default:
2564                 break;
2565         }
2566         return 0;
2567 }
2568
2569 #if 0
2570 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2571 {
2572         /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2573         int status = 0;
2574
2575         dprintk(1, "\n");
2576
2577         static s32 QE_SN[] = {
2578                 51,             /* QPSK 1/2 */
2579                 69,             /* QPSK 2/3 */
2580                 79,             /* QPSK 3/4 */
2581                 89,             /* QPSK 5/6 */
2582                 97,             /* QPSK 7/8 */
2583                 108,            /* 16-QAM 1/2 */
2584                 131,            /* 16-QAM 2/3 */
2585                 146,            /* 16-QAM 3/4 */
2586                 156,            /* 16-QAM 5/6 */
2587                 160,            /* 16-QAM 7/8 */
2588                 165,            /* 64-QAM 1/2 */
2589                 187,            /* 64-QAM 2/3 */
2590                 202,            /* 64-QAM 3/4 */
2591                 216,            /* 64-QAM 5/6 */
2592                 225,            /* 64-QAM 7/8 */
2593         };
2594
2595         *p_quality = 0;
2596
2597         do {
2598                 s32 signal_to_noise = 0;
2599                 u16 constellation = 0;
2600                 u16 code_rate = 0;
2601                 u32 signal_to_noise_rel;
2602                 u32 ber_quality;
2603
2604                 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2605                 if (status < 0)
2606                         break;
2607                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &constellation);
2608                 if (status < 0)
2609                         break;
2610                 constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2611
2612                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &code_rate);
2613                 if (status < 0)
2614                         break;
2615                 code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2616
2617                 if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2618                     code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2619                         break;
2620                 signal_to_noise_rel = signal_to_noise -
2621                     QE_SN[constellation * 5 + code_rate];
2622                 ber_quality = 100;
2623
2624                 if (signal_to_noise_rel < -70)
2625                         *p_quality = 0;
2626                 else if (signal_to_noise_rel < 30)
2627                         *p_quality = ((signal_to_noise_rel + 70) *
2628                                      ber_quality) / 100;
2629                 else
2630                         *p_quality = ber_quality;
2631         } while (0);
2632         return 0;
2633 };
2634
2635 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2636 {
2637         int status = 0;
2638         *p_quality = 0;
2639
2640         dprintk(1, "\n");
2641
2642         do {
2643                 u32 signal_to_noise = 0;
2644                 u32 ber_quality = 100;
2645                 u32 signal_to_noise_rel = 0;
2646
2647                 status = get_qam_signal_to_noise(state, &signal_to_noise);
2648                 if (status < 0)
2649                         break;
2650
2651                 switch (state->props.modulation) {
2652                 case QAM_16:
2653                         signal_to_noise_rel = signal_to_noise - 200;
2654                         break;
2655                 case QAM_32:
2656                         signal_to_noise_rel = signal_to_noise - 230;
2657                         break;  /* Not in NorDig */
2658                 case QAM_64:
2659                         signal_to_noise_rel = signal_to_noise - 260;
2660                         break;
2661                 case QAM_128:
2662                         signal_to_noise_rel = signal_to_noise - 290;
2663                         break;
2664                 default:
2665                 case QAM_256:
2666                         signal_to_noise_rel = signal_to_noise - 320;
2667                         break;
2668                 }
2669
2670                 if (signal_to_noise_rel < -70)
2671                         *p_quality = 0;
2672                 else if (signal_to_noise_rel < 30)
2673                         *p_quality = ((signal_to_noise_rel + 70) *
2674                                      ber_quality) / 100;
2675                 else
2676                         *p_quality = ber_quality;
2677         } while (0);
2678
2679         return status;
2680 }
2681
2682 static int get_quality(struct drxk_state *state, s32 *p_quality)
2683 {
2684         dprintk(1, "\n");
2685
2686         switch (state->m_operation_mode) {
2687         case OM_DVBT:
2688                 return get_dvbt_quality(state, p_quality);
2689         case OM_QAM_ITU_A:
2690                 return get_dvbc_quality(state, p_quality);
2691         default:
2692                 break;
2693         }
2694
2695         return 0;
2696 }
2697 #endif
2698
2699 /* Free data ram in SIO HI */
2700 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2701 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2702
2703 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2704 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2705 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2706 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2707
2708 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2709 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2710 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2711
2712 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2713 {
2714         int status = -EINVAL;
2715
2716         dprintk(1, "\n");
2717
2718         if (state->m_drxk_state == DRXK_UNINITIALIZED)
2719                 return 0;
2720         if (state->m_drxk_state == DRXK_POWERED_DOWN)
2721                 goto error;
2722
2723         if (state->no_i2c_bridge)
2724                 return 0;
2725
2726         status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2727         if (status < 0)
2728                 goto error;
2729         if (b_enable_bridge) {
2730                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2731                 if (status < 0)
2732                         goto error;
2733         } else {
2734                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2735                 if (status < 0)
2736                         goto error;
2737         }
2738
2739         status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2740
2741 error:
2742         if (status < 0)
2743                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2744         return status;
2745 }
2746
2747 static int set_pre_saw(struct drxk_state *state,
2748                      struct s_cfg_pre_saw *p_pre_saw_cfg)
2749 {
2750         int status = -EINVAL;
2751
2752         dprintk(1, "\n");
2753
2754         if ((p_pre_saw_cfg == NULL)
2755             || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M))
2756                 goto error;
2757
2758         status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2759 error:
2760         if (status < 0)
2761                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2762         return status;
2763 }
2764
2765 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2766                        u16 rom_offset, u16 nr_of_elements, u32 time_out)
2767 {
2768         u16 bl_status = 0;
2769         u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF);
2770         u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF);
2771         int status;
2772         unsigned long end;
2773
2774         dprintk(1, "\n");
2775
2776         mutex_lock(&state->mutex);
2777         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2778         if (status < 0)
2779                 goto error;
2780         status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2781         if (status < 0)
2782                 goto error;
2783         status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2784         if (status < 0)
2785                 goto error;
2786         status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2787         if (status < 0)
2788                 goto error;
2789         status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2790         if (status < 0)
2791                 goto error;
2792         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2793         if (status < 0)
2794                 goto error;
2795
2796         end = jiffies + msecs_to_jiffies(time_out);
2797         do {
2798                 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2799                 if (status < 0)
2800                         goto error;
2801         } while ((bl_status == 0x1) && time_is_after_jiffies(end));
2802         if (bl_status == 0x1) {
2803                 printk(KERN_ERR "drxk: SIO not ready\n");
2804                 status = -EINVAL;
2805                 goto error2;
2806         }
2807 error:
2808         if (status < 0)
2809                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2810 error2:
2811         mutex_unlock(&state->mutex);
2812         return status;
2813
2814 }
2815
2816 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2817 {
2818         u16 data = 0;
2819         int status;
2820
2821         dprintk(1, "\n");
2822
2823         /* start measurement */
2824         status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2825         if (status < 0)
2826                 goto error;
2827         status = write16(state, IQM_AF_START_LOCK__A, 1);
2828         if (status < 0)
2829                 goto error;
2830
2831         *count = 0;
2832         status = read16(state, IQM_AF_PHASE0__A, &data);
2833         if (status < 0)
2834                 goto error;
2835         if (data == 127)
2836                 *count = *count + 1;
2837         status = read16(state, IQM_AF_PHASE1__A, &data);
2838         if (status < 0)
2839                 goto error;
2840         if (data == 127)
2841                 *count = *count + 1;
2842         status = read16(state, IQM_AF_PHASE2__A, &data);
2843         if (status < 0)
2844                 goto error;
2845         if (data == 127)
2846                 *count = *count + 1;
2847
2848 error:
2849         if (status < 0)
2850                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2851         return status;
2852 }
2853
2854 static int adc_synchronization(struct drxk_state *state)
2855 {
2856         u16 count = 0;
2857         int status;
2858
2859         dprintk(1, "\n");
2860
2861         status = adc_sync_measurement(state, &count);
2862         if (status < 0)
2863                 goto error;
2864
2865         if (count == 1) {
2866                 /* Try sampling on a diffrent edge */
2867                 u16 clk_neg = 0;
2868
2869                 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2870                 if (status < 0)
2871                         goto error;
2872                 if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2873                         IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2874                         clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2875                         clk_neg |=
2876                                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2877                 } else {
2878                         clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2879                         clk_neg |=
2880                                 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2881                 }
2882                 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2883                 if (status < 0)
2884                         goto error;
2885                 status = adc_sync_measurement(state, &count);
2886                 if (status < 0)
2887                         goto error;
2888         }
2889
2890         if (count < 2)
2891                 status = -EINVAL;
2892 error:
2893         if (status < 0)
2894                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2895         return status;
2896 }
2897
2898 static int set_frequency_shifter(struct drxk_state *state,
2899                                u16 intermediate_freqk_hz,
2900                                s32 tuner_freq_offset, bool is_dtv)
2901 {
2902         bool select_pos_image = false;
2903         u32 rf_freq_residual = tuner_freq_offset;
2904         u32 fm_frequency_shift = 0;
2905         bool tuner_mirror = !state->m_b_mirror_freq_spect;
2906         u32 adc_freq;
2907         bool adc_flip;
2908         int status;
2909         u32 if_freq_actual;
2910         u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2911         u32 frequency_shift;
2912         bool image_to_select;
2913
2914         dprintk(1, "\n");
2915
2916         /*
2917            Program frequency shifter
2918            No need to account for mirroring on RF
2919          */
2920         if (is_dtv) {
2921                 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2922                     (state->m_operation_mode == OM_QAM_ITU_C) ||
2923                     (state->m_operation_mode == OM_DVBT))
2924                         select_pos_image = true;
2925                 else
2926                         select_pos_image = false;
2927         }
2928         if (tuner_mirror)
2929                 /* tuner doesn't mirror */
2930                 if_freq_actual = intermediate_freqk_hz +
2931                     rf_freq_residual + fm_frequency_shift;
2932         else
2933                 /* tuner mirrors */
2934                 if_freq_actual = intermediate_freqk_hz -
2935                     rf_freq_residual - fm_frequency_shift;
2936         if (if_freq_actual > sampling_frequency / 2) {
2937                 /* adc mirrors */
2938                 adc_freq = sampling_frequency - if_freq_actual;
2939                 adc_flip = true;
2940         } else {
2941                 /* adc doesn't mirror */
2942                 adc_freq = if_freq_actual;
2943                 adc_flip = false;
2944         }
2945
2946         frequency_shift = adc_freq;
2947         image_to_select = state->m_rfmirror ^ tuner_mirror ^
2948             adc_flip ^ select_pos_image;
2949         state->m_iqm_fs_rate_ofs =
2950             Frac28a((frequency_shift), sampling_frequency);
2951
2952         if (image_to_select)
2953                 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2954
2955         /* Program frequency shifter with tuner offset compensation */
2956         /* frequency_shift += tuner_freq_offset; TODO */
2957         status = write32(state, IQM_FS_RATE_OFS_LO__A,
2958                          state->m_iqm_fs_rate_ofs);
2959         if (status < 0)
2960                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2961         return status;
2962 }
2963
2964 static int init_agc(struct drxk_state *state, bool is_dtv)
2965 {
2966         u16 ingain_tgt = 0;
2967         u16 ingain_tgt_min = 0;
2968         u16 ingain_tgt_max = 0;
2969         u16 clp_cyclen = 0;
2970         u16 clp_sum_min = 0;
2971         u16 clp_dir_to = 0;
2972         u16 sns_sum_min = 0;
2973         u16 sns_sum_max = 0;
2974         u16 clp_sum_max = 0;
2975         u16 sns_dir_to = 0;
2976         u16 ki_innergain_min = 0;
2977         u16 if_iaccu_hi_tgt = 0;
2978         u16 if_iaccu_hi_tgt_min = 0;
2979         u16 if_iaccu_hi_tgt_max = 0;
2980         u16 data = 0;
2981         u16 fast_clp_ctrl_delay = 0;
2982         u16 clp_ctrl_mode = 0;
2983         int status = 0;
2984
2985         dprintk(1, "\n");
2986
2987         /* Common settings */
2988         sns_sum_max = 1023;
2989         if_iaccu_hi_tgt_min = 2047;
2990         clp_cyclen = 500;
2991         clp_sum_max = 1023;
2992
2993         /* AGCInit() not available for DVBT; init done in microcode */
2994         if (!is_qam(state)) {
2995                 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_operation_mode);
2996                 return -EINVAL;
2997         }
2998
2999         /* FIXME: Analog TV AGC require different settings */
3000
3001         /* Standard specific settings */
3002         clp_sum_min = 8;
3003         clp_dir_to = (u16) -9;
3004         clp_ctrl_mode = 0;
3005         sns_sum_min = 8;
3006         sns_dir_to = (u16) -9;
3007         ki_innergain_min = (u16) -1030;
3008         if_iaccu_hi_tgt_max = 0x2380;
3009         if_iaccu_hi_tgt = 0x2380;
3010         ingain_tgt_min = 0x0511;
3011         ingain_tgt = 0x0511;
3012         ingain_tgt_max = 5119;
3013         fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3014
3015         status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fast_clp_ctrl_delay);
3016         if (status < 0)
3017                 goto error;
3018
3019         status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3020         if (status < 0)
3021                 goto error;
3022         status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3023         if (status < 0)
3024                 goto error;
3025         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3026         if (status < 0)
3027                 goto error;
3028         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3029         if (status < 0)
3030                 goto error;
3031         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min);
3032         if (status < 0)
3033                 goto error;
3034         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, if_iaccu_hi_tgt_max);
3035         if (status < 0)
3036                 goto error;
3037         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3038         if (status < 0)
3039                 goto error;
3040         status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3041         if (status < 0)
3042                 goto error;
3043         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3044         if (status < 0)
3045                 goto error;
3046         status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3047         if (status < 0)
3048                 goto error;
3049         status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3050         if (status < 0)
3051                 goto error;
3052         status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3053         if (status < 0)
3054                 goto error;
3055
3056         status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min);
3057         if (status < 0)
3058                 goto error;
3059         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, if_iaccu_hi_tgt);
3060         if (status < 0)
3061                 goto error;
3062         status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3063         if (status < 0)
3064                 goto error;
3065
3066         status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3067         if (status < 0)
3068                 goto error;
3069         status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3070         if (status < 0)
3071                 goto error;
3072         status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3073         if (status < 0)
3074                 goto error;
3075
3076         status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3077         if (status < 0)
3078                 goto error;
3079         status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3080         if (status < 0)
3081                 goto error;
3082         status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3083         if (status < 0)
3084                 goto error;
3085         status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3086         if (status < 0)
3087                 goto error;
3088         status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3089         if (status < 0)
3090                 goto error;
3091         status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3092         if (status < 0)
3093                 goto error;
3094         status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3095         if (status < 0)
3096                 goto error;
3097         status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3098         if (status < 0)
3099                 goto error;
3100         status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3101         if (status < 0)
3102                 goto error;
3103         status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3104         if (status < 0)
3105                 goto error;
3106         status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3107         if (status < 0)
3108                 goto error;
3109         status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3110         if (status < 0)
3111                 goto error;
3112         status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3113         if (status < 0)
3114                 goto error;
3115         status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3116         if (status < 0)
3117                 goto error;
3118         status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3119         if (status < 0)
3120                 goto error;
3121         status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3122         if (status < 0)
3123                 goto error;
3124         status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3125         if (status < 0)
3126                 goto error;
3127         status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3128         if (status < 0)
3129                 goto error;
3130         status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3131         if (status < 0)
3132                 goto error;
3133
3134         /* Initialize inner-loop KI gain factors */
3135         status = read16(state, SCU_RAM_AGC_KI__A, &data);
3136         if (status < 0)
3137                 goto error;
3138
3139         data = 0x0657;
3140         data &= ~SCU_RAM_AGC_KI_RF__M;
3141         data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3142         data &= ~SCU_RAM_AGC_KI_IF__M;
3143         data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3144
3145         status = write16(state, SCU_RAM_AGC_KI__A, data);
3146 error:
3147         if (status < 0)
3148                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3149         return status;
3150 }
3151
3152 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3153 {
3154         int status;
3155
3156         dprintk(1, "\n");
3157         if (packet_err == NULL)
3158                 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3159         else
3160                 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packet_err);
3161         if (status < 0)
3162                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3163         return status;
3164 }
3165
3166 static int dvbt_sc_command(struct drxk_state *state,
3167                          u16 cmd, u16 subcmd,
3168                          u16 param0, u16 param1, u16 param2,
3169                          u16 param3, u16 param4)
3170 {
3171         u16 cur_cmd = 0;
3172         u16 err_code = 0;
3173         u16 retry_cnt = 0;
3174         u16 sc_exec = 0;
3175         int status;
3176
3177         dprintk(1, "\n");
3178         status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3179         if (sc_exec != 1) {
3180                 /* SC is not running */
3181                 status = -EINVAL;
3182         }
3183         if (status < 0)
3184                 goto error;
3185
3186         /* Wait until sc is ready to receive command */
3187         retry_cnt = 0;
3188         do {
3189                 msleep(1);
3190                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3191                 retry_cnt++;
3192         } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3193         if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3194                 goto error;
3195
3196         /* Write sub-command */
3197         switch (cmd) {
3198                 /* All commands using sub-cmd */
3199         case OFDM_SC_RA_RAM_CMD_PROC_START:
3200         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3201         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3202                 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3203                 if (status < 0)
3204                         goto error;
3205                 break;
3206         default:
3207                 /* Do nothing */
3208                 break;
3209         }
3210
3211         /* Write needed parameters and the command */
3212         switch (cmd) {
3213                 /* All commands using 5 parameters */
3214                 /* All commands using 4 parameters */
3215                 /* All commands using 3 parameters */
3216                 /* All commands using 2 parameters */
3217         case OFDM_SC_RA_RAM_CMD_PROC_START:
3218         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3219         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3220                 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3221                 /* All commands using 1 parameters */
3222         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3223         case OFDM_SC_RA_RAM_CMD_USER_IO:
3224                 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3225                 /* All commands using 0 parameters */
3226         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3227         case OFDM_SC_RA_RAM_CMD_NULL:
3228                 /* Write command */
3229                 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3230                 break;
3231         default:
3232                 /* Unknown command */
3233                 status = -EINVAL;
3234         }
3235         if (status < 0)
3236                 goto error;
3237
3238         /* Wait until sc is ready processing command */
3239         retry_cnt = 0;
3240         do {
3241                 msleep(1);
3242                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3243                 retry_cnt++;
3244         } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
3245         if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))
3246                 goto error;
3247
3248         /* Check for illegal cmd */
3249         status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3250         if (err_code == 0xFFFF) {
3251                 /* illegal command */
3252                 status = -EINVAL;
3253         }
3254         if (status < 0)
3255                 goto error;
3256
3257         /* Retreive results parameters from SC */
3258         switch (cmd) {
3259                 /* All commands yielding 5 results */
3260                 /* All commands yielding 4 results */
3261                 /* All commands yielding 3 results */
3262                 /* All commands yielding 2 results */
3263                 /* All commands yielding 1 result */
3264         case OFDM_SC_RA_RAM_CMD_USER_IO:
3265         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3266                 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3267                 /* All commands yielding 0 results */
3268         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3269         case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3270         case OFDM_SC_RA_RAM_CMD_PROC_START:
3271         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3272         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3273         case OFDM_SC_RA_RAM_CMD_NULL:
3274                 break;
3275         default:
3276                 /* Unknown command */
3277                 status = -EINVAL;
3278                 break;
3279         }                       /* switch (cmd->cmd) */
3280 error:
3281         if (status < 0)
3282                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3283         return status;
3284 }
3285
3286 static int power_up_dvbt(struct drxk_state *state)
3287 {
3288         enum drx_power_mode power_mode = DRX_POWER_UP;
3289         int status;
3290
3291         dprintk(1, "\n");
3292         status = ctrl_power_mode(state, &power_mode);
3293         if (status < 0)
3294                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3295         return status;
3296 }
3297
3298 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3299 {
3300         int status;
3301
3302         dprintk(1, "\n");
3303         if (*enabled == true)
3304                 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3305         else
3306                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3307         if (status < 0)
3308                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3309         return status;
3310 }
3311
3312 #define DEFAULT_FR_THRES_8K     4000
3313 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3314 {
3315
3316         int status;
3317
3318         dprintk(1, "\n");
3319         if (*enabled == true) {
3320                 /* write mask to 1 */
3321                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3322                                    DEFAULT_FR_THRES_8K);
3323         } else {
3324                 /* write mask to 0 */
3325                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3326         }
3327         if (status < 0)
3328                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3329
3330         return status;
3331 }
3332
3333 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3334                                     struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
3335 {
3336         u16 data = 0;
3337         int status;
3338
3339         dprintk(1, "\n");
3340         status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3341         if (status < 0)
3342                 goto error;
3343
3344         switch (echo_thres->fft_mode) {
3345         case DRX_FFTMODE_2K:
3346                 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3347                 data |= ((echo_thres->threshold <<
3348                         OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3349                         & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3350                 break;
3351         case DRX_FFTMODE_8K:
3352                 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3353                 data |= ((echo_thres->threshold <<
3354                         OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3355                         & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3356                 break;
3357         default:
3358                 return -EINVAL;
3359         }
3360
3361         status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3362 error:
3363         if (status < 0)
3364                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3365         return status;
3366 }
3367
3368 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3369                                enum drxk_cfg_dvbt_sqi_speed *speed)
3370 {
3371         int status = -EINVAL;
3372
3373         dprintk(1, "\n");
3374
3375         switch (*speed) {
3376         case DRXK_DVBT_SQI_SPEED_FAST:
3377         case DRXK_DVBT_SQI_SPEED_MEDIUM:
3378         case DRXK_DVBT_SQI_SPEED_SLOW:
3379                 break;
3380         default:
3381                 goto error;
3382         }
3383         status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3384                            (u16) *speed);
3385 error:
3386         if (status < 0)
3387                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3388         return status;
3389 }
3390
3391 /*============================================================================*/
3392
3393 /**
3394 * \brief Activate DVBT specific presets
3395 * \param demod instance of demodulator.
3396 * \return DRXStatus_t.
3397 *
3398 * Called in DVBTSetStandard
3399 *
3400 */
3401 static int dvbt_activate_presets(struct drxk_state *state)
3402 {
3403         int status;
3404         bool setincenable = false;
3405         bool setfrenable = true;
3406
3407         struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K };
3408         struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K };
3409
3410         dprintk(1, "\n");
3411         status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3412         if (status < 0)
3413                 goto error;
3414         status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3415         if (status < 0)
3416                 goto error;
3417         status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3418         if (status < 0)
3419                 goto error;
3420         status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3421         if (status < 0)
3422                 goto error;
3423         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3424 error:
3425         if (status < 0)
3426                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3427         return status;
3428 }
3429
3430 /*============================================================================*/
3431
3432 /**
3433 * \brief Initialize channelswitch-independent settings for DVBT.
3434 * \param demod instance of demodulator.
3435 * \return DRXStatus_t.
3436 *
3437 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3438 * the DVB-T taps from the drxk_filters.h are used.
3439 */
3440 static int set_dvbt_standard(struct drxk_state *state,
3441                            enum operation_mode o_mode)
3442 {
3443         u16 cmd_result = 0;
3444         u16 data = 0;
3445         int status;
3446
3447         dprintk(1, "\n");
3448
3449         power_up_dvbt(state);
3450         /* added antenna switch */
3451         switch_antenna_to_dvbt(state);
3452         /* send OFDM reset command */
3453         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
3454         if (status < 0)
3455                 goto error;
3456
3457         /* send OFDM setenv command */
3458         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmd_result);
3459         if (status < 0)
3460                 goto error;
3461
3462         /* reset datapath for OFDM, processors first */
3463         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3464         if (status < 0)
3465                 goto error;
3466         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3467         if (status < 0)
3468                 goto error;
3469         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3470         if (status < 0)
3471                 goto error;
3472
3473         /* IQM setup */
3474         /* synchronize on ofdstate->m_festart */
3475         status = write16(state, IQM_AF_UPD_SEL__A, 1);
3476         if (status < 0)
3477                 goto error;
3478         /* window size for clipping ADC detection */
3479         status = write16(state, IQM_AF_CLP_LEN__A, 0);
3480         if (status < 0)
3481                 goto error;
3482         /* window size for for sense pre-SAW detection */
3483         status = write16(state, IQM_AF_SNS_LEN__A, 0);
3484         if (status < 0)
3485                 goto error;
3486         /* sense threshold for sense pre-SAW detection */
3487         status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3488         if (status < 0)
3489                 goto error;
3490         status = set_iqm_af(state, true);
3491         if (status < 0)
3492                 goto error;
3493
3494         status = write16(state, IQM_AF_AGC_RF__A, 0);
3495         if (status < 0)
3496                 goto error;
3497
3498         /* Impulse noise cruncher setup */
3499         status = write16(state, IQM_AF_INC_LCT__A, 0);  /* crunch in IQM_CF */
3500         if (status < 0)
3501                 goto error;
3502         status = write16(state, IQM_CF_DET_LCT__A, 0);  /* detect in IQM_CF */
3503         if (status < 0)
3504                 goto error;
3505         status = write16(state, IQM_CF_WND_LEN__A, 3);  /* peak detector window length */
3506         if (status < 0)
3507                 goto error;
3508
3509         status = write16(state, IQM_RC_STRETCH__A, 16);
3510         if (status < 0)
3511                 goto error;
3512         status = write16(state, IQM_CF_OUT_ENA__A, 0x4);        /* enable output 2 */
3513         if (status < 0)
3514                 goto error;
3515         status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3516         if (status < 0)
3517                 goto error;
3518         status = write16(state, IQM_CF_SCALE__A, 1600);
3519         if (status < 0)
3520                 goto error;
3521         status = write16(state, IQM_CF_SCALE_SH__A, 0);
3522         if (status < 0)
3523                 goto error;
3524
3525         /* virtual clipping threshold for clipping ADC detection */
3526         status = write16(state, IQM_AF_CLP_TH__A, 448);
3527         if (status < 0)
3528                 goto error;
3529         status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3530         if (status < 0)
3531                 goto error;
3532
3533         status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3534         if (status < 0)
3535                 goto error;
3536
3537         status = write16(state, IQM_CF_PKDTH__A, 2);    /* peak detector threshold */
3538         if (status < 0)
3539                 goto error;
3540         status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3541         if (status < 0)
3542                 goto error;
3543         /* enable power measurement interrupt */
3544         status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3545         if (status < 0)
3546                 goto error;
3547         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3548         if (status < 0)
3549                 goto error;
3550
3551         /* IQM will not be reset from here, sync ADC and update/init AGC */
3552         status = adc_synchronization(state);
3553         if (status < 0)
3554                 goto error;
3555         status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3556         if (status < 0)
3557                 goto error;
3558
3559         /* Halt SCU to enable safe non-atomic accesses */
3560         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3561         if (status < 0)
3562                 goto error;
3563
3564         status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3565         if (status < 0)
3566                 goto error;
3567         status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3568         if (status < 0)
3569                 goto error;
3570
3571         /* Set Noise Estimation notch width and enable DC fix */
3572         status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3573         if (status < 0)
3574                 goto error;
3575         data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3576         status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3577         if (status < 0)
3578                 goto error;
3579
3580         /* Activate SCU to enable SCU commands */
3581         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3582         if (status < 0)
3583                 goto error;
3584
3585         if (!state->m_drxk_a3_rom_code) {
3586                 /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay  */
3587                 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3588                 if (status < 0)
3589                         goto error;
3590         }
3591
3592         /* OFDM_SC setup */
3593 #ifdef COMPILE_FOR_NONRT
3594         status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3595         if (status < 0)
3596                 goto error;
3597         status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3598         if (status < 0)
3599                 goto error;
3600 #endif
3601
3602         /* FEC setup */
3603         status = write16(state, FEC_DI_INPUT_CTL__A, 1);        /* OFDM input */
3604         if (status < 0)
3605                 goto error;
3606
3607
3608 #ifdef COMPILE_FOR_NONRT
3609         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3610         if (status < 0)
3611                 goto error;
3612 #else
3613         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3614         if (status < 0)
3615                 goto error;
3616 #endif
3617         status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3618         if (status < 0)
3619                 goto error;
3620
3621         /* Setup MPEG bus */
3622         status = mpegts_dto_setup(state, OM_DVBT);
3623         if (status < 0)
3624                 goto error;
3625         /* Set DVBT Presets */
3626         status = dvbt_activate_presets(state);
3627         if (status < 0)
3628                 goto error;
3629
3630 error:
3631         if (status < 0)
3632                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3633         return status;
3634 }
3635
3636 /*============================================================================*/
3637 /**
3638 * \brief start dvbt demodulating for channel.
3639 * \param demod instance of demodulator.
3640 * \return DRXStatus_t.
3641 */
3642 static int dvbt_start(struct drxk_state *state)
3643 {
3644         u16 param1;
3645         int status;
3646         /* drxk_ofdm_sc_cmd_t scCmd; */
3647
3648         dprintk(1, "\n");
3649         /* start correct processes to get in lock */
3650         /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3651         param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3652         status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3653         if (status < 0)
3654                 goto error;
3655         /* start FEC OC */
3656         status = mpegts_start(state);
3657         if (status < 0)
3658                 goto error;
3659         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3660         if (status < 0)
3661                 goto error;
3662 error:
3663         if (status < 0)
3664                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3665         return status;
3666 }
3667
3668
3669 /*============================================================================*/
3670
3671 /**
3672 * \brief Set up dvbt demodulator for channel.
3673 * \param demod instance of demodulator.
3674 * \return DRXStatus_t.
3675 * // original DVBTSetChannel()
3676 */
3677 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3678                    s32 tuner_freq_offset)
3679 {
3680         u16 cmd_result = 0;
3681         u16 transmission_params = 0;
3682         u16 operation_mode = 0;
3683         u32 iqm_rc_rate_ofs = 0;
3684         u32 bandwidth = 0;
3685         u16 param1;
3686         int status;
3687
3688         dprintk(1, "IF =%d, TFO = %d\n", intermediate_freqk_hz, tuner_freq_offset);
3689
3690         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
3691         if (status < 0)
3692                 goto error;
3693
3694         /* Halt SCU to enable safe non-atomic accesses */
3695         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3696         if (status < 0)
3697                 goto error;
3698
3699         /* Stop processors */
3700         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3701         if (status < 0)
3702                 goto error;
3703         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3704         if (status < 0)
3705                 goto error;
3706
3707         /* Mandatory fix, always stop CP, required to set spl offset back to
3708                 hardware default (is set to 0 by ucode during pilot detection */
3709         status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3710         if (status < 0)
3711                 goto error;
3712
3713         /*== Write channel settings to device =====================================*/
3714
3715         /* mode */
3716         switch (state->props.transmission_mode) {
3717         case TRANSMISSION_MODE_AUTO:
3718         default:
3719                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3720                 /* fall through , try first guess DRX_FFTMODE_8K */
3721         case TRANSMISSION_MODE_8K:
3722                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3723                 break;
3724         case TRANSMISSION_MODE_2K:
3725                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3726                 break;
3727         }
3728
3729         /* guard */
3730         switch (state->props.guard_interval) {
3731         default:
3732         case GUARD_INTERVAL_AUTO:
3733                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3734                 /* fall through , try first guess DRX_GUARD_1DIV4 */
3735         case GUARD_INTERVAL_1_4:
3736                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3737                 break;
3738         case GUARD_INTERVAL_1_32:
3739                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3740                 break;
3741         case GUARD_INTERVAL_1_16:
3742                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3743                 break;
3744         case GUARD_INTERVAL_1_8:
3745                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3746                 break;
3747         }
3748
3749         /* hierarchy */
3750         switch (state->props.hierarchy) {
3751         case HIERARCHY_AUTO:
3752         case HIERARCHY_NONE:
3753         default:
3754                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3755                 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3756                 /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3757                 /* break; */
3758         case HIERARCHY_1:
3759                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3760                 break;
3761         case HIERARCHY_2:
3762                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3763                 break;
3764         case HIERARCHY_4:
3765                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3766                 break;
3767         }
3768
3769
3770         /* modulation */
3771         switch (state->props.modulation) {
3772         case QAM_AUTO:
3773         default:
3774                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3775                 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3776         case QAM_64:
3777                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3778                 break;
3779         case QPSK:
3780                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3781                 break;
3782         case QAM_16:
3783                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3784                 break;
3785         }
3786 #if 0
3787         /* No hierachical channels support in BDA */
3788         /* Priority (only for hierarchical channels) */
3789         switch (channel->priority) {
3790         case DRX_PRIORITY_LOW:
3791                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3792                 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3793                         OFDM_EC_SB_PRIOR_LO);
3794                 break;
3795         case DRX_PRIORITY_HIGH:
3796                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3797                 WR16(dev_addr, OFDM_EC_SB_PRIOR__A,
3798                         OFDM_EC_SB_PRIOR_HI));
3799                 break;
3800         case DRX_PRIORITY_UNKNOWN:      /* fall through */
3801         default:
3802                 status = -EINVAL;
3803                 goto error;
3804         }
3805 #else
3806         /* Set Priorty high */
3807         transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3808         status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3809         if (status < 0)
3810                 goto error;
3811 #endif
3812
3813         /* coderate */
3814         switch (state->props.code_rate_HP) {
3815         case FEC_AUTO:
3816         default:
3817                 operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3818                 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3819         case FEC_2_3:
3820                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3821                 break;
3822         case FEC_1_2:
3823                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3824                 break;
3825         case FEC_3_4:
3826                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3827                 break;
3828         case FEC_5_6:
3829                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3830                 break;
3831         case FEC_7_8:
3832                 transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3833                 break;
3834         }
3835
3836         /* SAW filter selection: normaly not necesarry, but if wanted
3837                 the application can select a SAW filter via the driver by using UIOs */
3838         /* First determine real bandwidth (Hz) */
3839         /* Also set delay for impulse noise cruncher */
3840         /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3841                 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3842                 functions */
3843         switch (state->props.bandwidth_hz) {
3844         case 0:
3845                 state->props.bandwidth_hz = 8000000;
3846                 /* fall though */
3847         case 8000000:
3848                 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3849                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3850                 if (status < 0)
3851                         goto error;
3852                 /* cochannel protection for PAL 8 MHz */
3853                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3854                 if (status < 0)
3855                         goto error;
3856                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3857                 if (status < 0)
3858                         goto error;
3859                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3860                 if (status < 0)
3861                         goto error;
3862                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3863                 if (status < 0)
3864                         goto error;
3865                 break;
3866         case 7000000:
3867                 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3868                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3869                 if (status < 0)
3870                         goto error;
3871                 /* cochannel protection for PAL 7 MHz */
3872                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3873                 if (status < 0)
3874                         goto error;
3875                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3876                 if (status < 0)
3877                         goto error;
3878                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3879                 if (status < 0)
3880                         goto error;
3881                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3882                 if (status < 0)
3883                         goto error;
3884                 break;
3885         case 6000000:
3886                 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3887                 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3888                 if (status < 0)
3889                         goto error;
3890                 /* cochannel protection for NTSC 6 MHz */
3891                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3892                 if (status < 0)
3893                         goto error;
3894                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3895                 if (status < 0)
3896                         goto error;
3897                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3898                 if (status < 0)
3899                         goto error;
3900                 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3901                 if (status < 0)
3902                         goto error;
3903                 break;
3904         default:
3905                 status = -EINVAL;
3906                 goto error;
3907         }
3908
3909         if (iqm_rc_rate_ofs == 0) {
3910                 /* Now compute IQM_RC_RATE_OFS
3911                         (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3912                         =>
3913                         ((SysFreq / BandWidth) * (2^21)) - (2^23)
3914                         */
3915                 /* (SysFreq / BandWidth) * (2^28)  */
3916                 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3917                         => assert(MAX(sysClk) < 16*MIN(bandwidth))
3918                         => assert(109714272 > 48000000) = true so Frac 28 can be used  */
3919                 iqm_rc_rate_ofs = Frac28a((u32)
3920                                         ((state->m_sys_clock_freq *
3921                                                 1000) / 3), bandwidth);
3922                 /* (SysFreq / BandWidth) * (2^21), rounding before truncating  */
3923                 if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
3924                         iqm_rc_rate_ofs += 0x80L;
3925                 iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
3926                 /* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
3927                 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23);
3928         }
3929
3930         iqm_rc_rate_ofs &=
3931                 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3932                 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
3933         status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
3934         if (status < 0)
3935                 goto error;
3936
3937         /* Bandwidth setting done */
3938
3939 #if 0
3940         status = dvbt_set_frequency_shift(demod, channel, tuner_offset);
3941         if (status < 0)
3942                 goto error;
3943 #endif
3944         status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true);
3945         if (status < 0)
3946                 goto error;
3947
3948         /*== start SC, write channel settings to SC ===============================*/
3949
3950         /* Activate SCU to enable SCU commands */
3951         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3952         if (status < 0)
3953                 goto error;
3954
3955         /* Enable SC after setting all other parameters */
3956         status = write16(state, OFDM_SC_COMM_STATE__A, 0);
3957         if (status < 0)
3958                 goto error;
3959         status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
3960         if (status < 0)
3961                 goto error;
3962
3963
3964         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result);
3965         if (status < 0)
3966                 goto error;
3967
3968         /* Write SC parameter registers, set all AUTO flags in operation mode */
3969         param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
3970                         OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
3971                         OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
3972                         OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
3973                         OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
3974         status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
3975                                 0, transmission_params, param1, 0, 0, 0);
3976         if (status < 0)
3977                 goto error;
3978
3979         if (!state->m_drxk_a3_rom_code)
3980                 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
3981 error:
3982         if (status < 0)
3983                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3984
3985         return status;
3986 }
3987
3988
3989 /*============================================================================*/
3990
3991 /**
3992 * \brief Retreive lock status .
3993 * \param demod    Pointer to demodulator instance.
3994 * \param lockStat Pointer to lock status structure.
3995 * \return DRXStatus_t.
3996 *
3997 */
3998 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
3999 {
4000         int status;
4001         const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4002                                     OFDM_SC_RA_RAM_LOCK_FEC__M);
4003         const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4004         const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4005
4006         u16 sc_ra_ram_lock = 0;
4007         u16 sc_comm_exec = 0;
4008
4009         dprintk(1, "\n");
4010
4011         *p_lock_status = NOT_LOCKED;
4012         /* driver 0.9.0 */
4013         /* Check if SC is running */
4014         status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4015         if (status < 0)
4016                 goto end;
4017         if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP)
4018                 goto end;
4019
4020         status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4021         if (status < 0)
4022                 goto end;
4023
4024         if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask)
4025                 *p_lock_status = MPEG_LOCK;
4026         else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask)
4027                 *p_lock_status = FEC_LOCK;
4028         else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask)
4029                 *p_lock_status = DEMOD_LOCK;
4030         else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4031                 *p_lock_status = NEVER_LOCK;
4032 end:
4033         if (status < 0)
4034                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4035
4036         return status;
4037 }
4038
4039 static int power_up_qam(struct drxk_state *state)
4040 {
4041         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
4042         int status;
4043
4044         dprintk(1, "\n");
4045         status = ctrl_power_mode(state, &power_mode);
4046         if (status < 0)
4047                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4048
4049         return status;
4050 }
4051
4052
4053 /** Power Down QAM */
4054 static int power_down_qam(struct drxk_state *state)
4055 {
4056         u16 data = 0;
4057         u16 cmd_result;
4058         int status = 0;
4059
4060         dprintk(1, "\n");
4061         status = read16(state, SCU_COMM_EXEC__A, &data);
4062         if (status < 0)
4063                 goto error;
4064         if (data == SCU_COMM_EXEC_ACTIVE) {
4065                 /*
4066                         STOP demodulator
4067                         QAM and HW blocks
4068                         */
4069                 /* stop all comstate->m_exec */
4070                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4071                 if (status < 0)
4072                         goto error;
4073                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
4074                 if (status < 0)
4075                         goto error;
4076         }
4077         /* powerdown AFE                   */
4078         status = set_iqm_af(state, false);
4079
4080 error:
4081         if (status < 0)
4082                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4083
4084         return status;
4085 }
4086
4087 /*============================================================================*/
4088
4089 /**
4090 * \brief Setup of the QAM Measurement intervals for signal quality
4091 * \param demod instance of demod.
4092 * \param modulation current modulation.
4093 * \return DRXStatus_t.
4094 *
4095 *  NOTE:
4096 *  Take into account that for certain settings the errorcounters can overflow.
4097 *  The implementation does not check this.
4098 *
4099 */
4100 static int set_qam_measurement(struct drxk_state *state,
4101                              enum e_drxk_constellation modulation,
4102                              u32 symbol_rate)
4103 {
4104         u32 fec_bits_desired = 0;       /* BER accounting period */
4105         u32 fec_rs_period_total = 0;    /* Total period */
4106         u16 fec_rs_prescale = 0;        /* ReedSolomon Measurement Prescale */
4107         u16 fec_rs_period = 0;  /* Value for corresponding I2C register */
4108         int status = 0;
4109
4110         dprintk(1, "\n");
4111
4112         fec_rs_prescale = 1;
4113         /* fec_bits_desired = symbol_rate [kHz] *
4114                 FrameLenght [ms] *
4115                 (modulation + 1) *
4116                 SyncLoss (== 1) *
4117                 ViterbiLoss (==1)
4118                 */
4119         switch (modulation) {
4120         case DRX_CONSTELLATION_QAM16:
4121                 fec_bits_desired = 4 * symbol_rate;
4122                 break;
4123         case DRX_CONSTELLATION_QAM32:
4124                 fec_bits_desired = 5 * symbol_rate;
4125                 break;
4126         case DRX_CONSTELLATION_QAM64:
4127                 fec_bits_desired = 6 * symbol_rate;
4128                 break;
4129         case DRX_CONSTELLATION_QAM128:
4130                 fec_bits_desired = 7 * symbol_rate;
4131                 break;
4132         case DRX_CONSTELLATION_QAM256:
4133                 fec_bits_desired = 8 * symbol_rate;
4134                 break;
4135         default:
4136                 status = -EINVAL;
4137         }
4138         if (status < 0)
4139                 goto error;
4140
4141         fec_bits_desired /= 1000;       /* symbol_rate [Hz] -> symbol_rate [kHz]  */
4142         fec_bits_desired *= 500;        /* meas. period [ms] */
4143
4144         /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4145         /* fec_rs_period_total = fec_bits_desired / 1632 */
4146         fec_rs_period_total = (fec_bits_desired / 1632UL) + 1;  /* roughly ceil */
4147
4148         /* fec_rs_period_total =  fec_rs_prescale * fec_rs_period  */
4149         fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16);
4150         if (fec_rs_prescale == 0) {
4151                 /* Divide by zero (though impossible) */
4152                 status = -EINVAL;
4153                 if (status < 0)
4154                         goto error;
4155         }
4156         fec_rs_period =
4157                 ((u16) fec_rs_period_total +
4158                 (fec_rs_prescale >> 1)) / fec_rs_prescale;
4159
4160         /* write corresponding registers */
4161         status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4162         if (status < 0)
4163                 goto error;
4164         status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale);
4165         if (status < 0)
4166                 goto error;
4167         status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4168 error:
4169         if (status < 0)
4170                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4171         return status;
4172 }
4173
4174 static int set_qam16(struct drxk_state *state)
4175 {
4176         int status = 0;
4177
4178         dprintk(1, "\n");
4179         /* QAM Equalizer Setup */
4180         /* Equalizer */
4181         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4182         if (status < 0)
4183                 goto error;
4184         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4185         if (status < 0)
4186                 goto error;
4187         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4188         if (status < 0)
4189                 goto error;
4190         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4191         if (status < 0)
4192                 goto error;
4193         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4194         if (status < 0)
4195                 goto error;
4196         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4197         if (status < 0)
4198                 goto error;
4199         /* Decision Feedback Equalizer */
4200         status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4201         if (status < 0)
4202                 goto error;
4203         status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4204         if (status < 0)
4205                 goto error;
4206         status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4207         if (status < 0)
4208                 goto error;
4209         status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4210         if (status < 0)
4211                 goto error;
4212         status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4213         if (status < 0)
4214                 goto error;
4215         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4216         if (status < 0)
4217                 goto error;
4218
4219         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4220         if (status < 0)
4221                 goto error;
4222         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4223         if (status < 0)
4224                 goto error;
4225         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4226         if (status < 0)
4227                 goto error;
4228
4229         /* QAM Slicer Settings */
4230         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4231         if (status < 0)
4232                 goto error;
4233
4234         /* QAM Loop Controller Coeficients */
4235         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4236         if (status < 0)
4237                 goto error;
4238         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4239         if (status < 0)
4240                 goto error;
4241         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4242         if (status < 0)
4243                 goto error;
4244         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4245         if (status < 0)
4246                 goto error;
4247         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4248         if (status < 0)
4249                 goto error;
4250         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4251         if (status < 0)
4252                 goto error;
4253         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4254         if (status < 0)
4255                 goto error;
4256         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4257         if (status < 0)
4258                 goto error;
4259
4260         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4261         if (status < 0)
4262                 goto error;
4263         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4264         if (status < 0)
4265                 goto error;
4266         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4267         if (status < 0)
4268                 goto error;
4269         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4270         if (status < 0)
4271                 goto error;
4272         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4273         if (status < 0)
4274                 goto error;
4275         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4276         if (status < 0)
4277                 goto error;
4278         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4279         if (status < 0)
4280                 goto error;
4281         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4282         if (status < 0)
4283                 goto error;
4284         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4285         if (status < 0)
4286                 goto error;
4287         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4288         if (status < 0)
4289                 goto error;
4290         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4291         if (status < 0)
4292                 goto error;
4293         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4294         if (status < 0)
4295                 goto error;
4296
4297
4298         /* QAM State Machine (FSM) Thresholds */
4299
4300         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4301         if (status < 0)
4302                 goto error;
4303         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4304         if (status < 0)
4305                 goto error;
4306         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4307         if (status < 0)
4308                 goto error;
4309         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4310         if (status < 0)
4311                 goto error;
4312         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4313         if (status < 0)
4314                 goto error;
4315         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4316         if (status < 0)
4317                 goto error;
4318
4319         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4320         if (status < 0)
4321                 goto error;
4322         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4323         if (status < 0)
4324                 goto error;
4325         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4326         if (status < 0)
4327                 goto error;
4328
4329
4330         /* QAM FSM Tracking Parameters */
4331
4332         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4333         if (status < 0)
4334                 goto error;
4335         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4336         if (status < 0)
4337                 goto error;
4338         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4339         if (status < 0)
4340                 goto error;
4341         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4342         if (status < 0)
4343                 goto error;
4344         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4345         if (status < 0)
4346                 goto error;
4347         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4348         if (status < 0)
4349                 goto error;
4350         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4351         if (status < 0)
4352                 goto error;
4353
4354 error:
4355         if (status < 0)
4356                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4357         return status;
4358 }
4359
4360 /*============================================================================*/
4361
4362 /**
4363 * \brief QAM32 specific setup
4364 * \param demod instance of demod.
4365 * \return DRXStatus_t.
4366 */
4367 static int set_qam32(struct drxk_state *state)
4368 {
4369         int status = 0;
4370
4371         dprintk(1, "\n");
4372
4373         /* QAM Equalizer Setup */
4374         /* Equalizer */
4375         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4376         if (status < 0)
4377                 goto error;
4378         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4379         if (status < 0)
4380                 goto error;
4381         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4382         if (status < 0)
4383                 goto error;
4384         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4385         if (status < 0)
4386                 goto error;
4387         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4388         if (status < 0)
4389                 goto error;
4390         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4391         if (status < 0)
4392                 goto error;
4393
4394         /* Decision Feedback Equalizer */
4395         status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4396         if (status < 0)
4397                 goto error;
4398         status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4399         if (status < 0)
4400                 goto error;
4401         status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4402         if (status < 0)
4403                 goto error;
4404         status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4405         if (status < 0)
4406                 goto error;
4407         status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4408         if (status < 0)
4409                 goto error;
4410         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4411         if (status < 0)
4412                 goto error;
4413
4414         status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4415         if (status < 0)
4416                 goto error;
4417         status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4418         if (status < 0)
4419                 goto error;
4420         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4421         if (status < 0)
4422                 goto error;
4423
4424         /* QAM Slicer Settings */
4425
4426         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4427         if (status < 0)
4428                 goto error;
4429
4430
4431         /* QAM Loop Controller Coeficients */
4432
4433         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4434         if (status < 0)
4435                 goto error;
4436         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4437         if (status < 0)
4438                 goto error;
4439         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4440         if (status < 0)
4441                 goto error;
4442         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4443         if (status < 0)
4444                 goto error;
4445         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4446         if (status < 0)
4447                 goto error;
4448         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4449         if (status < 0)
4450                 goto error;
4451         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4452         if (status < 0)
4453                 goto error;
4454         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4455         if (status < 0)
4456                 goto error;
4457
4458         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4459         if (status < 0)
4460                 goto error;
4461         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4462         if (status < 0)
4463                 goto error;
4464         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4465         if (status < 0)
4466                 goto error;
4467         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4468         if (status < 0)
4469                 goto error;
4470         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4471         if (status < 0)
4472                 goto error;
4473         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4474         if (status < 0)
4475                 goto error;
4476         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4477         if (status < 0)
4478                 goto error;
4479         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4480         if (status < 0)
4481                 goto error;
4482         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4483         if (status < 0)
4484                 goto error;
4485         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4486         if (status < 0)
4487                 goto error;
4488         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4489         if (status < 0)
4490                 goto error;
4491         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4492         if (status < 0)
4493                 goto error;
4494
4495
4496         /* QAM State Machine (FSM) Thresholds */
4497
4498         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4499         if (status < 0)
4500                 goto error;
4501         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4502         if (status < 0)
4503                 goto error;
4504         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4505         if (status < 0)
4506                 goto error;
4507         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4508         if (status < 0)
4509                 goto error;
4510         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4511         if (status < 0)
4512                 goto error;
4513         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4514         if (status < 0)
4515                 goto error;
4516
4517         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4518         if (status < 0)
4519                 goto error;
4520         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4521         if (status < 0)
4522                 goto error;
4523         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4524         if (status < 0)
4525                 goto error;
4526
4527
4528         /* QAM FSM Tracking Parameters */
4529
4530         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4531         if (status < 0)
4532                 goto error;
4533         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4534         if (status < 0)
4535                 goto error;
4536         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4537         if (status < 0)
4538                 goto error;
4539         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4540         if (status < 0)
4541                 goto error;
4542         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4543         if (status < 0)
4544                 goto error;
4545         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4546         if (status < 0)
4547                 goto error;
4548         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4549 error:
4550         if (status < 0)
4551                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4552         return status;
4553 }
4554
4555 /*============================================================================*/
4556
4557 /**
4558 * \brief QAM64 specific setup
4559 * \param demod instance of demod.
4560 * \return DRXStatus_t.
4561 */
4562 static int set_qam64(struct drxk_state *state)
4563 {
4564         int status = 0;
4565
4566         dprintk(1, "\n");
4567         /* QAM Equalizer Setup */
4568         /* Equalizer */
4569         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4570         if (status < 0)
4571                 goto error;
4572         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4573         if (status < 0)
4574                 goto error;
4575         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4576         if (status < 0)
4577                 goto error;
4578         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4579         if (status < 0)
4580                 goto error;
4581         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4582         if (status < 0)
4583                 goto error;
4584         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4585         if (status < 0)
4586                 goto error;
4587
4588         /* Decision Feedback Equalizer */
4589         status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4590         if (status < 0)
4591                 goto error;
4592         status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4593         if (status < 0)
4594                 goto error;
4595         status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4596         if (status < 0)
4597                 goto error;
4598         status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4599         if (status < 0)
4600                 goto error;
4601         status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4602         if (status < 0)
4603                 goto error;
4604         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4605         if (status < 0)
4606                 goto error;
4607
4608         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4609         if (status < 0)
4610                 goto error;
4611         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4612         if (status < 0)
4613                 goto error;
4614         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4615         if (status < 0)
4616                 goto error;
4617
4618         /* QAM Slicer Settings */
4619         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4620         if (status < 0)
4621                 goto error;
4622
4623
4624         /* QAM Loop Controller Coeficients */
4625
4626         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4627         if (status < 0)
4628                 goto error;
4629         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4630         if (status < 0)
4631                 goto error;
4632         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4633         if (status < 0)
4634                 goto error;
4635         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4636         if (status < 0)
4637                 goto error;
4638         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4639         if (status < 0)
4640                 goto error;
4641         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4642         if (status < 0)
4643                 goto error;
4644         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4645         if (status < 0)
4646                 goto error;
4647         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4648         if (status < 0)
4649                 goto error;
4650
4651         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4652         if (status < 0)
4653                 goto error;
4654         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4655         if (status < 0)
4656                 goto error;
4657         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4658         if (status < 0)
4659                 goto error;
4660         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4661         if (status < 0)
4662                 goto error;
4663         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4664         if (status < 0)
4665                 goto error;
4666         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4667         if (status < 0)
4668                 goto error;
4669         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4670         if (status < 0)
4671                 goto error;
4672         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4673         if (status < 0)
4674                 goto error;
4675         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4676         if (status < 0)
4677                 goto error;
4678         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4679         if (status < 0)
4680                 goto error;
4681         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4682         if (status < 0)
4683                 goto error;
4684         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4685         if (status < 0)
4686                 goto error;
4687
4688
4689         /* QAM State Machine (FSM) Thresholds */
4690
4691         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4692         if (status < 0)
4693                 goto error;
4694         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4695         if (status < 0)
4696                 goto error;
4697         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4698         if (status < 0)
4699                 goto error;
4700         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4701         if (status < 0)
4702                 goto error;
4703         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4704         if (status < 0)
4705                 goto error;
4706         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4707         if (status < 0)
4708                 goto error;
4709
4710         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4711         if (status < 0)
4712                 goto error;
4713         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4714         if (status < 0)
4715                 goto error;
4716         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4717         if (status < 0)
4718                 goto error;
4719
4720
4721         /* QAM FSM Tracking Parameters */
4722
4723         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4724         if (status < 0)
4725                 goto error;
4726         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4727         if (status < 0)
4728                 goto error;
4729         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4730         if (status < 0)
4731                 goto error;
4732         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4733         if (status < 0)
4734                 goto error;
4735         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4736         if (status < 0)
4737                 goto error;
4738         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4739         if (status < 0)
4740                 goto error;
4741         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4742 error:
4743         if (status < 0)
4744                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4745
4746         return status;
4747 }
4748
4749 /*============================================================================*/
4750
4751 /**
4752 * \brief QAM128 specific setup
4753 * \param demod: instance of demod.
4754 * \return DRXStatus_t.
4755 */
4756 static int set_qam128(struct drxk_state *state)
4757 {
4758         int status = 0;
4759
4760         dprintk(1, "\n");
4761         /* QAM Equalizer Setup */
4762         /* Equalizer */
4763         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4764         if (status < 0)
4765                 goto error;
4766         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4767         if (status < 0)
4768                 goto error;
4769         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4770         if (status < 0)
4771                 goto error;
4772         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4773         if (status < 0)
4774                 goto error;
4775         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4776         if (status < 0)
4777                 goto error;
4778         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4779         if (status < 0)
4780                 goto error;
4781
4782         /* Decision Feedback Equalizer */
4783         status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4784         if (status < 0)
4785                 goto error;
4786         status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4787         if (status < 0)
4788                 goto error;
4789         status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4790         if (status < 0)
4791                 goto error;
4792         status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4793         if (status < 0)
4794                 goto error;
4795         status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4796         if (status < 0)
4797                 goto error;
4798         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4799         if (status < 0)
4800                 goto error;
4801
4802         status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4803         if (status < 0)
4804                 goto error;
4805         status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4806         if (status < 0)
4807                 goto error;
4808         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4809         if (status < 0)
4810                 goto error;
4811
4812
4813         /* QAM Slicer Settings */
4814
4815         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4816         if (status < 0)
4817                 goto error;
4818
4819
4820         /* QAM Loop Controller Coeficients */
4821
4822         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4823         if (status < 0)
4824                 goto error;
4825         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4826         if (status < 0)
4827                 goto error;
4828         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4829         if (status < 0)
4830                 goto error;
4831         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4832         if (status < 0)
4833                 goto error;
4834         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4835         if (status < 0)
4836                 goto error;
4837         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4838         if (status < 0)
4839                 goto error;
4840         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4841         if (status < 0)
4842                 goto error;
4843         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4844         if (status < 0)
4845                 goto error;
4846
4847         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4848         if (status < 0)
4849                 goto error;
4850         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4851         if (status < 0)
4852                 goto error;
4853         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4854         if (status < 0)
4855                 goto error;
4856         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4857         if (status < 0)
4858                 goto error;
4859         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4860         if (status < 0)
4861                 goto error;
4862         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4863         if (status < 0)
4864                 goto error;
4865         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4866         if (status < 0)
4867                 goto error;
4868         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4869         if (status < 0)
4870                 goto error;
4871         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4872         if (status < 0)
4873                 goto error;
4874         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4875         if (status < 0)
4876                 goto error;
4877         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4878         if (status < 0)
4879                 goto error;
4880         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4881         if (status < 0)
4882                 goto error;
4883
4884
4885         /* QAM State Machine (FSM) Thresholds */
4886
4887         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4888         if (status < 0)
4889                 goto error;
4890         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4891         if (status < 0)
4892                 goto error;
4893         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4894         if (status < 0)
4895                 goto error;
4896         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4897         if (status < 0)
4898                 goto error;
4899         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4900         if (status < 0)
4901                 goto error;
4902         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4903         if (status < 0)
4904                 goto error;
4905
4906         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4907         if (status < 0)
4908                 goto error;
4909         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4910         if (status < 0)
4911                 goto error;
4912
4913         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4914         if (status < 0)
4915                 goto error;
4916
4917         /* QAM FSM Tracking Parameters */
4918
4919         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4920         if (status < 0)
4921                 goto error;
4922         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4923         if (status < 0)
4924                 goto error;
4925         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4926         if (status < 0)
4927                 goto error;
4928         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4929         if (status < 0)
4930                 goto error;
4931         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4932         if (status < 0)
4933                 goto error;
4934         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
4935         if (status < 0)
4936                 goto error;
4937         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
4938 error:
4939         if (status < 0)
4940                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4941
4942         return status;
4943 }
4944
4945 /*============================================================================*/
4946
4947 /**
4948 * \brief QAM256 specific setup
4949 * \param demod: instance of demod.
4950 * \return DRXStatus_t.
4951 */
4952 static int set_qam256(struct drxk_state *state)
4953 {
4954         int status = 0;
4955
4956         dprintk(1, "\n");
4957         /* QAM Equalizer Setup */
4958         /* Equalizer */
4959         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
4960         if (status < 0)
4961                 goto error;
4962         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
4963         if (status < 0)
4964                 goto error;
4965         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
4966         if (status < 0)
4967                 goto error;
4968         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
4969         if (status < 0)
4970                 goto error;
4971         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
4972         if (status < 0)
4973                 goto error;
4974         status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
4975         if (status < 0)
4976                 goto error;
4977
4978         /* Decision Feedback Equalizer */
4979         status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
4980         if (status < 0)
4981                 goto error;
4982         status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
4983         if (status < 0)
4984                 goto error;
4985         status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
4986         if (status < 0)
4987                 goto error;
4988         status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
4989         if (status < 0)
4990                 goto error;
4991         status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
4992         if (status < 0)
4993                 goto error;
4994         status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4995         if (status < 0)
4996                 goto error;
4997
4998         status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4999         if (status < 0)
5000                 goto error;
5001         status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5002         if (status < 0)
5003                 goto error;
5004         status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5005         if (status < 0)
5006                 goto error;
5007
5008         /* QAM Slicer Settings */
5009
5010         status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5011         if (status < 0)
5012                 goto error;
5013
5014
5015         /* QAM Loop Controller Coeficients */
5016
5017         status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5018         if (status < 0)
5019                 goto error;
5020         status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5021         if (status < 0)
5022                 goto error;
5023         status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5024         if (status < 0)
5025                 goto error;
5026         status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5027         if (status < 0)
5028                 goto error;
5029         status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5030         if (status < 0)
5031                 goto error;
5032         status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5033         if (status < 0)
5034                 goto error;
5035         status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5036         if (status < 0)
5037                 goto error;
5038         status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5039         if (status < 0)
5040                 goto error;
5041
5042         status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5043         if (status < 0)
5044                 goto error;
5045         status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5046         if (status < 0)
5047                 goto error;
5048         status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5049         if (status < 0)
5050                 goto error;
5051         status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5052         if (status < 0)
5053                 goto error;
5054         status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5055         if (status < 0)
5056                 goto error;
5057         status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5058         if (status < 0)
5059                 goto error;
5060         status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5061         if (status < 0)
5062                 goto error;
5063         status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5064         if (status < 0)
5065                 goto error;
5066         status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5067         if (status < 0)
5068                 goto error;
5069         status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5070         if (status < 0)
5071                 goto error;
5072         status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5073         if (status < 0)
5074                 goto error;
5075         status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5076         if (status < 0)
5077                 goto error;
5078
5079
5080         /* QAM State Machine (FSM) Thresholds */
5081
5082         status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5083         if (status < 0)
5084                 goto error;
5085         status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5086         if (status < 0)
5087                 goto error;
5088         status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5089         if (status < 0)
5090                 goto error;
5091         status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5092         if (status < 0)
5093                 goto error;
5094         status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5095         if (status < 0)
5096                 goto error;
5097         status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5098         if (status < 0)
5099                 goto error;
5100
5101         status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5102         if (status < 0)
5103                 goto error;
5104         status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5105         if (status < 0)
5106                 goto error;
5107         status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5108         if (status < 0)
5109                 goto error;
5110
5111
5112         /* QAM FSM Tracking Parameters */
5113
5114         status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5115         if (status < 0)
5116                 goto error;
5117         status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5118         if (status < 0)
5119                 goto error;
5120         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5121         if (status < 0)
5122                 goto error;
5123         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5124         if (status < 0)
5125                 goto error;
5126         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5127         if (status < 0)
5128                 goto error;
5129         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5130         if (status < 0)
5131                 goto error;
5132         status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5133 error:
5134         if (status < 0)
5135                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5136         return status;
5137 }
5138
5139
5140 /*============================================================================*/
5141 /**
5142 * \brief Reset QAM block.
5143 * \param demod:   instance of demod.
5144 * \param channel: pointer to channel data.
5145 * \return DRXStatus_t.
5146 */
5147 static int qam_reset_qam(struct drxk_state *state)
5148 {
5149         int status;
5150         u16 cmd_result;
5151
5152         dprintk(1, "\n");
5153         /* Stop QAM comstate->m_exec */
5154         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5155         if (status < 0)
5156                 goto error;
5157
5158         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
5159 error:
5160         if (status < 0)
5161                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5162         return status;
5163 }
5164
5165 /*============================================================================*/
5166
5167 /**
5168 * \brief Set QAM symbolrate.
5169 * \param demod:   instance of demod.
5170 * \param channel: pointer to channel data.
5171 * \return DRXStatus_t.
5172 */
5173 static int qam_set_symbolrate(struct drxk_state *state)
5174 {
5175         u32 adc_frequency = 0;
5176         u32 symb_freq = 0;
5177         u32 iqm_rc_rate = 0;
5178         u16 ratesel = 0;
5179         u32 lc_symb_rate = 0;
5180         int status;
5181
5182         dprintk(1, "\n");
5183         /* Select & calculate correct IQM rate */
5184         adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5185         ratesel = 0;
5186         /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5187         if (state->props.symbol_rate <= 1188750)
5188                 ratesel = 3;
5189         else if (state->props.symbol_rate <= 2377500)
5190                 ratesel = 2;
5191         else if (state->props.symbol_rate <= 4755000)
5192                 ratesel = 1;
5193         status = write16(state, IQM_FD_RATESEL__A, ratesel);
5194         if (status < 0)
5195                 goto error;
5196
5197         /*
5198                 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5199                 */
5200         symb_freq = state->props.symbol_rate * (1 << ratesel);
5201         if (symb_freq == 0) {
5202                 /* Divide by zero */
5203                 status = -EINVAL;
5204                 goto error;
5205         }
5206         iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) +
5207                 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) -
5208                 (1 << 23);
5209         status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5210         if (status < 0)
5211                 goto error;
5212         state->m_iqm_rc_rate = iqm_rc_rate;
5213         /*
5214                 LcSymbFreq = round (.125 *  symbolrate / adc_freq * (1<<15))
5215                 */
5216         symb_freq = state->props.symbol_rate;
5217         if (adc_frequency == 0) {
5218                 /* Divide by zero */
5219                 status = -EINVAL;
5220                 goto error;
5221         }
5222         lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) +
5223                 (Frac28a((symb_freq % adc_frequency), adc_frequency) >>
5224                 16);
5225         if (lc_symb_rate > 511)
5226                 lc_symb_rate = 511;
5227         status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5228
5229 error:
5230         if (status < 0)
5231                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5232         return status;
5233 }
5234
5235 /*============================================================================*/
5236
5237 /**
5238 * \brief Get QAM lock status.
5239 * \param demod:   instance of demod.
5240 * \param channel: pointer to channel data.
5241 * \return DRXStatus_t.
5242 */
5243
5244 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5245 {
5246         int status;
5247         u16 result[2] = { 0, 0 };
5248
5249         dprintk(1, "\n");
5250         *p_lock_status = NOT_LOCKED;
5251         status = scu_command(state,
5252                         SCU_RAM_COMMAND_STANDARD_QAM |
5253                         SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5254                         result);
5255         if (status < 0)
5256                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5257
5258         if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5259                 /* 0x0000 NOT LOCKED */
5260         } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5261                 /* 0x4000 DEMOD LOCKED */
5262                 *p_lock_status = DEMOD_LOCK;
5263         } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5264                 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5265                 *p_lock_status = MPEG_LOCK;
5266         } else {
5267                 /* 0xC000 NEVER LOCKED */
5268                 /* (system will never be able to lock to the signal) */
5269                 /* TODO: check this, intermediate & standard specific lock states are not
5270                    taken into account here */
5271                 *p_lock_status = NEVER_LOCK;
5272         }
5273         return status;
5274 }
5275
5276 #define QAM_MIRROR__M         0x03
5277 #define QAM_MIRROR_NORMAL     0x00
5278 #define QAM_MIRRORED          0x01
5279 #define QAM_MIRROR_AUTO_ON    0x02
5280 #define QAM_LOCKRANGE__M      0x10
5281 #define QAM_LOCKRANGE_NORMAL  0x10
5282
5283 static int qam_demodulator_command(struct drxk_state *state,
5284                                  int number_of_parameters)
5285 {
5286         int status;
5287         u16 cmd_result;
5288         u16 set_param_parameters[4] = { 0, 0, 0, 0 };
5289
5290         set_param_parameters[0] = state->m_constellation;       /* modulation     */
5291         set_param_parameters[1] = DRXK_QAM_I12_J17;     /* interleave mode   */
5292
5293         if (number_of_parameters == 2) {
5294                 u16 set_env_parameters[1] = { 0 };
5295
5296                 if (state->m_operation_mode == OM_QAM_ITU_C)
5297                         set_env_parameters[0] = QAM_TOP_ANNEX_C;
5298                 else
5299                         set_env_parameters[0] = QAM_TOP_ANNEX_A;
5300
5301                 status = scu_command(state,
5302                                      SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
5303                                      1, set_env_parameters, 1, &cmd_result);
5304                 if (status < 0)
5305                         goto error;
5306
5307                 status = scu_command(state,
5308                                      SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5309                                      number_of_parameters, set_param_parameters,
5310                                      1, &cmd_result);
5311         } else if (number_of_parameters == 4) {
5312                 if (state->m_operation_mode == OM_QAM_ITU_C)
5313                         set_param_parameters[2] = QAM_TOP_ANNEX_C;
5314                 else
5315                         set_param_parameters[2] = QAM_TOP_ANNEX_A;
5316
5317                 set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON);
5318                 /* Env parameters */
5319                 /* check for LOCKRANGE Extented */
5320                 /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
5321
5322                 status = scu_command(state,
5323                                      SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
5324                                      number_of_parameters, set_param_parameters,
5325                                      1, &cmd_result);
5326         } else {
5327                 printk(KERN_WARNING "drxk: Unknown QAM demodulator parameter "
5328                         "count %d\n", number_of_parameters);
5329                 status = -EINVAL;
5330         }
5331
5332 error:
5333         if (status < 0)
5334                 printk(KERN_WARNING "drxk: Warning %d on %s\n",
5335                        status, __func__);
5336         return status;
5337 }
5338
5339 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5340                   s32 tuner_freq_offset)
5341 {
5342         int status;
5343         u16 cmd_result;
5344         int qam_demod_param_count = state->qam_demod_parameter_count;
5345
5346         dprintk(1, "\n");
5347         /*
5348          * STEP 1: reset demodulator
5349          *      resets FEC DI and FEC RS
5350          *      resets QAM block
5351          *      resets SCU variables
5352          */
5353         status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5354         if (status < 0)
5355                 goto error;
5356         status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5357         if (status < 0)
5358                 goto error;
5359         status = qam_reset_qam(state);
5360         if (status < 0)
5361                 goto error;
5362
5363         /*
5364          * STEP 2: configure demodulator
5365          *      -set params; resets IQM,QAM,FEC HW; initializes some
5366          *       SCU variables
5367          */
5368         status = qam_set_symbolrate(state);
5369         if (status < 0)
5370                 goto error;
5371
5372         /* Set params */
5373         switch (state->props.modulation) {
5374         case QAM_256:
5375                 state->m_constellation = DRX_CONSTELLATION_QAM256;
5376                 break;
5377         case QAM_AUTO:
5378         case QAM_64:
5379                 state->m_constellation = DRX_CONSTELLATION_QAM64;
5380                 break;
5381         case QAM_16:
5382                 state->m_constellation = DRX_CONSTELLATION_QAM16;
5383                 break;
5384         case QAM_32:
5385                 state->m_constellation = DRX_CONSTELLATION_QAM32;
5386                 break;
5387         case QAM_128:
5388                 state->m_constellation = DRX_CONSTELLATION_QAM128;
5389                 break;
5390         default:
5391                 status = -EINVAL;
5392                 break;
5393         }
5394         if (status < 0)
5395                 goto error;
5396
5397         /* Use the 4-parameter if it's requested or we're probing for
5398          * the correct command. */
5399         if (state->qam_demod_parameter_count == 4
5400                 || !state->qam_demod_parameter_count) {
5401                 qam_demod_param_count = 4;
5402                 status = qam_demodulator_command(state, qam_demod_param_count);
5403         }
5404
5405         /* Use the 2-parameter command if it was requested or if we're
5406          * probing for the correct command and the 4-parameter command
5407          * failed. */
5408         if (state->qam_demod_parameter_count == 2
5409                 || (!state->qam_demod_parameter_count && status < 0)) {
5410                 qam_demod_param_count = 2;
5411                 status = qam_demodulator_command(state, qam_demod_param_count);
5412         }
5413
5414         if (status < 0) {
5415                 dprintk(1, "Could not set demodulator parameters. Make "
5416                         "sure qam_demod_parameter_count (%d) is correct for "
5417                         "your firmware (%s).\n",
5418                         state->qam_demod_parameter_count,
5419                         state->microcode_name);
5420                 goto error;
5421         } else if (!state->qam_demod_parameter_count) {
5422                 dprintk(1, "Auto-probing the correct QAM demodulator command "
5423                         "parameters was successful - using %d parameters.\n",
5424                         qam_demod_param_count);
5425
5426                 /*
5427                  * One of our commands was successful. We don't need to
5428                  * auto-probe anymore, now that we got the correct command.
5429                  */
5430                 state->qam_demod_parameter_count = qam_demod_param_count;
5431         }
5432
5433         /*
5434          * STEP 3: enable the system in a mode where the ADC provides valid
5435          * signal setup modulation independent registers
5436          */
5437 #if 0
5438         status = set_frequency(channel, tuner_freq_offset));
5439         if (status < 0)
5440                 goto error;
5441 #endif
5442         status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true);
5443         if (status < 0)
5444                 goto error;
5445
5446         /* Setup BER measurement */
5447         status = set_qam_measurement(state, state->m_constellation, state->props.symbol_rate);
5448         if (status < 0)
5449                 goto error;
5450
5451         /* Reset default values */
5452         status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5453         if (status < 0)
5454                 goto error;
5455         status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5456         if (status < 0)
5457                 goto error;
5458
5459         /* Reset default LC values */
5460         status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5461         if (status < 0)
5462                 goto error;
5463         status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5464         if (status < 0)
5465                 goto error;
5466         status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5467         if (status < 0)
5468                 goto error;
5469         status = write16(state, QAM_LC_MODE__A, 7);
5470         if (status < 0)
5471                 goto error;
5472
5473         status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5474         if (status < 0)
5475                 goto error;
5476         status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5477         if (status < 0)
5478                 goto error;
5479         status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5480         if (status < 0)
5481                 goto error;
5482         status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5483         if (status < 0)
5484                 goto error;
5485         status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5486         if (status < 0)
5487                 goto error;
5488         status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5489         if (status < 0)
5490                 goto error;
5491         status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5492         if (status < 0)
5493                 goto error;
5494         status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5495         if (status < 0)
5496                 goto error;
5497         status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5498         if (status < 0)
5499                 goto error;
5500         status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5501         if (status < 0)
5502                 goto error;
5503         status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5504         if (status < 0)
5505                 goto error;
5506         status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5507         if (status < 0)
5508                 goto error;
5509         status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5510         if (status < 0)
5511                 goto error;
5512         status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5513         if (status < 0)
5514                 goto error;
5515         status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5516         if (status < 0)
5517                 goto error;
5518
5519         /* Mirroring, QAM-block starting point not inverted */
5520         status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5521         if (status < 0)
5522                 goto error;
5523
5524         /* Halt SCU to enable safe non-atomic accesses */
5525         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5526         if (status < 0)
5527                 goto error;
5528
5529         /* STEP 4: modulation specific setup */
5530         switch (state->props.modulation) {
5531         case QAM_16:
5532                 status = set_qam16(state);
5533                 break;
5534         case QAM_32:
5535                 status = set_qam32(state);
5536                 break;
5537         case QAM_AUTO:
5538         case QAM_64:
5539                 status = set_qam64(state);
5540                 break;
5541         case QAM_128:
5542                 status = set_qam128(state);
5543                 break;
5544         case QAM_256:
5545                 status = set_qam256(state);
5546                 break;
5547         default:
5548                 status = -EINVAL;
5549                 break;
5550         }
5551         if (status < 0)
5552                 goto error;
5553
5554         /* Activate SCU to enable SCU commands */
5555         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5556         if (status < 0)
5557                 goto error;
5558
5559         /* Re-configure MPEG output, requires knowledge of channel bitrate */
5560         /* extAttr->currentChannel.modulation = channel->modulation; */
5561         /* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5562         status = mpegts_dto_setup(state, state->m_operation_mode);
5563         if (status < 0)
5564                 goto error;
5565
5566         /* start processes */
5567         status = mpegts_start(state);
5568         if (status < 0)
5569                 goto error;
5570         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5571         if (status < 0)
5572                 goto error;
5573         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5574         if (status < 0)
5575                 goto error;
5576         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5577         if (status < 0)
5578                 goto error;
5579
5580         /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5581         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result);
5582         if (status < 0)
5583                 goto error;
5584
5585         /* update global DRXK data container */
5586 /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5587
5588 error:
5589         if (status < 0)
5590                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5591         return status;
5592 }
5593
5594 static int set_qam_standard(struct drxk_state *state,
5595                           enum operation_mode o_mode)
5596 {
5597         int status;
5598 #ifdef DRXK_QAM_TAPS
5599 #define DRXK_QAMA_TAPS_SELECT
5600 #include "drxk_filters.h"
5601 #undef DRXK_QAMA_TAPS_SELECT
5602 #endif
5603
5604         dprintk(1, "\n");
5605
5606         /* added antenna switch */
5607         switch_antenna_to_qam(state);
5608
5609         /* Ensure correct power-up mode */
5610         status = power_up_qam(state);
5611         if (status < 0)
5612                 goto error;
5613         /* Reset QAM block */
5614         status = qam_reset_qam(state);
5615         if (status < 0)
5616                 goto error;
5617
5618         /* Setup IQM */
5619
5620         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5621         if (status < 0)
5622                 goto error;
5623         status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5624         if (status < 0)
5625                 goto error;
5626
5627         /* Upload IQM Channel Filter settings by
5628                 boot loader from ROM table */
5629         switch (o_mode) {
5630         case OM_QAM_ITU_A:
5631                 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5632                 break;
5633         case OM_QAM_ITU_C:
5634                 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5635                 if (status < 0)
5636                         goto error;
5637                 status = bl_direct_cmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5638                 break;
5639         default:
5640                 status = -EINVAL;
5641         }
5642         if (status < 0)
5643                 goto error;
5644
5645         status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5646         if (status < 0)
5647                 goto error;
5648         status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5649         if (status < 0)
5650                 goto error;
5651         status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5652         if (status < 0)
5653                 goto error;
5654
5655         status = write16(state, IQM_RC_STRETCH__A, 21);
5656         if (status < 0)
5657                 goto error;
5658         status = write16(state, IQM_AF_CLP_LEN__A, 0);
5659         if (status < 0)
5660                 goto error;
5661         status = write16(state, IQM_AF_CLP_TH__A, 448);
5662         if (status < 0)
5663                 goto error;
5664         status = write16(state, IQM_AF_SNS_LEN__A, 0);
5665         if (status < 0)
5666                 goto error;
5667         status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5668         if (status < 0)
5669                 goto error;
5670
5671         status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5672         if (status < 0)
5673                 goto error;
5674         status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5675         if (status < 0)
5676                 goto error;
5677         status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5678         if (status < 0)
5679                 goto error;
5680         status = write16(state, IQM_AF_UPD_SEL__A, 0);
5681         if (status < 0)
5682                 goto error;
5683
5684         /* IQM Impulse Noise Processing Unit */
5685         status = write16(state, IQM_CF_CLP_VAL__A, 500);
5686         if (status < 0)
5687                 goto error;
5688         status = write16(state, IQM_CF_DATATH__A, 1000);
5689         if (status < 0)
5690                 goto error;
5691         status = write16(state, IQM_CF_BYPASSDET__A, 1);
5692         if (status < 0)
5693                 goto error;
5694         status = write16(state, IQM_CF_DET_LCT__A, 0);
5695         if (status < 0)
5696                 goto error;
5697         status = write16(state, IQM_CF_WND_LEN__A, 1);
5698         if (status < 0)
5699                 goto error;
5700         status = write16(state, IQM_CF_PKDTH__A, 1);
5701         if (status < 0)
5702                 goto error;
5703         status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5704         if (status < 0)
5705                 goto error;
5706
5707         /* turn on IQMAF. Must be done before setAgc**() */
5708         status = set_iqm_af(state, true);
5709         if (status < 0)
5710                 goto error;
5711         status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5712         if (status < 0)
5713                 goto error;
5714
5715         /* IQM will not be reset from here, sync ADC and update/init AGC */
5716         status = adc_synchronization(state);
5717         if (status < 0)
5718                 goto error;
5719
5720         /* Set the FSM step period */
5721         status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5722         if (status < 0)
5723                 goto error;
5724
5725         /* Halt SCU to enable safe non-atomic accesses */
5726         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5727         if (status < 0)
5728                 goto error;
5729
5730         /* No more resets of the IQM, current standard correctly set =>
5731                 now AGCs can be configured. */
5732
5733         status = init_agc(state, true);
5734         if (status < 0)
5735                 goto error;
5736         status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5737         if (status < 0)
5738                 goto error;
5739
5740         /* Configure AGC's */
5741         status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5742         if (status < 0)
5743                 goto error;
5744         status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5745         if (status < 0)
5746                 goto error;
5747
5748         /* Activate SCU to enable SCU commands */
5749         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5750 error:
5751         if (status < 0)
5752                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5753         return status;
5754 }
5755
5756 static int write_gpio(struct drxk_state *state)
5757 {
5758         int status;
5759         u16 value = 0;
5760
5761         dprintk(1, "\n");
5762         /* stop lock indicator process */
5763         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5764         if (status < 0)
5765                 goto error;
5766
5767         /*  Write magic word to enable pdr reg write               */
5768         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5769         if (status < 0)
5770                 goto error;
5771
5772         if (state->m_has_sawsw) {
5773                 if (state->uio_mask & 0x0001) { /* UIO-1 */
5774                         /* write to io pad configuration register - output mode */
5775                         status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_gpio_cfg);
5776                         if (status < 0)
5777                                 goto error;
5778
5779                         /* use corresponding bit in io data output registar */
5780                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5781                         if (status < 0)
5782                                 goto error;
5783                         if ((state->m_gpio & 0x0001) == 0)
5784                                 value &= 0x7FFF;        /* write zero to 15th bit - 1st UIO */
5785                         else
5786                                 value |= 0x8000;        /* write one to 15th bit - 1st UIO */
5787                         /* write back to io data output register */
5788                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5789                         if (status < 0)
5790                                 goto error;
5791                 }
5792                 if (state->uio_mask & 0x0002) { /* UIO-2 */
5793                         /* write to io pad configuration register - output mode */
5794                         status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_gpio_cfg);
5795                         if (status < 0)
5796                                 goto error;
5797
5798                         /* use corresponding bit in io data output registar */
5799                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5800                         if (status < 0)
5801                                 goto error;
5802                         if ((state->m_gpio & 0x0002) == 0)
5803                                 value &= 0xBFFF;        /* write zero to 14th bit - 2st UIO */
5804                         else
5805                                 value |= 0x4000;        /* write one to 14th bit - 2st UIO */
5806                         /* write back to io data output register */
5807                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5808                         if (status < 0)
5809                                 goto error;
5810                 }
5811                 if (state->uio_mask & 0x0004) { /* UIO-3 */
5812                         /* write to io pad configuration register - output mode */
5813                         status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_gpio_cfg);
5814                         if (status < 0)
5815                                 goto error;
5816
5817                         /* use corresponding bit in io data output registar */
5818                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5819                         if (status < 0)
5820                                 goto error;
5821                         if ((state->m_gpio & 0x0004) == 0)
5822                                 value &= 0xFFFB;            /* write zero to 2nd bit - 3rd UIO */
5823                         else
5824                                 value |= 0x0004;            /* write one to 2nd bit - 3rd UIO */
5825                         /* write back to io data output register */
5826                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5827                         if (status < 0)
5828                                 goto error;
5829                 }
5830         }
5831         /*  Write magic word to disable pdr reg write               */
5832         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5833 error:
5834         if (status < 0)
5835                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5836         return status;
5837 }
5838
5839 static int switch_antenna_to_qam(struct drxk_state *state)
5840 {
5841         int status = 0;
5842         bool gpio_state;
5843
5844         dprintk(1, "\n");
5845
5846         if (!state->antenna_gpio)
5847                 return 0;
5848
5849         gpio_state = state->m_gpio & state->antenna_gpio;
5850
5851         if (state->antenna_dvbt ^ gpio_state) {
5852                 /* Antenna is on DVB-T mode. Switch */
5853                 if (state->antenna_dvbt)
5854                         state->m_gpio &= ~state->antenna_gpio;
5855                 else
5856                         state->m_gpio |= state->antenna_gpio;
5857                 status = write_gpio(state);
5858         }
5859         if (status < 0)
5860                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5861         return status;
5862 }
5863
5864 static int switch_antenna_to_dvbt(struct drxk_state *state)
5865 {
5866         int status = 0;
5867         bool gpio_state;
5868
5869         dprintk(1, "\n");
5870
5871         if (!state->antenna_gpio)
5872                 return 0;
5873
5874         gpio_state = state->m_gpio & state->antenna_gpio;
5875
5876         if (!(state->antenna_dvbt ^ gpio_state)) {
5877                 /* Antenna is on DVB-C mode. Switch */
5878                 if (state->antenna_dvbt)
5879                         state->m_gpio |= state->antenna_gpio;
5880                 else
5881                         state->m_gpio &= ~state->antenna_gpio;
5882                 status = write_gpio(state);
5883         }
5884         if (status < 0)
5885                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5886         return status;
5887 }
5888
5889
5890 static int power_down_device(struct drxk_state *state)
5891 {
5892         /* Power down to requested mode */
5893         /* Backup some register settings */
5894         /* Set pins with possible pull-ups connected to them in input mode */
5895         /* Analog power down */
5896         /* ADC power down */
5897         /* Power down device */
5898         int status;
5899
5900         dprintk(1, "\n");
5901         if (state->m_b_p_down_open_bridge) {
5902                 /* Open I2C bridge before power down of DRXK */
5903                 status = ConfigureI2CBridge(state, true);
5904                 if (status < 0)
5905                         goto error;
5906         }
5907         /* driver 0.9.0 */
5908         status = dvbt_enable_ofdm_token_ring(state, false);
5909         if (status < 0)
5910                 goto error;
5911
5912         status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5913         if (status < 0)
5914                 goto error;
5915         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5916         if (status < 0)
5917                 goto error;
5918         state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5919         status = hi_cfg_command(state);
5920 error:
5921         if (status < 0)
5922                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5923
5924         return status;
5925 }
5926
5927 static int init_drxk(struct drxk_state *state)
5928 {
5929         int status = 0, n = 0;
5930         enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM;
5931         u16 driver_version;
5932
5933         dprintk(1, "\n");
5934         if ((state->m_drxk_state == DRXK_UNINITIALIZED)) {
5935                 drxk_i2c_lock(state);
5936                 status = power_up_device(state);
5937                 if (status < 0)
5938                         goto error;
5939                 status = drxx_open(state);
5940                 if (status < 0)
5941                         goto error;
5942                 /* Soft reset of OFDM-, sys- and osc-clockdomain */
5943                 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5944                 if (status < 0)
5945                         goto error;
5946                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5947                 if (status < 0)
5948                         goto error;
5949                 /* TODO is this needed, if yes how much delay in worst case scenario */
5950                 msleep(1);
5951                 state->m_drxk_a3_patch_code = true;
5952                 status = get_device_capabilities(state);
5953                 if (status < 0)
5954                         goto error;
5955
5956                 /* Bridge delay, uses oscilator clock */
5957                 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
5958                 /* SDA brdige delay */
5959                 state->m_hi_cfg_bridge_delay =
5960                         (u16) ((state->m_osc_clock_freq / 1000) *
5961                                 HI_I2C_BRIDGE_DELAY) / 1000;
5962                 /* Clipping */
5963                 if (state->m_hi_cfg_bridge_delay >
5964                         SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
5965                         state->m_hi_cfg_bridge_delay =
5966                                 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
5967                 }
5968                 /* SCL bridge delay, same as SDA for now */
5969                 state->m_hi_cfg_bridge_delay +=
5970                         state->m_hi_cfg_bridge_delay <<
5971                         SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5972
5973                 status = init_hi(state);
5974                 if (status < 0)
5975                         goto error;
5976                 /* disable various processes */
5977 #if NOA1ROM
5978                 if (!(state->m_DRXK_A1_ROM_CODE)
5979                         && !(state->m_DRXK_A2_ROM_CODE))
5980 #endif
5981                 {
5982                         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5983                         if (status < 0)
5984                                 goto error;
5985                 }
5986
5987                 /* disable MPEG port */
5988                 status = mpegts_disable(state);
5989                 if (status < 0)
5990                         goto error;
5991
5992                 /* Stop AUD and SCU */
5993                 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
5994                 if (status < 0)
5995                         goto error;
5996                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
5997                 if (status < 0)
5998                         goto error;
5999
6000                 /* enable token-ring bus through OFDM block for possible ucode upload */
6001                 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6002                 if (status < 0)
6003                         goto error;
6004
6005                 /* include boot loader section */
6006                 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6007                 if (status < 0)
6008                         goto error;
6009                 status = bl_chain_cmd(state, 0, 6, 100);
6010                 if (status < 0)
6011                         goto error;
6012
6013                 if (state->fw) {
6014                         status = download_microcode(state, state->fw->data,
6015                                                    state->fw->size);
6016                         if (status < 0)
6017                                 goto error;
6018                 }
6019
6020                 /* disable token-ring bus through OFDM block for possible ucode upload */
6021                 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6022                 if (status < 0)
6023                         goto error;
6024
6025                 /* Run SCU for a little while to initialize microcode version numbers */
6026                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6027                 if (status < 0)
6028                         goto error;
6029                 status = drxx_open(state);
6030                 if (status < 0)
6031                         goto error;
6032                 /* added for test */
6033                 msleep(30);
6034
6035                 power_mode = DRXK_POWER_DOWN_OFDM;
6036                 status = ctrl_power_mode(state, &power_mode);
6037                 if (status < 0)
6038                         goto error;
6039
6040                 /* Stamp driver version number in SCU data RAM in BCD code
6041                         Done to enable field application engineers to retreive drxdriver version
6042                         via I2C from SCU RAM.
6043                         Not using SCU command interface for SCU register access since no
6044                         microcode may be present.
6045                         */
6046                 driver_version =
6047                         (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6048                         (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6049                         ((DRXK_VERSION_MAJOR % 10) << 4) +
6050                         (DRXK_VERSION_MINOR % 10);
6051                 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driver_version);
6052                 if (status < 0)
6053                         goto error;
6054                 driver_version =
6055                         (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6056                         (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6057                         (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6058                         (DRXK_VERSION_PATCH % 10);
6059                 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driver_version);
6060                 if (status < 0)
6061                         goto error;
6062
6063                 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6064                         DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6065                         DRXK_VERSION_PATCH);
6066
6067                 /* Dirty fix of default values for ROM/PATCH microcode
6068                         Dirty because this fix makes it impossible to setup suitable values
6069                         before calling DRX_Open. This solution requires changes to RF AGC speed
6070                         to be done via the CTRL function after calling DRX_Open */
6071
6072                 /* m_dvbt_rf_agc_cfg.speed = 3; */
6073
6074                 /* Reset driver debug flags to 0 */
6075                 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6076                 if (status < 0)
6077                         goto error;
6078                 /* driver 0.9.0 */
6079                 /* Setup FEC OC:
6080                         NOTE: No more full FEC resets allowed afterwards!! */
6081                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6082                 if (status < 0)
6083                         goto error;
6084                 /* MPEGTS functions are still the same */
6085                 status = mpegts_dto_init(state);
6086                 if (status < 0)
6087                         goto error;
6088                 status = mpegts_stop(state);
6089                 if (status < 0)
6090                         goto error;
6091                 status = mpegts_configure_polarity(state);
6092                 if (status < 0)
6093                         goto error;
6094                 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6095                 if (status < 0)
6096                         goto error;
6097                 /* added: configure GPIO */
6098                 status = write_gpio(state);
6099                 if (status < 0)
6100                         goto error;
6101
6102                 state->m_drxk_state = DRXK_STOPPED;
6103
6104                 if (state->m_b_power_down) {
6105                         status = power_down_device(state);
6106                         if (status < 0)
6107                                 goto error;
6108                         state->m_drxk_state = DRXK_POWERED_DOWN;
6109                 } else
6110                         state->m_drxk_state = DRXK_STOPPED;
6111
6112                 /* Initialize the supported delivery systems */
6113                 n = 0;
6114                 if (state->m_has_dvbc) {
6115                         state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6116                         state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6117                         strlcat(state->frontend.ops.info.name, " DVB-C",
6118                                 sizeof(state->frontend.ops.info.name));
6119                 }
6120                 if (state->m_has_dvbt) {
6121                         state->frontend.ops.delsys[n++] = SYS_DVBT;
6122                         strlcat(state->frontend.ops.info.name, " DVB-T",
6123                                 sizeof(state->frontend.ops.info.name));
6124                 }
6125                 drxk_i2c_unlock(state);
6126         }
6127 error:
6128         if (status < 0) {
6129                 state->m_drxk_state = DRXK_NO_DEV;
6130                 drxk_i2c_unlock(state);
6131                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6132         }
6133
6134         return status;
6135 }
6136
6137 static void load_firmware_cb(const struct firmware *fw,
6138                              void *context)
6139 {
6140         struct drxk_state *state = context;
6141
6142         dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded");
6143         if (!fw) {
6144                 printk(KERN_ERR
6145                        "drxk: Could not load firmware file %s.\n",
6146                         state->microcode_name);
6147                 printk(KERN_INFO
6148                        "drxk: Copy %s to your hotplug directory!\n",
6149                         state->microcode_name);
6150                 state->microcode_name = NULL;
6151
6152                 /*
6153                  * As firmware is now load asynchronous, it is not possible
6154                  * anymore to fail at frontend attach. We might silently
6155                  * return here, and hope that the driver won't crash.
6156                  * We might also change all DVB callbacks to return -ENODEV
6157                  * if the device is not initialized.
6158                  * As the DRX-K devices have their own internal firmware,
6159                  * let's just hope that it will match a firmware revision
6160                  * compatible with this driver and proceed.
6161                  */
6162         }
6163         state->fw = fw;
6164
6165         init_drxk(state);
6166 }
6167
6168 static void drxk_release(struct dvb_frontend *fe)
6169 {
6170         struct drxk_state *state = fe->demodulator_priv;
6171
6172         dprintk(1, "\n");
6173         if (state->fw)
6174                 release_firmware(state->fw);
6175
6176         kfree(state);
6177 }
6178
6179 static int drxk_sleep(struct dvb_frontend *fe)
6180 {
6181         struct drxk_state *state = fe->demodulator_priv;
6182
6183         dprintk(1, "\n");
6184
6185         if (state->m_drxk_state == DRXK_NO_DEV)
6186                 return -ENODEV;
6187         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6188                 return 0;
6189
6190         shut_down(state);
6191         return 0;
6192 }
6193
6194 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6195 {
6196         struct drxk_state *state = fe->demodulator_priv;
6197
6198         dprintk(1, ": %s\n", enable ? "enable" : "disable");
6199
6200         if (state->m_drxk_state == DRXK_NO_DEV)
6201                 return -ENODEV;
6202
6203         return ConfigureI2CBridge(state, enable ? true : false);
6204 }
6205
6206 static int drxk_set_parameters(struct dvb_frontend *fe)
6207 {
6208         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6209         u32 delsys  = p->delivery_system, old_delsys;
6210         struct drxk_state *state = fe->demodulator_priv;
6211         u32 IF;
6212
6213         dprintk(1, "\n");
6214
6215         if (state->m_drxk_state == DRXK_NO_DEV)
6216                 return -ENODEV;
6217
6218         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6219                 return -EAGAIN;
6220
6221         if (!fe->ops.tuner_ops.get_if_frequency) {
6222                 printk(KERN_ERR
6223                        "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6224                 return -EINVAL;
6225         }
6226
6227         if (fe->ops.i2c_gate_ctrl)
6228                 fe->ops.i2c_gate_ctrl(fe, 1);
6229         if (fe->ops.tuner_ops.set_params)
6230                 fe->ops.tuner_ops.set_params(fe);
6231         if (fe->ops.i2c_gate_ctrl)
6232                 fe->ops.i2c_gate_ctrl(fe, 0);
6233
6234         old_delsys = state->props.delivery_system;
6235         state->props = *p;
6236
6237         if (old_delsys != delsys) {
6238                 shut_down(state);
6239                 switch (delsys) {
6240                 case SYS_DVBC_ANNEX_A:
6241                 case SYS_DVBC_ANNEX_C:
6242                         if (!state->m_has_dvbc)
6243                                 return -EINVAL;
6244                         state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6245                         if (state->m_itut_annex_c)
6246                                 setoperation_mode(state, OM_QAM_ITU_C);
6247                         else
6248                                 setoperation_mode(state, OM_QAM_ITU_A);
6249                         break;
6250                 case SYS_DVBT:
6251                         if (!state->m_has_dvbt)
6252                                 return -EINVAL;
6253                         setoperation_mode(state, OM_DVBT);
6254                         break;
6255                 default:
6256                         return -EINVAL;
6257                 }
6258         }
6259
6260         fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6261         start(state, 0, IF);
6262
6263         /* After set_frontend, stats aren't avaliable */
6264         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6265         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6266         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6267         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6268         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6269         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6270         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6271         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6272
6273         /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6274
6275         return 0;
6276 }
6277
6278 static int get_strength(struct drxk_state *state, u64 *strength)
6279 {
6280         int status;
6281         struct s_cfg_agc   rf_agc, if_agc;
6282         u32          total_gain  = 0;
6283         u32          atten      = 0;
6284         u32          agc_range   = 0;
6285         u16            scu_lvl  = 0;
6286         u16            scu_coc  = 0;
6287         /* FIXME: those are part of the tuner presets */
6288         u16 tuner_rf_gain         = 50; /* Default value on az6007 driver */
6289         u16 tuner_if_gain         = 40; /* Default value on az6007 driver */
6290
6291         *strength = 0;
6292
6293         if (is_dvbt(state)) {
6294                 rf_agc = state->m_dvbt_rf_agc_cfg;
6295                 if_agc = state->m_dvbt_if_agc_cfg;
6296         } else if (is_qam(state)) {
6297                 rf_agc = state->m_qam_rf_agc_cfg;
6298                 if_agc = state->m_qam_if_agc_cfg;
6299         } else {
6300                 rf_agc = state->m_atv_rf_agc_cfg;
6301                 if_agc = state->m_atv_if_agc_cfg;
6302         }
6303
6304         if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6305                 /* SCU output_level */
6306                 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6307                 if (status < 0)
6308                         return status;
6309
6310                 /* SCU c.o.c. */
6311                 read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6312                 if (status < 0)
6313                         return status;
6314
6315                 if (((u32) scu_lvl + (u32) scu_coc) < 0xffff)
6316                         rf_agc.output_level = scu_lvl + scu_coc;
6317                 else
6318                         rf_agc.output_level = 0xffff;
6319
6320                 /* Take RF gain into account */
6321                 total_gain += tuner_rf_gain;
6322
6323                 /* clip output value */
6324                 if (rf_agc.output_level < rf_agc.min_output_level)
6325                         rf_agc.output_level = rf_agc.min_output_level;
6326                 if (rf_agc.output_level > rf_agc.max_output_level)
6327                         rf_agc.output_level = rf_agc.max_output_level;
6328
6329                 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level);
6330                 if (agc_range > 0) {
6331                         atten += 100UL *
6332                                 ((u32)(tuner_rf_gain)) *
6333                                 ((u32)(rf_agc.output_level - rf_agc.min_output_level))
6334                                 / agc_range;
6335                 }
6336         }
6337
6338         if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) {
6339                 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6340                                 &if_agc.output_level);
6341                 if (status < 0)
6342                         return status;
6343
6344                 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6345                                 &if_agc.top);
6346                 if (status < 0)
6347                         return status;
6348
6349                 /* Take IF gain into account */
6350                 total_gain += (u32) tuner_if_gain;
6351
6352                 /* clip output value */
6353                 if (if_agc.output_level < if_agc.min_output_level)
6354                         if_agc.output_level = if_agc.min_output_level;
6355                 if (if_agc.output_level > if_agc.max_output_level)
6356                         if_agc.output_level = if_agc.max_output_level;
6357
6358                 agc_range  = (u32) (if_agc.max_output_level - if_agc.min_output_level);
6359                 if (agc_range > 0) {
6360                         atten += 100UL *
6361                                 ((u32)(tuner_if_gain)) *
6362                                 ((u32)(if_agc.output_level - if_agc.min_output_level))
6363                                 / agc_range;
6364                 }
6365         }
6366
6367         /*
6368          * Convert to 0..65535 scale.
6369          * If it can't be measured (AGC is disabled), just show 100%.
6370          */
6371         if (total_gain > 0)
6372                 *strength = (65535UL * atten / total_gain / 100);
6373         else
6374                 *strength = 65535;
6375
6376         return 0;
6377 }
6378
6379 static int drxk_get_stats(struct dvb_frontend *fe)
6380 {
6381         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6382         struct drxk_state *state = fe->demodulator_priv;
6383         int status;
6384         u32 stat;
6385         u16 reg16;
6386         u32 post_bit_count;
6387         u32 post_bit_err_count;
6388         u32 post_bit_error_scale;
6389         u32 pre_bit_err_count;
6390         u32 pre_bit_count;
6391         u32 pkt_count;
6392         u32 pkt_error_count;
6393         s32 cnr;
6394
6395         if (state->m_drxk_state == DRXK_NO_DEV)
6396                 return -ENODEV;
6397         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6398                 return -EAGAIN;
6399
6400         /* get status */
6401         state->fe_status = 0;
6402         get_lock_status(state, &stat);
6403         if (stat == MPEG_LOCK)
6404                 state->fe_status |= 0x1f;
6405         if (stat == FEC_LOCK)
6406                 state->fe_status |= 0x0f;
6407         if (stat == DEMOD_LOCK)
6408                 state->fe_status |= 0x07;
6409
6410         /*
6411          * Estimate signal strength from AGC
6412          */
6413         get_strength(state, &c->strength.stat[0].uvalue);
6414         c->strength.stat[0].scale = FE_SCALE_RELATIVE;
6415
6416
6417         if (stat >= DEMOD_LOCK) {
6418                 get_signal_to_noise(state, &cnr);
6419                 c->cnr.stat[0].svalue = cnr * 100;
6420                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
6421         } else {
6422                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6423         }
6424
6425         if (stat < FEC_LOCK) {
6426                 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6427                 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6428                 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6429                 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6430                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6431                 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6432                 return 0;
6433         }
6434
6435         /* Get post BER */
6436
6437         /* BER measurement is valid if at least FEC lock is achieved */
6438
6439         /* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be written
6440                 to set nr of symbols or bits over which
6441                 to measure EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). */
6442
6443         /* Read registers for post/preViterbi BER calculation */
6444         status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);
6445         if (status < 0)
6446                 goto error;
6447         pre_bit_err_count = reg16;
6448
6449         status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);
6450         if (status < 0)
6451                 goto error;
6452         pre_bit_count = reg16;
6453
6454         /* Number of bit-errors */
6455         status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);
6456         if (status < 0)
6457                 goto error;
6458         post_bit_err_count = reg16;
6459
6460         status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);
6461         if (status < 0)
6462                 goto error;
6463         post_bit_error_scale = reg16;
6464
6465         status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);
6466         if (status < 0)
6467                 goto error;
6468         pkt_count = reg16;
6469
6470         status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);
6471         if (status < 0)
6472                 goto error;
6473         pkt_error_count = reg16;
6474         write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6475
6476         post_bit_err_count *= post_bit_error_scale;
6477
6478         post_bit_count = pkt_count * 204 * 8;
6479
6480         /* Store the results */
6481         c->block_error.stat[0].scale = FE_SCALE_COUNTER;
6482         c->block_error.stat[0].uvalue += pkt_error_count;
6483         c->block_count.stat[0].scale = FE_SCALE_COUNTER;
6484         c->block_count.stat[0].uvalue += pkt_count;
6485
6486         c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6487         c->pre_bit_error.stat[0].uvalue += pre_bit_err_count;
6488         c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6489         c->pre_bit_count.stat[0].uvalue += pre_bit_count;
6490
6491         c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
6492         c->post_bit_error.stat[0].uvalue += post_bit_err_count;
6493         c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
6494         c->post_bit_count.stat[0].uvalue += post_bit_count;
6495
6496 error:
6497         return status;
6498 }
6499
6500
6501 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6502 {
6503         struct drxk_state *state = fe->demodulator_priv;
6504         int rc;
6505
6506         dprintk(1, "\n");
6507
6508         rc = drxk_get_stats(fe);
6509         if (rc < 0)
6510                 return rc;
6511
6512         *status = state->fe_status;
6513
6514         return 0;
6515 }
6516
6517 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6518                                      u16 *strength)
6519 {
6520         struct drxk_state *state = fe->demodulator_priv;
6521         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
6522
6523         dprintk(1, "\n");
6524
6525         if (state->m_drxk_state == DRXK_NO_DEV)
6526                 return -ENODEV;
6527         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6528                 return -EAGAIN;
6529
6530         *strength = c->strength.stat[0].uvalue;
6531         return 0;
6532 }
6533
6534 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6535 {
6536         struct drxk_state *state = fe->demodulator_priv;
6537         s32 snr2;
6538
6539         dprintk(1, "\n");
6540
6541         if (state->m_drxk_state == DRXK_NO_DEV)
6542                 return -ENODEV;
6543         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6544                 return -EAGAIN;
6545
6546         get_signal_to_noise(state, &snr2);
6547
6548         /* No negative SNR, clip to zero */
6549         if (snr2 < 0)
6550                 snr2 = 0;
6551         *snr = snr2 & 0xffff;
6552         return 0;
6553 }
6554
6555 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6556 {
6557         struct drxk_state *state = fe->demodulator_priv;
6558         u16 err;
6559
6560         dprintk(1, "\n");
6561
6562         if (state->m_drxk_state == DRXK_NO_DEV)
6563                 return -ENODEV;
6564         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6565                 return -EAGAIN;
6566
6567         dvbtqam_get_acc_pkt_err(state, &err);
6568         *ucblocks = (u32) err;
6569         return 0;
6570 }
6571
6572 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6573                                     *sets)
6574 {
6575         struct drxk_state *state = fe->demodulator_priv;
6576         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6577
6578         dprintk(1, "\n");
6579
6580         if (state->m_drxk_state == DRXK_NO_DEV)
6581                 return -ENODEV;
6582         if (state->m_drxk_state == DRXK_UNINITIALIZED)
6583                 return -EAGAIN;
6584
6585         switch (p->delivery_system) {
6586         case SYS_DVBC_ANNEX_A:
6587         case SYS_DVBC_ANNEX_C:
6588         case SYS_DVBT:
6589                 sets->min_delay_ms = 3000;
6590                 sets->max_drift = 0;
6591                 sets->step_size = 0;
6592                 return 0;
6593         default:
6594                 return -EINVAL;
6595         }
6596 }
6597
6598 static struct dvb_frontend_ops drxk_ops = {
6599         /* .delsys will be filled dynamically */
6600         .info = {
6601                 .name = "DRXK",
6602                 .frequency_min = 47000000,
6603                 .frequency_max = 865000000,
6604                  /* For DVB-C */
6605                 .symbol_rate_min = 870000,
6606                 .symbol_rate_max = 11700000,
6607                 /* For DVB-T */
6608                 .frequency_stepsize = 166667,
6609
6610                 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6611                         FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6612                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6613                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6614                         FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6615                         FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6616         },
6617
6618         .release = drxk_release,
6619         .sleep = drxk_sleep,
6620         .i2c_gate_ctrl = drxk_gate_ctrl,
6621
6622         .set_frontend = drxk_set_parameters,
6623         .get_tune_settings = drxk_get_tune_settings,
6624
6625         .read_status = drxk_read_status,
6626         .read_signal_strength = drxk_read_signal_strength,
6627         .read_snr = drxk_read_snr,
6628         .read_ucblocks = drxk_read_ucblocks,
6629 };
6630
6631 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6632                                  struct i2c_adapter *i2c)
6633 {
6634         struct dtv_frontend_properties *p;
6635         struct drxk_state *state = NULL;
6636         u8 adr = config->adr;
6637         int status;
6638
6639         dprintk(1, "\n");
6640         state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6641         if (!state)
6642                 return NULL;
6643
6644         state->i2c = i2c;
6645         state->demod_address = adr;
6646         state->single_master = config->single_master;
6647         state->microcode_name = config->microcode_name;
6648         state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6649         state->no_i2c_bridge = config->no_i2c_bridge;
6650         state->antenna_gpio = config->antenna_gpio;
6651         state->antenna_dvbt = config->antenna_dvbt;
6652         state->m_chunk_size = config->chunk_size;
6653         state->enable_merr_cfg = config->enable_merr_cfg;
6654
6655         if (config->dynamic_clk) {
6656                 state->m_dvbt_static_clk = 0;
6657                 state->m_dvbc_static_clk = 0;
6658         } else {
6659                 state->m_dvbt_static_clk = 1;
6660                 state->m_dvbc_static_clk = 1;
6661         }
6662
6663
6664         if (config->mpeg_out_clk_strength)
6665                 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6666         else
6667                 state->m_ts_clockk_strength = 0x06;
6668
6669         if (config->parallel_ts)
6670                 state->m_enable_parallel = true;
6671         else
6672                 state->m_enable_parallel = false;
6673
6674         /* NOTE: as more UIO bits will be used, add them to the mask */
6675         state->uio_mask = config->antenna_gpio;
6676
6677         /* Default gpio to DVB-C */
6678         if (!state->antenna_dvbt && state->antenna_gpio)
6679                 state->m_gpio |= state->antenna_gpio;
6680         else
6681                 state->m_gpio &= ~state->antenna_gpio;
6682
6683         mutex_init(&state->mutex);
6684
6685         memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6686         state->frontend.demodulator_priv = state;
6687
6688         init_state(state);
6689
6690         /* Load firmware and initialize DRX-K */
6691         if (state->microcode_name) {
6692                 if (config->load_firmware_sync) {
6693                         const struct firmware *fw = NULL;
6694
6695                         status = request_firmware(&fw, state->microcode_name,
6696                                                   state->i2c->dev.parent);
6697                         if (status < 0)
6698                                 fw = NULL;
6699                         load_firmware_cb(fw, state);
6700                 } else {
6701                         status = request_firmware_nowait(THIS_MODULE, 1,
6702                                               state->microcode_name,
6703                                               state->i2c->dev.parent,
6704                                               GFP_KERNEL,
6705                                               state, load_firmware_cb);
6706                         if (status < 0) {
6707                                 printk(KERN_ERR
6708                                        "drxk: failed to request a firmware\n");
6709                                 return NULL;
6710                         }
6711                 }
6712         } else if (init_drxk(state) < 0)
6713                 goto error;
6714
6715
6716         /* Initialize stats */
6717         p = &state->frontend.dtv_property_cache;
6718         p->strength.len = 1;
6719         p->cnr.len = 1;
6720         p->block_error.len = 1;
6721         p->block_count.len = 1;
6722         p->pre_bit_error.len = 1;
6723         p->pre_bit_count.len = 1;
6724         p->post_bit_error.len = 1;
6725         p->post_bit_count.len = 1;
6726
6727         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
6728         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6729         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6730         p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6731         p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6732         p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6733         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6734         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
6735
6736         printk(KERN_INFO "drxk: frontend initialized.\n");
6737         return &state->frontend;
6738
6739 error:
6740         printk(KERN_ERR "drxk: not found\n");
6741         kfree(state);
6742         return NULL;
6743 }
6744 EXPORT_SYMBOL(drxk_attach);
6745
6746 MODULE_DESCRIPTION("DRX-K driver");
6747 MODULE_AUTHOR("Ralph Metzler");
6748 MODULE_LICENSE("GPL");