2 * Montage M88DS3103 demodulator driver
4 * Copyright (C) 2013 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "m88ds3103_priv.h"
19 static struct dvb_frontend_ops m88ds3103_ops;
21 /* write multiple registers */
22 static int m88ds3103_wr_regs(struct m88ds3103_priv *priv,
23 u8 reg, const u8 *val, int len)
26 #define MAX_WR_XFER_LEN (MAX_WR_LEN + 1)
28 u8 buf[MAX_WR_XFER_LEN];
29 struct i2c_msg msg[1] = {
31 .addr = priv->cfg->i2c_addr,
38 if (WARN_ON(len > MAX_WR_LEN))
42 memcpy(&buf[1], val, len);
44 mutex_lock(&priv->i2c_mutex);
45 ret = i2c_transfer(priv->i2c, msg, 1);
46 mutex_unlock(&priv->i2c_mutex);
50 dev_warn(&priv->i2c->dev,
51 "%s: i2c wr failed=%d reg=%02x len=%d\n",
52 KBUILD_MODNAME, ret, reg, len);
59 /* read multiple registers */
60 static int m88ds3103_rd_regs(struct m88ds3103_priv *priv,
61 u8 reg, u8 *val, int len)
64 #define MAX_RD_XFER_LEN (MAX_RD_LEN)
66 u8 buf[MAX_RD_XFER_LEN];
67 struct i2c_msg msg[2] = {
69 .addr = priv->cfg->i2c_addr,
74 .addr = priv->cfg->i2c_addr,
81 if (WARN_ON(len > MAX_RD_LEN))
84 mutex_lock(&priv->i2c_mutex);
85 ret = i2c_transfer(priv->i2c, msg, 2);
86 mutex_unlock(&priv->i2c_mutex);
88 memcpy(val, buf, len);
91 dev_warn(&priv->i2c->dev,
92 "%s: i2c rd failed=%d reg=%02x len=%d\n",
93 KBUILD_MODNAME, ret, reg, len);
100 /* write single register */
101 static int m88ds3103_wr_reg(struct m88ds3103_priv *priv, u8 reg, u8 val)
103 return m88ds3103_wr_regs(priv, reg, &val, 1);
106 /* read single register */
107 static int m88ds3103_rd_reg(struct m88ds3103_priv *priv, u8 reg, u8 *val)
109 return m88ds3103_rd_regs(priv, reg, val, 1);
112 /* write single register with mask */
113 static int m88ds3103_wr_reg_mask(struct m88ds3103_priv *priv,
114 u8 reg, u8 val, u8 mask)
119 /* no need for read if whole reg is written */
121 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
130 return m88ds3103_wr_regs(priv, reg, &val, 1);
133 /* read single register with mask */
134 static int m88ds3103_rd_reg_mask(struct m88ds3103_priv *priv,
135 u8 reg, u8 *val, u8 mask)
140 ret = m88ds3103_rd_regs(priv, reg, &u8tmp, 1);
146 /* find position of the first bit */
147 for (i = 0; i < 8; i++) {
148 if ((mask >> i) & 0x01)
156 /* write reg val table using reg addr auto increment */
157 static int m88ds3103_wr_reg_val_tab(struct m88ds3103_priv *priv,
158 const struct m88ds3103_reg_val *tab, int tab_len)
163 dev_dbg(&priv->i2c->dev, "%s: tab_len=%d\n", __func__, tab_len);
170 for (i = 0, j = 0; i < tab_len; i++, j++) {
173 if (i == tab_len - 1 || tab[i].reg != tab[i + 1].reg - 1 ||
174 !((j + 1) % (priv->cfg->i2c_wr_max - 1))) {
175 ret = m88ds3103_wr_regs(priv, tab[i].reg - j, buf, j + 1);
185 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
189 static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t *status)
191 struct m88ds3103_priv *priv = fe->demodulator_priv;
192 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
203 switch (c->delivery_system) {
205 ret = m88ds3103_rd_reg_mask(priv, 0xd1, &u8tmp, 0x07);
210 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
211 FE_HAS_VITERBI | FE_HAS_SYNC |
215 ret = m88ds3103_rd_reg_mask(priv, 0x0d, &u8tmp, 0x8f);
220 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
221 FE_HAS_VITERBI | FE_HAS_SYNC |
225 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
231 priv->fe_status = *status;
233 dev_dbg(&priv->i2c->dev, "%s: lock=%02x status=%02x\n",
234 __func__, u8tmp, *status);
238 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
242 static int m88ds3103_set_frontend(struct dvb_frontend *fe)
244 struct m88ds3103_priv *priv = fe->demodulator_priv;
245 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
247 const struct m88ds3103_reg_val *init;
248 u8 u8tmp, u8tmp1, u8tmp2;
250 u16 u16tmp, divide_ratio;
251 u32 tuner_frequency, target_mclk;
254 dev_dbg(&priv->i2c->dev,
255 "%s: delivery_system=%d modulation=%d frequency=%d symbol_rate=%d inversion=%d pilot=%d rolloff=%d\n",
256 __func__, c->delivery_system,
257 c->modulation, c->frequency, c->symbol_rate,
258 c->inversion, c->pilot, c->rolloff);
266 if (fe->ops.tuner_ops.set_params) {
267 ret = fe->ops.tuner_ops.set_params(fe);
272 if (fe->ops.tuner_ops.get_frequency) {
273 ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_frequency);
278 * Use nominal target frequency as tuner driver does not provide
279 * actual frequency used. Carrier offset calculation is not
282 tuner_frequency = c->frequency;
286 ret = m88ds3103_wr_reg(priv, 0x07, 0x80);
290 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
294 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
298 ret = m88ds3103_wr_reg(priv, 0x00, 0x01);
302 switch (c->delivery_system) {
304 len = ARRAY_SIZE(m88ds3103_dvbs_init_reg_vals);
305 init = m88ds3103_dvbs_init_reg_vals;
309 len = ARRAY_SIZE(m88ds3103_dvbs2_init_reg_vals);
310 init = m88ds3103_dvbs2_init_reg_vals;
312 switch (priv->cfg->ts_mode) {
313 case M88DS3103_TS_SERIAL:
314 case M88DS3103_TS_SERIAL_D7:
315 if (c->symbol_rate < 18000000)
318 target_mclk = 144000;
320 case M88DS3103_TS_PARALLEL:
321 case M88DS3103_TS_CI:
322 if (c->symbol_rate < 18000000)
324 else if (c->symbol_rate < 28000000)
325 target_mclk = 144000;
327 target_mclk = 192000;
330 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n",
337 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
343 /* program init table */
344 if (c->delivery_system != priv->delivery_system) {
345 ret = m88ds3103_wr_reg_val_tab(priv, init, len);
350 u8tmp1 = 0; /* silence compiler warning */
351 switch (priv->cfg->ts_mode) {
352 case M88DS3103_TS_SERIAL:
356 case M88DS3103_TS_SERIAL_D7:
360 case M88DS3103_TS_PARALLEL:
363 case M88DS3103_TS_CI:
367 dev_dbg(&priv->i2c->dev, "%s: invalid ts_mode\n", __func__);
372 if (priv->cfg->ts_clk_pol)
376 ret = m88ds3103_wr_reg(priv, 0xfd, u8tmp);
380 switch (priv->cfg->ts_mode) {
381 case M88DS3103_TS_SERIAL:
382 case M88DS3103_TS_SERIAL_D7:
383 ret = m88ds3103_wr_reg_mask(priv, 0x29, u8tmp1, 0x20);
388 if (priv->cfg->ts_clk) {
389 divide_ratio = DIV_ROUND_UP(target_mclk, priv->cfg->ts_clk);
390 u8tmp1 = divide_ratio / 2;
391 u8tmp2 = DIV_ROUND_UP(divide_ratio, 2);
398 dev_dbg(&priv->i2c->dev,
399 "%s: target_mclk=%d ts_clk=%d divide_ratio=%d\n",
400 __func__, target_mclk, priv->cfg->ts_clk, divide_ratio);
404 /* u8tmp1[5:2] => fe[3:0], u8tmp1[1:0] => ea[7:6] */
406 /* u8tmp2[5:0] => ea[5:0] */
409 ret = m88ds3103_rd_reg(priv, 0xfe, &u8tmp);
413 u8tmp = ((u8tmp & 0xf0) << 0) | u8tmp1 >> 2;
414 ret = m88ds3103_wr_reg(priv, 0xfe, u8tmp);
418 u8tmp = ((u8tmp1 & 0x03) << 6) | u8tmp2 >> 0;
419 ret = m88ds3103_wr_reg(priv, 0xea, u8tmp);
423 switch (target_mclk) {
425 u8tmp1 = 0x02; /* 0b10 */
426 u8tmp2 = 0x01; /* 0b01 */
429 u8tmp1 = 0x00; /* 0b00 */
430 u8tmp2 = 0x01; /* 0b01 */
433 u8tmp1 = 0x03; /* 0b11 */
434 u8tmp2 = 0x00; /* 0b00 */
438 ret = m88ds3103_wr_reg_mask(priv, 0x22, u8tmp1 << 6, 0xc0);
442 ret = m88ds3103_wr_reg_mask(priv, 0x24, u8tmp2 << 6, 0xc0);
446 if (c->symbol_rate <= 3000000)
448 else if (c->symbol_rate <= 10000000)
453 ret = m88ds3103_wr_reg(priv, 0xc3, 0x08);
457 ret = m88ds3103_wr_reg(priv, 0xc8, u8tmp);
461 ret = m88ds3103_wr_reg(priv, 0xc4, 0x08);
465 ret = m88ds3103_wr_reg(priv, 0xc7, 0x00);
469 u16tmp = DIV_ROUND_CLOSEST((c->symbol_rate / 1000) << 15, M88DS3103_MCLK_KHZ / 2);
470 buf[0] = (u16tmp >> 0) & 0xff;
471 buf[1] = (u16tmp >> 8) & 0xff;
472 ret = m88ds3103_wr_regs(priv, 0x61, buf, 2);
476 ret = m88ds3103_wr_reg_mask(priv, 0x4d, priv->cfg->spec_inv << 1, 0x02);
480 ret = m88ds3103_wr_reg_mask(priv, 0x30, priv->cfg->agc_inv << 4, 0x10);
484 ret = m88ds3103_wr_reg(priv, 0x33, priv->cfg->agc);
488 dev_dbg(&priv->i2c->dev, "%s: carrier offset=%d\n", __func__,
489 (tuner_frequency - c->frequency));
491 s32tmp = 0x10000 * (tuner_frequency - c->frequency);
492 s32tmp = DIV_ROUND_CLOSEST(s32tmp, M88DS3103_MCLK_KHZ);
496 buf[0] = (s32tmp >> 0) & 0xff;
497 buf[1] = (s32tmp >> 8) & 0xff;
498 ret = m88ds3103_wr_regs(priv, 0x5e, buf, 2);
502 ret = m88ds3103_wr_reg(priv, 0x00, 0x00);
506 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
510 priv->delivery_system = c->delivery_system;
514 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
518 static int m88ds3103_init(struct dvb_frontend *fe)
520 struct m88ds3103_priv *priv = fe->demodulator_priv;
521 int ret, len, remaining;
522 const struct firmware *fw = NULL;
523 u8 *fw_file = M88DS3103_FIRMWARE;
526 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
528 /* set cold state by default */
531 /* wake up device from sleep */
532 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x01, 0x01);
536 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x00, 0x01);
540 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x00, 0x10);
545 ret = m88ds3103_wr_reg(priv, 0x07, 0x60);
549 ret = m88ds3103_wr_reg(priv, 0x07, 0x00);
553 /* firmware status */
554 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
558 dev_dbg(&priv->i2c->dev, "%s: firmware=%02x\n", __func__, u8tmp);
561 goto skip_fw_download;
563 /* cold state - try to download firmware */
564 dev_info(&priv->i2c->dev, "%s: found a '%s' in cold state\n",
565 KBUILD_MODNAME, m88ds3103_ops.info.name);
567 /* request the firmware, this will block and timeout */
568 ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
570 dev_err(&priv->i2c->dev, "%s: firmare file '%s' not found\n",
571 KBUILD_MODNAME, fw_file);
575 dev_info(&priv->i2c->dev, "%s: downloading firmware from file '%s'\n",
576 KBUILD_MODNAME, fw_file);
578 ret = m88ds3103_wr_reg(priv, 0xb2, 0x01);
582 for (remaining = fw->size; remaining > 0;
583 remaining -= (priv->cfg->i2c_wr_max - 1)) {
585 if (len > (priv->cfg->i2c_wr_max - 1))
586 len = (priv->cfg->i2c_wr_max - 1);
588 ret = m88ds3103_wr_regs(priv, 0xb0,
589 &fw->data[fw->size - remaining], len);
591 dev_err(&priv->i2c->dev,
592 "%s: firmware download failed=%d\n",
593 KBUILD_MODNAME, ret);
598 ret = m88ds3103_wr_reg(priv, 0xb2, 0x00);
602 release_firmware(fw);
605 ret = m88ds3103_rd_reg(priv, 0xb9, &u8tmp);
610 dev_info(&priv->i2c->dev, "%s: firmware did not run\n",
616 dev_info(&priv->i2c->dev, "%s: found a '%s' in warm state\n",
617 KBUILD_MODNAME, m88ds3103_ops.info.name);
618 dev_info(&priv->i2c->dev, "%s: firmware version %X.%X\n",
619 KBUILD_MODNAME, (u8tmp >> 4) & 0xf, (u8tmp >> 0 & 0xf));
628 release_firmware(fw);
630 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
634 static int m88ds3103_sleep(struct dvb_frontend *fe)
636 struct m88ds3103_priv *priv = fe->demodulator_priv;
639 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
641 priv->delivery_system = SYS_UNDEFINED;
644 ret = m88ds3103_wr_reg_mask(priv, 0x27, 0x00, 0x01);
649 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
653 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
657 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
663 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
667 static int m88ds3103_get_frontend(struct dvb_frontend *fe)
669 struct m88ds3103_priv *priv = fe->demodulator_priv;
670 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
674 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
676 if (!priv->warm || !(priv->fe_status & FE_HAS_LOCK)) {
681 switch (c->delivery_system) {
683 ret = m88ds3103_rd_reg(priv, 0xe0, &buf[0]);
687 ret = m88ds3103_rd_reg(priv, 0xe6, &buf[1]);
691 switch ((buf[0] >> 2) & 0x01) {
693 c->inversion = INVERSION_OFF;
696 c->inversion = INVERSION_ON;
700 switch ((buf[1] >> 5) & 0x07) {
702 c->fec_inner = FEC_7_8;
705 c->fec_inner = FEC_5_6;
708 c->fec_inner = FEC_3_4;
711 c->fec_inner = FEC_2_3;
714 c->fec_inner = FEC_1_2;
717 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
721 c->modulation = QPSK;
725 ret = m88ds3103_rd_reg(priv, 0x7e, &buf[0]);
729 ret = m88ds3103_rd_reg(priv, 0x89, &buf[1]);
733 ret = m88ds3103_rd_reg(priv, 0xf2, &buf[2]);
737 switch ((buf[0] >> 0) & 0x0f) {
739 c->fec_inner = FEC_2_5;
742 c->fec_inner = FEC_1_2;
745 c->fec_inner = FEC_3_5;
748 c->fec_inner = FEC_2_3;
751 c->fec_inner = FEC_3_4;
754 c->fec_inner = FEC_4_5;
757 c->fec_inner = FEC_5_6;
760 c->fec_inner = FEC_8_9;
763 c->fec_inner = FEC_9_10;
766 dev_dbg(&priv->i2c->dev, "%s: invalid fec_inner\n",
770 switch ((buf[0] >> 5) & 0x01) {
772 c->pilot = PILOT_OFF;
779 switch ((buf[0] >> 6) & 0x07) {
781 c->modulation = QPSK;
784 c->modulation = PSK_8;
787 c->modulation = APSK_16;
790 c->modulation = APSK_32;
793 dev_dbg(&priv->i2c->dev, "%s: invalid modulation\n",
797 switch ((buf[1] >> 7) & 0x01) {
799 c->inversion = INVERSION_OFF;
802 c->inversion = INVERSION_ON;
806 switch ((buf[2] >> 0) & 0x03) {
808 c->rolloff = ROLLOFF_35;
811 c->rolloff = ROLLOFF_25;
814 c->rolloff = ROLLOFF_20;
817 dev_dbg(&priv->i2c->dev, "%s: invalid rolloff\n",
822 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
828 ret = m88ds3103_rd_regs(priv, 0x6d, buf, 2);
832 c->symbol_rate = 1ull * ((buf[1] << 8) | (buf[0] << 0)) *
833 M88DS3103_MCLK_KHZ * 1000 / 0x10000;
837 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
841 static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *snr)
843 struct m88ds3103_priv *priv = fe->demodulator_priv;
844 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
848 u32 noise_tot, signal_tot;
850 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
851 /* reports SNR in resolution of 0.1 dB */
853 /* more iterations for more accurate estimation */
854 #define M88DS3103_SNR_ITERATIONS 3
856 switch (c->delivery_system) {
860 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
861 ret = m88ds3103_rd_reg(priv, 0xff, &buf[0]);
868 /* use of one register limits max value to 15 dB */
869 /* SNR(X) dB = 10 * ln(X) / ln(10) dB */
870 tmp = DIV_ROUND_CLOSEST(tmp, 8 * M88DS3103_SNR_ITERATIONS);
872 *snr = div_u64((u64) 100 * intlog2(tmp), intlog2(10));
880 for (i = 0; i < M88DS3103_SNR_ITERATIONS; i++) {
881 ret = m88ds3103_rd_regs(priv, 0x8c, buf, 3);
885 noise = buf[1] << 6; /* [13:6] */
886 noise |= buf[0] & 0x3f; /* [5:0] */
888 signal = buf[2] * buf[2];
892 signal_tot += signal;
895 noise = noise_tot / M88DS3103_SNR_ITERATIONS;
896 signal = signal_tot / M88DS3103_SNR_ITERATIONS;
898 /* SNR(X) dB = 10 * log10(X) dB */
899 if (signal > noise) {
900 tmp = signal / noise;
901 *snr = div_u64((u64) 100 * intlog10(tmp), (1 << 24));
907 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
915 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
919 static int m88ds3103_read_ber(struct dvb_frontend *fe, u32 *ber)
921 struct m88ds3103_priv *priv = fe->demodulator_priv;
922 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
927 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
929 switch (c->delivery_system) {
931 ret = m88ds3103_wr_reg(priv, 0xf9, 0x04);
935 ret = m88ds3103_rd_reg(priv, 0xf8, &u8tmp);
939 if (!(u8tmp & 0x10)) {
942 ret = m88ds3103_rd_regs(priv, 0xf6, buf, 2);
946 priv->ber = (buf[1] << 8) | (buf[0] << 0);
948 /* restart counters */
949 ret = m88ds3103_wr_reg(priv, 0xf8, u8tmp);
955 ret = m88ds3103_rd_regs(priv, 0xd5, buf, 3);
959 utmp = (buf[2] << 16) | (buf[1] << 8) | (buf[0] << 0);
962 ret = m88ds3103_rd_regs(priv, 0xf7, buf, 2);
966 priv->ber = (buf[1] << 8) | (buf[0] << 0);
968 /* restart counters */
969 ret = m88ds3103_wr_reg(priv, 0xd1, 0x01);
973 ret = m88ds3103_wr_reg(priv, 0xf9, 0x01);
977 ret = m88ds3103_wr_reg(priv, 0xf9, 0x00);
981 ret = m88ds3103_wr_reg(priv, 0xd1, 0x00);
987 dev_dbg(&priv->i2c->dev, "%s: invalid delivery_system\n",
997 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1001 static int m88ds3103_set_tone(struct dvb_frontend *fe,
1002 fe_sec_tone_mode_t fe_sec_tone_mode)
1004 struct m88ds3103_priv *priv = fe->demodulator_priv;
1006 u8 u8tmp, tone, reg_a1_mask;
1008 dev_dbg(&priv->i2c->dev, "%s: fe_sec_tone_mode=%d\n", __func__,
1016 switch (fe_sec_tone_mode) {
1026 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_tone_mode\n",
1032 u8tmp = tone << 7 | priv->cfg->envelope_mode << 5;
1033 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1038 ret = m88ds3103_wr_reg_mask(priv, 0xa1, u8tmp, reg_a1_mask);
1044 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1048 static int m88ds3103_set_voltage(struct dvb_frontend *fe,
1049 fe_sec_voltage_t fe_sec_voltage)
1051 struct m88ds3103_priv *priv = fe->demodulator_priv;
1054 bool voltage_sel, voltage_dis;
1056 dev_dbg(&priv->i2c->dev, "%s: fe_sec_voltage=%d\n", __func__,
1064 switch (fe_sec_voltage) {
1065 case SEC_VOLTAGE_18:
1067 voltage_dis = false;
1069 case SEC_VOLTAGE_13:
1070 voltage_sel = false;
1071 voltage_dis = false;
1073 case SEC_VOLTAGE_OFF:
1074 voltage_sel = false;
1078 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_voltage\n",
1084 /* output pin polarity */
1085 voltage_sel ^= priv->cfg->lnb_hv_pol;
1086 voltage_dis ^= priv->cfg->lnb_en_pol;
1088 u8tmp = voltage_dis << 1 | voltage_sel << 0;
1089 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0x03);
1095 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1099 static int m88ds3103_diseqc_send_master_cmd(struct dvb_frontend *fe,
1100 struct dvb_diseqc_master_cmd *diseqc_cmd)
1102 struct m88ds3103_priv *priv = fe->demodulator_priv;
1106 dev_dbg(&priv->i2c->dev, "%s: msg=%*ph\n", __func__,
1107 diseqc_cmd->msg_len, diseqc_cmd->msg);
1114 if (diseqc_cmd->msg_len < 3 || diseqc_cmd->msg_len > 6) {
1119 u8tmp = priv->cfg->envelope_mode << 5;
1120 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1124 ret = m88ds3103_wr_regs(priv, 0xa3, diseqc_cmd->msg,
1125 diseqc_cmd->msg_len);
1129 ret = m88ds3103_wr_reg(priv, 0xa1,
1130 (diseqc_cmd->msg_len - 1) << 3 | 0x07);
1134 /* DiSEqC message typical period is 54 ms */
1135 usleep_range(40000, 60000);
1137 /* wait DiSEqC TX ready */
1138 for (i = 20, u8tmp = 1; i && u8tmp; i--) {
1139 usleep_range(5000, 10000);
1141 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1146 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1149 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1151 ret = m88ds3103_wr_reg_mask(priv, 0xa1, 0x40, 0xc0);
1156 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1167 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1171 static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe,
1172 fe_sec_mini_cmd_t fe_sec_mini_cmd)
1174 struct m88ds3103_priv *priv = fe->demodulator_priv;
1178 dev_dbg(&priv->i2c->dev, "%s: fe_sec_mini_cmd=%d\n", __func__,
1186 u8tmp = priv->cfg->envelope_mode << 5;
1187 ret = m88ds3103_wr_reg_mask(priv, 0xa2, u8tmp, 0xe0);
1191 switch (fe_sec_mini_cmd) {
1199 dev_dbg(&priv->i2c->dev, "%s: invalid fe_sec_mini_cmd\n",
1205 ret = m88ds3103_wr_reg(priv, 0xa1, burst);
1209 /* DiSEqC ToneBurst period is 12.5 ms */
1210 usleep_range(11000, 20000);
1212 /* wait DiSEqC TX ready */
1213 for (i = 5, u8tmp = 1; i && u8tmp; i--) {
1214 usleep_range(800, 2000);
1216 ret = m88ds3103_rd_reg_mask(priv, 0xa1, &u8tmp, 0x40);
1221 dev_dbg(&priv->i2c->dev, "%s: loop=%d\n", __func__, i);
1223 ret = m88ds3103_wr_reg_mask(priv, 0xa2, 0x80, 0xc0);
1228 dev_dbg(&priv->i2c->dev, "%s: diseqc tx timeout\n", __func__);
1235 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
1239 static int m88ds3103_get_tune_settings(struct dvb_frontend *fe,
1240 struct dvb_frontend_tune_settings *s)
1242 s->min_delay_ms = 3000;
1247 static void m88ds3103_release(struct dvb_frontend *fe)
1249 struct m88ds3103_priv *priv = fe->demodulator_priv;
1251 i2c_del_mux_adapter(priv->i2c_adapter);
1255 static int m88ds3103_select(struct i2c_adapter *adap, void *mux_priv, u32 chan)
1257 struct m88ds3103_priv *priv = mux_priv;
1259 struct i2c_msg gate_open_msg[1] = {
1261 .addr = priv->cfg->i2c_addr,
1268 mutex_lock(&priv->i2c_mutex);
1270 /* open tuner I2C repeater for 1 xfer, closes automatically */
1271 ret = __i2c_transfer(priv->i2c, gate_open_msg, 1);
1273 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d\n",
1274 KBUILD_MODNAME, ret);
1284 static int m88ds3103_deselect(struct i2c_adapter *adap, void *mux_priv,
1287 struct m88ds3103_priv *priv = mux_priv;
1289 mutex_unlock(&priv->i2c_mutex);
1294 struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg,
1295 struct i2c_adapter *i2c, struct i2c_adapter **tuner_i2c_adapter)
1298 struct m88ds3103_priv *priv;
1301 /* allocate memory for the internal priv */
1302 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1305 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
1311 mutex_init(&priv->i2c_mutex);
1313 ret = m88ds3103_rd_reg(priv, 0x01, &chip_id);
1317 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
1326 switch (priv->cfg->clock_out) {
1327 case M88DS3103_CLOCK_OUT_DISABLED:
1330 case M88DS3103_CLOCK_OUT_ENABLED:
1333 case M88DS3103_CLOCK_OUT_ENABLED_DIV2:
1340 ret = m88ds3103_wr_reg(priv, 0x29, u8tmp);
1345 ret = m88ds3103_wr_reg_mask(priv, 0x08, 0x00, 0x01);
1349 ret = m88ds3103_wr_reg_mask(priv, 0x04, 0x01, 0x01);
1353 ret = m88ds3103_wr_reg_mask(priv, 0x23, 0x10, 0x10);
1357 /* create mux i2c adapter for tuner */
1358 priv->i2c_adapter = i2c_add_mux_adapter(i2c, &i2c->dev, priv, 0, 0, 0,
1359 m88ds3103_select, m88ds3103_deselect);
1360 if (priv->i2c_adapter == NULL)
1363 *tuner_i2c_adapter = priv->i2c_adapter;
1365 /* create dvb_frontend */
1366 memcpy(&priv->fe.ops, &m88ds3103_ops, sizeof(struct dvb_frontend_ops));
1367 priv->fe.demodulator_priv = priv;
1371 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
1375 EXPORT_SYMBOL(m88ds3103_attach);
1377 static struct dvb_frontend_ops m88ds3103_ops = {
1378 .delsys = { SYS_DVBS, SYS_DVBS2 },
1380 .name = "Montage M88DS3103",
1381 .frequency_min = 950000,
1382 .frequency_max = 2150000,
1383 .frequency_tolerance = 5000,
1384 .symbol_rate_min = 1000000,
1385 .symbol_rate_max = 45000000,
1386 .caps = FE_CAN_INVERSION_AUTO |
1398 FE_CAN_2G_MODULATION
1401 .release = m88ds3103_release,
1403 .get_tune_settings = m88ds3103_get_tune_settings,
1405 .init = m88ds3103_init,
1406 .sleep = m88ds3103_sleep,
1408 .set_frontend = m88ds3103_set_frontend,
1409 .get_frontend = m88ds3103_get_frontend,
1411 .read_status = m88ds3103_read_status,
1412 .read_snr = m88ds3103_read_snr,
1413 .read_ber = m88ds3103_read_ber,
1415 .diseqc_send_master_cmd = m88ds3103_diseqc_send_master_cmd,
1416 .diseqc_send_burst = m88ds3103_diseqc_send_burst,
1418 .set_tone = m88ds3103_set_tone,
1419 .set_voltage = m88ds3103_set_voltage,
1422 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
1423 MODULE_DESCRIPTION("Montage M88DS3103 DVB-S/S2 demodulator driver");
1424 MODULE_LICENSE("GPL");
1425 MODULE_FIRMWARE(M88DS3103_FIRMWARE);