drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30 #include <linux/delay.h>
  31 #include <linux/gpio/consumer.h>
  32 #include <linux/i2c.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/slab.h>
  36 #include <linux/v4l2-dv-timings.h>
  37 #include <linux/videodev2.h>
  38 #include <linux/workqueue.h>
  39
  40 #include <media/adv7604.h>
  41 #include <media/v4l2-ctrls.h>
  42 #include <media/v4l2-device.h>
  43 #include <media/v4l2-dv-timings.h>
  44 #include <media/v4l2-of.h>
  45
  46 static int debug;
  47 module_param(debug, int, 0644);
  48 MODULE_PARM_DESC(debug, "debug level (0-2)");
  49
  50 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  51 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  52 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  53 MODULE_LICENSE("GPL");
  54
  55 /* ADV7604 system clock frequency */
  56 #define ADV7604_fsc (28636360)
  57
  58 #define ADV7604_RGB_OUT                                 (1 << 1)
  59
  60 #define ADV7604_OP_FORMAT_SEL_8BIT                      (0 << 0)
  61 #define ADV7604_OP_FORMAT_SEL_10BIT                     (1 << 0)
  62 #define ADV7604_OP_FORMAT_SEL_12BIT                     (2 << 0)
  63
  64 #define ADV7604_OP_MODE_SEL_SDR_422                     (0 << 5)
  65 #define ADV7604_OP_MODE_SEL_DDR_422                     (1 << 5)
  66 #define ADV7604_OP_MODE_SEL_SDR_444                     (2 << 5)
  67 #define ADV7604_OP_MODE_SEL_DDR_444                     (3 << 5)
  68 #define ADV7604_OP_MODE_SEL_SDR_422_2X                  (4 << 5)
  69 #define ADV7604_OP_MODE_SEL_ADI_CM                      (5 << 5)
  70
  71 #define ADV7604_OP_CH_SEL_GBR                           (0 << 5)
  72 #define ADV7604_OP_CH_SEL_GRB                           (1 << 5)
  73 #define ADV7604_OP_CH_SEL_BGR                           (2 << 5)
  74 #define ADV7604_OP_CH_SEL_RGB                           (3 << 5)
  75 #define ADV7604_OP_CH_SEL_BRG                           (4 << 5)
  76 #define ADV7604_OP_CH_SEL_RBG                           (5 << 5)
  77
  78 #define ADV7604_OP_SWAP_CB_CR                           (1 << 0)
  79
  80 enum adv7604_type {
  81         ADV7604,
  82         ADV7611,
  83 };
  84
  85 struct adv7604_reg_seq {
  86         unsigned int reg;
  87         u8 val;
  88 };
  89
  90 struct adv7604_format_info {
  91         u32 code;
  92         u8 op_ch_sel;
  93         bool rgb_out;
  94         bool swap_cb_cr;
  95         u8 op_format_sel;
  96 };
  97
  98 struct adv7604_chip_info {
  99         enum adv7604_type type;
 100
 101         bool has_afe;
 102         unsigned int max_port;
 103         unsigned int num_dv_ports;
 104
 105         unsigned int edid_enable_reg;
 106         unsigned int edid_status_reg;
 107         unsigned int lcf_reg;
 108
 109         unsigned int cable_det_mask;
 110         unsigned int tdms_lock_mask;
 111         unsigned int fmt_change_digital_mask;
 112
 113         const struct adv7604_format_info *formats;
 114         unsigned int nformats;
 115
 116         void (*set_termination)(struct v4l2_subdev *sd, bool enable);
 117         void (*setup_irqs)(struct v4l2_subdev *sd);
 118         unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
 119         unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
 120
 121         /* 0 = AFE, 1 = HDMI */
 122         const struct adv7604_reg_seq *recommended_settings[2];
 123         unsigned int num_recommended_settings[2];
 124
 125         unsigned long page_mask;
 126 };
 127
 128 /*
 129  **********************************************************************
 130  *
 131  *  Arrays with configuration parameters for the ADV7604
 132  *
 133  **********************************************************************
 134  */
 135
 136 struct adv7604_state {
 137         const struct adv7604_chip_info *info;
 138         struct adv7604_platform_data pdata;
 139
 140         struct gpio_desc *hpd_gpio[4];
 141
 142         struct v4l2_subdev sd;
 143         struct media_pad pads[ADV7604_PAD_MAX];
 144         unsigned int source_pad;
 145
 146         struct v4l2_ctrl_handler hdl;
 147
 148         enum adv7604_pad selected_input;
 149
 150         struct v4l2_dv_timings timings;
 151         const struct adv7604_format_info *format;
 152
 153         struct {
 154                 u8 edid[256];
 155                 u32 present;
 156                 unsigned blocks;
 157         } edid;
 158         u16 spa_port_a[2];
 159         struct v4l2_fract aspect_ratio;
 160         u32 rgb_quantization_range;
 161         struct workqueue_struct *work_queues;
 162         struct delayed_work delayed_work_enable_hotplug;
 163         bool restart_stdi_once;
 164
 165         /* i2c clients */
 166         struct i2c_client *i2c_clients[ADV7604_PAGE_MAX];
 167
 168         /* controls */
 169         struct v4l2_ctrl *detect_tx_5v_ctrl;
 170         struct v4l2_ctrl *analog_sampling_phase_ctrl;
 171         struct v4l2_ctrl *free_run_color_manual_ctrl;
 172         struct v4l2_ctrl *free_run_color_ctrl;
 173         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 174 };
 175
 176 static bool adv7604_has_afe(struct adv7604_state *state)
 177 {
 178         return state->info->has_afe;
 179 }
 180
 181 /* Supported CEA and DMT timings */
 182 static const struct v4l2_dv_timings adv7604_timings[] = {
 183         V4L2_DV_BT_CEA_720X480P59_94,
 184         V4L2_DV_BT_CEA_720X576P50,
 185         V4L2_DV_BT_CEA_1280X720P24,
 186         V4L2_DV_BT_CEA_1280X720P25,
 187         V4L2_DV_BT_CEA_1280X720P50,
 188         V4L2_DV_BT_CEA_1280X720P60,
 189         V4L2_DV_BT_CEA_1920X1080P24,
 190         V4L2_DV_BT_CEA_1920X1080P25,
 191         V4L2_DV_BT_CEA_1920X1080P30,
 192         V4L2_DV_BT_CEA_1920X1080P50,
 193         V4L2_DV_BT_CEA_1920X1080P60,
 194
 195         /* sorted by DMT ID */
 196         V4L2_DV_BT_DMT_640X350P85,
 197         V4L2_DV_BT_DMT_640X400P85,
 198         V4L2_DV_BT_DMT_720X400P85,
 199         V4L2_DV_BT_DMT_640X480P60,
 200         V4L2_DV_BT_DMT_640X480P72,
 201         V4L2_DV_BT_DMT_640X480P75,
 202         V4L2_DV_BT_DMT_640X480P85,
 203         V4L2_DV_BT_DMT_800X600P56,
 204         V4L2_DV_BT_DMT_800X600P60,
 205         V4L2_DV_BT_DMT_800X600P72,
 206         V4L2_DV_BT_DMT_800X600P75,
 207         V4L2_DV_BT_DMT_800X600P85,
 208         V4L2_DV_BT_DMT_848X480P60,
 209         V4L2_DV_BT_DMT_1024X768P60,
 210         V4L2_DV_BT_DMT_1024X768P70,
 211         V4L2_DV_BT_DMT_1024X768P75,
 212         V4L2_DV_BT_DMT_1024X768P85,
 213         V4L2_DV_BT_DMT_1152X864P75,
 214         V4L2_DV_BT_DMT_1280X768P60_RB,
 215         V4L2_DV_BT_DMT_1280X768P60,
 216         V4L2_DV_BT_DMT_1280X768P75,
 217         V4L2_DV_BT_DMT_1280X768P85,
 218         V4L2_DV_BT_DMT_1280X800P60_RB,
 219         V4L2_DV_BT_DMT_1280X800P60,
 220         V4L2_DV_BT_DMT_1280X800P75,
 221         V4L2_DV_BT_DMT_1280X800P85,
 222         V4L2_DV_BT_DMT_1280X960P60,
 223         V4L2_DV_BT_DMT_1280X960P85,
 224         V4L2_DV_BT_DMT_1280X1024P60,
 225         V4L2_DV_BT_DMT_1280X1024P75,
 226         V4L2_DV_BT_DMT_1280X1024P85,
 227         V4L2_DV_BT_DMT_1360X768P60,
 228         V4L2_DV_BT_DMT_1400X1050P60_RB,
 229         V4L2_DV_BT_DMT_1400X1050P60,
 230         V4L2_DV_BT_DMT_1400X1050P75,
 231         V4L2_DV_BT_DMT_1400X1050P85,
 232         V4L2_DV_BT_DMT_1440X900P60_RB,
 233         V4L2_DV_BT_DMT_1440X900P60,
 234         V4L2_DV_BT_DMT_1600X1200P60,
 235         V4L2_DV_BT_DMT_1680X1050P60_RB,
 236         V4L2_DV_BT_DMT_1680X1050P60,
 237         V4L2_DV_BT_DMT_1792X1344P60,
 238         V4L2_DV_BT_DMT_1856X1392P60,
 239         V4L2_DV_BT_DMT_1920X1200P60_RB,
 240         V4L2_DV_BT_DMT_1366X768P60_RB,
 241         V4L2_DV_BT_DMT_1366X768P60,
 242         V4L2_DV_BT_DMT_1920X1080P60,
 243         { },
 244 };
 245
 246 struct adv7604_video_standards {
 247         struct v4l2_dv_timings timings;
 248         u8 vid_std;
 249         u8 v_freq;
 250 };
 251
 252 /* sorted by number of lines */
 253 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 254         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 255         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 256         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 257         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 258         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 259         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 260         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 261         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 262         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 263         /* TODO add 1920x1080P60_RB (CVT timing) */
 264         { },
 265 };
 266
 267 /* sorted by number of lines */
 268 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 269         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 270         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 271         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 272         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 273         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 274         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 275         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 276         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 277         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 278         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 279         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 280         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 281         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 282         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 283         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 284         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 285         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 286         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 287         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 288         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 289         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 290         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 291         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 292         { },
 293 };
 294
 295 /* sorted by number of lines */
 296 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 297         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 298         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 299         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 300         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 301         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 302         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 303         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 304         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 305         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 306         { },
 307 };
 308
 309 /* sorted by number of lines */
 310 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 311         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 312         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 313         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 314         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 315         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 316         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 317         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 318         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 319         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 320         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 321         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 322         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 323         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 324         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 325         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 326         { },
 327 };
 328
 329 /* ----------------------------------------------------------------------- */
 330
 331 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 332 {
 333         return container_of(sd, struct adv7604_state, sd);
 334 }
 335
 336 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 337 {
 338         return V4L2_DV_BT_BLANKING_WIDTH(t);
 339 }
 340
 341 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 342 {
 343         return V4L2_DV_BT_FRAME_WIDTH(t);
 344 }
 345
 346 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 347 {
 348         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 349 }
 350
 351 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 352 {
 353         return V4L2_DV_BT_FRAME_HEIGHT(t);
 354 }
 355
 356 /* ----------------------------------------------------------------------- */
 357
 358 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 359                 u8 command, bool check)
 360 {
 361         union i2c_smbus_data data;
 362
 363         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 364                         I2C_SMBUS_READ, command,
 365                         I2C_SMBUS_BYTE_DATA, &data))
 366                 return data.byte;
 367         if (check)
 368                 v4l_err(client, "error reading %02x, %02x\n",
 369                                 client->addr, command);
 370         return -EIO;
 371 }
 372
 373 static s32 adv_smbus_read_byte_data(struct adv7604_state *state,
 374                                     enum adv7604_page page, u8 command)
 375 {
 376         return adv_smbus_read_byte_data_check(state->i2c_clients[page],
 377                                               command, true);
 378 }
 379
 380 static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
 381                                      enum adv7604_page page, u8 command,
 382                                      u8 value)
 383 {
 384         struct i2c_client *client = state->i2c_clients[page];
 385         union i2c_smbus_data data;
 386         int err;
 387         int i;
 388
 389         data.byte = value;
 390         for (i = 0; i < 3; i++) {
 391                 err = i2c_smbus_xfer(client->adapter, client->addr,
 392                                 client->flags,
 393                                 I2C_SMBUS_WRITE, command,
 394                                 I2C_SMBUS_BYTE_DATA, &data);
 395                 if (!err)
 396                         break;
 397         }
 398         if (err < 0)
 399                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 400                                 client->addr, command, value);
 401         return err;
 402 }
 403
 404 static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
 405                                           enum adv7604_page page, u8 command,
 406                                           unsigned length, const u8 *values)
 407 {
 408         struct i2c_client *client = state->i2c_clients[page];
 409         union i2c_smbus_data data;
 410
 411         if (length > I2C_SMBUS_BLOCK_MAX)
 412                 length = I2C_SMBUS_BLOCK_MAX;
 413         data.block[0] = length;
 414         memcpy(data.block + 1, values, length);
 415         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 416                               I2C_SMBUS_WRITE, command,
 417                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 418 }
 419
 420 /* ----------------------------------------------------------------------- */
 421
 422 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 423 {
 424         struct adv7604_state *state = to_state(sd);
 425
 426         return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg);
 427 }
 428
 429 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 430 {
 431         struct adv7604_state *state = to_state(sd);
 432
 433         return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
 434 }
 435
 436 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 437 {
 438         return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
 439 }
 440
 441 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 442 {
 443         struct adv7604_state *state = to_state(sd);
 444
 445         return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
 446 }
 447
 448 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 449 {
 450         struct adv7604_state *state = to_state(sd);
 451
 452         return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
 453 }
 454
 455 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 456 {
 457         struct adv7604_state *state = to_state(sd);
 458
 459         return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg);
 460 }
 461
 462 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 463 {
 464         struct adv7604_state *state = to_state(sd);
 465
 466         return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
 467 }
 468
 469 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 470 {
 471         return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
 472 }
 473
 474 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 475 {
 476         struct adv7604_state *state = to_state(sd);
 477
 478         return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg);
 479 }
 480
 481 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 482 {
 483         struct adv7604_state *state = to_state(sd);
 484
 485         return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME,
 486                                          reg, val);
 487 }
 488
 489 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 490 {
 491         struct adv7604_state *state = to_state(sd);
 492
 493         return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg);
 494 }
 495
 496 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 497 {
 498         struct adv7604_state *state = to_state(sd);
 499
 500         return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val);
 501 }
 502
 503 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 504 {
 505         struct adv7604_state *state = to_state(sd);
 506
 507         return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg);
 508 }
 509
 510 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 511 {
 512         struct adv7604_state *state = to_state(sd);
 513
 514         return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val);
 515 }
 516
 517 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 518 {
 519         struct adv7604_state *state = to_state(sd);
 520
 521         return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg);
 522 }
 523
 524 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 525 {
 526         struct adv7604_state *state = to_state(sd);
 527
 528         return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val);
 529 }
 530
 531 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 532 {
 533         struct adv7604_state *state = to_state(sd);
 534
 535         return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg);
 536 }
 537
 538 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 539 {
 540         struct adv7604_state *state = to_state(sd);
 541
 542         return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
 543 }
 544
 545 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 546 {
 547         return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
 548 }
 549
 550 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 551 {
 552         struct adv7604_state *state = to_state(sd);
 553
 554         return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg);
 555 }
 556
 557 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 558 {
 559         struct adv7604_state *state = to_state(sd);
 560
 561         return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val);
 562 }
 563
 564 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 565 {
 566         struct adv7604_state *state = to_state(sd);
 567         struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID];
 568         u8 msgbuf0[1] = { 0 };
 569         u8 msgbuf1[256];
 570         struct i2c_msg msg[2] = {
 571                 {
 572                         .addr = client->addr,
 573                         .len = 1,
 574                         .buf = msgbuf0
 575                 },
 576                 {
 577                         .addr = client->addr,
 578                         .flags = I2C_M_RD,
 579                         .len = len,
 580                         .buf = msgbuf1
 581                 },
 582         };
 583
 584         if (i2c_transfer(client->adapter, msg, 2) < 0)
 585                 return -EIO;
 586         memcpy(val, msgbuf1, len);
 587         return 0;
 588 }
 589
 590 static inline int edid_write_block(struct v4l2_subdev *sd,
 591                                         unsigned len, const u8 *val)
 592 {
 593         struct adv7604_state *state = to_state(sd);
 594         int err = 0;
 595         int i;
 596
 597         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 598
 599         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 600                 err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID,
 601                                 i, I2C_SMBUS_BLOCK_MAX, val + i);
 602         return err;
 603 }
 604
 605 static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd)
 606 {
 607         unsigned int i;
 608
 609         for (i = 0; i < state->info->num_dv_ports; ++i) {
 610                 if (IS_ERR(state->hpd_gpio[i]))
 611                         continue;
 612
 613                 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
 614         }
 615
 616         v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd);
 617 }
 618
 619 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 620 {
 621         struct delayed_work *dwork = to_delayed_work(work);
 622         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 623                                                 delayed_work_enable_hotplug);
 624         struct v4l2_subdev *sd = &state->sd;
 625
 626         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 627
 628         adv7604_set_hpd(state, state->edid.present);
 629 }
 630
 631 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 632 {
 633         struct adv7604_state *state = to_state(sd);
 634
 635         return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg);
 636 }
 637
 638 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 639 {
 640         return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
 641 }
 642
 643 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 644 {
 645         struct adv7604_state *state = to_state(sd);
 646
 647         return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
 648 }
 649
 650 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 651 {
 652         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
 653 }
 654
 655 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 656 {
 657         struct adv7604_state *state = to_state(sd);
 658
 659         return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg);
 660 }
 661
 662 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 663 {
 664         struct adv7604_state *state = to_state(sd);
 665
 666         return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val);
 667 }
 668
 669 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 670 {
 671         struct adv7604_state *state = to_state(sd);
 672
 673         return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg);
 674 }
 675
 676 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
 677 {
 678         return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
 679 }
 680
 681 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 682 {
 683         struct adv7604_state *state = to_state(sd);
 684
 685         return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
 686 }
 687
 688 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 689 {
 690         return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
 691 }
 692
 693 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 694 {
 695         struct adv7604_state *state = to_state(sd);
 696
 697         return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
 698 }
 699
 700 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 701 {
 702         struct adv7604_state *state = to_state(sd);
 703
 704         return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
 705 }
 706
 707 #define ADV7604_REG(page, offset)       (((page) << 8) | (offset))
 708 #define ADV7604_REG_SEQ_TERM            0xffff
 709
 710 #ifdef CONFIG_VIDEO_ADV_DEBUG
 711 static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
 712 {
 713         struct adv7604_state *state = to_state(sd);
 714         unsigned int page = reg >> 8;
 715
 716         if (!(BIT(page) & state->info->page_mask))
 717                 return -EINVAL;
 718
 719         reg &= 0xff;
 720
 721         return adv_smbus_read_byte_data(state, page, reg);
 722 }
 723 #endif
 724
 725 static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
 726 {
 727         struct adv7604_state *state = to_state(sd);
 728         unsigned int page = reg >> 8;
 729
 730         if (!(BIT(page) & state->info->page_mask))
 731                 return -EINVAL;
 732
 733         reg &= 0xff;
 734
 735         return adv_smbus_write_byte_data(state, page, reg, val);
 736 }
 737
 738 static void adv7604_write_reg_seq(struct v4l2_subdev *sd,
 739                                   const struct adv7604_reg_seq *reg_seq)
 740 {
 741         unsigned int i;
 742
 743         for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++)
 744                 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
 745 }
 746
 747 /* -----------------------------------------------------------------------------
 748  * Format helpers
 749  */
 750
 751 static const struct adv7604_format_info adv7604_formats[] = {
 752         { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
 753           ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
 754         { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
 755           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 756         { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
 757           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 758         { MEDIA_BUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
 759           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 760         { MEDIA_BUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
 761           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
 762         { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
 763           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 764         { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
 765           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 766         { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
 767           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 768         { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
 769           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 770         { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
 771           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 772         { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
 773           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 774         { MEDIA_BUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
 775           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 776         { MEDIA_BUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
 777           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 778         { MEDIA_BUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
 779           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 780         { MEDIA_BUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
 781           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
 782         { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
 783           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 784         { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
 785           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 786         { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
 787           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 788         { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
 789           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 790 };
 791
 792 static const struct adv7604_format_info adv7611_formats[] = {
 793         { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
 794           ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
 795         { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
 796           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 797         { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
 798           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
 799         { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
 800           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 801         { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
 802           ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
 803         { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
 804           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 805         { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
 806           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 807         { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
 808           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 809         { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
 810           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
 811         { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
 812           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 813         { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
 814           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 815         { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
 816           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 817         { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
 818           ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
 819 };
 820
 821 static const struct adv7604_format_info *
 822 adv7604_format_info(struct adv7604_state *state, u32 code)
 823 {
 824         unsigned int i;
 825
 826         for (i = 0; i < state->info->nformats; ++i) {
 827                 if (state->info->formats[i].code == code)
 828                         return &state->info->formats[i];
 829         }
 830
 831         return NULL;
 832 }
 833
 834 /* ----------------------------------------------------------------------- */
 835
 836 static inline bool is_analog_input(struct v4l2_subdev *sd)
 837 {
 838         struct adv7604_state *state = to_state(sd);
 839
 840         return state->selected_input == ADV7604_PAD_VGA_RGB ||
 841                state->selected_input == ADV7604_PAD_VGA_COMP;
 842 }
 843
 844 static inline bool is_digital_input(struct v4l2_subdev *sd)
 845 {
 846         struct adv7604_state *state = to_state(sd);
 847
 848         return state->selected_input == ADV7604_PAD_HDMI_PORT_A ||
 849                state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
 850                state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
 851                state->selected_input == ADV7604_PAD_HDMI_PORT_D;
 852 }
 853
 854 /* ----------------------------------------------------------------------- */
 855
 856 #ifdef CONFIG_VIDEO_ADV_DEBUG
 857 static void adv7604_inv_register(struct v4l2_subdev *sd)
 858 {
 859         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 860         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 861         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 862         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 863         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 864         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 865         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 866         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 867         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 868         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 869         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 870         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 871         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 872 }
 873
 874 static int adv7604_g_register(struct v4l2_subdev *sd,
 875                                         struct v4l2_dbg_register *reg)
 876 {
 877         int ret;
 878
 879         ret = adv7604_read_reg(sd, reg->reg);
 880         if (ret < 0) {
 881                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 882                 adv7604_inv_register(sd);
 883                 return ret;
 884         }
 885
 886         reg->size = 1;
 887         reg->val = ret;
 888
 889         return 0;
 890 }
 891
 892 static int adv7604_s_register(struct v4l2_subdev *sd,
 893                                         const struct v4l2_dbg_register *reg)
 894 {
 895         int ret;
 896
 897         ret = adv7604_write_reg(sd, reg->reg, reg->val);
 898         if (ret < 0) {
 899                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 900                 adv7604_inv_register(sd);
 901                 return ret;
 902         }
 903
 904         return 0;
 905 }
 906 #endif
 907
 908 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
 909 {
 910         u8 value = io_read(sd, 0x6f);
 911
 912         return ((value & 0x10) >> 4)
 913              | ((value & 0x08) >> 2)
 914              | ((value & 0x04) << 0)
 915              | ((value & 0x02) << 2);
 916 }
 917
 918 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
 919 {
 920         u8 value = io_read(sd, 0x6f);
 921
 922         return value & 1;
 923 }
 924
 925 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 926 {
 927         struct adv7604_state *state = to_state(sd);
 928         const struct adv7604_chip_info *info = state->info;
 929
 930         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 931                                 info->read_cable_det(sd));
 932 }
 933
 934 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 935                 u8 prim_mode,
 936                 const struct adv7604_video_standards *predef_vid_timings,
 937                 const struct v4l2_dv_timings *timings)
 938 {
 939         int i;
 940
 941         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 942                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 943                                         is_digital_input(sd) ? 250000 : 1000000))
 944                         continue;
 945                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 946                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 947                                 prim_mode); /* v_freq and prim mode */
 948                 return 0;
 949         }
 950
 951         return -1;
 952 }
 953
 954 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 955                 struct v4l2_dv_timings *timings)
 956 {
 957         struct adv7604_state *state = to_state(sd);
 958         int err;
 959
 960         v4l2_dbg(1, debug, sd, "%s", __func__);
 961
 962         if (adv7604_has_afe(state)) {
 963                 /* reset to default values */
 964                 io_write(sd, 0x16, 0x43);
 965                 io_write(sd, 0x17, 0x5a);
 966         }
 967         /* disable embedded syncs for auto graphics mode */
 968         cp_write_clr_set(sd, 0x81, 0x10, 0x00);
 969         cp_write(sd, 0x8f, 0x00);
 970         cp_write(sd, 0x90, 0x00);
 971         cp_write(sd, 0xa2, 0x00);
 972         cp_write(sd, 0xa3, 0x00);
 973         cp_write(sd, 0xa4, 0x00);
 974         cp_write(sd, 0xa5, 0x00);
 975         cp_write(sd, 0xa6, 0x00);
 976         cp_write(sd, 0xa7, 0x00);
 977         cp_write(sd, 0xab, 0x00);
 978         cp_write(sd, 0xac, 0x00);
 979
 980         if (is_analog_input(sd)) {
 981                 err = find_and_set_predefined_video_timings(sd,
 982                                 0x01, adv7604_prim_mode_comp, timings);
 983                 if (err)
 984                         err = find_and_set_predefined_video_timings(sd,
 985                                         0x02, adv7604_prim_mode_gr, timings);
 986         } else if (is_digital_input(sd)) {
 987                 err = find_and_set_predefined_video_timings(sd,
 988                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 989                 if (err)
 990                         err = find_and_set_predefined_video_timings(sd,
 991                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 992         } else {
 993                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 994                                 __func__, state->selected_input);
 995                 err = -1;
 996         }
 997
 998
 999         return err;
1000 }
1001
1002 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1003                 const struct v4l2_bt_timings *bt)
1004 {
1005         struct adv7604_state *state = to_state(sd);
1006         u32 width = htotal(bt);
1007         u32 height = vtotal(bt);
1008         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1009         u16 cp_start_eav = width - bt->hfrontporch;
1010         u16 cp_start_vbi = height - bt->vfrontporch;
1011         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
1012         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1013                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1014         const u8 pll[2] = {
1015                 0xc0 | ((width >> 8) & 0x1f),
1016                 width & 0xff
1017         };
1018
1019         v4l2_dbg(2, debug, sd, "%s\n", __func__);
1020
1021         if (is_analog_input(sd)) {
1022                 /* auto graphics */
1023                 io_write(sd, 0x00, 0x07); /* video std */
1024                 io_write(sd, 0x01, 0x02); /* prim mode */
1025                 /* enable embedded syncs for auto graphics mode */
1026                 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1027
1028                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1029                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
1030                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
1031                 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO,
1032                                                    0x16, 2, pll))
1033                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1034
1035                 /* active video - horizontal timing */
1036                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1037                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1038                                    ((cp_start_eav >> 8) & 0x0f));
1039                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1040
1041                 /* active video - vertical timing */
1042                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1043                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1044                                    ((cp_end_vbi >> 8) & 0xf));
1045                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1046         } else if (is_digital_input(sd)) {
1047                 /* set default prim_mode/vid_std for HDMI
1048                    according to [REF_03, c. 4.2] */
1049                 io_write(sd, 0x00, 0x02); /* video std */
1050                 io_write(sd, 0x01, 0x06); /* prim mode */
1051         } else {
1052                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1053                                 __func__, state->selected_input);
1054         }
1055
1056         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1057         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1058         cp_write(sd, 0xab, (height >> 4) & 0xff);
1059         cp_write(sd, 0xac, (height & 0x0f) << 4);
1060 }
1061
1062 static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1063 {
1064         struct adv7604_state *state = to_state(sd);
1065         u8 offset_buf[4];
1066
1067         if (auto_offset) {
1068                 offset_a = 0x3ff;
1069                 offset_b = 0x3ff;
1070                 offset_c = 0x3ff;
1071         }
1072
1073         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1074                         __func__, auto_offset ? "Auto" : "Manual",
1075                         offset_a, offset_b, offset_c);
1076
1077         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1078         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1079         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1080         offset_buf[3] = offset_c & 0x0ff;
1081
1082         /* Registers must be written in this order with no i2c access in between */
1083         if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1084                                            0x77, 4, offset_buf))
1085                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1086 }
1087
1088 static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1089 {
1090         struct adv7604_state *state = to_state(sd);
1091         u8 gain_buf[4];
1092         u8 gain_man = 1;
1093         u8 agc_mode_man = 1;
1094
1095         if (auto_gain) {
1096                 gain_man = 0;
1097                 agc_mode_man = 0;
1098                 gain_a = 0x100;
1099                 gain_b = 0x100;
1100                 gain_c = 0x100;
1101         }
1102
1103         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1104                         __func__, auto_gain ? "Auto" : "Manual",
1105                         gain_a, gain_b, gain_c);
1106
1107         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1108         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1109         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1110         gain_buf[3] = ((gain_c & 0x0ff));
1111
1112         /* Registers must be written in this order with no i2c access in between */
1113         if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1114                                            0x73, 4, gain_buf))
1115                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1116 }
1117
1118 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1119 {
1120         struct adv7604_state *state = to_state(sd);
1121         bool rgb_output = io_read(sd, 0x02) & 0x02;
1122         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1123
1124         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1125                         __func__, state->rgb_quantization_range,
1126                         rgb_output, hdmi_signal);
1127
1128         adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
1129         adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
1130
1131         switch (state->rgb_quantization_range) {
1132         case V4L2_DV_RGB_RANGE_AUTO:
1133                 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1134                         /* Receiving analog RGB signal
1135                          * Set RGB full range (0-255) */
1136                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1137                         break;
1138                 }
1139
1140                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1141                         /* Receiving analog YPbPr signal
1142                          * Set automode */
1143                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1144                         break;
1145                 }
1146
1147                 if (hdmi_signal) {
1148                         /* Receiving HDMI signal
1149                          * Set automode */
1150                         io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1151                         break;
1152                 }
1153
1154                 /* Receiving DVI-D signal
1155                  * ADV7604 selects RGB limited range regardless of
1156                  * input format (CE/IT) in automatic mode */
1157                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1158                         /* RGB limited range (16-235) */
1159                         io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1160                 } else {
1161                         /* RGB full range (0-255) */
1162                         io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1163
1164                         if (is_digital_input(sd) && rgb_output) {
1165                                 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1166                         } else {
1167                                 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1168                                 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1169                         }
1170                 }
1171                 break;
1172         case V4L2_DV_RGB_RANGE_LIMITED:
1173                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1174                         /* YCrCb limited range (16-235) */
1175                         io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1176                         break;
1177                 }
1178
1179                 /* RGB limited range (16-235) */
1180                 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1181
1182                 break;
1183         case V4L2_DV_RGB_RANGE_FULL:
1184                 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1185                         /* YCrCb full range (0-255) */
1186                         io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1187                         break;
1188                 }
1189
1190                 /* RGB full range (0-255) */
1191                 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1192
1193                 if (is_analog_input(sd) || hdmi_signal)
1194                         break;
1195
1196                 /* Adjust gain/offset for DVI-D signals only */
1197                 if (rgb_output) {
1198                         adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1199                 } else {
1200                         adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1201                         adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1202                 }
1203                 break;
1204         }
1205 }
1206
1207 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1208 {
1209         struct v4l2_subdev *sd =
1210                 &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
1211
1212         struct adv7604_state *state = to_state(sd);
1213
1214         switch (ctrl->id) {
1215         case V4L2_CID_BRIGHTNESS:
1216                 cp_write(sd, 0x3c, ctrl->val);
1217                 return 0;
1218         case V4L2_CID_CONTRAST:
1219                 cp_write(sd, 0x3a, ctrl->val);
1220                 return 0;
1221         case V4L2_CID_SATURATION:
1222                 cp_write(sd, 0x3b, ctrl->val);
1223                 return 0;
1224         case V4L2_CID_HUE:
1225                 cp_write(sd, 0x3d, ctrl->val);
1226                 return 0;
1227         case  V4L2_CID_DV_RX_RGB_RANGE:
1228                 state->rgb_quantization_range = ctrl->val;
1229                 set_rgb_quantization_range(sd);
1230                 return 0;
1231         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1232                 if (!adv7604_has_afe(state))
1233                         return -EINVAL;
1234                 /* Set the analog sampling phase. This is needed to find the
1235                    best sampling phase for analog video: an application or
1236                    driver has to try a number of phases and analyze the picture
1237                    quality before settling on the best performing phase. */
1238                 afe_write(sd, 0xc8, ctrl->val);
1239                 return 0;
1240         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1241                 /* Use the default blue color for free running mode,
1242                    or supply your own. */
1243                 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1244                 return 0;
1245         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1246                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1247                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1248                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1249                 return 0;
1250         }
1251         return -EINVAL;
1252 }
1253
1254 /* ----------------------------------------------------------------------- */
1255
1256 static inline bool no_power(struct v4l2_subdev *sd)
1257 {
1258         /* Entire chip or CP powered off */
1259         return io_read(sd, 0x0c) & 0x24;
1260 }
1261
1262 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1263 {
1264         struct adv7604_state *state = to_state(sd);
1265
1266         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1267 }
1268
1269 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1270 {
1271         struct adv7604_state *state = to_state(sd);
1272         const struct adv7604_chip_info *info = state->info;
1273
1274         return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1275 }
1276
1277 static inline bool is_hdmi(struct v4l2_subdev *sd)
1278 {
1279         return hdmi_read(sd, 0x05) & 0x80;
1280 }
1281
1282 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1283 {
1284         struct adv7604_state *state = to_state(sd);
1285
1286         /*
1287          * Chips without a AFE don't expose registers for the SSPD, so just assume
1288          * that we have a lock.
1289          */
1290         if (adv7604_has_afe(state))
1291                 return false;
1292
1293         /* TODO channel 2 */
1294         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1295 }
1296
1297 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1298 {
1299         /* TODO channel 2 */
1300         return !(cp_read(sd, 0xb1) & 0x80);
1301 }
1302
1303 static inline bool no_signal(struct v4l2_subdev *sd)
1304 {
1305         bool ret;
1306
1307         ret = no_power(sd);
1308
1309         ret |= no_lock_stdi(sd);
1310         ret |= no_lock_sspd(sd);
1311
1312         if (is_digital_input(sd)) {
1313                 ret |= no_lock_tmds(sd);
1314                 ret |= no_signal_tmds(sd);
1315         }
1316
1317         return ret;
1318 }
1319
1320 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1321 {
1322         struct adv7604_state *state = to_state(sd);
1323
1324         if (!adv7604_has_afe(state))
1325                 return false;
1326
1327         /* CP has detected a non standard number of lines on the incoming
1328            video compared to what it is configured to receive by s_dv_timings */
1329         return io_read(sd, 0x12) & 0x01;
1330 }
1331
1332 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1333 {
1334         *status = 0;
1335         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1336         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1337         if (no_lock_cp(sd))
1338                 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1339
1340         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1341
1342         return 0;
1343 }
1344
1345 /* ----------------------------------------------------------------------- */
1346
1347 struct stdi_readback {
1348         u16 bl, lcf, lcvs;
1349         u8 hs_pol, vs_pol;
1350         bool interlaced;
1351 };
1352
1353 static int stdi2dv_timings(struct v4l2_subdev *sd,
1354                 struct stdi_readback *stdi,
1355                 struct v4l2_dv_timings *timings)
1356 {
1357         struct adv7604_state *state = to_state(sd);
1358         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1359         u32 pix_clk;
1360         int i;
1361
1362         for (i = 0; adv7604_timings[i].bt.height; i++) {
1363                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1364                         continue;
1365                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1366                         continue;
1367
1368                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1369
1370                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1371                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1372                         *timings = adv7604_timings[i];
1373                         return 0;
1374                 }
1375         }
1376
1377         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1378                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1379                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1380                         timings))
1381                 return 0;
1382         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1383                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1384                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1385                         state->aspect_ratio, timings))
1386                 return 0;
1387
1388         v4l2_dbg(2, debug, sd,
1389                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1390                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1391                 stdi->hs_pol, stdi->vs_pol);
1392         return -1;
1393 }
1394
1395
1396 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1397 {
1398         struct adv7604_state *state = to_state(sd);
1399         const struct adv7604_chip_info *info = state->info;
1400         u8 polarity;
1401
1402         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1403                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1404                 return -1;
1405         }
1406
1407         /* read STDI */
1408         stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1409         stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1410         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1411         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1412
1413         if (adv7604_has_afe(state)) {
1414                 /* read SSPD */
1415                 polarity = cp_read(sd, 0xb5);
1416                 if ((polarity & 0x03) == 0x01) {
1417                         stdi->hs_pol = polarity & 0x10
1418                                      ? (polarity & 0x08 ? '+' : '-') : 'x';
1419                         stdi->vs_pol = polarity & 0x40
1420                                      ? (polarity & 0x20 ? '+' : '-') : 'x';
1421                 } else {
1422                         stdi->hs_pol = 'x';
1423                         stdi->vs_pol = 'x';
1424                 }
1425         } else {
1426                 polarity = hdmi_read(sd, 0x05);
1427                 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1428                 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1429         }
1430
1431         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1432                 v4l2_dbg(2, debug, sd,
1433                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1434                 return -1;
1435         }
1436
1437         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1438                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1439                 memset(stdi, 0, sizeof(struct stdi_readback));
1440                 return -1;
1441         }
1442
1443         v4l2_dbg(2, debug, sd,
1444                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1445                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1446                 stdi->hs_pol, stdi->vs_pol,
1447                 stdi->interlaced ? "interlaced" : "progressive");
1448
1449         return 0;
1450 }
1451
1452 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1453                         struct v4l2_enum_dv_timings *timings)
1454 {
1455         struct adv7604_state *state = to_state(sd);
1456
1457         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1458                 return -EINVAL;
1459
1460         if (timings->pad >= state->source_pad)
1461                 return -EINVAL;
1462
1463         memset(timings->reserved, 0, sizeof(timings->reserved));
1464         timings->timings = adv7604_timings[timings->index];
1465         return 0;
1466 }
1467
1468 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1469                         struct v4l2_dv_timings_cap *cap)
1470 {
1471         struct adv7604_state *state = to_state(sd);
1472
1473         if (cap->pad >= state->source_pad)
1474                 return -EINVAL;
1475
1476         cap->type = V4L2_DV_BT_656_1120;
1477         cap->bt.max_width = 1920;
1478         cap->bt.max_height = 1200;
1479         cap->bt.min_pixelclock = 25000000;
1480
1481         switch (cap->pad) {
1482         case ADV7604_PAD_HDMI_PORT_A:
1483         case ADV7604_PAD_HDMI_PORT_B:
1484         case ADV7604_PAD_HDMI_PORT_C:
1485         case ADV7604_PAD_HDMI_PORT_D:
1486                 cap->bt.max_pixelclock = 225000000;
1487                 break;
1488         case ADV7604_PAD_VGA_RGB:
1489         case ADV7604_PAD_VGA_COMP:
1490         default:
1491                 cap->bt.max_pixelclock = 170000000;
1492                 break;
1493         }
1494
1495         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1496                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1497         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1498                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1499         return 0;
1500 }
1501
1502 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1503    if the format is listed in adv7604_timings[] */
1504 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1505                 struct v4l2_dv_timings *timings)
1506 {
1507         int i;
1508
1509         for (i = 0; adv7604_timings[i].bt.width; i++) {
1510                 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1511                                         is_digital_input(sd) ? 250000 : 1000000)) {
1512                         *timings = adv7604_timings[i];
1513                         break;
1514                 }
1515         }
1516 }
1517
1518 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1519 {
1520         unsigned int freq;
1521         int a, b;
1522
1523         a = hdmi_read(sd, 0x06);
1524         b = hdmi_read(sd, 0x3b);
1525         if (a < 0 || b < 0)
1526                 return 0;
1527         freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;
1528
1529         if (is_hdmi(sd)) {
1530                 /* adjust for deep color mode */
1531                 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1532
1533                 freq = freq * 8 / bits_per_channel;
1534         }
1535
1536         return freq;
1537 }
1538
1539 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1540 {
1541         int a, b;
1542
1543         a = hdmi_read(sd, 0x51);
1544         b = hdmi_read(sd, 0x52);
1545         if (a < 0 || b < 0)
1546                 return 0;
1547         return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1548 }
1549
1550 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1551                         struct v4l2_dv_timings *timings)
1552 {
1553         struct adv7604_state *state = to_state(sd);
1554         const struct adv7604_chip_info *info = state->info;
1555         struct v4l2_bt_timings *bt = &timings->bt;
1556         struct stdi_readback stdi;
1557
1558         if (!timings)
1559                 return -EINVAL;
1560
1561         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1562
1563         if (no_signal(sd)) {
1564                 state->restart_stdi_once = true;
1565                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1566                 return -ENOLINK;
1567         }
1568
1569         /* read STDI */
1570         if (read_stdi(sd, &stdi)) {
1571                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1572                 return -ENOLINK;
1573         }
1574         bt->interlaced = stdi.interlaced ?
1575                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1576
1577         if (is_digital_input(sd)) {
1578                 timings->type = V4L2_DV_BT_656_1120;
1579
1580                 /* FIXME: All masks are incorrect for ADV7611 */
1581                 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1582                 bt->height = hdmi_read16(sd, 0x09, 0xfff);
1583                 bt->pixelclock = info->read_hdmi_pixelclock(sd);
1584                 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1585                 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1586                 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1587                 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1588                 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1589                 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
1590                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1591                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1592                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1593                         bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1594                         bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1595                         bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
1596                         bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1597                 }
1598                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1599         } else {
1600                 /* find format
1601                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1602                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1603                  */
1604                 if (!stdi2dv_timings(sd, &stdi, timings))
1605                         goto found;
1606                 stdi.lcvs += 1;
1607                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1608                 if (!stdi2dv_timings(sd, &stdi, timings))
1609                         goto found;
1610                 stdi.lcvs -= 2;
1611                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1612                 if (stdi2dv_timings(sd, &stdi, timings)) {
1613                         /*
1614                          * The STDI block may measure wrong values, especially
1615                          * for lcvs and lcf. If the driver can not find any
1616                          * valid timing, the STDI block is restarted to measure
1617                          * the video timings again. The function will return an
1618                          * error, but the restart of STDI will generate a new
1619                          * STDI interrupt and the format detection process will
1620                          * restart.
1621                          */
1622                         if (state->restart_stdi_once) {
1623                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1624                                 /* TODO restart STDI for Sync Channel 2 */
1625                                 /* enter one-shot mode */
1626                                 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1627                                 /* trigger STDI restart */
1628                                 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1629                                 /* reset to continuous mode */
1630                                 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1631                                 state->restart_stdi_once = false;
1632                                 return -ENOLINK;
1633                         }
1634                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1635                         return -ERANGE;
1636                 }
1637                 state->restart_stdi_once = true;
1638         }
1639 found:
1640
1641         if (no_signal(sd)) {
1642                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1643                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1644                 return -ENOLINK;
1645         }
1646
1647         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1648                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1649                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1650                                 __func__, (u32)bt->pixelclock);
1651                 return -ERANGE;
1652         }
1653
1654         if (debug > 1)
1655                 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1656                                       timings, true);
1657
1658         return 0;
1659 }
1660
1661 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1662                 struct v4l2_dv_timings *timings)
1663 {
1664         struct adv7604_state *state = to_state(sd);
1665         struct v4l2_bt_timings *bt;
1666         int err;
1667
1668         if (!timings)
1669                 return -EINVAL;
1670
1671         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1672                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1673                 return 0;
1674         }
1675
1676         bt = &timings->bt;
1677
1678         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1679                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1680                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1681                                 __func__, (u32)bt->pixelclock);
1682                 return -ERANGE;
1683         }
1684
1685         adv7604_fill_optional_dv_timings_fields(sd, timings);
1686
1687         state->timings = *timings;
1688
1689         cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1690
1691         /* Use prim_mode and vid_std when available */
1692         err = configure_predefined_video_timings(sd, timings);
1693         if (err) {
1694                 /* custom settings when the video format
1695                  does not have prim_mode/vid_std */
1696                 configure_custom_video_timings(sd, bt);
1697         }
1698
1699         set_rgb_quantization_range(sd);
1700
1701         if (debug > 1)
1702                 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1703                                       timings, true);
1704         return 0;
1705 }
1706
1707 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1708                 struct v4l2_dv_timings *timings)
1709 {
1710         struct adv7604_state *state = to_state(sd);
1711
1712         *timings = state->timings;
1713         return 0;
1714 }
1715
1716 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1717 {
1718         hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1719 }
1720
1721 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1722 {
1723         hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1724 }
1725
1726 static void enable_input(struct v4l2_subdev *sd)
1727 {
1728         struct adv7604_state *state = to_state(sd);
1729
1730         if (is_analog_input(sd)) {
1731                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1732         } else if (is_digital_input(sd)) {
1733                 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1734                 state->info->set_termination(sd, true);
1735                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1736                 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1737         } else {
1738                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1739                                 __func__, state->selected_input);
1740         }
1741 }
1742
1743 static void disable_input(struct v4l2_subdev *sd)
1744 {
1745         struct adv7604_state *state = to_state(sd);
1746
1747         hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1748         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1749         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1750         state->info->set_termination(sd, false);
1751 }
1752
1753 static void select_input(struct v4l2_subdev *sd)
1754 {
1755         struct adv7604_state *state = to_state(sd);
1756         const struct adv7604_chip_info *info = state->info;
1757
1758         if (is_analog_input(sd)) {
1759                 adv7604_write_reg_seq(sd, info->recommended_settings[0]);
1760
1761                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1762                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1763                 afe_write(sd, 0xc8, 0x00); /* phase control */
1764         } else if (is_digital_input(sd)) {
1765                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1766
1767                 adv7604_write_reg_seq(sd, info->recommended_settings[1]);
1768
1769                 if (adv7604_has_afe(state)) {
1770                         afe_write(sd, 0x00, 0xff); /* power down ADC */
1771                         afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1772                         afe_write(sd, 0xc8, 0x40); /* phase control */
1773                 }
1774
1775                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1776                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1777                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1778         } else {
1779                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1780                                 __func__, state->selected_input);
1781         }
1782 }
1783
1784 static int adv7604_s_routing(struct v4l2_subdev *sd,
1785                 u32 input, u32 output, u32 config)
1786 {
1787         struct adv7604_state *state = to_state(sd);
1788
1789         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1790                         __func__, input, state->selected_input);
1791
1792         if (input == state->selected_input)
1793                 return 0;
1794
1795         if (input > state->info->max_port)
1796                 return -EINVAL;
1797
1798         state->selected_input = input;
1799
1800         disable_input(sd);
1801
1802         select_input(sd);
1803
1804         enable_input(sd);
1805
1806         return 0;
1807 }
1808
1809 static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
1810                                   struct v4l2_subdev_fh *fh,
1811                                   struct v4l2_subdev_mbus_code_enum *code)
1812 {
1813         struct adv7604_state *state = to_state(sd);
1814
1815         if (code->index >= state->info->nformats)
1816                 return -EINVAL;
1817
1818         code->code = state->info->formats[code->index].code;
1819
1820         return 0;
1821 }
1822
1823 static void adv7604_fill_format(struct adv7604_state *state,
1824                                 struct v4l2_mbus_framefmt *format)
1825 {
1826         memset(format, 0, sizeof(*format));
1827
1828         format->width = state->timings.bt.width;
1829         format->height = state->timings.bt.height;
1830         format->field = V4L2_FIELD_NONE;
1831
1832         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
1833                 format->colorspace = (state->timings.bt.height <= 576) ?
1834                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1835 }
1836
1837 /*
1838  * Compute the op_ch_sel value required to obtain on the bus the component order
1839  * corresponding to the selected format taking into account bus reordering
1840  * applied by the board at the output of the device.
1841  *
1842  * The following table gives the op_ch_value from the format component order
1843  * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1844  * adv7604_bus_order value in row).
1845  *
1846  *           |  GBR(0)  GRB(1)  BGR(2)  RGB(3)  BRG(4)  RBG(5)
1847  * ----------+-------------------------------------------------
1848  * RGB (NOP) |  GBR     GRB     BGR     RGB     BRG     RBG
1849  * GRB (1-2) |  BGR     RGB     GBR     GRB     RBG     BRG
1850  * RBG (2-3) |  GRB     GBR     BRG     RBG     BGR     RGB
1851  * BGR (1-3) |  RBG     BRG     RGB     BGR     GRB     GBR
1852  * BRG (ROR) |  BRG     RBG     GRB     GBR     RGB     BGR
1853  * GBR (ROL) |  RGB     BGR     RBG     BRG     GBR     GRB
1854  */
1855 static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
1856 {
1857 #define _SEL(a,b,c,d,e,f)       { \
1858         ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
1859         ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
1860 #define _BUS(x)                 [ADV7604_BUS_ORDER_##x]
1861
1862         static const unsigned int op_ch_sel[6][6] = {
1863                 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1864                 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1865                 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1866                 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1867                 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1868                 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1869         };
1870
1871         return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1872 }
1873
1874 static void adv7604_setup_format(struct adv7604_state *state)
1875 {
1876         struct v4l2_subdev *sd = &state->sd;
1877
1878         io_write_clr_set(sd, 0x02, 0x02,
1879                         state->format->rgb_out ? ADV7604_RGB_OUT : 0);
1880         io_write(sd, 0x03, state->format->op_format_sel |
1881                  state->pdata.op_format_mode_sel);
1882         io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
1883         io_write_clr_set(sd, 0x05, 0x01,
1884                         state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
1885 }
1886
1887 static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1888                               struct v4l2_subdev_format *format)
1889 {
1890         struct adv7604_state *state = to_state(sd);
1891
1892         if (format->pad != state->source_pad)
1893                 return -EINVAL;
1894
1895         adv7604_fill_format(state, &format->format);
1896
1897         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1898                 struct v4l2_mbus_framefmt *fmt;
1899
1900                 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1901                 format->format.code = fmt->code;
1902         } else {
1903                 format->format.code = state->format->code;
1904         }
1905
1906         return 0;
1907 }
1908
1909 static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1910                               struct v4l2_subdev_format *format)
1911 {
1912         struct adv7604_state *state = to_state(sd);
1913         const struct adv7604_format_info *info;
1914
1915         if (format->pad != state->source_pad)
1916                 return -EINVAL;
1917
1918         info = adv7604_format_info(state, format->format.code);
1919         if (info == NULL)
1920                 info = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1921
1922         adv7604_fill_format(state, &format->format);
1923         format->format.code = info->code;
1924
1925         if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1926                 struct v4l2_mbus_framefmt *fmt;
1927
1928                 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1929                 fmt->code = format->format.code;
1930         } else {
1931                 state->format = info;
1932                 adv7604_setup_format(state);
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1939 {
1940         struct adv7604_state *state = to_state(sd);
1941         const struct adv7604_chip_info *info = state->info;
1942         const u8 irq_reg_0x43 = io_read(sd, 0x43);
1943         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1944         const u8 irq_reg_0x70 = io_read(sd, 0x70);
1945         u8 fmt_change_digital;
1946         u8 fmt_change;
1947         u8 tx_5v;
1948
1949         if (irq_reg_0x43)
1950                 io_write(sd, 0x44, irq_reg_0x43);
1951         if (irq_reg_0x70)
1952                 io_write(sd, 0x71, irq_reg_0x70);
1953         if (irq_reg_0x6b)
1954                 io_write(sd, 0x6c, irq_reg_0x6b);
1955
1956         v4l2_dbg(2, debug, sd, "%s: ", __func__);
1957
1958         /* format change */
1959         fmt_change = irq_reg_0x43 & 0x98;
1960         fmt_change_digital = is_digital_input(sd)
1961                            ? irq_reg_0x6b & info->fmt_change_digital_mask
1962                            : 0;
1963
1964         if (fmt_change || fmt_change_digital) {
1965                 v4l2_dbg(1, debug, sd,
1966                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1967                         __func__, fmt_change, fmt_change_digital);
1968
1969                 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1970
1971                 if (handled)
1972                         *handled = true;
1973         }
1974         /* HDMI/DVI mode */
1975         if (irq_reg_0x6b & 0x01) {
1976                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1977                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1978                 set_rgb_quantization_range(sd);
1979                 if (handled)
1980                         *handled = true;
1981         }
1982
1983         /* tx 5v detect */
1984         tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
1985         if (tx_5v) {
1986                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1987                 io_write(sd, 0x71, tx_5v);
1988                 adv7604_s_detect_tx_5v_ctrl(sd);
1989                 if (handled)
1990                         *handled = true;
1991         }
1992         return 0;
1993 }
1994
1995 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1996 {
1997         struct adv7604_state *state = to_state(sd);
1998         u8 *data = NULL;
1999
2000         memset(edid->reserved, 0, sizeof(edid->reserved));
2001
2002         switch (edid->pad) {
2003         case ADV7604_PAD_HDMI_PORT_A:
2004         case ADV7604_PAD_HDMI_PORT_B:
2005         case ADV7604_PAD_HDMI_PORT_C:
2006         case ADV7604_PAD_HDMI_PORT_D:
2007                 if (state->edid.present & (1 << edid->pad))
2008                         data = state->edid.edid;
2009                 break;
2010         default:
2011                 return -EINVAL;
2012         }
2013
2014         if (edid->start_block == 0 && edid->blocks == 0) {
2015                 edid->blocks = data ? state->edid.blocks : 0;
2016                 return 0;
2017         }
2018
2019         if (data == NULL)
2020                 return -ENODATA;
2021
2022         if (edid->start_block >= state->edid.blocks)
2023                 return -EINVAL;
2024
2025         if (edid->start_block + edid->blocks > state->edid.blocks)
2026                 edid->blocks = state->edid.blocks - edid->start_block;
2027
2028         memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2029
2030         return 0;
2031 }
2032
2033 static int get_edid_spa_location(const u8 *edid)
2034 {
2035         u8 d;
2036
2037         if ((edid[0x7e] != 1) ||
2038             (edid[0x80] != 0x02) ||
2039             (edid[0x81] != 0x03)) {
2040                 return -1;
2041         }
2042
2043         /* search Vendor Specific Data Block (tag 3) */
2044         d = edid[0x82] & 0x7f;
2045         if (d > 4) {
2046                 int i = 0x84;
2047                 int end = 0x80 + d;
2048
2049                 do {
2050                         u8 tag = edid[i] >> 5;
2051                         u8 len = edid[i] & 0x1f;
2052
2053                         if ((tag == 3) && (len >= 5))
2054                                 return i + 4;
2055                         i += len + 1;
2056                 } while (i < end);
2057         }
2058         return -1;
2059 }
2060
2061 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2062 {
2063         struct adv7604_state *state = to_state(sd);
2064         const struct adv7604_chip_info *info = state->info;
2065         int spa_loc;
2066         int err;
2067         int i;
2068
2069         memset(edid->reserved, 0, sizeof(edid->reserved));
2070
2071         if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2072                 return -EINVAL;
2073         if (edid->start_block != 0)
2074                 return -EINVAL;
2075         if (edid->blocks == 0) {
2076                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
2077                 state->edid.present &= ~(1 << edid->pad);
2078                 adv7604_set_hpd(state, state->edid.present);
2079                 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2080
2081                 /* Fall back to a 16:9 aspect ratio */
2082                 state->aspect_ratio.numerator = 16;
2083                 state->aspect_ratio.denominator = 9;
2084
2085                 if (!state->edid.present)
2086                         state->edid.blocks = 0;
2087
2088                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2089                                 __func__, edid->pad, state->edid.present);
2090                 return 0;
2091         }
2092         if (edid->blocks > 2) {
2093                 edid->blocks = 2;
2094                 return -E2BIG;
2095         }
2096
2097         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2098                         __func__, edid->pad, state->edid.present);
2099
2100         /* Disable hotplug and I2C access to EDID RAM from DDC port */
2101         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2102         adv7604_set_hpd(state, 0);
2103         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2104
2105         spa_loc = get_edid_spa_location(edid->edid);
2106         if (spa_loc < 0)
2107                 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2108
2109         switch (edid->pad) {
2110         case ADV7604_PAD_HDMI_PORT_A:
2111                 state->spa_port_a[0] = edid->edid[spa_loc];
2112                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
2113                 break;
2114         case ADV7604_PAD_HDMI_PORT_B:
2115                 rep_write(sd, 0x70, edid->edid[spa_loc]);
2116                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2117                 break;
2118         case ADV7604_PAD_HDMI_PORT_C:
2119                 rep_write(sd, 0x72, edid->edid[spa_loc]);
2120                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2121                 break;
2122         case ADV7604_PAD_HDMI_PORT_D:
2123                 rep_write(sd, 0x74, edid->edid[spa_loc]);
2124                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2125                 break;
2126         default:
2127                 return -EINVAL;
2128         }
2129
2130         if (info->type == ADV7604) {
2131                 rep_write(sd, 0x76, spa_loc & 0xff);
2132                 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2133         } else {
2134                 /* FIXME: Where is the SPA location LSB register ? */
2135                 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2136         }
2137
2138         edid->edid[spa_loc] = state->spa_port_a[0];
2139         edid->edid[spa_loc + 1] = state->spa_port_a[1];
2140
2141         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2142         state->edid.blocks = edid->blocks;
2143         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2144                         edid->edid[0x16]);
2145         state->edid.present |= 1 << edid->pad;
2146
2147         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2148         if (err < 0) {
2149                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2150                 return err;
2151         }
2152
2153         /* adv7604 calculates the checksums and enables I2C access to internal
2154            EDID RAM from DDC port. */
2155         rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2156
2157         for (i = 0; i < 1000; i++) {
2158                 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2159                         break;
2160                 mdelay(1);
2161         }
2162         if (i == 1000) {
2163                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2164                 return -EIO;
2165         }
2166
2167         /* enable hotplug after 100 ms */
2168         queue_delayed_work(state->work_queues,
2169                         &state->delayed_work_enable_hotplug, HZ / 10);
2170         return 0;
2171 }
2172
2173 /*********** avi info frame CEA-861-E **************/
2174
2175 static void print_avi_infoframe(struct v4l2_subdev *sd)
2176 {
2177         int i;
2178         u8 buf[14];
2179         u8 avi_len;
2180         u8 avi_ver;
2181
2182         if (!is_hdmi(sd)) {
2183                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2184                 return;
2185         }
2186         if (!(io_read(sd, 0x60) & 0x01)) {
2187                 v4l2_info(sd, "AVI infoframe not received\n");
2188                 return;
2189         }
2190
2191         if (io_read(sd, 0x83) & 0x01) {
2192                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2193                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2194                 if (io_read(sd, 0x83) & 0x01) {
2195                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
2196                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2197                 }
2198         }
2199
2200         avi_len = infoframe_read(sd, 0xe2);
2201         avi_ver = infoframe_read(sd, 0xe1);
2202         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2203                         avi_ver, avi_len);
2204
2205         if (avi_ver != 0x02)
2206                 return;
2207
2208         for (i = 0; i < 14; i++)
2209                 buf[i] = infoframe_read(sd, i);
2210
2211         v4l2_info(sd,
2212                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2213                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2214                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2215 }
2216
2217 static int adv7604_log_status(struct v4l2_subdev *sd)
2218 {
2219         struct adv7604_state *state = to_state(sd);
2220         const struct adv7604_chip_info *info = state->info;
2221         struct v4l2_dv_timings timings;
2222         struct stdi_readback stdi;
2223         u8 reg_io_0x02 = io_read(sd, 0x02);
2224         u8 edid_enabled;
2225         u8 cable_det;
2226
2227         static const char * const csc_coeff_sel_rb[16] = {
2228                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2229                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2230                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2231                 "reserved", "reserved", "reserved", "reserved", "manual"
2232         };
2233         static const char * const input_color_space_txt[16] = {
2234                 "RGB limited range (16-235)", "RGB full range (0-255)",
2235                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2236                 "xvYCC Bt.601", "xvYCC Bt.709",
2237                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2238                 "invalid", "invalid", "invalid", "invalid", "invalid",
2239                 "invalid", "invalid", "automatic"
2240         };
2241         static const char * const rgb_quantization_range_txt[] = {
2242                 "Automatic",
2243                 "RGB limited range (16-235)",
2244                 "RGB full range (0-255)",
2245         };
2246         static const char * const deep_color_mode_txt[4] = {
2247                 "8-bits per channel",
2248                 "10-bits per channel",
2249                 "12-bits per channel",
2250                 "16-bits per channel (not supported)"
2251         };
2252
2253         v4l2_info(sd, "-----Chip status-----\n");
2254         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2255         edid_enabled = rep_read(sd, info->edid_status_reg);
2256         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2257                         ((edid_enabled & 0x01) ? "Yes" : "No"),
2258                         ((edid_enabled & 0x02) ? "Yes" : "No"),
2259                         ((edid_enabled & 0x04) ? "Yes" : "No"),
2260                         ((edid_enabled & 0x08) ? "Yes" : "No"));
2261         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2262                         "enabled" : "disabled");
2263
2264         v4l2_info(sd, "-----Signal status-----\n");
2265         cable_det = info->read_cable_det(sd);
2266         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2267                         ((cable_det & 0x01) ? "Yes" : "No"),
2268                         ((cable_det & 0x02) ? "Yes" : "No"),
2269                         ((cable_det & 0x04) ? "Yes" : "No"),
2270                         ((cable_det & 0x08) ? "Yes" : "No"));
2271         v4l2_info(sd, "TMDS signal detected: %s\n",
2272                         no_signal_tmds(sd) ? "false" : "true");
2273         v4l2_info(sd, "TMDS signal locked: %s\n",
2274                         no_lock_tmds(sd) ? "false" : "true");
2275         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2276         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2277         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2278         v4l2_info(sd, "CP free run: %s\n",
2279                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2280         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2281                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2282                         (io_read(sd, 0x01) & 0x70) >> 4);
2283
2284         v4l2_info(sd, "-----Video Timings-----\n");
2285         if (read_stdi(sd, &stdi))
2286                 v4l2_info(sd, "STDI: not locked\n");
2287         else
2288                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2289                                 stdi.lcf, stdi.bl, stdi.lcvs,
2290                                 stdi.interlaced ? "interlaced" : "progressive",
2291                                 stdi.hs_pol, stdi.vs_pol);
2292         if (adv7604_query_dv_timings(sd, &timings))
2293                 v4l2_info(sd, "No video detected\n");
2294         else
2295                 v4l2_print_dv_timings(sd->name, "Detected format: ",
2296                                       &timings, true);
2297         v4l2_print_dv_timings(sd->name, "Configured format: ",
2298                               &state->timings, true);
2299
2300         if (no_signal(sd))
2301                 return 0;
2302
2303         v4l2_info(sd, "-----Color space-----\n");
2304         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2305                         rgb_quantization_range_txt[state->rgb_quantization_range]);
2306         v4l2_info(sd, "Input color space: %s\n",
2307                         input_color_space_txt[reg_io_0x02 >> 4]);
2308         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2309                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2310                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2311                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2312                                 "enabled" : "disabled");
2313         v4l2_info(sd, "Color space conversion: %s\n",
2314                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
2315
2316         if (!is_digital_input(sd))
2317                 return 0;
2318
2319         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2320         v4l2_info(sd, "Digital video port selected: %c\n",
2321                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
2322         v4l2_info(sd, "HDCP encrypted content: %s\n",
2323                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2324         v4l2_info(sd, "HDCP keys read: %s%s\n",
2325                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2326                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2327         if (is_hdmi(sd)) {
2328                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2329                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2330                 bool audio_mute = io_read(sd, 0x65) & 0x40;
2331
2332                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2333                                 audio_pll_locked ? "locked" : "not locked",
2334                                 audio_sample_packet_detect ? "detected" : "not detected",
2335                                 audio_mute ? "muted" : "enabled");
2336                 if (audio_pll_locked && audio_sample_packet_detect) {
2337                         v4l2_info(sd, "Audio format: %s\n",
2338                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2339                 }
2340                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2341                                 (hdmi_read(sd, 0x5c) << 8) +
2342                                 (hdmi_read(sd, 0x5d) & 0xf0));
2343                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2344                                 (hdmi_read(sd, 0x5e) << 8) +
2345                                 hdmi_read(sd, 0x5f));
2346                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2347
2348                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2349
2350                 print_avi_infoframe(sd);
2351         }
2352
2353         return 0;
2354 }
2355
2356 /* ----------------------------------------------------------------------- */
2357
2358 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
2359         .s_ctrl = adv7604_s_ctrl,
2360 };
2361
2362 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2363         .log_status = adv7604_log_status,
2364         .interrupt_service_routine = adv7604_isr,
2365 #ifdef CONFIG_VIDEO_ADV_DEBUG
2366         .g_register = adv7604_g_register,
2367         .s_register = adv7604_s_register,
2368 #endif
2369 };
2370
2371 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2372         .s_routing = adv7604_s_routing,
2373         .g_input_status = adv7604_g_input_status,
2374         .s_dv_timings = adv7604_s_dv_timings,
2375         .g_dv_timings = adv7604_g_dv_timings,
2376         .query_dv_timings = adv7604_query_dv_timings,
2377 };
2378
2379 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
2380         .enum_mbus_code = adv7604_enum_mbus_code,
2381         .get_fmt = adv7604_get_format,
2382         .set_fmt = adv7604_set_format,
2383         .get_edid = adv7604_get_edid,
2384         .set_edid = adv7604_set_edid,
2385         .dv_timings_cap = adv7604_dv_timings_cap,
2386         .enum_dv_timings = adv7604_enum_dv_timings,
2387 };
2388
2389 static const struct v4l2_subdev_ops adv7604_ops = {
2390         .core = &adv7604_core_ops,
2391         .video = &adv7604_video_ops,
2392         .pad = &adv7604_pad_ops,
2393 };
2394
2395 /* -------------------------- custom ctrls ---------------------------------- */
2396
2397 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2398         .ops = &adv7604_ctrl_ops,
2399         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2400         .name = "Analog Sampling Phase",
2401         .type = V4L2_CTRL_TYPE_INTEGER,
2402         .min = 0,
2403         .max = 0x1f,
2404         .step = 1,
2405         .def = 0,
2406 };
2407
2408 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2409         .ops = &adv7604_ctrl_ops,
2410         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2411         .name = "Free Running Color, Manual",
2412         .type = V4L2_CTRL_TYPE_BOOLEAN,
2413         .min = false,
2414         .max = true,
2415         .step = 1,
2416         .def = false,
2417 };
2418
2419 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2420         .ops = &adv7604_ctrl_ops,
2421         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2422         .name = "Free Running Color",
2423         .type = V4L2_CTRL_TYPE_INTEGER,
2424         .min = 0x0,
2425         .max = 0xffffff,
2426         .step = 0x1,
2427         .def = 0x0,
2428 };
2429
2430 /* ----------------------------------------------------------------------- */
2431
2432 static int adv7604_core_init(struct v4l2_subdev *sd)
2433 {
2434         struct adv7604_state *state = to_state(sd);
2435         const struct adv7604_chip_info *info = state->info;
2436         struct adv7604_platform_data *pdata = &state->pdata;
2437
2438         hdmi_write(sd, 0x48,
2439                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2440                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2441
2442         disable_input(sd);
2443
2444         if (pdata->default_input >= 0 &&
2445             pdata->default_input < state->source_pad) {
2446                 state->selected_input = pdata->default_input;
2447                 select_input(sd);
2448                 enable_input(sd);
2449         }
2450
2451         /* power */
2452         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2453         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2454         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2455
2456         /* video format */
2457         io_write_clr_set(sd, 0x02, 0x0f,
2458                         pdata->alt_gamma << 3 |
2459                         pdata->op_656_range << 2 |
2460                         pdata->alt_data_sat << 0);
2461         io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2462                         pdata->insert_av_codes << 2 |
2463                         pdata->replicate_av_codes << 1);
2464         adv7604_setup_format(state);
2465
2466         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2467
2468         /* VS, HS polarities */
2469         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2470                  pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2471
2472         /* Adjust drive strength */
2473         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2474                                 pdata->dr_str_clk << 2 |
2475                                 pdata->dr_str_sync);
2476
2477         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2478         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2479         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2480                                       ADI recommended setting [REF_01, c. 2.3.3] */
2481         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2482                                       ADI recommended setting [REF_01, c. 2.3.3] */
2483         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2484                                      for digital formats */
2485
2486         /* HDMI audio */
2487         hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2488         hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2489         hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2490
2491         /* TODO from platform data */
2492         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2493
2494         if (adv7604_has_afe(state)) {
2495                 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2496                 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2497         }
2498
2499         /* interrupts */
2500         io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2501         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2502         io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2503         io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2504         info->setup_irqs(sd);
2505
2506         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2507 }
2508
2509 static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2510 {
2511         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2512 }
2513
2514 static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2515 {
2516         io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2517 }
2518
2519 static void adv7604_unregister_clients(struct adv7604_state *state)
2520 {
2521         unsigned int i;
2522
2523         for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2524                 if (state->i2c_clients[i])
2525                         i2c_unregister_device(state->i2c_clients[i]);
2526         }
2527 }
2528
2529 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2530                                                         u8 addr, u8 io_reg)
2531 {
2532         struct i2c_client *client = v4l2_get_subdevdata(sd);
2533
2534         if (addr)
2535                 io_write(sd, io_reg, addr << 1);
2536         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2537 }
2538
2539 static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = {
2540         /* reset ADI recommended settings for HDMI: */
2541         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2542         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2543         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2544         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2545         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2546         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2547         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2548         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2549         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2550         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2551         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2552         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2553         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2554
2555         /* set ADI recommended settings for digitizer */
2556         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2557         { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2558         { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2559         { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2560         { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2561         { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2562
2563         { ADV7604_REG_SEQ_TERM, 0 },
2564 };
2565
2566 static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = {
2567         /* set ADI recommended settings for HDMI: */
2568         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2569         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2570         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2571         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2572         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2573         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2574         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2575         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2576         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2577         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2578         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2579         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2580
2581         /* reset ADI recommended settings for digitizer */
2582         /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2583         { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2584         { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2585
2586         { ADV7604_REG_SEQ_TERM, 0 },
2587 };
2588
2589 static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = {
2590         /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
2591         { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 },
2592         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x9b), 0x03 },
2593         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x08 },
2594         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x85), 0x1f },
2595         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 },
2596         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda },
2597         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 },
2598         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 },
2599         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 },
2600         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 },
2601         { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e },
2602
2603         { ADV7604_REG_SEQ_TERM, 0 },
2604 };
2605
2606 static const struct adv7604_chip_info adv7604_chip_info[] = {
2607         [ADV7604] = {
2608                 .type = ADV7604,
2609                 .has_afe = true,
2610                 .max_port = ADV7604_PAD_VGA_COMP,
2611                 .num_dv_ports = 4,
2612                 .edid_enable_reg = 0x77,
2613                 .edid_status_reg = 0x7d,
2614                 .lcf_reg = 0xb3,
2615                 .tdms_lock_mask = 0xe0,
2616                 .cable_det_mask = 0x1e,
2617                 .fmt_change_digital_mask = 0xc1,
2618                 .formats = adv7604_formats,
2619                 .nformats = ARRAY_SIZE(adv7604_formats),
2620                 .set_termination = adv7604_set_termination,
2621                 .setup_irqs = adv7604_setup_irqs,
2622                 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2623                 .read_cable_det = adv7604_read_cable_det,
2624                 .recommended_settings = {
2625                     [0] = adv7604_recommended_settings_afe,
2626                     [1] = adv7604_recommended_settings_hdmi,
2627                 },
2628                 .num_recommended_settings = {
2629                     [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2630                     [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2631                 },
2632                 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2633                         BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) |
2634                         BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2635                         BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) |
2636                         BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) |
2637                         BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) |
2638                         BIT(ADV7604_PAGE_VDP),
2639         },
2640         [ADV7611] = {
2641                 .type = ADV7611,
2642                 .has_afe = false,
2643                 .max_port = ADV7604_PAD_HDMI_PORT_A,
2644                 .num_dv_ports = 1,
2645                 .edid_enable_reg = 0x74,
2646                 .edid_status_reg = 0x76,
2647                 .lcf_reg = 0xa3,
2648                 .tdms_lock_mask = 0x43,
2649                 .cable_det_mask = 0x01,
2650                 .fmt_change_digital_mask = 0x03,
2651                 .formats = adv7611_formats,
2652                 .nformats = ARRAY_SIZE(adv7611_formats),
2653                 .set_termination = adv7611_set_termination,
2654                 .setup_irqs = adv7611_setup_irqs,
2655                 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2656                 .read_cable_det = adv7611_read_cable_det,
2657                 .recommended_settings = {
2658                     [1] = adv7611_recommended_settings_hdmi,
2659                 },
2660                 .num_recommended_settings = {
2661                     [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2662                 },
2663                 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) |
2664                         BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) |
2665                         BIT(ADV7604_PAGE_REP) |  BIT(ADV7604_PAGE_EDID) |
2666                         BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP),
2667         },
2668 };
2669
2670 static struct i2c_device_id adv7604_i2c_id[] = {
2671         { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] },
2672         { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] },
2673         { }
2674 };
2675 MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id);
2676
2677 static struct of_device_id adv7604_of_id[] __maybe_unused = {
2678         { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] },
2679         { }
2680 };
2681 MODULE_DEVICE_TABLE(of, adv7604_of_id);
2682
2683 static int adv7604_parse_dt(struct adv7604_state *state)
2684 {
2685         struct v4l2_of_endpoint bus_cfg;
2686         struct device_node *endpoint;
2687         struct device_node *np;
2688         unsigned int flags;
2689
2690         np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node;
2691
2692         /* Parse the endpoint. */
2693         endpoint = of_graph_get_next_endpoint(np, NULL);
2694         if (!endpoint)
2695                 return -EINVAL;
2696
2697         v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2698         of_node_put(endpoint);
2699
2700         flags = bus_cfg.bus.parallel.flags;
2701
2702         if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2703                 state->pdata.inv_hs_pol = 1;
2704
2705         if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2706                 state->pdata.inv_vs_pol = 1;
2707
2708         if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2709                 state->pdata.inv_llc_pol = 1;
2710
2711         if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2712                 state->pdata.insert_av_codes = 1;
2713                 state->pdata.op_656_range = 1;
2714         }
2715
2716         /* Disable the interrupt for now as no DT-based board uses it. */
2717         state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED;
2718
2719         /* Use the default I2C addresses. */
2720         state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2721         state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40;
2722         state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e;
2723         state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2724         state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2725         state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26;
2726         state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32;
2727         state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36;
2728         state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34;
2729         state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30;
2730         state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22;
2731         state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2732
2733         /* Hardcode the remaining platform data fields. */
2734         state->pdata.disable_pwrdnb = 0;
2735         state->pdata.disable_cable_det_rst = 0;
2736         state->pdata.default_input = -1;
2737         state->pdata.blank_data = 1;
2738         state->pdata.alt_data_sat = 1;
2739         state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2740         state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2741
2742         return 0;
2743 }
2744
2745 static int adv7604_probe(struct i2c_client *client,
2746                          const struct i2c_device_id *id)
2747 {
2748         static const struct v4l2_dv_timings cea640x480 =
2749                 V4L2_DV_BT_CEA_640X480P59_94;
2750         struct adv7604_state *state;
2751         struct v4l2_ctrl_handler *hdl;
2752         struct v4l2_subdev *sd;
2753         unsigned int i;
2754         u16 val;
2755         int err;
2756
2757         /* Check if the adapter supports the needed features */
2758         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2759                 return -EIO;
2760         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2761                         client->addr << 1);
2762
2763         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2764         if (!state) {
2765                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2766                 return -ENOMEM;
2767         }
2768
2769         state->i2c_clients[ADV7604_PAGE_IO] = client;
2770
2771         /* initialize variables */
2772         state->restart_stdi_once = true;
2773         state->selected_input = ~0;
2774
2775         if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2776                 const struct of_device_id *oid;
2777
2778                 oid = of_match_node(adv7604_of_id, client->dev.of_node);
2779                 state->info = oid->data;
2780
2781                 err = adv7604_parse_dt(state);
2782                 if (err < 0) {
2783                         v4l_err(client, "DT parsing error\n");
2784                         return err;
2785                 }
2786         } else if (client->dev.platform_data) {
2787                 struct adv7604_platform_data *pdata = client->dev.platform_data;
2788
2789                 state->info = (const struct adv7604_chip_info *)id->driver_data;
2790                 state->pdata = *pdata;
2791         } else {
2792                 v4l_err(client, "No platform data!\n");
2793                 return -ENODEV;
2794         }
2795
2796         /* Request GPIOs. */
2797         for (i = 0; i < state->info->num_dv_ports; ++i) {
2798                 state->hpd_gpio[i] =
2799                         devm_gpiod_get_index(&client->dev, "hpd", i);
2800                 if (IS_ERR(state->hpd_gpio[i]))
2801                         continue;
2802
2803                 gpiod_direction_output(state->hpd_gpio[i], 0);
2804
2805                 v4l_info(client, "Handling HPD %u GPIO\n", i);
2806         }
2807
2808         state->timings = cea640x480;
2809         state->format = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
2810
2811         sd = &state->sd;
2812         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2813         snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2814                 id->name, i2c_adapter_id(client->adapter),
2815                 client->addr);
2816         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2817
2818         /*
2819          * Verify that the chip is present. On ADV7604 the RD_INFO register only
2820          * identifies the revision, while on ADV7611 it identifies the model as
2821          * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2822          */
2823         if (state->info->type == ADV7604) {
2824                 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2825                 if (val != 0x68) {
2826                         v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2827                                         client->addr << 1);
2828                         return -ENODEV;
2829                 }
2830         } else {
2831                 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2832                     | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2833                 if (val != 0x2051) {
2834                         v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2835                                         client->addr << 1);
2836                         return -ENODEV;
2837                 }
2838         }
2839
2840         /* control handlers */
2841         hdl = &state->hdl;
2842         v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8);
2843
2844         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2845                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2846         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2847                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2848         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2849                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2850         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2851                         V4L2_CID_HUE, 0, 128, 1, 0);
2852
2853         /* private controls */
2854         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2855                         V4L2_CID_DV_RX_POWER_PRESENT, 0,
2856                         (1 << state->info->num_dv_ports) - 1, 0, 0);
2857         state->rgb_quantization_range_ctrl =
2858                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2859                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2860                         0, V4L2_DV_RGB_RANGE_AUTO);
2861
2862         /* custom controls */
2863         if (adv7604_has_afe(state))
2864                 state->analog_sampling_phase_ctrl =
2865                         v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2866         state->free_run_color_manual_ctrl =
2867                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2868         state->free_run_color_ctrl =
2869                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2870
2871         sd->ctrl_handler = hdl;
2872         if (hdl->error) {
2873                 err = hdl->error;
2874                 goto err_hdl;
2875         }
2876         state->detect_tx_5v_ctrl->is_private = true;
2877         state->rgb_quantization_range_ctrl->is_private = true;
2878         if (adv7604_has_afe(state))
2879                 state->analog_sampling_phase_ctrl->is_private = true;
2880         state->free_run_color_manual_ctrl->is_private = true;
2881         state->free_run_color_ctrl->is_private = true;
2882
2883         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2884                 err = -ENODEV;
2885                 goto err_hdl;
2886         }
2887
2888         for (i = 1; i < ADV7604_PAGE_MAX; ++i) {
2889                 if (!(BIT(i) & state->info->page_mask))
2890                         continue;
2891
2892                 state->i2c_clients[i] =
2893                         adv7604_dummy_client(sd, state->pdata.i2c_addresses[i],
2894                                              0xf2 + i);
2895                 if (state->i2c_clients[i] == NULL) {
2896                         err = -ENOMEM;
2897                         v4l2_err(sd, "failed to create i2c client %u\n", i);
2898                         goto err_i2c;
2899                 }
2900         }
2901
2902         /* work queues */
2903         state->work_queues = create_singlethread_workqueue(client->name);
2904         if (!state->work_queues) {
2905                 v4l2_err(sd, "Could not create work queue\n");
2906                 err = -ENOMEM;
2907                 goto err_i2c;
2908         }
2909
2910         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2911                         adv7604_delayed_work_enable_hotplug);
2912
2913         state->source_pad = state->info->num_dv_ports
2914                           + (state->info->has_afe ? 2 : 0);
2915         for (i = 0; i < state->source_pad; ++i)
2916                 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2917         state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2918
2919         err = media_entity_init(&sd->entity, state->source_pad + 1,
2920                                 state->pads, 0);
2921         if (err)
2922                 goto err_work_queues;
2923
2924         err = adv7604_core_init(sd);
2925         if (err)
2926                 goto err_entity;
2927         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2928                         client->addr << 1, client->adapter->name);
2929
2930         err = v4l2_async_register_subdev(sd);
2931         if (err)
2932                 goto err_entity;
2933
2934         return 0;
2935
2936 err_entity:
2937         media_entity_cleanup(&sd->entity);
2938 err_work_queues:
2939         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2940         destroy_workqueue(state->work_queues);
2941 err_i2c:
2942         adv7604_unregister_clients(state);
2943 err_hdl:
2944         v4l2_ctrl_handler_free(hdl);
2945         return err;
2946 }
2947
2948 /* ----------------------------------------------------------------------- */
2949
2950 static int adv7604_remove(struct i2c_client *client)
2951 {
2952         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2953         struct adv7604_state *state = to_state(sd);
2954
2955         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2956         destroy_workqueue(state->work_queues);
2957         v4l2_async_unregister_subdev(sd);
2958         v4l2_device_unregister_subdev(sd);
2959         media_entity_cleanup(&sd->entity);
2960         adv7604_unregister_clients(to_state(sd));
2961         v4l2_ctrl_handler_free(sd->ctrl_handler);
2962         return 0;
2963 }
2964
2965 /* ----------------------------------------------------------------------- */
2966
2967 static struct i2c_driver adv7604_driver = {
2968         .driver = {
2969                 .owner = THIS_MODULE,
2970                 .name = "adv7604",
2971                 .of_match_table = of_match_ptr(adv7604_of_id),
2972         },
2973         .probe = adv7604_probe,
2974         .remove = adv7604_remove,
2975         .id_table = adv7604_i2c_id,
2976 };
2977
2978 module_i2c_driver(adv7604_driver);