drivers/media/platform/coda/coda-bit.c

   1 /*
   2  * Coda multi-standard codec IP - BIT processor functions
   3  *
   4  * Copyright (C) 2012 Vista Silicon S.L.
   5  *    Javier Martin, <javier.martin@vista-silicon.com>
   6  *    Xavier Duret
   7  * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/irqreturn.h>
  17 #include <linux/kernel.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/reset.h>
  20 #include <linux/videodev2.h>
  21
  22 #include <media/v4l2-common.h>
  23 #include <media/v4l2-ctrls.h>
  24 #include <media/v4l2-fh.h>
  25 #include <media/v4l2-mem2mem.h>
  26 #include <media/videobuf2-core.h>
  27 #include <media/videobuf2-dma-contig.h>
  28 #include <media/videobuf2-vmalloc.h>
  29
  30 #include "coda.h"
  31
  32 #define CODA7_PS_BUF_SIZE       0x28000
  33 #define CODA9_PS_SAVE_SIZE      (512 * 1024)
  34
  35 #define CODA_DEFAULT_GAMMA      4096
  36 #define CODA9_DEFAULT_GAMMA     24576   /* 0.75 * 32768 */
  37
  38 static inline int coda_is_initialized(struct coda_dev *dev)
  39 {
  40         return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  41 }
  42
  43 static inline unsigned long coda_isbusy(struct coda_dev *dev)
  44 {
  45         return coda_read(dev, CODA_REG_BIT_BUSY);
  46 }
  47
  48 static int coda_wait_timeout(struct coda_dev *dev)
  49 {
  50         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  51
  52         while (coda_isbusy(dev)) {
  53                 if (time_after(jiffies, timeout))
  54                         return -ETIMEDOUT;
  55         }
  56         return 0;
  57 }
  58
  59 static void coda_command_async(struct coda_ctx *ctx, int cmd)
  60 {
  61         struct coda_dev *dev = ctx->dev;
  62
  63         if (dev->devtype->product == CODA_960 ||
  64             dev->devtype->product == CODA_7541) {
  65                 /* Restore context related registers to CODA */
  66                 coda_write(dev, ctx->bit_stream_param,
  67                                 CODA_REG_BIT_BIT_STREAM_PARAM);
  68                 coda_write(dev, ctx->frm_dis_flg,
  69                                 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  70                 coda_write(dev, ctx->frame_mem_ctrl,
  71                                 CODA_REG_BIT_FRAME_MEM_CTRL);
  72                 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  73         }
  74
  75         if (dev->devtype->product == CODA_960) {
  76                 coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  77                 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  78         }
  79
  80         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  81
  82         coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  83         coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  84         coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  85
  86         coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  87 }
  88
  89 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  90 {
  91         struct coda_dev *dev = ctx->dev;
  92
  93         coda_command_async(ctx, cmd);
  94         return coda_wait_timeout(dev);
  95 }
  96
  97 int coda_hw_reset(struct coda_ctx *ctx)
  98 {
  99         struct coda_dev *dev = ctx->dev;
 100         unsigned long timeout;
 101         unsigned int idx;
 102         int ret;
 103
 104         if (!dev->rstc)
 105                 return -ENOENT;
 106
 107         idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
 108
 109         if (dev->devtype->product == CODA_960) {
 110                 timeout = jiffies + msecs_to_jiffies(100);
 111                 coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
 112                 while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
 113                         if (time_after(jiffies, timeout))
 114                                 return -ETIME;
 115                         cpu_relax();
 116                 }
 117         }
 118
 119         ret = reset_control_reset(dev->rstc);
 120         if (ret < 0)
 121                 return ret;
 122
 123         if (dev->devtype->product == CODA_960)
 124                 coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
 125         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 126         coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
 127         ret = coda_wait_timeout(dev);
 128         coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
 129
 130         return ret;
 131 }
 132
 133 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
 134 {
 135         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 136         struct coda_dev *dev = ctx->dev;
 137         u32 rd_ptr;
 138
 139         rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 140         kfifo->out = (kfifo->in & ~kfifo->mask) |
 141                       (rd_ptr - ctx->bitstream.paddr);
 142         if (kfifo->out > kfifo->in)
 143                 kfifo->out -= kfifo->mask + 1;
 144 }
 145
 146 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
 147 {
 148         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 149         struct coda_dev *dev = ctx->dev;
 150         u32 rd_ptr, wr_ptr;
 151
 152         rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
 153         coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 154         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 155         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 156 }
 157
 158 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
 159 {
 160         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 161         struct coda_dev *dev = ctx->dev;
 162         u32 wr_ptr;
 163
 164         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 165         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 166 }
 167
 168 static int coda_bitstream_queue(struct coda_ctx *ctx, struct vb2_buffer *src_buf)
 169 {
 170         u32 src_size = vb2_get_plane_payload(src_buf, 0);
 171         u32 n;
 172
 173         n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0), src_size);
 174         if (n < src_size)
 175                 return -ENOSPC;
 176
 177         dma_sync_single_for_device(&ctx->dev->plat_dev->dev, ctx->bitstream.paddr,
 178                                    ctx->bitstream.size, DMA_TO_DEVICE);
 179
 180         src_buf->v4l2_buf.sequence = ctx->qsequence++;
 181
 182         return 0;
 183 }
 184
 185 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
 186                                      struct vb2_buffer *src_buf)
 187 {
 188         int ret;
 189
 190         if (coda_get_bitstream_payload(ctx) +
 191             vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
 192                 return false;
 193
 194         if (vb2_plane_vaddr(src_buf, 0) == NULL) {
 195                 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
 196                 return true;
 197         }
 198
 199         ret = coda_bitstream_queue(ctx, src_buf);
 200         if (ret < 0) {
 201                 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
 202                 return false;
 203         }
 204         /* Sync read pointer to device */
 205         if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
 206                 coda_kfifo_sync_to_device_write(ctx);
 207
 208         ctx->hold = false;
 209
 210         return true;
 211 }
 212
 213 void coda_fill_bitstream(struct coda_ctx *ctx)
 214 {
 215         struct vb2_buffer *src_buf;
 216         struct coda_timestamp *ts;
 217
 218         while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
 219                 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
 220
 221                 if (coda_bitstream_try_queue(ctx, src_buf)) {
 222                         /*
 223                          * Source buffer is queued in the bitstream ringbuffer;
 224                          * queue the timestamp and mark source buffer as done
 225                          */
 226                         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
 227
 228                         ts = kmalloc(sizeof(*ts), GFP_KERNEL);
 229                         if (ts) {
 230                                 ts->sequence = src_buf->v4l2_buf.sequence;
 231                                 ts->timecode = src_buf->v4l2_buf.timecode;
 232                                 ts->timestamp = src_buf->v4l2_buf.timestamp;
 233                                 list_add_tail(&ts->list, &ctx->timestamp_list);
 234                         }
 235
 236                         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
 237                 } else {
 238                         break;
 239                 }
 240         }
 241 }
 242
 243 void coda_bit_stream_end_flag(struct coda_ctx *ctx)
 244 {
 245         struct coda_dev *dev = ctx->dev;
 246
 247         ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
 248
 249         if ((dev->devtype->product == CODA_960) &&
 250             coda_isbusy(dev) &&
 251             (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
 252                 /* If this context is currently running, update the hardware flag */
 253                 coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM);
 254         }
 255 }
 256
 257 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
 258 {
 259         struct coda_dev *dev = ctx->dev;
 260         u32 *p = ctx->parabuf.vaddr;
 261
 262         if (dev->devtype->product == CODA_DX6)
 263                 p[index] = value;
 264         else
 265                 p[index ^ 1] = value;
 266 }
 267
 268 static void coda_free_framebuffers(struct coda_ctx *ctx)
 269 {
 270         int i;
 271
 272         for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
 273                 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
 274 }
 275
 276 static int coda_alloc_framebuffers(struct coda_ctx *ctx,
 277                                    struct coda_q_data *q_data, u32 fourcc)
 278 {
 279         struct coda_dev *dev = ctx->dev;
 280         int width, height;
 281         dma_addr_t paddr;
 282         int ysize;
 283         int ret;
 284         int i;
 285
 286         if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
 287              ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
 288                 width = round_up(q_data->width, 16);
 289                 height = round_up(q_data->height, 16);
 290         } else {
 291                 width = round_up(q_data->width, 8);
 292                 height = q_data->height;
 293         }
 294         ysize = width * height;
 295
 296         /* Allocate frame buffers */
 297         for (i = 0; i < ctx->num_internal_frames; i++) {
 298                 size_t size;
 299                 char *name;
 300
 301                 size = ysize + ysize / 2;
 302                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
 303                     dev->devtype->product != CODA_DX6)
 304                         size += ysize / 4;
 305                 name = kasprintf(GFP_KERNEL, "fb%d", i);
 306                 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
 307                                              size, name);
 308                 kfree(name);
 309                 if (ret < 0) {
 310                         coda_free_framebuffers(ctx);
 311                         return ret;
 312                 }
 313         }
 314
 315         /* Register frame buffers in the parameter buffer */
 316         for (i = 0; i < ctx->num_internal_frames; i++) {
 317                 paddr = ctx->internal_frames[i].paddr;
 318                 coda_parabuf_write(ctx, i * 3 + 0, paddr); /* Y */
 319                 coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize); /* Cb */
 320                 coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize/4); /* Cr */
 321
 322                 /* mvcol buffer for h.264 */
 323                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
 324                     dev->devtype->product != CODA_DX6)
 325                         coda_parabuf_write(ctx, 96 + i,
 326                                            ctx->internal_frames[i].paddr +
 327                                            ysize + ysize/4 + ysize/4);
 328         }
 329
 330         /* mvcol buffer for mpeg4 */
 331         if ((dev->devtype->product != CODA_DX6) &&
 332             (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
 333                 coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
 334                                             ysize + ysize/4 + ysize/4);
 335
 336         return 0;
 337 }
 338
 339 static void coda_free_context_buffers(struct coda_ctx *ctx)
 340 {
 341         struct coda_dev *dev = ctx->dev;
 342
 343         coda_free_aux_buf(dev, &ctx->slicebuf);
 344         coda_free_aux_buf(dev, &ctx->psbuf);
 345         if (dev->devtype->product != CODA_DX6)
 346                 coda_free_aux_buf(dev, &ctx->workbuf);
 347 }
 348
 349 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
 350                                       struct coda_q_data *q_data)
 351 {
 352         struct coda_dev *dev = ctx->dev;
 353         size_t size;
 354         int ret;
 355
 356         if (dev->devtype->product == CODA_DX6)
 357                 return 0;
 358
 359         if (ctx->psbuf.vaddr) {
 360                 v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
 361                 return -EBUSY;
 362         }
 363         if (ctx->slicebuf.vaddr) {
 364                 v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
 365                 return -EBUSY;
 366         }
 367         if (ctx->workbuf.vaddr) {
 368                 v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
 369                 ret = -EBUSY;
 370                 return -ENOMEM;
 371         }
 372
 373         if (q_data->fourcc == V4L2_PIX_FMT_H264) {
 374                 /* worst case slice size */
 375                 size = (DIV_ROUND_UP(q_data->width, 16) *
 376                         DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
 377                 ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size, "slicebuf");
 378                 if (ret < 0) {
 379                         v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte slice buffer",
 380                                  ctx->slicebuf.size);
 381                         return ret;
 382                 }
 383         }
 384
 385         if (dev->devtype->product == CODA_7541) {
 386                 ret = coda_alloc_context_buf(ctx, &ctx->psbuf, CODA7_PS_BUF_SIZE, "psbuf");
 387                 if (ret < 0) {
 388                         v4l2_err(&dev->v4l2_dev, "failed to allocate psmem buffer");
 389                         goto err;
 390                 }
 391         }
 392
 393         size = dev->devtype->workbuf_size;
 394         if (dev->devtype->product == CODA_960 &&
 395             q_data->fourcc == V4L2_PIX_FMT_H264)
 396                 size += CODA9_PS_SAVE_SIZE;
 397         ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
 398         if (ret < 0) {
 399                 v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte context buffer",
 400                          ctx->workbuf.size);
 401                 goto err;
 402         }
 403
 404         return 0;
 405
 406 err:
 407         coda_free_context_buffers(ctx);
 408         return ret;
 409 }
 410
 411 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
 412                               int header_code, u8 *header, int *size)
 413 {
 414         struct coda_dev *dev = ctx->dev;
 415         size_t bufsize;
 416         int ret;
 417         int i;
 418
 419         if (dev->devtype->product == CODA_960)
 420                 memset(vb2_plane_vaddr(buf, 0), 0, 64);
 421
 422         coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
 423                    CODA_CMD_ENC_HEADER_BB_START);
 424         bufsize = vb2_plane_size(buf, 0);
 425         if (dev->devtype->product == CODA_960)
 426                 bufsize /= 1024;
 427         coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
 428         coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
 429         ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
 430         if (ret < 0) {
 431                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
 432                 return ret;
 433         }
 434
 435         if (dev->devtype->product == CODA_960) {
 436                 for (i = 63; i > 0; i--)
 437                         if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
 438                                 break;
 439                 *size = i + 1;
 440         } else {
 441                 *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
 442                         coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
 443         }
 444         memcpy(header, vb2_plane_vaddr(buf, 0), *size);
 445
 446         return 0;
 447 }
 448
 449 static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
 450 {
 451         phys_addr_t ret;
 452
 453         size = round_up(size, 1024);
 454         if (size > iram->remaining)
 455                 return 0;
 456         iram->remaining -= size;
 457
 458         ret = iram->next_paddr;
 459         iram->next_paddr += size;
 460
 461         return ret;
 462 }
 463
 464 static void coda_setup_iram(struct coda_ctx *ctx)
 465 {
 466         struct coda_iram_info *iram_info = &ctx->iram_info;
 467         struct coda_dev *dev = ctx->dev;
 468         int mb_width;
 469         int dbk_bits;
 470         int bit_bits;
 471         int ip_bits;
 472
 473         memset(iram_info, 0, sizeof(*iram_info));
 474         iram_info->next_paddr = dev->iram.paddr;
 475         iram_info->remaining = dev->iram.size;
 476
 477         if (!dev->iram.vaddr)
 478                 return;
 479
 480         switch (dev->devtype->product) {
 481         case CODA_7541:
 482                 dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
 483                 bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
 484                 ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
 485                 break;
 486         case CODA_960:
 487                 dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
 488                 bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
 489                 ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
 490                 break;
 491         default: /* CODA_DX6 */
 492                 return;
 493         }
 494
 495         if (ctx->inst_type == CODA_INST_ENCODER) {
 496                 struct coda_q_data *q_data_src;
 497
 498                 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 499                 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
 500
 501                 /* Prioritize in case IRAM is too small for everything */
 502                 if (dev->devtype->product == CODA_7541) {
 503                         iram_info->search_ram_size = round_up(mb_width * 16 *
 504                                                               36 + 2048, 1024);
 505                         iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
 506                                                         iram_info->search_ram_size);
 507                         if (!iram_info->search_ram_paddr) {
 508                                 pr_err("IRAM is smaller than the search ram size\n");
 509                                 goto out;
 510                         }
 511                         iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
 512                                                    CODA7_USE_ME_ENABLE;
 513                 }
 514
 515                 /* Only H.264BP and H.263P3 are considered */
 516                 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, 64 * mb_width);
 517                 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, 64 * mb_width);
 518                 if (!iram_info->buf_dbk_c_use)
 519                         goto out;
 520                 iram_info->axi_sram_use |= dbk_bits;
 521
 522                 iram_info->buf_bit_use = coda_iram_alloc(iram_info, 128 * mb_width);
 523                 if (!iram_info->buf_bit_use)
 524                         goto out;
 525                 iram_info->axi_sram_use |= bit_bits;
 526
 527                 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, 128 * mb_width);
 528                 if (!iram_info->buf_ip_ac_dc_use)
 529                         goto out;
 530                 iram_info->axi_sram_use |= ip_bits;
 531
 532                 /* OVL and BTP disabled for encoder */
 533         } else if (ctx->inst_type == CODA_INST_DECODER) {
 534                 struct coda_q_data *q_data_dst;
 535
 536                 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 537                 mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
 538
 539                 iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, 128 * mb_width);
 540                 iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, 128 * mb_width);
 541                 if (!iram_info->buf_dbk_c_use)
 542                         goto out;
 543                 iram_info->axi_sram_use |= dbk_bits;
 544
 545                 iram_info->buf_bit_use = coda_iram_alloc(iram_info, 128 * mb_width);
 546                 if (!iram_info->buf_bit_use)
 547                         goto out;
 548                 iram_info->axi_sram_use |= bit_bits;
 549
 550                 iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, 128 * mb_width);
 551                 if (!iram_info->buf_ip_ac_dc_use)
 552                         goto out;
 553                 iram_info->axi_sram_use |= ip_bits;
 554
 555                 /* OVL and BTP unused as there is no VC1 support yet */
 556         }
 557
 558 out:
 559         if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
 560                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 561                          "IRAM smaller than needed\n");
 562
 563         if (dev->devtype->product == CODA_7541) {
 564                 /* TODO - Enabling these causes picture errors on CODA7541 */
 565                 if (ctx->inst_type == CODA_INST_DECODER) {
 566                         /* fw 1.4.50 */
 567                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
 568                                                      CODA7_USE_IP_ENABLE);
 569                 } else {
 570                         /* fw 13.4.29 */
 571                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
 572                                                      CODA7_USE_HOST_DBK_ENABLE |
 573                                                      CODA7_USE_IP_ENABLE |
 574                                                      CODA7_USE_DBK_ENABLE);
 575                 }
 576         }
 577 }
 578
 579 static u32 coda_supported_firmwares[] = {
 580         CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
 581         CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
 582         CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
 583 };
 584
 585 static bool coda_firmware_supported(u32 vernum)
 586 {
 587         int i;
 588
 589         for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
 590                 if (vernum == coda_supported_firmwares[i])
 591                         return true;
 592         return false;
 593 }
 594
 595 int coda_check_firmware(struct coda_dev *dev)
 596 {
 597         u16 product, major, minor, release;
 598         u32 data;
 599         int ret;
 600
 601         ret = clk_prepare_enable(dev->clk_per);
 602         if (ret)
 603                 goto err_clk_per;
 604
 605         ret = clk_prepare_enable(dev->clk_ahb);
 606         if (ret)
 607                 goto err_clk_ahb;
 608
 609         coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
 610         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 611         coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
 612         coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
 613         coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
 614         if (coda_wait_timeout(dev)) {
 615                 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
 616                 ret = -EIO;
 617                 goto err_run_cmd;
 618         }
 619
 620         if (dev->devtype->product == CODA_960) {
 621                 data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
 622                 v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
 623                           data);
 624         }
 625
 626         /* Check we are compatible with the loaded firmware */
 627         data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
 628         product = CODA_FIRMWARE_PRODUCT(data);
 629         major = CODA_FIRMWARE_MAJOR(data);
 630         minor = CODA_FIRMWARE_MINOR(data);
 631         release = CODA_FIRMWARE_RELEASE(data);
 632
 633         clk_disable_unprepare(dev->clk_per);
 634         clk_disable_unprepare(dev->clk_ahb);
 635
 636         if (product != dev->devtype->product) {
 637                 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
 638                          " Version: %u.%u.%u\n",
 639                          coda_product_name(dev->devtype->product),
 640                          coda_product_name(product), major, minor, release);
 641                 return -EINVAL;
 642         }
 643
 644         v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
 645                   coda_product_name(product));
 646
 647         if (coda_firmware_supported(data)) {
 648                 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
 649                           major, minor, release);
 650         } else {
 651                 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
 652                           "%u.%u.%u\n", major, minor, release);
 653         }
 654
 655         return 0;
 656
 657 err_run_cmd:
 658         clk_disable_unprepare(dev->clk_ahb);
 659 err_clk_ahb:
 660         clk_disable_unprepare(dev->clk_per);
 661 err_clk_per:
 662         return ret;
 663 }
 664
 665 /*
 666  * Encoder context operations
 667  */
 668
 669 static int coda_start_encoding(struct coda_ctx *ctx)
 670 {
 671         struct coda_dev *dev = ctx->dev;
 672         struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
 673         struct coda_q_data *q_data_src, *q_data_dst;
 674         u32 bitstream_buf, bitstream_size;
 675         struct vb2_buffer *buf;
 676         int gamma, ret, value;
 677         u32 dst_fourcc;
 678
 679         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 680         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 681         dst_fourcc = q_data_dst->fourcc;
 682
 683         /* Allocate per-instance buffers */
 684         ret = coda_alloc_context_buffers(ctx, q_data_src);
 685         if (ret < 0)
 686                 return ret;
 687
 688         buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 689         bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
 690         bitstream_size = q_data_dst->sizeimage;
 691
 692         if (!coda_is_initialized(dev)) {
 693                 v4l2_err(v4l2_dev, "coda is not initialized.\n");
 694                 return -EFAULT;
 695         }
 696
 697         mutex_lock(&dev->coda_mutex);
 698
 699         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
 700         coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 701         coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 702         switch (dev->devtype->product) {
 703         case CODA_DX6:
 704                 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
 705                         CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
 706                 break;
 707         case CODA_960:
 708                 coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
 709                 /* fallthrough */
 710         case CODA_7541:
 711                 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
 712                         CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
 713                 break;
 714         }
 715
 716         value = coda_read(dev, CODA_REG_BIT_FRAME_MEM_CTRL);
 717         value &= ~(1 << 2 | 0x7 << 9);
 718         ctx->frame_mem_ctrl = value;
 719         coda_write(dev, value, CODA_REG_BIT_FRAME_MEM_CTRL);
 720
 721         if (dev->devtype->product == CODA_DX6) {
 722                 /* Configure the coda */
 723                 coda_write(dev, dev->iram.paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
 724         }
 725
 726         /* Could set rotation here if needed */
 727         switch (dev->devtype->product) {
 728         case CODA_DX6:
 729                 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
 730                 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
 731                 break;
 732         case CODA_7541:
 733                 if (dst_fourcc == V4L2_PIX_FMT_H264) {
 734                         value = (round_up(q_data_src->width, 16) &
 735                                  CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
 736                         value |= (round_up(q_data_src->height, 16) &
 737                                   CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
 738                         break;
 739                 }
 740                 /* fallthrough */
 741         case CODA_960:
 742                 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
 743                 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
 744         }
 745         coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
 746         coda_write(dev, ctx->params.framerate,
 747                    CODA_CMD_ENC_SEQ_SRC_F_RATE);
 748
 749         ctx->params.codec_mode = ctx->codec->mode;
 750         switch (dst_fourcc) {
 751         case V4L2_PIX_FMT_MPEG4:
 752                 if (dev->devtype->product == CODA_960)
 753                         coda_write(dev, CODA9_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
 754                 else
 755                         coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
 756                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
 757                 break;
 758         case V4L2_PIX_FMT_H264:
 759                 if (dev->devtype->product == CODA_960)
 760                         coda_write(dev, CODA9_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
 761                 else
 762                         coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
 763                 if (ctx->params.h264_deblk_enabled) {
 764                         value = ((ctx->params.h264_deblk_alpha &
 765                                   CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
 766                                  CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
 767                                 ((ctx->params.h264_deblk_beta &
 768                                   CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
 769                                  CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
 770                 } else {
 771                         value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
 772                 }
 773                 coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
 774                 break;
 775         default:
 776                 v4l2_err(v4l2_dev,
 777                          "dst format (0x%08x) invalid.\n", dst_fourcc);
 778                 ret = -EINVAL;
 779                 goto out;
 780         }
 781
 782         switch (ctx->params.slice_mode) {
 783         case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
 784                 value = 0;
 785                 break;
 786         case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
 787                 value  = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
 788                 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
 789                 value |=  1 & CODA_SLICING_MODE_MASK;
 790                 break;
 791         case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
 792                 value  = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
 793                 value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
 794                 value |=  1 & CODA_SLICING_MODE_MASK;
 795                 break;
 796         }
 797         coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
 798         value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
 799         coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
 800
 801         if (ctx->params.bitrate) {
 802                 /* Rate control enabled */
 803                 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
 804                 value |=  1 & CODA_RATECONTROL_ENABLE_MASK;
 805                 if (dev->devtype->product == CODA_960)
 806                         value |= BIT(31); /* disable autoskip */
 807         } else {
 808                 value = 0;
 809         }
 810         coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
 811
 812         coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
 813         coda_write(dev, ctx->params.intra_refresh,
 814                    CODA_CMD_ENC_SEQ_INTRA_REFRESH);
 815
 816         coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
 817         coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
 818
 819
 820         value = 0;
 821         if (dev->devtype->product == CODA_960)
 822                 gamma = CODA9_DEFAULT_GAMMA;
 823         else
 824                 gamma = CODA_DEFAULT_GAMMA;
 825         if (gamma > 0) {
 826                 coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
 827                            CODA_CMD_ENC_SEQ_RC_GAMMA);
 828         }
 829
 830         if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
 831                 coda_write(dev,
 832                            ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
 833                            ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
 834                            CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
 835         }
 836         if (dev->devtype->product == CODA_960) {
 837                 if (ctx->params.h264_max_qp)
 838                         value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
 839                 if (CODA_DEFAULT_GAMMA > 0)
 840                         value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
 841         } else {
 842                 if (CODA_DEFAULT_GAMMA > 0) {
 843                         if (dev->devtype->product == CODA_DX6)
 844                                 value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
 845                         else
 846                                 value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
 847                 }
 848                 if (ctx->params.h264_min_qp)
 849                         value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
 850                 if (ctx->params.h264_max_qp)
 851                         value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
 852         }
 853         coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
 854
 855         coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
 856
 857         coda_setup_iram(ctx);
 858
 859         if (dst_fourcc == V4L2_PIX_FMT_H264) {
 860                 switch (dev->devtype->product) {
 861                 case CODA_DX6:
 862                         value = FMO_SLICE_SAVE_BUF_SIZE << 7;
 863                         coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
 864                         break;
 865                 case CODA_7541:
 866                         coda_write(dev, ctx->iram_info.search_ram_paddr,
 867                                         CODA7_CMD_ENC_SEQ_SEARCH_BASE);
 868                         coda_write(dev, ctx->iram_info.search_ram_size,
 869                                         CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
 870                         break;
 871                 case CODA_960:
 872                         coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
 873                         coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
 874                 }
 875         }
 876
 877         ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
 878         if (ret < 0) {
 879                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
 880                 goto out;
 881         }
 882
 883         if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
 884                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
 885                 ret = -EFAULT;
 886                 goto out;
 887         }
 888
 889         if (dev->devtype->product == CODA_960)
 890                 ctx->num_internal_frames = 4;
 891         else
 892                 ctx->num_internal_frames = 2;
 893         ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
 894         if (ret < 0) {
 895                 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
 896                 goto out;
 897         }
 898
 899         coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
 900         coda_write(dev, q_data_src->bytesperline,
 901                         CODA_CMD_SET_FRAME_BUF_STRIDE);
 902         if (dev->devtype->product == CODA_7541) {
 903                 coda_write(dev, q_data_src->bytesperline,
 904                                 CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
 905         }
 906         if (dev->devtype->product != CODA_DX6) {
 907                 coda_write(dev, ctx->iram_info.buf_bit_use,
 908                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
 909                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
 910                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
 911                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
 912                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
 913                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
 914                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
 915                 coda_write(dev, ctx->iram_info.buf_ovl_use,
 916                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
 917                 if (dev->devtype->product == CODA_960) {
 918                         coda_write(dev, ctx->iram_info.buf_btp_use,
 919                                         CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
 920
 921                         /* FIXME */
 922                         coda_write(dev, ctx->internal_frames[2].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_A);
 923                         coda_write(dev, ctx->internal_frames[3].paddr, CODA9_CMD_SET_FRAME_SUBSAMP_B);
 924                 }
 925         }
 926
 927         ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
 928         if (ret < 0) {
 929                 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
 930                 goto out;
 931         }
 932
 933         /* Save stream headers */
 934         buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
 935         switch (dst_fourcc) {
 936         case V4L2_PIX_FMT_H264:
 937                 /*
 938                  * Get SPS in the first frame and copy it to an
 939                  * intermediate buffer.
 940                  */
 941                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
 942                                          &ctx->vpu_header[0][0],
 943                                          &ctx->vpu_header_size[0]);
 944                 if (ret < 0)
 945                         goto out;
 946
 947                 /*
 948                  * Get PPS in the first frame and copy it to an
 949                  * intermediate buffer.
 950                  */
 951                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
 952                                          &ctx->vpu_header[1][0],
 953                                          &ctx->vpu_header_size[1]);
 954                 if (ret < 0)
 955                         goto out;
 956
 957                 /*
 958                  * Length of H.264 headers is variable and thus it might not be
 959                  * aligned for the coda to append the encoded frame. In that is
 960                  * the case a filler NAL must be added to header 2.
 961                  */
 962                 ctx->vpu_header_size[2] = coda_h264_padding(
 963                                         (ctx->vpu_header_size[0] +
 964                                          ctx->vpu_header_size[1]),
 965                                          ctx->vpu_header[2]);
 966                 break;
 967         case V4L2_PIX_FMT_MPEG4:
 968                 /*
 969                  * Get VOS in the first frame and copy it to an
 970                  * intermediate buffer
 971                  */
 972                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
 973                                          &ctx->vpu_header[0][0],
 974                                          &ctx->vpu_header_size[0]);
 975                 if (ret < 0)
 976                         goto out;
 977
 978                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
 979                                          &ctx->vpu_header[1][0],
 980                                          &ctx->vpu_header_size[1]);
 981                 if (ret < 0)
 982                         goto out;
 983
 984                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
 985                                          &ctx->vpu_header[2][0],
 986                                          &ctx->vpu_header_size[2]);
 987                 if (ret < 0)
 988                         goto out;
 989                 break;
 990         default:
 991                 /* No more formats need to save headers at the moment */
 992                 break;
 993         }
 994
 995 out:
 996         mutex_unlock(&dev->coda_mutex);
 997         return ret;
 998 }
 999
1000 static int coda_prepare_encode(struct coda_ctx *ctx)
1001 {
1002         struct coda_q_data *q_data_src, *q_data_dst;
1003         struct vb2_buffer *src_buf, *dst_buf;
1004         struct coda_dev *dev = ctx->dev;
1005         int force_ipicture;
1006         int quant_param = 0;
1007         u32 picture_y, picture_cb, picture_cr;
1008         u32 pic_stream_buffer_addr, pic_stream_buffer_size;
1009         u32 dst_fourcc;
1010
1011         src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1012         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1013         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1014         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1015         dst_fourcc = q_data_dst->fourcc;
1016
1017         src_buf->v4l2_buf.sequence = ctx->osequence;
1018         dst_buf->v4l2_buf.sequence = ctx->osequence;
1019         ctx->osequence++;
1020
1021         /*
1022          * Workaround coda firmware BUG that only marks the first
1023          * frame as IDR. This is a problem for some decoders that can't
1024          * recover when a frame is lost.
1025          */
1026         if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
1027                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1028                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1029         } else {
1030                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1031                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1032         }
1033
1034         if (dev->devtype->product == CODA_960)
1035                 coda_set_gdi_regs(ctx);
1036
1037         /*
1038          * Copy headers at the beginning of the first frame for H.264 only.
1039          * In MPEG4 they are already copied by the coda.
1040          */
1041         if (src_buf->v4l2_buf.sequence == 0) {
1042                 pic_stream_buffer_addr =
1043                         vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
1044                         ctx->vpu_header_size[0] +
1045                         ctx->vpu_header_size[1] +
1046                         ctx->vpu_header_size[2];
1047                 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
1048                         ctx->vpu_header_size[0] -
1049                         ctx->vpu_header_size[1] -
1050                         ctx->vpu_header_size[2];
1051                 memcpy(vb2_plane_vaddr(dst_buf, 0),
1052                        &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
1053                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
1054                        &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
1055                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
1056                         ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
1057                         ctx->vpu_header_size[2]);
1058         } else {
1059                 pic_stream_buffer_addr =
1060                         vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1061                 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
1062         }
1063
1064         if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1065                 force_ipicture = 1;
1066                 switch (dst_fourcc) {
1067                 case V4L2_PIX_FMT_H264:
1068                         quant_param = ctx->params.h264_intra_qp;
1069                         break;
1070                 case V4L2_PIX_FMT_MPEG4:
1071                         quant_param = ctx->params.mpeg4_intra_qp;
1072                         break;
1073                 default:
1074                         v4l2_warn(&ctx->dev->v4l2_dev,
1075                                 "cannot set intra qp, fmt not supported\n");
1076                         break;
1077                 }
1078         } else {
1079                 force_ipicture = 0;
1080                 switch (dst_fourcc) {
1081                 case V4L2_PIX_FMT_H264:
1082                         quant_param = ctx->params.h264_inter_qp;
1083                         break;
1084                 case V4L2_PIX_FMT_MPEG4:
1085                         quant_param = ctx->params.mpeg4_inter_qp;
1086                         break;
1087                 default:
1088                         v4l2_warn(&ctx->dev->v4l2_dev,
1089                                 "cannot set inter qp, fmt not supported\n");
1090                         break;
1091                 }
1092         }
1093
1094         /* submit */
1095         coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
1096         coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
1097
1098
1099         picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
1100         switch (q_data_src->fourcc) {
1101         case V4L2_PIX_FMT_YVU420:
1102                 /* Switch Cb and Cr for YVU420 format */
1103                 picture_cr = picture_y + q_data_src->bytesperline *
1104                                 q_data_src->height;
1105                 picture_cb = picture_cr + q_data_src->bytesperline / 2 *
1106                                 q_data_src->height / 2;
1107                 break;
1108         case V4L2_PIX_FMT_YUV420:
1109         default:
1110                 picture_cb = picture_y + q_data_src->bytesperline *
1111                                 q_data_src->height;
1112                 picture_cr = picture_cb + q_data_src->bytesperline / 2 *
1113                                 q_data_src->height / 2;
1114                 break;
1115         }
1116
1117         if (dev->devtype->product == CODA_960) {
1118                 coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
1119                 coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
1120                 coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
1121
1122                 coda_write(dev, picture_y, CODA9_CMD_ENC_PIC_SRC_ADDR_Y);
1123                 coda_write(dev, picture_cb, CODA9_CMD_ENC_PIC_SRC_ADDR_CB);
1124                 coda_write(dev, picture_cr, CODA9_CMD_ENC_PIC_SRC_ADDR_CR);
1125         } else {
1126                 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
1127                 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
1128                 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
1129         }
1130         coda_write(dev, force_ipicture << 1 & 0x2,
1131                    CODA_CMD_ENC_PIC_OPTION);
1132
1133         coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
1134         coda_write(dev, pic_stream_buffer_size / 1024,
1135                    CODA_CMD_ENC_PIC_BB_SIZE);
1136
1137         if (!ctx->streamon_out) {
1138                 /* After streamoff on the output side, set the stream end flag */
1139                 ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
1140                 coda_write(dev, ctx->bit_stream_param, CODA_REG_BIT_BIT_STREAM_PARAM);
1141         }
1142
1143         if (dev->devtype->product != CODA_DX6)
1144                 coda_write(dev, ctx->iram_info.axi_sram_use,
1145                                 CODA7_REG_BIT_AXI_SRAM_USE);
1146
1147         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1148
1149         return 0;
1150 }
1151
1152 static void coda_finish_encode(struct coda_ctx *ctx)
1153 {
1154         struct vb2_buffer *src_buf, *dst_buf;
1155         struct coda_dev *dev = ctx->dev;
1156         u32 wr_ptr, start_ptr;
1157
1158         src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1159         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1160
1161         /* Get results from the coda */
1162         start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1163         wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1164
1165         /* Calculate bytesused field */
1166         if (dst_buf->v4l2_buf.sequence == 0) {
1167                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
1168                                         ctx->vpu_header_size[0] +
1169                                         ctx->vpu_header_size[1] +
1170                                         ctx->vpu_header_size[2]);
1171         } else {
1172                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
1173         }
1174
1175         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1176                  wr_ptr - start_ptr);
1177
1178         coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1179         coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1180
1181         if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
1182                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1183                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1184         } else {
1185                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1186                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1187         }
1188
1189         dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
1190         dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1191         dst_buf->v4l2_buf.flags |=
1192                 src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1193         dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
1194
1195         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1196
1197         dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1198         v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1199
1200         ctx->gopcounter--;
1201         if (ctx->gopcounter < 0)
1202                 ctx->gopcounter = ctx->params.gop_size - 1;
1203
1204         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1205                 "job finished: encoding frame (%d) (%s)\n",
1206                 dst_buf->v4l2_buf.sequence,
1207                 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1208                 "KEYFRAME" : "PFRAME");
1209 }
1210
1211 static void coda_seq_end_work(struct work_struct *work)
1212 {
1213         struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
1214         struct coda_dev *dev = ctx->dev;
1215
1216         mutex_lock(&ctx->buffer_mutex);
1217         mutex_lock(&dev->coda_mutex);
1218
1219         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1220                  "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx, __func__);
1221         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1222                 v4l2_err(&dev->v4l2_dev,
1223                          "CODA_COMMAND_SEQ_END failed\n");
1224         }
1225
1226         kfifo_init(&ctx->bitstream_fifo,
1227                 ctx->bitstream.vaddr, ctx->bitstream.size);
1228
1229         coda_free_framebuffers(ctx);
1230         coda_free_context_buffers(ctx);
1231
1232         mutex_unlock(&dev->coda_mutex);
1233         mutex_unlock(&ctx->buffer_mutex);
1234 }
1235
1236 static void coda_bit_release(struct coda_ctx *ctx)
1237 {
1238         coda_free_framebuffers(ctx);
1239         coda_free_context_buffers(ctx);
1240 }
1241
1242 const struct coda_context_ops coda_bit_encode_ops = {
1243         .queue_init = coda_encoder_queue_init,
1244         .start_streaming = coda_start_encoding,
1245         .prepare_run = coda_prepare_encode,
1246         .finish_run = coda_finish_encode,
1247         .seq_end_work = coda_seq_end_work,
1248         .release = coda_bit_release,
1249 };
1250
1251 /*
1252  * Decoder context operations
1253  */
1254
1255 static int __coda_start_decoding(struct coda_ctx *ctx)
1256 {
1257         struct coda_q_data *q_data_src, *q_data_dst;
1258         u32 bitstream_buf, bitstream_size;
1259         struct coda_dev *dev = ctx->dev;
1260         int width, height;
1261         u32 src_fourcc;
1262         u32 val;
1263         int ret;
1264
1265         /* Start decoding */
1266         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1267         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1268         bitstream_buf = ctx->bitstream.paddr;
1269         bitstream_size = ctx->bitstream.size;
1270         src_fourcc = q_data_src->fourcc;
1271
1272         /* Allocate per-instance buffers */
1273         ret = coda_alloc_context_buffers(ctx, q_data_src);
1274         if (ret < 0)
1275                 return ret;
1276
1277         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1278
1279         /* Update coda bitstream read and write pointers from kfifo */
1280         coda_kfifo_sync_to_device_full(ctx);
1281
1282         ctx->display_idx = -1;
1283         ctx->frm_dis_flg = 0;
1284         coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1285
1286         coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
1287                         CODA_REG_BIT_BIT_STREAM_PARAM);
1288
1289         coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
1290         coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
1291         val = 0;
1292         if ((dev->devtype->product == CODA_7541) ||
1293             (dev->devtype->product == CODA_960))
1294                 val |= CODA_REORDER_ENABLE;
1295         coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
1296
1297         ctx->params.codec_mode = ctx->codec->mode;
1298         if (dev->devtype->product == CODA_960 &&
1299             src_fourcc == V4L2_PIX_FMT_MPEG4)
1300                 ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
1301         else
1302                 ctx->params.codec_mode_aux = 0;
1303         if (src_fourcc == V4L2_PIX_FMT_H264) {
1304                 if (dev->devtype->product == CODA_7541) {
1305                         coda_write(dev, ctx->psbuf.paddr,
1306                                         CODA_CMD_DEC_SEQ_PS_BB_START);
1307                         coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
1308                                         CODA_CMD_DEC_SEQ_PS_BB_SIZE);
1309                 }
1310                 if (dev->devtype->product == CODA_960) {
1311                         coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
1312                         coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
1313                 }
1314         }
1315         if (dev->devtype->product != CODA_960)
1316                 coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
1317
1318         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1319                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1320                 coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1321                 return -ETIMEDOUT;
1322         }
1323
1324         /* Update kfifo out pointer from coda bitstream read pointer */
1325         coda_kfifo_sync_from_device(ctx);
1326
1327         coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
1328
1329         if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
1330                 v4l2_err(&dev->v4l2_dev,
1331                         "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
1332                         coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
1333                 return -EAGAIN;
1334         }
1335
1336         val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
1337         if (dev->devtype->product == CODA_DX6) {
1338                 width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
1339                 height = val & CODADX6_PICHEIGHT_MASK;
1340         } else {
1341                 width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
1342                 height = val & CODA7_PICHEIGHT_MASK;
1343         }
1344
1345         if (width > q_data_dst->width || height > q_data_dst->height) {
1346                 v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
1347                          width, height, q_data_dst->width, q_data_dst->height);
1348                 return -EINVAL;
1349         }
1350
1351         width = round_up(width, 16);
1352         height = round_up(height, 16);
1353
1354         v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
1355                  __func__, ctx->idx, width, height);
1356
1357         ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
1358         if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
1359                 v4l2_err(&dev->v4l2_dev,
1360                          "not enough framebuffers to decode (%d < %d)\n",
1361                          CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
1362                 return -EINVAL;
1363         }
1364
1365         if (src_fourcc == V4L2_PIX_FMT_H264) {
1366                 u32 left_right;
1367                 u32 top_bottom;
1368
1369                 left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
1370                 top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
1371
1372                 q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
1373                 q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
1374                 q_data_dst->rect.width = width - q_data_dst->rect.left -
1375                                          (left_right & 0x3ff);
1376                 q_data_dst->rect.height = height - q_data_dst->rect.top -
1377                                           (top_bottom & 0x3ff);
1378         }
1379
1380         ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
1381         if (ret < 0) {
1382                 v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
1383                 return ret;
1384         }
1385
1386         /* Tell the decoder how many frame buffers we allocated. */
1387         coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1388         coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1389
1390         if (dev->devtype->product != CODA_DX6) {
1391                 /* Set secondary AXI IRAM */
1392                 coda_setup_iram(ctx);
1393
1394                 coda_write(dev, ctx->iram_info.buf_bit_use,
1395                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1396                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1397                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1398                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1399                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1400                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1401                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1402                 coda_write(dev, ctx->iram_info.buf_ovl_use,
1403                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1404                 if (dev->devtype->product == CODA_960)
1405                         coda_write(dev, ctx->iram_info.buf_btp_use,
1406                                         CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
1407         }
1408
1409         if (dev->devtype->product == CODA_960) {
1410                 coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
1411
1412                 coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
1413                 coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
1414                                 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
1415                                 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
1416                                 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
1417                                 CODA9_CMD_SET_FRAME_CACHE_CONFIG);
1418         }
1419
1420         if (src_fourcc == V4L2_PIX_FMT_H264) {
1421                 coda_write(dev, ctx->slicebuf.paddr,
1422                                 CODA_CMD_SET_FRAME_SLICE_BB_START);
1423                 coda_write(dev, ctx->slicebuf.size / 1024,
1424                                 CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
1425         }
1426
1427         if (dev->devtype->product == CODA_7541) {
1428                 int max_mb_x = 1920 / 16;
1429                 int max_mb_y = 1088 / 16;
1430                 int max_mb_num = max_mb_x * max_mb_y;
1431
1432                 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1433                                 CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
1434         } else if (dev->devtype->product == CODA_960) {
1435                 int max_mb_x = 1920 / 16;
1436                 int max_mb_y = 1088 / 16;
1437                 int max_mb_num = max_mb_x * max_mb_y;
1438
1439                 coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
1440                                 CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
1441         }
1442
1443         if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1444                 v4l2_err(&ctx->dev->v4l2_dev,
1445                          "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1446                 return -ETIMEDOUT;
1447         }
1448
1449         return 0;
1450 }
1451
1452 static int coda_start_decoding(struct coda_ctx *ctx)
1453 {
1454         struct coda_dev *dev = ctx->dev;
1455         int ret;
1456
1457         mutex_lock(&dev->coda_mutex);
1458         ret = __coda_start_decoding(ctx);
1459         mutex_unlock(&dev->coda_mutex);
1460
1461         return ret;
1462 }
1463
1464 static int coda_prepare_decode(struct coda_ctx *ctx)
1465 {
1466         struct vb2_buffer *dst_buf;
1467         struct coda_dev *dev = ctx->dev;
1468         struct coda_q_data *q_data_dst;
1469         u32 stridey, height;
1470         u32 picture_y, picture_cb, picture_cr;
1471
1472         dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
1473         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1474
1475         if (ctx->params.rot_mode & CODA_ROT_90) {
1476                 stridey = q_data_dst->height;
1477                 height = q_data_dst->width;
1478         } else {
1479                 stridey = q_data_dst->width;
1480                 height = q_data_dst->height;
1481         }
1482
1483         /* Try to copy source buffer contents into the bitstream ringbuffer */
1484         mutex_lock(&ctx->bitstream_mutex);
1485         coda_fill_bitstream(ctx);
1486         mutex_unlock(&ctx->bitstream_mutex);
1487
1488         if (coda_get_bitstream_payload(ctx) < 512 &&
1489             (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
1490                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1491                          "bitstream payload: %d, skipping\n",
1492                          coda_get_bitstream_payload(ctx));
1493                 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1494                 return -EAGAIN;
1495         }
1496
1497         /* Run coda_start_decoding (again) if not yet initialized */
1498         if (!ctx->initialized) {
1499                 int ret = __coda_start_decoding(ctx);
1500
1501                 if (ret < 0) {
1502                         v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
1503                         v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
1504                         return -EAGAIN;
1505                 } else {
1506                         ctx->initialized = 1;
1507                 }
1508         }
1509
1510         if (dev->devtype->product == CODA_960)
1511                 coda_set_gdi_regs(ctx);
1512
1513         /* Set rotator output */
1514         picture_y = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
1515         if (q_data_dst->fourcc == V4L2_PIX_FMT_YVU420) {
1516                 /* Switch Cr and Cb for YVU420 format */
1517                 picture_cr = picture_y + stridey * height;
1518                 picture_cb = picture_cr + stridey / 2 * height / 2;
1519         } else {
1520                 picture_cb = picture_y + stridey * height;
1521                 picture_cr = picture_cb + stridey / 2 * height / 2;
1522         }
1523
1524         if (dev->devtype->product == CODA_960) {
1525                 /*
1526                  * The CODA960 seems to have an internal list of buffers with
1527                  * 64 entries that includes the registered frame buffers as
1528                  * well as the rotator buffer output.
1529                  * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
1530                  */
1531                 coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
1532                                 CODA9_CMD_DEC_PIC_ROT_INDEX);
1533                 coda_write(dev, picture_y, CODA9_CMD_DEC_PIC_ROT_ADDR_Y);
1534                 coda_write(dev, picture_cb, CODA9_CMD_DEC_PIC_ROT_ADDR_CB);
1535                 coda_write(dev, picture_cr, CODA9_CMD_DEC_PIC_ROT_ADDR_CR);
1536                 coda_write(dev, stridey, CODA9_CMD_DEC_PIC_ROT_STRIDE);
1537         } else {
1538                 coda_write(dev, picture_y, CODA_CMD_DEC_PIC_ROT_ADDR_Y);
1539                 coda_write(dev, picture_cb, CODA_CMD_DEC_PIC_ROT_ADDR_CB);
1540                 coda_write(dev, picture_cr, CODA_CMD_DEC_PIC_ROT_ADDR_CR);
1541                 coda_write(dev, stridey, CODA_CMD_DEC_PIC_ROT_STRIDE);
1542         }
1543         coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
1544                         CODA_CMD_DEC_PIC_ROT_MODE);
1545
1546         switch (dev->devtype->product) {
1547         case CODA_DX6:
1548                 /* TBD */
1549         case CODA_7541:
1550                 coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
1551                 break;
1552         case CODA_960:
1553                 coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION); /* 'hardcode to use interrupt disable mode'? */
1554                 break;
1555         }
1556
1557         coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
1558
1559         coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
1560         coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
1561
1562         if (dev->devtype->product != CODA_DX6)
1563                 coda_write(dev, ctx->iram_info.axi_sram_use,
1564                                 CODA7_REG_BIT_AXI_SRAM_USE);
1565
1566         coda_kfifo_sync_to_device_full(ctx);
1567
1568         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
1569
1570         return 0;
1571 }
1572
1573 static void coda_finish_decode(struct coda_ctx *ctx)
1574 {
1575         struct coda_dev *dev = ctx->dev;
1576         struct coda_q_data *q_data_src;
1577         struct coda_q_data *q_data_dst;
1578         struct vb2_buffer *dst_buf;
1579         struct coda_timestamp *ts;
1580         int width, height;
1581         int decoded_idx;
1582         int display_idx;
1583         u32 src_fourcc;
1584         int success;
1585         u32 err_mb;
1586         u32 val;
1587
1588         /* Update kfifo out pointer from coda bitstream read pointer */
1589         coda_kfifo_sync_from_device(ctx);
1590
1591         /*
1592          * in stream-end mode, the read pointer can overshoot the write pointer
1593          * by up to 512 bytes
1594          */
1595         if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
1596                 if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
1597                         kfifo_init(&ctx->bitstream_fifo,
1598                                 ctx->bitstream.vaddr, ctx->bitstream.size);
1599         }
1600
1601         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1602         src_fourcc = q_data_src->fourcc;
1603
1604         val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
1605         if (val != 1)
1606                 pr_err("DEC_PIC_SUCCESS = %d\n", val);
1607
1608         success = val & 0x1;
1609         if (!success)
1610                 v4l2_err(&dev->v4l2_dev, "decode failed\n");
1611
1612         if (src_fourcc == V4L2_PIX_FMT_H264) {
1613                 if (val & (1 << 3))
1614                         v4l2_err(&dev->v4l2_dev,
1615                                  "insufficient PS buffer space (%d bytes)\n",
1616                                  ctx->psbuf.size);
1617                 if (val & (1 << 2))
1618                         v4l2_err(&dev->v4l2_dev,
1619                                  "insufficient slice buffer space (%d bytes)\n",
1620                                  ctx->slicebuf.size);
1621         }
1622
1623         val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
1624         width = (val >> 16) & 0xffff;
1625         height = val & 0xffff;
1626
1627         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1628
1629         /* frame crop information */
1630         if (src_fourcc == V4L2_PIX_FMT_H264) {
1631                 u32 left_right;
1632                 u32 top_bottom;
1633
1634                 left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
1635                 top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
1636
1637                 if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
1638                         /* Keep current crop information */
1639                 } else {
1640                         struct v4l2_rect *rect = &q_data_dst->rect;
1641
1642                         rect->left = left_right >> 16 & 0xffff;
1643                         rect->top = top_bottom >> 16 & 0xffff;
1644                         rect->width = width - rect->left -
1645                                       (left_right & 0xffff);
1646                         rect->height = height - rect->top -
1647                                        (top_bottom & 0xffff);
1648                 }
1649         } else {
1650                 /* no cropping */
1651         }
1652
1653         err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
1654         if (err_mb > 0)
1655                 v4l2_err(&dev->v4l2_dev,
1656                          "errors in %d macroblocks\n", err_mb);
1657
1658         if (dev->devtype->product == CODA_7541) {
1659                 val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
1660                 if (val == 0) {
1661                         /* not enough bitstream data */
1662                         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1663                                  "prescan failed: %d\n", val);
1664                         ctx->hold = true;
1665                         return;
1666                 }
1667         }
1668
1669         ctx->frm_dis_flg = coda_read(dev, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1670
1671         /*
1672          * The previous display frame was copied out by the rotator,
1673          * now it can be overwritten again
1674          */
1675         if (ctx->display_idx >= 0 &&
1676             ctx->display_idx < ctx->num_internal_frames) {
1677                 ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
1678                 coda_write(dev, ctx->frm_dis_flg,
1679                                 CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
1680         }
1681
1682         /*
1683          * The index of the last decoded frame, not necessarily in
1684          * display order, and the index of the next display frame.
1685          * The latter could have been decoded in a previous run.
1686          */
1687         decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
1688         display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
1689
1690         if (decoded_idx == -1) {
1691                 /* no frame was decoded, but we might have a display frame */
1692                 if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
1693                         ctx->sequence_offset++;
1694                 else if (ctx->display_idx < 0)
1695                         ctx->hold = true;
1696         } else if (decoded_idx == -2) {
1697                 /* no frame was decoded, we still return the remaining buffers */
1698         } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
1699                 v4l2_err(&dev->v4l2_dev,
1700                          "decoded frame index out of range: %d\n", decoded_idx);
1701         } else {
1702                 ts = list_first_entry(&ctx->timestamp_list,
1703                                       struct coda_timestamp, list);
1704                 list_del(&ts->list);
1705                 val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
1706                 val -= ctx->sequence_offset;
1707                 if (val != (ts->sequence & 0xffff)) {
1708                         v4l2_err(&dev->v4l2_dev,
1709                                  "sequence number mismatch (%d(%d) != %d)\n",
1710                                  val, ctx->sequence_offset, ts->sequence);
1711                 }
1712                 ctx->frame_timestamps[decoded_idx] = *ts;
1713                 kfree(ts);
1714
1715                 val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
1716                 if (val == 0)
1717                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
1718                 else if (val == 1)
1719                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
1720                 else
1721                         ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
1722
1723                 ctx->frame_errors[decoded_idx] = err_mb;
1724         }
1725
1726         if (display_idx == -1) {
1727                 /*
1728                  * no more frames to be decoded, but there could still
1729                  * be rotator output to dequeue
1730                  */
1731                 ctx->hold = true;
1732         } else if (display_idx == -3) {
1733                 /* possibly prescan failure */
1734         } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
1735                 v4l2_err(&dev->v4l2_dev,
1736                          "presentation frame index out of range: %d\n",
1737                          display_idx);
1738         }
1739
1740         /* If a frame was copied out, return it */
1741         if (ctx->display_idx >= 0 &&
1742             ctx->display_idx < ctx->num_internal_frames) {
1743                 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1744                 dst_buf->v4l2_buf.sequence = ctx->osequence++;
1745
1746                 dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
1747                                              V4L2_BUF_FLAG_PFRAME |
1748                                              V4L2_BUF_FLAG_BFRAME);
1749                 dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
1750                 ts = &ctx->frame_timestamps[ctx->display_idx];
1751                 dst_buf->v4l2_buf.timecode = ts->timecode;
1752                 dst_buf->v4l2_buf.timestamp = ts->timestamp;
1753
1754                 vb2_set_plane_payload(dst_buf, 0, width * height * 3 / 2);
1755
1756                 v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
1757                                   VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
1758
1759                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1760                         "job finished: decoding frame (%d) (%s)\n",
1761                         dst_buf->v4l2_buf.sequence,
1762                         (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1763                         "KEYFRAME" : "PFRAME");
1764         } else {
1765                 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1766                         "job finished: no frame decoded\n");
1767         }
1768
1769         /* The rotator will copy the current display frame next time */
1770         ctx->display_idx = display_idx;
1771 }
1772
1773 const struct coda_context_ops coda_bit_decode_ops = {
1774         .queue_init = coda_decoder_queue_init,
1775         .start_streaming = coda_start_decoding,
1776         .prepare_run = coda_prepare_decode,
1777         .finish_run = coda_finish_decode,
1778         .seq_end_work = coda_seq_end_work,
1779         .release = coda_bit_release,
1780 };
1781
1782 irqreturn_t coda_irq_handler(int irq, void *data)
1783 {
1784         struct coda_dev *dev = data;
1785         struct coda_ctx *ctx;
1786
1787         /* read status register to attend the IRQ */
1788         coda_read(dev, CODA_REG_BIT_INT_STATUS);
1789         coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1790                       CODA_REG_BIT_INT_CLEAR);
1791
1792         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1793         if (ctx == NULL) {
1794                 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
1795                 mutex_unlock(&dev->coda_mutex);
1796                 return IRQ_HANDLED;
1797         }
1798
1799         if (ctx->aborting) {
1800                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1801                          "task has been aborted\n");
1802         }
1803
1804         if (coda_isbusy(ctx->dev)) {
1805                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1806                          "coda is still busy!!!!\n");
1807                 return IRQ_NONE;
1808         }
1809
1810         complete(&ctx->completion);
1811
1812         return IRQ_HANDLED;
1813 }