drivers/media/platform/omap3isp/ispcsiphy.c

   1 /*
   2  * ispcsiphy.c
   3  *
   4  * TI OMAP3 ISP - CSI PHY module
   5  *
   6  * Copyright (C) 2010 Nokia Corporation
   7  * Copyright (C) 2009 Texas Instruments, Inc.
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/regulator/consumer.h>
  20
  21 #include "isp.h"
  22 #include "ispreg.h"
  23 #include "ispcsiphy.h"
  24
  25 static void csiphy_routing_cfg_3630(struct isp_csiphy *phy,
  26                                     enum isp_interface_type iface,
  27                                     bool ccp2_strobe)
  28 {
  29         u32 reg = isp_reg_readl(
  30                 phy->isp, OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL, 0);
  31         u32 shift, mode;
  32
  33         switch (iface) {
  34         default:
  35         /* Should not happen in practice, but let's keep the compiler happy. */
  36         case ISP_INTERFACE_CCP2B_PHY1:
  37                 reg &= ~OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2;
  38                 shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT;
  39                 break;
  40         case ISP_INTERFACE_CSI2C_PHY1:
  41                 shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT;
  42                 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY;
  43                 break;
  44         case ISP_INTERFACE_CCP2B_PHY2:
  45                 reg |= OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2;
  46                 shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT;
  47                 break;
  48         case ISP_INTERFACE_CSI2A_PHY2:
  49                 shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT;
  50                 mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY;
  51                 break;
  52         }
  53
  54         /* Select data/clock or data/strobe mode for CCP2 */
  55         if (iface == ISP_INTERFACE_CCP2B_PHY1 ||
  56             iface == ISP_INTERFACE_CCP2B_PHY2) {
  57                 if (ccp2_strobe)
  58                         mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE;
  59                 else
  60                         mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK;
  61         }
  62
  63         reg &= ~(OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK << shift);
  64         reg |= mode << shift;
  65
  66         isp_reg_writel(phy->isp, reg,
  67                        OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL, 0);
  68 }
  69
  70 static void csiphy_routing_cfg_3430(struct isp_csiphy *phy, u32 iface, bool on,
  71                                     bool ccp2_strobe)
  72 {
  73         u32 csirxfe = OMAP343X_CONTROL_CSIRXFE_PWRDNZ
  74                 | OMAP343X_CONTROL_CSIRXFE_RESET;
  75
  76         /* Only the CCP2B on PHY1 is configurable. */
  77         if (iface != ISP_INTERFACE_CCP2B_PHY1)
  78                 return;
  79
  80         if (!on) {
  81                 isp_reg_writel(phy->isp, 0,
  82                                OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE, 0);
  83                 return;
  84         }
  85
  86         if (ccp2_strobe)
  87                 csirxfe |= OMAP343X_CONTROL_CSIRXFE_SELFORM;
  88
  89         isp_reg_writel(phy->isp, csirxfe,
  90                        OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE, 0);
  91 }
  92
  93 /*
  94  * Configure OMAP 3 CSI PHY routing.
  95  * @phy: relevant phy device
  96  * @iface: ISP_INTERFACE_*
  97  * @on: power on or off
  98  * @ccp2_strobe: false: data/clock, true: data/strobe
  99  *
 100  * Note that the underlying routing configuration registers are part of the
 101  * control (SCM) register space and part of the CORE power domain on both 3430
 102  * and 3630, so they will not hold their contents in off-mode. This isn't an
 103  * issue since the MPU power domain is forced on whilst the ISP is in use.
 104  */
 105 static void csiphy_routing_cfg(struct isp_csiphy *phy,
 106                                enum isp_interface_type iface, bool on,
 107                                bool ccp2_strobe)
 108 {
 109         if (phy->isp->mmio_base[OMAP3_ISP_IOMEM_3630_CONTROL_CAMERA_PHY_CTRL]
 110             && on)
 111                 return csiphy_routing_cfg_3630(phy, iface, ccp2_strobe);
 112         if (phy->isp->mmio_base[OMAP3_ISP_IOMEM_343X_CONTROL_CSIRXFE])
 113                 return csiphy_routing_cfg_3430(phy, iface, on, ccp2_strobe);
 114 }
 115
 116 /*
 117  * csiphy_power_autoswitch_enable
 118  * @enable: Sets or clears the autoswitch function enable flag.
 119  */
 120 static void csiphy_power_autoswitch_enable(struct isp_csiphy *phy, bool enable)
 121 {
 122         isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,
 123                         ISPCSI2_PHY_CFG_PWR_AUTO,
 124                         enable ? ISPCSI2_PHY_CFG_PWR_AUTO : 0);
 125 }
 126
 127 /*
 128  * csiphy_set_power
 129  * @power: Power state to be set.
 130  *
 131  * Returns 0 if successful, or -EBUSY if the retry count is exceeded.
 132  */
 133 static int csiphy_set_power(struct isp_csiphy *phy, u32 power)
 134 {
 135         u32 reg;
 136         u8 retry_count;
 137
 138         isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,
 139                         ISPCSI2_PHY_CFG_PWR_CMD_MASK, power);
 140
 141         retry_count = 0;
 142         do {
 143                 udelay(50);
 144                 reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) &
 145                                     ISPCSI2_PHY_CFG_PWR_STATUS_MASK;
 146
 147                 if (reg != power >> 2)
 148                         retry_count++;
 149
 150         } while ((reg != power >> 2) && (retry_count < 100));
 151
 152         if (retry_count == 100) {
 153                 dev_err(phy->isp->dev, "CSI2 CIO set power failed!\n");
 154                 return -EBUSY;
 155         }
 156
 157         return 0;
 158 }
 159
 160 /*
 161  * TCLK values are OK at their reset values
 162  */
 163 #define TCLK_TERM       0
 164 #define TCLK_MISS       1
 165 #define TCLK_SETTLE     14
 166
 167 static int omap3isp_csiphy_config(struct isp_csiphy *phy)
 168 {
 169         struct isp_csi2_device *csi2 = phy->csi2;
 170         struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
 171         struct isp_v4l2_subdevs_group *subdevs = pipe->external->host_priv;
 172         struct isp_csiphy_lanes_cfg *lanes;
 173         int csi2_ddrclk_khz;
 174         unsigned int used_lanes = 0;
 175         unsigned int i;
 176         u32 reg;
 177
 178         if (subdevs->interface == ISP_INTERFACE_CCP2B_PHY1
 179             || subdevs->interface == ISP_INTERFACE_CCP2B_PHY2)
 180                 lanes = &subdevs->bus.ccp2.lanecfg;
 181         else
 182                 lanes = &subdevs->bus.csi2.lanecfg;
 183
 184         /* Clock and data lanes verification */
 185         for (i = 0; i < phy->num_data_lanes; i++) {
 186                 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3)
 187                         return -EINVAL;
 188
 189                 if (used_lanes & (1 << lanes->data[i].pos))
 190                         return -EINVAL;
 191
 192                 used_lanes |= 1 << lanes->data[i].pos;
 193         }
 194
 195         if (lanes->clk.pol > 1 || lanes->clk.pos > 3)
 196                 return -EINVAL;
 197
 198         if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
 199                 return -EINVAL;
 200
 201         /*
 202          * The PHY configuration is lost in off mode, that's not an
 203          * issue since the MPU power domain is forced on whilst the
 204          * ISP is in use.
 205          */
 206         csiphy_routing_cfg(phy, subdevs->interface, true,
 207                            subdevs->bus.ccp2.phy_layer);
 208
 209         /* DPHY timing configuration */
 210         /* CSI-2 is DDR and we only count used lanes. */
 211         csi2_ddrclk_khz = pipe->external_rate / 1000
 212                 / (2 * hweight32(used_lanes)) * pipe->external_width;
 213
 214         reg = isp_reg_readl(csi2->isp, phy->phy_regs, ISPCSIPHY_REG0);
 215
 216         reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK |
 217                  ISPCSIPHY_REG0_THS_SETTLE_MASK);
 218         /* THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1. */
 219         reg |= (DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1)
 220                 << ISPCSIPHY_REG0_THS_TERM_SHIFT;
 221         /* THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3. */
 222         reg |= (DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3)
 223                 << ISPCSIPHY_REG0_THS_SETTLE_SHIFT;
 224
 225         isp_reg_writel(csi2->isp, reg, phy->phy_regs, ISPCSIPHY_REG0);
 226
 227         reg = isp_reg_readl(csi2->isp, phy->phy_regs, ISPCSIPHY_REG1);
 228
 229         reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK |
 230                  ISPCSIPHY_REG1_TCLK_MISS_MASK |
 231                  ISPCSIPHY_REG1_TCLK_SETTLE_MASK);
 232         reg |= TCLK_TERM << ISPCSIPHY_REG1_TCLK_TERM_SHIFT;
 233         reg |= TCLK_MISS << ISPCSIPHY_REG1_TCLK_MISS_SHIFT;
 234         reg |= TCLK_SETTLE << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT;
 235
 236         isp_reg_writel(csi2->isp, reg, phy->phy_regs, ISPCSIPHY_REG1);
 237
 238         /* DPHY lane configuration */
 239         reg = isp_reg_readl(csi2->isp, phy->cfg_regs, ISPCSI2_PHY_CFG);
 240
 241         for (i = 0; i < phy->num_data_lanes; i++) {
 242                 reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) |
 243                          ISPCSI2_PHY_CFG_DATA_POSITION_MASK(i + 1));
 244                 reg |= (lanes->data[i].pol <<
 245                         ISPCSI2_PHY_CFG_DATA_POL_SHIFT(i + 1));
 246                 reg |= (lanes->data[i].pos <<
 247                         ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(i + 1));
 248         }
 249
 250         reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK |
 251                  ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK);
 252         reg |= lanes->clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT;
 253         reg |= lanes->clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT;
 254
 255         isp_reg_writel(csi2->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG);
 256
 257         return 0;
 258 }
 259
 260 int omap3isp_csiphy_acquire(struct isp_csiphy *phy)
 261 {
 262         int rval;
 263
 264         if (phy->vdd == NULL) {
 265                 dev_err(phy->isp->dev, "Power regulator for CSI PHY not "
 266                         "available\n");
 267                 return -ENODEV;
 268         }
 269
 270         mutex_lock(&phy->mutex);
 271
 272         rval = regulator_enable(phy->vdd);
 273         if (rval < 0)
 274                 goto done;
 275
 276         rval = omap3isp_csi2_reset(phy->csi2);
 277         if (rval < 0)
 278                 goto done;
 279
 280         rval = omap3isp_csiphy_config(phy);
 281         if (rval < 0)
 282                 goto done;
 283
 284         rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON);
 285         if (rval) {
 286                 regulator_disable(phy->vdd);
 287                 goto done;
 288         }
 289
 290         csiphy_power_autoswitch_enable(phy, true);
 291         phy->phy_in_use = 1;
 292
 293 done:
 294         mutex_unlock(&phy->mutex);
 295         return rval;
 296 }
 297
 298 void omap3isp_csiphy_release(struct isp_csiphy *phy)
 299 {
 300         mutex_lock(&phy->mutex);
 301         if (phy->phy_in_use) {
 302                 struct isp_csi2_device *csi2 = phy->csi2;
 303                 struct isp_pipeline *pipe =
 304                         to_isp_pipeline(&csi2->subdev.entity);
 305                 struct isp_v4l2_subdevs_group *subdevs =
 306                         pipe->external->host_priv;
 307
 308                 csiphy_routing_cfg(phy, subdevs->interface, false,
 309                                    subdevs->bus.ccp2.phy_layer);
 310                 csiphy_power_autoswitch_enable(phy, false);
 311                 csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF);
 312                 regulator_disable(phy->vdd);
 313                 phy->phy_in_use = 0;
 314         }
 315         mutex_unlock(&phy->mutex);
 316 }
 317
 318 /*
 319  * omap3isp_csiphy_init - Initialize the CSI PHY frontends
 320  */
 321 int omap3isp_csiphy_init(struct isp_device *isp)
 322 {
 323         struct isp_csiphy *phy1 = &isp->isp_csiphy1;
 324         struct isp_csiphy *phy2 = &isp->isp_csiphy2;
 325
 326         phy2->isp = isp;
 327         phy2->csi2 = &isp->isp_csi2a;
 328         phy2->num_data_lanes = ISP_CSIPHY2_NUM_DATA_LANES;
 329         phy2->cfg_regs = OMAP3_ISP_IOMEM_CSI2A_REGS1;
 330         phy2->phy_regs = OMAP3_ISP_IOMEM_CSIPHY2;
 331         mutex_init(&phy2->mutex);
 332
 333         if (isp->revision == ISP_REVISION_15_0) {
 334                 phy1->isp = isp;
 335                 phy1->csi2 = &isp->isp_csi2c;
 336                 phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES;
 337                 phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1;
 338                 phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1;
 339                 mutex_init(&phy1->mutex);
 340         }
 341
 342         return 0;
 343 }