4 * TI OMAP3 ISP - Histogram module
6 * Copyright (C) 2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
9 * Contacts: David Cohen <dacohen@gmail.com>
10 * Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/uaccess.h>
21 #include <linux/device.h>
27 #define OMAP24XX_DMA_NO_DEVICE 0
29 #define HIST_CONFIG_DMA 1
31 #define HIST_USING_DMA(hist) ((hist)->dma_ch >= 0)
34 * hist_reset_mem - clear Histogram memory before start stats engine.
36 static void hist_reset_mem(struct ispstat *hist)
38 struct isp_device *isp = hist->isp;
39 struct omap3isp_hist_config *conf = hist->priv;
42 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
45 * By setting it, the histogram internal buffer is being cleared at the
46 * same time it's being read. This bit must be cleared afterwards.
48 isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
51 * We'll clear 4 words at each iteration for optimization. It avoids
52 * 3/4 of the jumps. We also know HIST_MEM_SIZE is divisible by 4.
54 for (i = OMAP3ISP_HIST_MEM_SIZE / 4; i > 0; i--) {
55 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
56 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
57 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
58 isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
60 isp_reg_clr(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
62 hist->wait_acc_frames = conf->num_acc_frames;
65 static void hist_dma_config(struct ispstat *hist)
67 struct isp_device *isp = hist->isp;
69 hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32;
70 hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT;
71 hist->dma_config.frame_count = 1;
72 hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT;
73 hist->dma_config.src_start = isp->mmio_base_phys[OMAP3_ISP_IOMEM_HIST]
75 hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC;
76 hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC;
80 * hist_setup_regs - Helper function to update Histogram registers.
82 static void hist_setup_regs(struct ispstat *hist, void *priv)
84 struct isp_device *isp = hist->isp;
85 struct omap3isp_hist_config *conf = priv;
89 u32 reg_hor[OMAP3ISP_HIST_MAX_REGIONS];
90 u32 reg_ver[OMAP3ISP_HIST_MAX_REGIONS];
92 if (!hist->update || hist->state == ISPSTAT_DISABLED ||
93 hist->state == ISPSTAT_DISABLING)
96 cnt = conf->cfa << ISPHIST_CNT_CFA_SHIFT;
98 wb_gain = conf->wg[0] << ISPHIST_WB_GAIN_WG00_SHIFT;
99 wb_gain |= conf->wg[1] << ISPHIST_WB_GAIN_WG01_SHIFT;
100 wb_gain |= conf->wg[2] << ISPHIST_WB_GAIN_WG02_SHIFT;
101 if (conf->cfa == OMAP3ISP_HIST_CFA_BAYER)
102 wb_gain |= conf->wg[3] << ISPHIST_WB_GAIN_WG03_SHIFT;
104 /* Regions size and position */
105 for (c = 0; c < OMAP3ISP_HIST_MAX_REGIONS; c++) {
106 if (c < conf->num_regions) {
107 reg_hor[c] = (conf->region[c].h_start <<
108 ISPHIST_REG_START_SHIFT)
109 | (conf->region[c].h_end <<
110 ISPHIST_REG_END_SHIFT);
111 reg_ver[c] = (conf->region[c].v_start <<
112 ISPHIST_REG_START_SHIFT)
113 | (conf->region[c].v_end <<
114 ISPHIST_REG_END_SHIFT);
121 cnt |= conf->hist_bins << ISPHIST_CNT_BINS_SHIFT;
122 switch (conf->hist_bins) {
123 case OMAP3ISP_HIST_BINS_256:
124 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 8) <<
125 ISPHIST_CNT_SHIFT_SHIFT;
127 case OMAP3ISP_HIST_BINS_128:
128 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 7) <<
129 ISPHIST_CNT_SHIFT_SHIFT;
131 case OMAP3ISP_HIST_BINS_64:
132 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 6) <<
133 ISPHIST_CNT_SHIFT_SHIFT;
135 default: /* OMAP3ISP_HIST_BINS_32 */
136 cnt |= (ISPHIST_IN_BIT_WIDTH_CCDC - 5) <<
137 ISPHIST_CNT_SHIFT_SHIFT;
141 hist_reset_mem(hist);
143 isp_reg_writel(isp, cnt, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT);
144 isp_reg_writel(isp, wb_gain, OMAP3_ISP_IOMEM_HIST, ISPHIST_WB_GAIN);
145 isp_reg_writel(isp, reg_hor[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_HORZ);
146 isp_reg_writel(isp, reg_ver[0], OMAP3_ISP_IOMEM_HIST, ISPHIST_R0_VERT);
147 isp_reg_writel(isp, reg_hor[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_HORZ);
148 isp_reg_writel(isp, reg_ver[1], OMAP3_ISP_IOMEM_HIST, ISPHIST_R1_VERT);
149 isp_reg_writel(isp, reg_hor[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_HORZ);
150 isp_reg_writel(isp, reg_ver[2], OMAP3_ISP_IOMEM_HIST, ISPHIST_R2_VERT);
151 isp_reg_writel(isp, reg_hor[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_HORZ);
152 isp_reg_writel(isp, reg_ver[3], OMAP3_ISP_IOMEM_HIST, ISPHIST_R3_VERT);
155 hist->config_counter += hist->inc_config;
156 hist->inc_config = 0;
157 hist->buf_size = conf->buf_size;
160 static void hist_enable(struct ispstat *hist, int enable)
163 isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
165 omap3isp_subclk_enable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
167 isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR,
169 omap3isp_subclk_disable(hist->isp, OMAP3_ISP_SUBCLK_HIST);
173 static int hist_busy(struct ispstat *hist)
175 return isp_reg_readl(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_PCR)
179 static void hist_dma_cb(int lch, u16 ch_status, void *data)
181 struct ispstat *hist = data;
183 if (ch_status & ~OMAP_DMA_BLOCK_IRQ) {
184 dev_dbg(hist->isp->dev, "hist: DMA error. status = 0x%04x\n",
187 hist_reset_mem(hist);
188 atomic_set(&hist->buf_err, 1);
190 isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
193 omap3isp_stat_dma_isr(hist);
194 if (hist->state != ISPSTAT_DISABLED)
195 omap3isp_hist_dma_done(hist->isp);
198 static int hist_buf_dma(struct ispstat *hist)
200 dma_addr_t dma_addr = hist->active_buf->dma_addr;
202 if (unlikely(!dma_addr)) {
203 dev_dbg(hist->isp->dev, "hist: invalid DMA buffer address\n");
204 hist_reset_mem(hist);
208 isp_reg_writel(hist->isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
209 isp_reg_set(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
211 omap3isp_flush(hist->isp);
212 hist->dma_config.dst_start = dma_addr;
213 hist->dma_config.elem_count = hist->buf_size / sizeof(u32);
214 omap_set_dma_params(hist->dma_ch, &hist->dma_config);
216 omap_start_dma(hist->dma_ch);
218 return STAT_BUF_WAITING_DMA;
221 static int hist_buf_pio(struct ispstat *hist)
223 struct isp_device *isp = hist->isp;
224 u32 *buf = hist->active_buf->virt_addr;
228 dev_dbg(isp->dev, "hist: invalid PIO buffer address\n");
229 hist_reset_mem(hist);
233 isp_reg_writel(isp, 0, OMAP3_ISP_IOMEM_HIST, ISPHIST_ADDR);
236 * By setting it, the histogram internal buffer is being cleared at the
237 * same time it's being read. This bit must be cleared just after all
240 isp_reg_set(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT, ISPHIST_CNT_CLEAR);
243 * We'll read 4 times a 4-bytes-word at each iteration for
244 * optimization. It avoids 3/4 of the jumps. We also know buf_size is
247 for (i = hist->buf_size / 16; i > 0; i--) {
248 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
249 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
250 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
251 *buf++ = isp_reg_readl(isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_DATA);
253 isp_reg_clr(hist->isp, OMAP3_ISP_IOMEM_HIST, ISPHIST_CNT,
256 return STAT_BUF_DONE;
260 * hist_buf_process - Callback from ISP driver for HIST interrupt.
262 static int hist_buf_process(struct ispstat *hist)
264 struct omap3isp_hist_config *user_cfg = hist->priv;
267 if (atomic_read(&hist->buf_err) || hist->state != ISPSTAT_ENABLED) {
268 hist_reset_mem(hist);
272 if (--(hist->wait_acc_frames))
275 if (HIST_USING_DMA(hist))
276 ret = hist_buf_dma(hist);
278 ret = hist_buf_pio(hist);
280 hist->wait_acc_frames = user_cfg->num_acc_frames;
285 static u32 hist_get_buf_size(struct omap3isp_hist_config *conf)
287 return OMAP3ISP_HIST_MEM_SIZE_BINS(conf->hist_bins) * conf->num_regions;
291 * hist_validate_params - Helper function to check user given params.
292 * @new_conf: Pointer to user configuration structure.
294 * Returns 0 on success configuration.
296 static int hist_validate_params(struct ispstat *hist, void *new_conf)
298 struct omap3isp_hist_config *user_cfg = new_conf;
302 if (user_cfg->cfa > OMAP3ISP_HIST_CFA_FOVEONX3)
305 /* Regions size and position */
307 if ((user_cfg->num_regions < OMAP3ISP_HIST_MIN_REGIONS) ||
308 (user_cfg->num_regions > OMAP3ISP_HIST_MAX_REGIONS))
312 for (c = 0; c < user_cfg->num_regions; c++) {
313 if (user_cfg->region[c].h_start & ~ISPHIST_REG_START_END_MASK)
315 if (user_cfg->region[c].h_end & ~ISPHIST_REG_START_END_MASK)
317 if (user_cfg->region[c].v_start & ~ISPHIST_REG_START_END_MASK)
319 if (user_cfg->region[c].v_end & ~ISPHIST_REG_START_END_MASK)
321 if (user_cfg->region[c].h_start > user_cfg->region[c].h_end)
323 if (user_cfg->region[c].v_start > user_cfg->region[c].v_end)
327 switch (user_cfg->num_regions) {
329 if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_256)
333 if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_128)
336 default: /* 3 or 4 */
337 if (user_cfg->hist_bins > OMAP3ISP_HIST_BINS_64)
342 buf_size = hist_get_buf_size(user_cfg);
343 if (buf_size > user_cfg->buf_size)
344 /* User's buf_size request wasn't enough */
345 user_cfg->buf_size = buf_size;
346 else if (user_cfg->buf_size > OMAP3ISP_HIST_MAX_BUF_SIZE)
347 user_cfg->buf_size = OMAP3ISP_HIST_MAX_BUF_SIZE;
352 static int hist_comp_params(struct ispstat *hist,
353 struct omap3isp_hist_config *user_cfg)
355 struct omap3isp_hist_config *cur_cfg = hist->priv;
358 if (cur_cfg->cfa != user_cfg->cfa)
361 if (cur_cfg->num_acc_frames != user_cfg->num_acc_frames)
364 if (cur_cfg->hist_bins != user_cfg->hist_bins)
367 for (c = 0; c < OMAP3ISP_HIST_MAX_WG; c++) {
368 if (c == 3 && user_cfg->cfa == OMAP3ISP_HIST_CFA_FOVEONX3)
370 else if (cur_cfg->wg[c] != user_cfg->wg[c])
374 if (cur_cfg->num_regions != user_cfg->num_regions)
378 for (c = 0; c < user_cfg->num_regions; c++) {
379 if (cur_cfg->region[c].h_start != user_cfg->region[c].h_start)
381 if (cur_cfg->region[c].h_end != user_cfg->region[c].h_end)
383 if (cur_cfg->region[c].v_start != user_cfg->region[c].v_start)
385 if (cur_cfg->region[c].v_end != user_cfg->region[c].v_end)
393 * hist_update_params - Helper function to check and store user given params.
394 * @new_conf: Pointer to user configuration structure.
396 static void hist_set_params(struct ispstat *hist, void *new_conf)
398 struct omap3isp_hist_config *user_cfg = new_conf;
399 struct omap3isp_hist_config *cur_cfg = hist->priv;
401 if (!hist->configured || hist_comp_params(hist, user_cfg)) {
402 memcpy(cur_cfg, user_cfg, sizeof(*user_cfg));
403 if (user_cfg->num_acc_frames == 0)
404 user_cfg->num_acc_frames = 1;
408 * User might be asked for a bigger buffer than necessary for
409 * this configuration. In order to return the right amount of
410 * data during buffer request, let's calculate the size here
411 * instead of stick with user_cfg->buf_size.
413 cur_cfg->buf_size = hist_get_buf_size(cur_cfg);
418 static long hist_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
420 struct ispstat *stat = v4l2_get_subdevdata(sd);
423 case VIDIOC_OMAP3ISP_HIST_CFG:
424 return omap3isp_stat_config(stat, arg);
425 case VIDIOC_OMAP3ISP_STAT_REQ:
426 return omap3isp_stat_request_statistics(stat, arg);
427 case VIDIOC_OMAP3ISP_STAT_EN: {
429 return omap3isp_stat_enable(stat, !!*en);
437 static const struct ispstat_ops hist_ops = {
438 .validate_params = hist_validate_params,
439 .set_params = hist_set_params,
440 .setup_regs = hist_setup_regs,
441 .enable = hist_enable,
443 .buf_process = hist_buf_process,
446 static const struct v4l2_subdev_core_ops hist_subdev_core_ops = {
448 .subscribe_event = omap3isp_stat_subscribe_event,
449 .unsubscribe_event = omap3isp_stat_unsubscribe_event,
452 static const struct v4l2_subdev_video_ops hist_subdev_video_ops = {
453 .s_stream = omap3isp_stat_s_stream,
456 static const struct v4l2_subdev_ops hist_subdev_ops = {
457 .core = &hist_subdev_core_ops,
458 .video = &hist_subdev_video_ops,
462 * omap3isp_hist_init - Module Initialization.
464 int omap3isp_hist_init(struct isp_device *isp)
466 struct ispstat *hist = &isp->isp_hist;
467 struct omap3isp_hist_config *hist_cfg;
470 hist_cfg = devm_kzalloc(isp->dev, sizeof(*hist_cfg), GFP_KERNEL);
471 if (hist_cfg == NULL)
477 ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST",
478 hist_dma_cb, hist, &hist->dma_ch);
481 dev_warn(isp->dev, "hist: DMA request channel failed. "
482 "Using PIO only.\n");
485 dev_dbg(isp->dev, "hist: DMA channel = %d\n", hist->dma_ch);
486 hist_dma_config(hist);
487 omap_enable_dma_irq(hist->dma_ch, OMAP_DMA_BLOCK_IRQ);
490 hist->ops = &hist_ops;
491 hist->priv = hist_cfg;
492 hist->event_type = V4L2_EVENT_OMAP3ISP_HIST;
494 ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops);
496 if (HIST_USING_DMA(hist))
497 omap_free_dma(hist->dma_ch);
504 * omap3isp_hist_cleanup - Module cleanup.
506 void omap3isp_hist_cleanup(struct isp_device *isp)
508 if (HIST_USING_DMA(&isp->isp_hist))
509 omap_free_dma(isp->isp_hist.dma_ch);
510 omap3isp_stat_cleanup(&isp->isp_hist);