2 * vsp1_pipe.c -- R-Car VSP1 Pipeline
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/list.h>
16 #include <linux/sched.h>
17 #include <linux/wait.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-subdev.h>
25 #include "vsp1_entity.h"
26 #include "vsp1_pipe.h"
27 #include "vsp1_rwpf.h"
30 /* -----------------------------------------------------------------------------
34 static const struct vsp1_format_info vsp1_video_formats[] = {
35 { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
36 VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
37 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
38 1, { 8, 0, 0 }, false, false, 1, 1, false },
39 { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
40 VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
42 1, { 16, 0, 0 }, false, false, 1, 1, true },
43 { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
44 VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
46 1, { 16, 0, 0 }, false, false, 1, 1, false },
47 { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
48 VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
50 1, { 16, 0, 0 }, false, false, 1, 1, true },
51 { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
52 VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
54 1, { 16, 0, 0 }, false, false, 1, 1, false },
55 { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
56 VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
58 1, { 16, 0, 0 }, false, false, 1, 1, false },
59 { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
60 VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
61 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
62 1, { 24, 0, 0 }, false, false, 1, 1, false },
63 { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
64 VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
65 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
66 1, { 24, 0, 0 }, false, false, 1, 1, false },
67 { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
68 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
69 1, { 32, 0, 0 }, false, false, 1, 1, true },
70 { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
71 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
72 1, { 32, 0, 0 }, false, false, 1, 1, false },
73 { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
74 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
75 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
76 1, { 32, 0, 0 }, false, false, 1, 1, true },
77 { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
78 VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
79 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
80 1, { 32, 0, 0 }, false, false, 1, 1, false },
81 { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
82 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
83 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
84 1, { 16, 0, 0 }, false, false, 2, 1, false },
85 { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
86 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
87 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
88 1, { 16, 0, 0 }, false, true, 2, 1, false },
89 { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
90 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
91 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
92 1, { 16, 0, 0 }, true, false, 2, 1, false },
93 { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
94 VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
95 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
96 1, { 16, 0, 0 }, true, true, 2, 1, false },
97 { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
98 VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
99 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
100 2, { 8, 16, 0 }, false, false, 2, 2, false },
101 { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
102 VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
103 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
104 2, { 8, 16, 0 }, false, true, 2, 2, false },
105 { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
106 VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
107 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
108 2, { 8, 16, 0 }, false, false, 2, 1, false },
109 { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
110 VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
111 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
112 2, { 8, 16, 0 }, false, true, 2, 1, false },
113 { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
114 VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
115 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
116 3, { 8, 8, 8 }, false, false, 2, 2, false },
117 { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
118 VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
119 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
120 3, { 8, 8, 8 }, false, true, 2, 2, false },
121 { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
122 VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
123 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
124 3, { 8, 8, 8 }, false, false, 2, 1, false },
125 { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
126 VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
127 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
128 3, { 8, 8, 8 }, false, true, 2, 1, false },
129 { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
130 VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
131 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
132 3, { 8, 8, 8 }, false, false, 1, 1, false },
133 { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
134 VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
135 VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
136 3, { 8, 8, 8 }, false, true, 1, 1, false },
140 * vsp1_get_format_info - Retrieve format information for a 4CC
141 * @fourcc: the format 4CC
143 * Return a pointer to the format information structure corresponding to the
144 * given V4L2 format 4CC, or NULL if no corresponding format can be found.
146 const struct vsp1_format_info *vsp1_get_format_info(u32 fourcc)
150 for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
151 const struct vsp1_format_info *info = &vsp1_video_formats[i];
153 if (info->fourcc == fourcc)
160 /* -----------------------------------------------------------------------------
161 * Pipeline Management
164 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
169 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
171 for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
172 bru->inputs[i].rpf = NULL;
175 for (i = 0; i < pipe->num_inputs; ++i) {
176 pipe->inputs[i]->pipe = NULL;
177 pipe->inputs[i] = NULL;
180 pipe->output->pipe = NULL;
183 INIT_LIST_HEAD(&pipe->entities);
184 pipe->state = VSP1_PIPELINE_STOPPED;
185 pipe->buffers_ready = 0;
186 pipe->num_inputs = 0;
192 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
194 mutex_init(&pipe->lock);
195 spin_lock_init(&pipe->irqlock);
196 init_waitqueue_head(&pipe->wq);
197 kref_init(&pipe->kref);
199 INIT_LIST_HEAD(&pipe->entities);
200 pipe->state = VSP1_PIPELINE_STOPPED;
203 /* Must be called with the pipe irqlock held. */
204 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
206 struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
208 if (pipe->state == VSP1_PIPELINE_STOPPED) {
209 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
211 pipe->state = VSP1_PIPELINE_RUNNING;
214 pipe->buffers_ready = 0;
217 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
222 spin_lock_irqsave(&pipe->irqlock, flags);
223 stopped = pipe->state == VSP1_PIPELINE_STOPPED;
224 spin_unlock_irqrestore(&pipe->irqlock, flags);
229 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
231 struct vsp1_entity *entity;
236 /* When using display lists in continuous frame mode the only
237 * way to stop the pipeline is to reset the hardware.
239 ret = vsp1_reset_wpf(pipe->output->entity.vsp1,
240 pipe->output->entity.index);
242 spin_lock_irqsave(&pipe->irqlock, flags);
243 pipe->state = VSP1_PIPELINE_STOPPED;
244 spin_unlock_irqrestore(&pipe->irqlock, flags);
247 /* Otherwise just request a stop and wait. */
248 spin_lock_irqsave(&pipe->irqlock, flags);
249 if (pipe->state == VSP1_PIPELINE_RUNNING)
250 pipe->state = VSP1_PIPELINE_STOPPING;
251 spin_unlock_irqrestore(&pipe->irqlock, flags);
253 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
254 msecs_to_jiffies(500));
255 ret = ret == 0 ? -ETIMEDOUT : 0;
258 list_for_each_entry(entity, &pipe->entities, list_pipe) {
259 if (entity->route && entity->route->reg)
260 vsp1_write(entity->vsp1, entity->route->reg,
261 VI6_DPR_NODE_UNUSED);
264 v4l2_subdev_call(&pipe->output->entity.subdev, video, s_stream, 0);
269 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
273 mask = ((1 << pipe->num_inputs) - 1) << 1;
277 return pipe->buffers_ready == mask;
280 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
285 vsp1_dlm_irq_frame_end(pipe->output->dlm);
288 pipe->frame_end(pipe);
292 * Propagate the alpha value through the pipeline.
294 * As the UDS has restricted scaling capabilities when the alpha component needs
295 * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
296 * value. The UDS then outputs a fixed alpha value which needs to be programmed
297 * from the input RPF alpha.
299 * This function can only be called from a subdev s_stream handler as it
300 * requires a valid display list context.
302 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
303 struct vsp1_entity *input,
304 struct vsp1_dl_list *dl,
307 struct vsp1_entity *entity;
308 struct media_pad *pad;
310 pad = media_entity_remote_pad(&input->pads[RWPF_PAD_SOURCE]);
313 if (!is_media_entity_v4l2_subdev(pad->entity))
316 entity = to_vsp1_entity(media_entity_to_v4l2_subdev(pad->entity));
318 /* The BRU background color has a fixed alpha value set to 255,
319 * the output alpha value is thus always equal to 255.
321 if (entity->type == VSP1_ENTITY_BRU)
324 if (entity->type == VSP1_ENTITY_UDS) {
325 struct vsp1_uds *uds = to_uds(&entity->subdev);
327 vsp1_uds_set_alpha(uds, dl, alpha);
331 pad = &entity->pads[entity->source_pad];
332 pad = media_entity_remote_pad(pad);
336 void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
342 /* To avoid increasing the system suspend time needlessly, loop over the
343 * pipelines twice, first to set them all to the stopping state, and
344 * then to wait for the stop to complete.
346 for (i = 0; i < vsp1->info->wpf_count; ++i) {
347 struct vsp1_rwpf *wpf = vsp1->wpf[i];
348 struct vsp1_pipeline *pipe;
357 spin_lock_irqsave(&pipe->irqlock, flags);
358 if (pipe->state == VSP1_PIPELINE_RUNNING)
359 pipe->state = VSP1_PIPELINE_STOPPING;
360 spin_unlock_irqrestore(&pipe->irqlock, flags);
363 for (i = 0; i < vsp1->info->wpf_count; ++i) {
364 struct vsp1_rwpf *wpf = vsp1->wpf[i];
365 struct vsp1_pipeline *pipe;
374 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
375 msecs_to_jiffies(500));
377 dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
382 void vsp1_pipelines_resume(struct vsp1_device *vsp1)
386 /* Resume pipeline all running pipelines. */
387 for (i = 0; i < vsp1->info->wpf_count; ++i) {
388 struct vsp1_rwpf *wpf = vsp1->wpf[i];
389 struct vsp1_pipeline *pipe;
398 if (vsp1_pipeline_ready(pipe))
399 vsp1_pipeline_run(pipe);