drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include <media/tuner.h>
  28 #include "pvrusb2.h"
  29 #include "pvrusb2-std.h"
  30 #include "pvrusb2-util.h"
  31 #include "pvrusb2-hdw.h"
  32 #include "pvrusb2-i2c-core.h"
  33 #include "pvrusb2-eeprom.h"
  34 #include "pvrusb2-hdw-internal.h"
  35 #include "pvrusb2-encoder.h"
  36 #include "pvrusb2-debug.h"
  37 #include "pvrusb2-fx2-cmd.h"
  38 #include "pvrusb2-wm8775.h"
  39 #include "pvrusb2-video-v4l.h"
  40 #include "pvrusb2-cx2584x-v4l.h"
  41 #include "pvrusb2-cs53l32a.h"
  42 #include "pvrusb2-audio.h"
  43
  44 #define TV_MIN_FREQ     55250000L
  45 #define TV_MAX_FREQ    850000000L
  46
  47 /* This defines a minimum interval that the decoder must remain quiet
  48    before we are allowed to start it running. */
  49 #define TIME_MSEC_DECODER_WAIT 50
  50
  51 /* This defines a minimum interval that the encoder must remain quiet
  52    before we are allowed to configure it.  I had this originally set to
  53    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  54    things work better when it's set to 100msec. */
  55 #define TIME_MSEC_ENCODER_WAIT 100
  56
  57 /* This defines the minimum interval that the encoder must successfully run
  58    before we consider that the encoder has run at least once since its
  59    firmware has been loaded.  This measurement is in important for cases
  60    where we can't do something until we know that the encoder has been run
  61    at least once. */
  62 #define TIME_MSEC_ENCODER_OK 250
  63
  64 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  65 static DEFINE_MUTEX(pvr2_unit_mtx);
  66
  67 static int ctlchg;
  68 static int procreload;
  69 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  70 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  72 static int init_pause_msec;
  73
  74 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  76 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  78 module_param(procreload, int, S_IRUGO|S_IWUSR);
  79 MODULE_PARM_DESC(procreload,
  80                  "Attempt init failure recovery with firmware reload");
  81 module_param_array(tuner,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  83 module_param_array(video_std,    int, NULL, 0444);
  84 MODULE_PARM_DESC(video_std,"specify initial video standard");
  85 module_param_array(tolerance,    int, NULL, 0444);
  86 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  87
  88 /* US Broadcast channel 7 (175.25 MHz) */
  89 static int default_tv_freq    = 175250000L;
  90 /* 104.3 MHz, a usable FM station for my area */
  91 static int default_radio_freq = 104300000L;
  92
  93 module_param_named(tv_freq, default_tv_freq, int, 0444);
  94 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  95 module_param_named(radio_freq, default_radio_freq, int, 0444);
  96 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  97
  98 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  99 #define PVR2_CTL_READ_ENDPOINT   0x81
 100
 101 #define PVR2_GPIO_IN 0x9008
 102 #define PVR2_GPIO_OUT 0x900c
 103 #define PVR2_GPIO_DIR 0x9020
 104
 105 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 106
 107 #define PVR2_FIRMWARE_ENDPOINT   0x02
 108
 109 /* size of a firmware chunk */
 110 #define FIRMWARE_CHUNK_SIZE 0x2000
 111
 112 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 113                                         struct v4l2_subdev *);
 114
 115 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 116         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 117         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 118         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 119         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 120         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 121 };
 122
 123 static const char *module_names[] = {
 124         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 125         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 126         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 127         [PVR2_CLIENT_ID_TUNER] = "tuner",
 128         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 129         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 130         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 131 };
 132
 133
 134 static const unsigned char *module_i2c_addresses[] = {
 135         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 136         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 137         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 138         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 139         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 140         [PVR2_CLIENT_ID_CX25840] = "\x44",
 141         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 142 };
 143
 144
 145 /* Define the list of additional controls we'll dynamically construct based
 146    on query of the cx2341x module. */
 147 struct pvr2_mpeg_ids {
 148         const char *strid;
 149         int id;
 150 };
 151 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 152         {
 153                 .strid = "audio_layer",
 154                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 155         },{
 156                 .strid = "audio_bitrate",
 157                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 158         },{
 159                 /* Already using audio_mode elsewhere :-( */
 160                 .strid = "mpeg_audio_mode",
 161                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 162         },{
 163                 .strid = "mpeg_audio_mode_extension",
 164                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 165         },{
 166                 .strid = "audio_emphasis",
 167                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 168         },{
 169                 .strid = "audio_crc",
 170                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 171         },{
 172                 .strid = "video_aspect",
 173                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 174         },{
 175                 .strid = "video_b_frames",
 176                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 177         },{
 178                 .strid = "video_gop_size",
 179                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 180         },{
 181                 .strid = "video_gop_closure",
 182                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 183         },{
 184                 .strid = "video_bitrate_mode",
 185                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 186         },{
 187                 .strid = "video_bitrate",
 188                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 189         },{
 190                 .strid = "video_bitrate_peak",
 191                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 192         },{
 193                 .strid = "video_temporal_decimation",
 194                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 195         },{
 196                 .strid = "stream_type",
 197                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 198         },{
 199                 .strid = "video_spatial_filter_mode",
 200                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 201         },{
 202                 .strid = "video_spatial_filter",
 203                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 204         },{
 205                 .strid = "video_luma_spatial_filter_type",
 206                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 207         },{
 208                 .strid = "video_chroma_spatial_filter_type",
 209                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 210         },{
 211                 .strid = "video_temporal_filter_mode",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 213         },{
 214                 .strid = "video_temporal_filter",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 216         },{
 217                 .strid = "video_median_filter_type",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 219         },{
 220                 .strid = "video_luma_median_filter_top",
 221                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 222         },{
 223                 .strid = "video_luma_median_filter_bottom",
 224                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 225         },{
 226                 .strid = "video_chroma_median_filter_top",
 227                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 228         },{
 229                 .strid = "video_chroma_median_filter_bottom",
 230                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 231         }
 232 };
 233 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 234
 235
 236 static const char *control_values_srate[] = {
 237         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 238         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 239         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 240 };
 241
 242
 243
 244 static const char *control_values_input[] = {
 245         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 246         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 247         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 248         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 249         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 250 };
 251
 252
 253 static const char *control_values_audiomode[] = {
 254         [V4L2_TUNER_MODE_MONO]   = "Mono",
 255         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 256         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 257         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 258         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 259 };
 260
 261
 262 static const char *control_values_hsm[] = {
 263         [PVR2_CVAL_HSM_FAIL] = "Fail",
 264         [PVR2_CVAL_HSM_HIGH] = "High",
 265         [PVR2_CVAL_HSM_FULL] = "Full",
 266 };
 267
 268
 269 static const char *pvr2_state_names[] = {
 270         [PVR2_STATE_NONE] =    "none",
 271         [PVR2_STATE_DEAD] =    "dead",
 272         [PVR2_STATE_COLD] =    "cold",
 273         [PVR2_STATE_WARM] =    "warm",
 274         [PVR2_STATE_ERROR] =   "error",
 275         [PVR2_STATE_READY] =   "ready",
 276         [PVR2_STATE_RUN] =     "run",
 277 };
 278
 279
 280 struct pvr2_fx2cmd_descdef {
 281         unsigned char id;
 282         unsigned char *desc;
 283 };
 284
 285 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 286         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 287         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 288         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 289         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 290         {FX2CMD_REG_WRITE, "write encoder register"},
 291         {FX2CMD_REG_READ, "read encoder register"},
 292         {FX2CMD_MEMSEL, "encoder memsel"},
 293         {FX2CMD_I2C_WRITE, "i2c write"},
 294         {FX2CMD_I2C_READ, "i2c read"},
 295         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 296         {FX2CMD_STREAMING_ON, "stream on"},
 297         {FX2CMD_STREAMING_OFF, "stream off"},
 298         {FX2CMD_FWPOST1, "fwpost1"},
 299         {FX2CMD_POWER_OFF, "power off"},
 300         {FX2CMD_POWER_ON, "power on"},
 301         {FX2CMD_DEEP_RESET, "deep reset"},
 302         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 303         {FX2CMD_GET_IR_CODE, "get IR code"},
 304         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 305         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 306         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 307         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 308         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 309         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 310         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 311 };
 312
 313
 314 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 315 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 316 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 317 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 318 static void pvr2_hdw_worker_poll(struct work_struct *work);
 319 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 320 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 321 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 322 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 323 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 324 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 325 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 326 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 327 static void pvr2_hdw_quiescent_timeout(unsigned long);
 328 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 329 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 330 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 331 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 332                                 unsigned int timeout,int probe_fl,
 333                                 void *write_data,unsigned int write_len,
 334                                 void *read_data,unsigned int read_len);
 335 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 336
 337
 338 static void trace_stbit(const char *name,int val)
 339 {
 340         pvr2_trace(PVR2_TRACE_STBITS,
 341                    "State bit %s <-- %s",
 342                    name,(val ? "true" : "false"));
 343 }
 344
 345 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 346 {
 347         struct pvr2_hdw *hdw = cptr->hdw;
 348         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 349                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 350         } else {
 351                 *vp = 0;
 352         }
 353         return 0;
 354 }
 355
 356 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 357 {
 358         struct pvr2_hdw *hdw = cptr->hdw;
 359         unsigned int slotId = hdw->freqProgSlot;
 360         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 361                 hdw->freqTable[slotId-1] = v;
 362                 /* Handle side effects correctly - if we're tuned to this
 363                    slot, then forgot the slot id relation since the stored
 364                    frequency has been changed. */
 365                 if (hdw->freqSelector) {
 366                         if (hdw->freqSlotRadio == slotId) {
 367                                 hdw->freqSlotRadio = 0;
 368                         }
 369                 } else {
 370                         if (hdw->freqSlotTelevision == slotId) {
 371                                 hdw->freqSlotTelevision = 0;
 372                         }
 373                 }
 374         }
 375         return 0;
 376 }
 377
 378 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 379 {
 380         *vp = cptr->hdw->freqProgSlot;
 381         return 0;
 382 }
 383
 384 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 385 {
 386         struct pvr2_hdw *hdw = cptr->hdw;
 387         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 388                 hdw->freqProgSlot = v;
 389         }
 390         return 0;
 391 }
 392
 393 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 394 {
 395         struct pvr2_hdw *hdw = cptr->hdw;
 396         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 397         return 0;
 398 }
 399
 400 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 401 {
 402         unsigned freq = 0;
 403         struct pvr2_hdw *hdw = cptr->hdw;
 404         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 405         if (slotId > 0) {
 406                 freq = hdw->freqTable[slotId-1];
 407                 if (!freq) return 0;
 408                 pvr2_hdw_set_cur_freq(hdw,freq);
 409         }
 410         if (hdw->freqSelector) {
 411                 hdw->freqSlotRadio = slotId;
 412         } else {
 413                 hdw->freqSlotTelevision = slotId;
 414         }
 415         return 0;
 416 }
 417
 418 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 419 {
 420         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 421         return 0;
 422 }
 423
 424 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 425 {
 426         return cptr->hdw->freqDirty != 0;
 427 }
 428
 429 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 430 {
 431         cptr->hdw->freqDirty = 0;
 432 }
 433
 434 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 435 {
 436         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 437         return 0;
 438 }
 439
 440 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 441 {
 442         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 443         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 444         if (stat != 0) {
 445                 return stat;
 446         }
 447         *left = cap->bounds.left;
 448         return 0;
 449 }
 450
 451 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 452 {
 453         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 454         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 455         if (stat != 0) {
 456                 return stat;
 457         }
 458         *left = cap->bounds.left;
 459         if (cap->bounds.width > cptr->hdw->cropw_val) {
 460                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 461         }
 462         return 0;
 463 }
 464
 465 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 466 {
 467         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 468         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 469         if (stat != 0) {
 470                 return stat;
 471         }
 472         *top = cap->bounds.top;
 473         return 0;
 474 }
 475
 476 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 477 {
 478         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 479         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 480         if (stat != 0) {
 481                 return stat;
 482         }
 483         *top = cap->bounds.top;
 484         if (cap->bounds.height > cptr->hdw->croph_val) {
 485                 *top += cap->bounds.height - cptr->hdw->croph_val;
 486         }
 487         return 0;
 488 }
 489
 490 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 491 {
 492         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 493         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 494         if (stat != 0) {
 495                 return stat;
 496         }
 497         *val = 0;
 498         if (cap->bounds.width > cptr->hdw->cropl_val) {
 499                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 500         }
 501         return 0;
 502 }
 503
 504 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 505 {
 506         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 507         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 508         if (stat != 0) {
 509                 return stat;
 510         }
 511         *val = 0;
 512         if (cap->bounds.height > cptr->hdw->cropt_val) {
 513                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 514         }
 515         return 0;
 516 }
 517
 518 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 519 {
 520         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 522         if (stat != 0) {
 523                 return stat;
 524         }
 525         *val = cap->bounds.left;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.top;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->bounds.width;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->bounds.height;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->defrect.left;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.top;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->defrect.width;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->defrect.height;
 603         return 0;
 604 }
 605
 606 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 607 {
 608         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 609         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 610         if (stat != 0) {
 611                 return stat;
 612         }
 613         *val = cap->pixelaspect.numerator;
 614         return 0;
 615 }
 616
 617 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 618 {
 619         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 620         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 621         if (stat != 0) {
 622                 return stat;
 623         }
 624         *val = cap->pixelaspect.denominator;
 625         return 0;
 626 }
 627
 628 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         /* Actual maximum depends on the video standard in effect. */
 631         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 632                 *vp = 480;
 633         } else {
 634                 *vp = 576;
 635         }
 636         return 0;
 637 }
 638
 639 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 640 {
 641         /* Actual minimum depends on device digitizer type. */
 642         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 643                 *vp = 75;
 644         } else {
 645                 *vp = 17;
 646         }
 647         return 0;
 648 }
 649
 650 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 651 {
 652         *vp = cptr->hdw->input_val;
 653         return 0;
 654 }
 655
 656 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 657 {
 658         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 659 }
 660
 661 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 662 {
 663         return pvr2_hdw_set_input(cptr->hdw,v);
 664 }
 665
 666 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 667 {
 668         return cptr->hdw->input_dirty != 0;
 669 }
 670
 671 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 672 {
 673         cptr->hdw->input_dirty = 0;
 674 }
 675
 676
 677 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 678 {
 679         unsigned long fv;
 680         struct pvr2_hdw *hdw = cptr->hdw;
 681         if (hdw->tuner_signal_stale) {
 682                 pvr2_hdw_status_poll(hdw);
 683         }
 684         fv = hdw->tuner_signal_info.rangehigh;
 685         if (!fv) {
 686                 /* Safety fallback */
 687                 *vp = TV_MAX_FREQ;
 688                 return 0;
 689         }
 690         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 691                 fv = (fv * 125) / 2;
 692         } else {
 693                 fv = fv * 62500;
 694         }
 695         *vp = fv;
 696         return 0;
 697 }
 698
 699 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 700 {
 701         unsigned long fv;
 702         struct pvr2_hdw *hdw = cptr->hdw;
 703         if (hdw->tuner_signal_stale) {
 704                 pvr2_hdw_status_poll(hdw);
 705         }
 706         fv = hdw->tuner_signal_info.rangelow;
 707         if (!fv) {
 708                 /* Safety fallback */
 709                 *vp = TV_MIN_FREQ;
 710                 return 0;
 711         }
 712         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 713                 fv = (fv * 125) / 2;
 714         } else {
 715                 fv = fv * 62500;
 716         }
 717         *vp = fv;
 718         return 0;
 719 }
 720
 721 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 722 {
 723         return cptr->hdw->enc_stale != 0;
 724 }
 725
 726 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 727 {
 728         cptr->hdw->enc_stale = 0;
 729         cptr->hdw->enc_unsafe_stale = 0;
 730 }
 731
 732 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 733 {
 734         int ret;
 735         struct v4l2_ext_controls cs;
 736         struct v4l2_ext_control c1;
 737         memset(&cs,0,sizeof(cs));
 738         memset(&c1,0,sizeof(c1));
 739         cs.controls = &c1;
 740         cs.count = 1;
 741         c1.id = cptr->info->v4l_id;
 742         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 743                                 VIDIOC_G_EXT_CTRLS);
 744         if (ret) return ret;
 745         *vp = c1.value;
 746         return 0;
 747 }
 748
 749 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 750 {
 751         int ret;
 752         struct pvr2_hdw *hdw = cptr->hdw;
 753         struct v4l2_ext_controls cs;
 754         struct v4l2_ext_control c1;
 755         memset(&cs,0,sizeof(cs));
 756         memset(&c1,0,sizeof(c1));
 757         cs.controls = &c1;
 758         cs.count = 1;
 759         c1.id = cptr->info->v4l_id;
 760         c1.value = v;
 761         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 762                                 hdw->state_encoder_run, &cs,
 763                                 VIDIOC_S_EXT_CTRLS);
 764         if (ret == -EBUSY) {
 765                 /* Oops.  cx2341x is telling us it's not safe to change
 766                    this control while we're capturing.  Make a note of this
 767                    fact so that the pipeline will be stopped the next time
 768                    controls are committed.  Then go on ahead and store this
 769                    change anyway. */
 770                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 771                                         0, &cs,
 772                                         VIDIOC_S_EXT_CTRLS);
 773                 if (!ret) hdw->enc_unsafe_stale = !0;
 774         }
 775         if (ret) return ret;
 776         hdw->enc_stale = !0;
 777         return 0;
 778 }
 779
 780 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 781 {
 782         struct v4l2_queryctrl qctrl;
 783         struct pvr2_ctl_info *info;
 784         qctrl.id = cptr->info->v4l_id;
 785         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 786         /* Strip out the const so we can adjust a function pointer.  It's
 787            OK to do this here because we know this is a dynamically created
 788            control, so the underlying storage for the info pointer is (a)
 789            private to us, and (b) not in read-only storage.  Either we do
 790            this or we significantly complicate the underlying control
 791            implementation. */
 792         info = (struct pvr2_ctl_info *)(cptr->info);
 793         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 794                 if (info->set_value) {
 795                         info->set_value = NULL;
 796                 }
 797         } else {
 798                 if (!(info->set_value)) {
 799                         info->set_value = ctrl_cx2341x_set;
 800                 }
 801         }
 802         return qctrl.flags;
 803 }
 804
 805 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 806 {
 807         *vp = cptr->hdw->state_pipeline_req;
 808         return 0;
 809 }
 810
 811 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 812 {
 813         *vp = cptr->hdw->master_state;
 814         return 0;
 815 }
 816
 817 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 818 {
 819         int result = pvr2_hdw_is_hsm(cptr->hdw);
 820         *vp = PVR2_CVAL_HSM_FULL;
 821         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 822         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 823         return 0;
 824 }
 825
 826 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 827 {
 828         *vp = cptr->hdw->std_mask_avail;
 829         return 0;
 830 }
 831
 832 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 833 {
 834         struct pvr2_hdw *hdw = cptr->hdw;
 835         v4l2_std_id ns;
 836         ns = hdw->std_mask_avail;
 837         ns = (ns & ~m) | (v & m);
 838         if (ns == hdw->std_mask_avail) return 0;
 839         hdw->std_mask_avail = ns;
 840         pvr2_hdw_internal_set_std_avail(hdw);
 841         pvr2_hdw_internal_find_stdenum(hdw);
 842         return 0;
 843 }
 844
 845 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 846                                char *bufPtr,unsigned int bufSize,
 847                                unsigned int *len)
 848 {
 849         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 850         return 0;
 851 }
 852
 853 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 854                                const char *bufPtr,unsigned int bufSize,
 855                                int *mskp,int *valp)
 856 {
 857         int ret;
 858         v4l2_std_id id;
 859         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 860         if (ret < 0) return ret;
 861         if (mskp) *mskp = id;
 862         if (valp) *valp = id;
 863         return 0;
 864 }
 865
 866 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 867 {
 868         *vp = cptr->hdw->std_mask_cur;
 869         return 0;
 870 }
 871
 872 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 873 {
 874         struct pvr2_hdw *hdw = cptr->hdw;
 875         v4l2_std_id ns;
 876         ns = hdw->std_mask_cur;
 877         ns = (ns & ~m) | (v & m);
 878         if (ns == hdw->std_mask_cur) return 0;
 879         hdw->std_mask_cur = ns;
 880         hdw->std_dirty = !0;
 881         pvr2_hdw_internal_find_stdenum(hdw);
 882         return 0;
 883 }
 884
 885 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 886 {
 887         return cptr->hdw->std_dirty != 0;
 888 }
 889
 890 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 891 {
 892         cptr->hdw->std_dirty = 0;
 893 }
 894
 895 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 896 {
 897         struct pvr2_hdw *hdw = cptr->hdw;
 898         pvr2_hdw_status_poll(hdw);
 899         *vp = hdw->tuner_signal_info.signal;
 900         return 0;
 901 }
 902
 903 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 904 {
 905         int val = 0;
 906         unsigned int subchan;
 907         struct pvr2_hdw *hdw = cptr->hdw;
 908         pvr2_hdw_status_poll(hdw);
 909         subchan = hdw->tuner_signal_info.rxsubchans;
 910         if (subchan & V4L2_TUNER_SUB_MONO) {
 911                 val |= (1 << V4L2_TUNER_MODE_MONO);
 912         }
 913         if (subchan & V4L2_TUNER_SUB_STEREO) {
 914                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 915         }
 916         if (subchan & V4L2_TUNER_SUB_LANG1) {
 917                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 918         }
 919         if (subchan & V4L2_TUNER_SUB_LANG2) {
 920                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 921         }
 922         *vp = val;
 923         return 0;
 924 }
 925
 926
 927 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 928 {
 929         struct pvr2_hdw *hdw = cptr->hdw;
 930         if (v < 0) return -EINVAL;
 931         if (v > hdw->std_enum_cnt) return -EINVAL;
 932         hdw->std_enum_cur = v;
 933         if (!v) return 0;
 934         v--;
 935         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 936         hdw->std_mask_cur = hdw->std_defs[v].id;
 937         hdw->std_dirty = !0;
 938         return 0;
 939 }
 940
 941
 942 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 943 {
 944         *vp = cptr->hdw->std_enum_cur;
 945         return 0;
 946 }
 947
 948
 949 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 950 {
 951         return cptr->hdw->std_dirty != 0;
 952 }
 953
 954
 955 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 956 {
 957         cptr->hdw->std_dirty = 0;
 958 }
 959
 960
 961 #define DEFINT(vmin,vmax) \
 962         .type = pvr2_ctl_int, \
 963         .def.type_int.min_value = vmin, \
 964         .def.type_int.max_value = vmax
 965
 966 #define DEFENUM(tab) \
 967         .type = pvr2_ctl_enum, \
 968         .def.type_enum.count = ARRAY_SIZE(tab), \
 969         .def.type_enum.value_names = tab
 970
 971 #define DEFBOOL \
 972         .type = pvr2_ctl_bool
 973
 974 #define DEFMASK(msk,tab) \
 975         .type = pvr2_ctl_bitmask, \
 976         .def.type_bitmask.valid_bits = msk, \
 977         .def.type_bitmask.bit_names = tab
 978
 979 #define DEFREF(vname) \
 980         .set_value = ctrl_set_##vname, \
 981         .get_value = ctrl_get_##vname, \
 982         .is_dirty = ctrl_isdirty_##vname, \
 983         .clear_dirty = ctrl_cleardirty_##vname
 984
 985
 986 #define VCREATE_FUNCS(vname) \
 987 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 988 {*vp = cptr->hdw->vname##_val; return 0;} \
 989 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 990 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 991 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 992 {return cptr->hdw->vname##_dirty != 0;} \
 993 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 994 {cptr->hdw->vname##_dirty = 0;}
 995
 996 VCREATE_FUNCS(brightness)
 997 VCREATE_FUNCS(contrast)
 998 VCREATE_FUNCS(saturation)
 999 VCREATE_FUNCS(hue)
1000 VCREATE_FUNCS(volume)
1001 VCREATE_FUNCS(balance)
1002 VCREATE_FUNCS(bass)
1003 VCREATE_FUNCS(treble)
1004 VCREATE_FUNCS(mute)
1005 VCREATE_FUNCS(cropl)
1006 VCREATE_FUNCS(cropt)
1007 VCREATE_FUNCS(cropw)
1008 VCREATE_FUNCS(croph)
1009 VCREATE_FUNCS(audiomode)
1010 VCREATE_FUNCS(res_hor)
1011 VCREATE_FUNCS(res_ver)
1012 VCREATE_FUNCS(srate)
1013
1014 /* Table definition of all controls which can be manipulated */
1015 static const struct pvr2_ctl_info control_defs[] = {
1016         {
1017                 .v4l_id = V4L2_CID_BRIGHTNESS,
1018                 .desc = "Brightness",
1019                 .name = "brightness",
1020                 .default_value = 128,
1021                 DEFREF(brightness),
1022                 DEFINT(0,255),
1023         },{
1024                 .v4l_id = V4L2_CID_CONTRAST,
1025                 .desc = "Contrast",
1026                 .name = "contrast",
1027                 .default_value = 68,
1028                 DEFREF(contrast),
1029                 DEFINT(0,127),
1030         },{
1031                 .v4l_id = V4L2_CID_SATURATION,
1032                 .desc = "Saturation",
1033                 .name = "saturation",
1034                 .default_value = 64,
1035                 DEFREF(saturation),
1036                 DEFINT(0,127),
1037         },{
1038                 .v4l_id = V4L2_CID_HUE,
1039                 .desc = "Hue",
1040                 .name = "hue",
1041                 .default_value = 0,
1042                 DEFREF(hue),
1043                 DEFINT(-128,127),
1044         },{
1045                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1046                 .desc = "Volume",
1047                 .name = "volume",
1048                 .default_value = 62000,
1049                 DEFREF(volume),
1050                 DEFINT(0,65535),
1051         },{
1052                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1053                 .desc = "Balance",
1054                 .name = "balance",
1055                 .default_value = 0,
1056                 DEFREF(balance),
1057                 DEFINT(-32768,32767),
1058         },{
1059                 .v4l_id = V4L2_CID_AUDIO_BASS,
1060                 .desc = "Bass",
1061                 .name = "bass",
1062                 .default_value = 0,
1063                 DEFREF(bass),
1064                 DEFINT(-32768,32767),
1065         },{
1066                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1067                 .desc = "Treble",
1068                 .name = "treble",
1069                 .default_value = 0,
1070                 DEFREF(treble),
1071                 DEFINT(-32768,32767),
1072         },{
1073                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1074                 .desc = "Mute",
1075                 .name = "mute",
1076                 .default_value = 0,
1077                 DEFREF(mute),
1078                 DEFBOOL,
1079         }, {
1080                 .desc = "Capture crop left margin",
1081                 .name = "crop_left",
1082                 .internal_id = PVR2_CID_CROPL,
1083                 .default_value = 0,
1084                 DEFREF(cropl),
1085                 DEFINT(-129, 340),
1086                 .get_min_value = ctrl_cropl_min_get,
1087                 .get_max_value = ctrl_cropl_max_get,
1088                 .get_def_value = ctrl_get_cropcapdl,
1089         }, {
1090                 .desc = "Capture crop top margin",
1091                 .name = "crop_top",
1092                 .internal_id = PVR2_CID_CROPT,
1093                 .default_value = 0,
1094                 DEFREF(cropt),
1095                 DEFINT(-35, 544),
1096                 .get_min_value = ctrl_cropt_min_get,
1097                 .get_max_value = ctrl_cropt_max_get,
1098                 .get_def_value = ctrl_get_cropcapdt,
1099         }, {
1100                 .desc = "Capture crop width",
1101                 .name = "crop_width",
1102                 .internal_id = PVR2_CID_CROPW,
1103                 .default_value = 720,
1104                 DEFREF(cropw),
1105                 .get_max_value = ctrl_cropw_max_get,
1106                 .get_def_value = ctrl_get_cropcapdw,
1107         }, {
1108                 .desc = "Capture crop height",
1109                 .name = "crop_height",
1110                 .internal_id = PVR2_CID_CROPH,
1111                 .default_value = 480,
1112                 DEFREF(croph),
1113                 .get_max_value = ctrl_croph_max_get,
1114                 .get_def_value = ctrl_get_cropcapdh,
1115         }, {
1116                 .desc = "Capture capability pixel aspect numerator",
1117                 .name = "cropcap_pixel_numerator",
1118                 .internal_id = PVR2_CID_CROPCAPPAN,
1119                 .get_value = ctrl_get_cropcappan,
1120         }, {
1121                 .desc = "Capture capability pixel aspect denominator",
1122                 .name = "cropcap_pixel_denominator",
1123                 .internal_id = PVR2_CID_CROPCAPPAD,
1124                 .get_value = ctrl_get_cropcappad,
1125         }, {
1126                 .desc = "Capture capability bounds top",
1127                 .name = "cropcap_bounds_top",
1128                 .internal_id = PVR2_CID_CROPCAPBT,
1129                 .get_value = ctrl_get_cropcapbt,
1130         }, {
1131                 .desc = "Capture capability bounds left",
1132                 .name = "cropcap_bounds_left",
1133                 .internal_id = PVR2_CID_CROPCAPBL,
1134                 .get_value = ctrl_get_cropcapbl,
1135         }, {
1136                 .desc = "Capture capability bounds width",
1137                 .name = "cropcap_bounds_width",
1138                 .internal_id = PVR2_CID_CROPCAPBW,
1139                 .get_value = ctrl_get_cropcapbw,
1140         }, {
1141                 .desc = "Capture capability bounds height",
1142                 .name = "cropcap_bounds_height",
1143                 .internal_id = PVR2_CID_CROPCAPBH,
1144                 .get_value = ctrl_get_cropcapbh,
1145         },{
1146                 .desc = "Video Source",
1147                 .name = "input",
1148                 .internal_id = PVR2_CID_INPUT,
1149                 .default_value = PVR2_CVAL_INPUT_TV,
1150                 .check_value = ctrl_check_input,
1151                 DEFREF(input),
1152                 DEFENUM(control_values_input),
1153         },{
1154                 .desc = "Audio Mode",
1155                 .name = "audio_mode",
1156                 .internal_id = PVR2_CID_AUDIOMODE,
1157                 .default_value = V4L2_TUNER_MODE_STEREO,
1158                 DEFREF(audiomode),
1159                 DEFENUM(control_values_audiomode),
1160         },{
1161                 .desc = "Horizontal capture resolution",
1162                 .name = "resolution_hor",
1163                 .internal_id = PVR2_CID_HRES,
1164                 .default_value = 720,
1165                 DEFREF(res_hor),
1166                 DEFINT(19,720),
1167         },{
1168                 .desc = "Vertical capture resolution",
1169                 .name = "resolution_ver",
1170                 .internal_id = PVR2_CID_VRES,
1171                 .default_value = 480,
1172                 DEFREF(res_ver),
1173                 DEFINT(17,576),
1174                 /* Hook in check for video standard and adjust maximum
1175                    depending on the standard. */
1176                 .get_max_value = ctrl_vres_max_get,
1177                 .get_min_value = ctrl_vres_min_get,
1178         },{
1179                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1180                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1181                 .desc = "Audio Sampling Frequency",
1182                 .name = "srate",
1183                 DEFREF(srate),
1184                 DEFENUM(control_values_srate),
1185         },{
1186                 .desc = "Tuner Frequency (Hz)",
1187                 .name = "frequency",
1188                 .internal_id = PVR2_CID_FREQUENCY,
1189                 .default_value = 0,
1190                 .set_value = ctrl_freq_set,
1191                 .get_value = ctrl_freq_get,
1192                 .is_dirty = ctrl_freq_is_dirty,
1193                 .clear_dirty = ctrl_freq_clear_dirty,
1194                 DEFINT(0,0),
1195                 /* Hook in check for input value (tv/radio) and adjust
1196                    max/min values accordingly */
1197                 .get_max_value = ctrl_freq_max_get,
1198                 .get_min_value = ctrl_freq_min_get,
1199         },{
1200                 .desc = "Channel",
1201                 .name = "channel",
1202                 .set_value = ctrl_channel_set,
1203                 .get_value = ctrl_channel_get,
1204                 DEFINT(0,FREQTABLE_SIZE),
1205         },{
1206                 .desc = "Channel Program Frequency",
1207                 .name = "freq_table_value",
1208                 .set_value = ctrl_channelfreq_set,
1209                 .get_value = ctrl_channelfreq_get,
1210                 DEFINT(0,0),
1211                 /* Hook in check for input value (tv/radio) and adjust
1212                    max/min values accordingly */
1213                 .get_max_value = ctrl_freq_max_get,
1214                 .get_min_value = ctrl_freq_min_get,
1215         },{
1216                 .desc = "Channel Program ID",
1217                 .name = "freq_table_channel",
1218                 .set_value = ctrl_channelprog_set,
1219                 .get_value = ctrl_channelprog_get,
1220                 DEFINT(0,FREQTABLE_SIZE),
1221         },{
1222                 .desc = "Streaming Enabled",
1223                 .name = "streaming_enabled",
1224                 .get_value = ctrl_streamingenabled_get,
1225                 DEFBOOL,
1226         },{
1227                 .desc = "USB Speed",
1228                 .name = "usb_speed",
1229                 .get_value = ctrl_hsm_get,
1230                 DEFENUM(control_values_hsm),
1231         },{
1232                 .desc = "Master State",
1233                 .name = "master_state",
1234                 .get_value = ctrl_masterstate_get,
1235                 DEFENUM(pvr2_state_names),
1236         },{
1237                 .desc = "Signal Present",
1238                 .name = "signal_present",
1239                 .get_value = ctrl_signal_get,
1240                 DEFINT(0,65535),
1241         },{
1242                 .desc = "Audio Modes Present",
1243                 .name = "audio_modes_present",
1244                 .get_value = ctrl_audio_modes_present_get,
1245                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1246                    v4l.  Nothing outside of this module cares about this,
1247                    but I reuse it in order to also reuse the
1248                    control_values_audiomode string table. */
1249                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1250                          (1 << V4L2_TUNER_MODE_STEREO)|
1251                          (1 << V4L2_TUNER_MODE_LANG1)|
1252                          (1 << V4L2_TUNER_MODE_LANG2)),
1253                         control_values_audiomode),
1254         },{
1255                 .desc = "Video Standards Available Mask",
1256                 .name = "video_standard_mask_available",
1257                 .internal_id = PVR2_CID_STDAVAIL,
1258                 .skip_init = !0,
1259                 .get_value = ctrl_stdavail_get,
1260                 .set_value = ctrl_stdavail_set,
1261                 .val_to_sym = ctrl_std_val_to_sym,
1262                 .sym_to_val = ctrl_std_sym_to_val,
1263                 .type = pvr2_ctl_bitmask,
1264         },{
1265                 .desc = "Video Standards In Use Mask",
1266                 .name = "video_standard_mask_active",
1267                 .internal_id = PVR2_CID_STDCUR,
1268                 .skip_init = !0,
1269                 .get_value = ctrl_stdcur_get,
1270                 .set_value = ctrl_stdcur_set,
1271                 .is_dirty = ctrl_stdcur_is_dirty,
1272                 .clear_dirty = ctrl_stdcur_clear_dirty,
1273                 .val_to_sym = ctrl_std_val_to_sym,
1274                 .sym_to_val = ctrl_std_sym_to_val,
1275                 .type = pvr2_ctl_bitmask,
1276         },{
1277                 .desc = "Video Standard Name",
1278                 .name = "video_standard",
1279                 .internal_id = PVR2_CID_STDENUM,
1280                 .skip_init = !0,
1281                 .get_value = ctrl_stdenumcur_get,
1282                 .set_value = ctrl_stdenumcur_set,
1283                 .is_dirty = ctrl_stdenumcur_is_dirty,
1284                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1285                 .type = pvr2_ctl_enum,
1286         }
1287 };
1288
1289 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1290
1291
1292 const char *pvr2_config_get_name(enum pvr2_config cfg)
1293 {
1294         switch (cfg) {
1295         case pvr2_config_empty: return "empty";
1296         case pvr2_config_mpeg: return "mpeg";
1297         case pvr2_config_vbi: return "vbi";
1298         case pvr2_config_pcm: return "pcm";
1299         case pvr2_config_rawvideo: return "raw video";
1300         }
1301         return "<unknown>";
1302 }
1303
1304
1305 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1306 {
1307         return hdw->usb_dev;
1308 }
1309
1310
1311 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1312 {
1313         return hdw->serial_number;
1314 }
1315
1316
1317 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1318 {
1319         return hdw->bus_info;
1320 }
1321
1322
1323 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1324 {
1325         return hdw->identifier;
1326 }
1327
1328
1329 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1330 {
1331         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1332 }
1333
1334 /* Set the currently tuned frequency and account for all possible
1335    driver-core side effects of this action. */
1336 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1337 {
1338         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1339                 if (hdw->freqSelector) {
1340                         /* Swing over to radio frequency selection */
1341                         hdw->freqSelector = 0;
1342                         hdw->freqDirty = !0;
1343                 }
1344                 if (hdw->freqValRadio != val) {
1345                         hdw->freqValRadio = val;
1346                         hdw->freqSlotRadio = 0;
1347                         hdw->freqDirty = !0;
1348                 }
1349         } else {
1350                 if (!(hdw->freqSelector)) {
1351                         /* Swing over to television frequency selection */
1352                         hdw->freqSelector = 1;
1353                         hdw->freqDirty = !0;
1354                 }
1355                 if (hdw->freqValTelevision != val) {
1356                         hdw->freqValTelevision = val;
1357                         hdw->freqSlotTelevision = 0;
1358                         hdw->freqDirty = !0;
1359                 }
1360         }
1361 }
1362
1363 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1364 {
1365         return hdw->unit_number;
1366 }
1367
1368
1369 /* Attempt to locate one of the given set of files.  Messages are logged
1370    appropriate to what has been found.  The return value will be 0 or
1371    greater on success (it will be the index of the file name found) and
1372    fw_entry will be filled in.  Otherwise a negative error is returned on
1373    failure.  If the return value is -ENOENT then no viable firmware file
1374    could be located. */
1375 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1376                                 const struct firmware **fw_entry,
1377                                 const char *fwtypename,
1378                                 unsigned int fwcount,
1379                                 const char *fwnames[])
1380 {
1381         unsigned int idx;
1382         int ret = -EINVAL;
1383         for (idx = 0; idx < fwcount; idx++) {
1384                 ret = request_firmware(fw_entry,
1385                                        fwnames[idx],
1386                                        &hdw->usb_dev->dev);
1387                 if (!ret) {
1388                         trace_firmware("Located %s firmware: %s;"
1389                                        " uploading...",
1390                                        fwtypename,
1391                                        fwnames[idx]);
1392                         return idx;
1393                 }
1394                 if (ret == -ENOENT) continue;
1395                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396                            "request_firmware fatal error with code=%d",ret);
1397                 return ret;
1398         }
1399         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1400                    "***WARNING***"
1401                    " Device %s firmware"
1402                    " seems to be missing.",
1403                    fwtypename);
1404         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1405                    "Did you install the pvrusb2 firmware files"
1406                    " in their proper location?");
1407         if (fwcount == 1) {
1408                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1409                            "request_firmware unable to locate %s file %s",
1410                            fwtypename,fwnames[0]);
1411         } else {
1412                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1413                            "request_firmware unable to locate"
1414                            " one of the following %s files:",
1415                            fwtypename);
1416                 for (idx = 0; idx < fwcount; idx++) {
1417                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1418                                    "request_firmware: Failed to find %s",
1419                                    fwnames[idx]);
1420                 }
1421         }
1422         return ret;
1423 }
1424
1425
1426 /*
1427  * pvr2_upload_firmware1().
1428  *
1429  * Send the 8051 firmware to the device.  After the upload, arrange for
1430  * device to re-enumerate.
1431  *
1432  * NOTE : the pointer to the firmware data given by request_firmware()
1433  * is not suitable for an usb transaction.
1434  *
1435  */
1436 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1437 {
1438         const struct firmware *fw_entry = NULL;
1439         void  *fw_ptr;
1440         unsigned int pipe;
1441         int ret;
1442         u16 address;
1443
1444         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1445                 hdw->fw1_state = FW1_STATE_OK;
1446                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1447                            "Connected device type defines"
1448                            " no firmware to upload; ignoring firmware");
1449                 return -ENOTTY;
1450         }
1451
1452         hdw->fw1_state = FW1_STATE_FAILED; // default result
1453
1454         trace_firmware("pvr2_upload_firmware1");
1455
1456         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1457                                    hdw->hdw_desc->fx2_firmware.cnt,
1458                                    hdw->hdw_desc->fx2_firmware.lst);
1459         if (ret < 0) {
1460                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1461                 return ret;
1462         }
1463
1464         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1465
1466         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1467
1468         if (fw_entry->size != 0x2000){
1469                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1470                 release_firmware(fw_entry);
1471                 return -ENOMEM;
1472         }
1473
1474         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1475         if (fw_ptr == NULL){
1476                 release_firmware(fw_entry);
1477                 return -ENOMEM;
1478         }
1479
1480         /* We have to hold the CPU during firmware upload. */
1481         pvr2_hdw_cpureset_assert(hdw,1);
1482
1483         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1484            chunk. */
1485
1486         ret = 0;
1487         for(address = 0; address < fw_entry->size; address += 0x800) {
1488                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1489                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1490                                        0, fw_ptr, 0x800, HZ);
1491         }
1492
1493         trace_firmware("Upload done, releasing device's CPU");
1494
1495         /* Now release the CPU.  It will disconnect and reconnect later. */
1496         pvr2_hdw_cpureset_assert(hdw,0);
1497
1498         kfree(fw_ptr);
1499         release_firmware(fw_entry);
1500
1501         trace_firmware("Upload done (%d bytes sent)",ret);
1502
1503         /* We should have written 8192 bytes */
1504         if (ret == 8192) {
1505                 hdw->fw1_state = FW1_STATE_RELOAD;
1506                 return 0;
1507         }
1508
1509         return -EIO;
1510 }
1511
1512
1513 /*
1514  * pvr2_upload_firmware2()
1515  *
1516  * This uploads encoder firmware on endpoint 2.
1517  *
1518  */
1519
1520 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1521 {
1522         const struct firmware *fw_entry = NULL;
1523         void  *fw_ptr;
1524         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1525         int actual_length;
1526         int ret = 0;
1527         int fwidx;
1528         static const char *fw_files[] = {
1529                 CX2341X_FIRM_ENC_FILENAME,
1530         };
1531
1532         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1533                 return 0;
1534         }
1535
1536         trace_firmware("pvr2_upload_firmware2");
1537
1538         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1539                                    ARRAY_SIZE(fw_files), fw_files);
1540         if (ret < 0) return ret;
1541         fwidx = ret;
1542         ret = 0;
1543         /* Since we're about to completely reinitialize the encoder,
1544            invalidate our cached copy of its configuration state.  Next
1545            time we configure the encoder, then we'll fully configure it. */
1546         hdw->enc_cur_valid = 0;
1547
1548         /* Encoder is about to be reset so note that as far as we're
1549            concerned now, the encoder has never been run. */
1550         del_timer_sync(&hdw->encoder_run_timer);
1551         if (hdw->state_encoder_runok) {
1552                 hdw->state_encoder_runok = 0;
1553                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1554         }
1555
1556         /* First prepare firmware loading */
1557         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1558         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1559         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1560         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1561         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1562         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1563         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1564         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1565         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1566         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1567         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1568         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1569         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1570         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1571         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1572         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1573         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1574         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1575
1576         if (ret) {
1577                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1578                            "firmware2 upload prep failed, ret=%d",ret);
1579                 release_firmware(fw_entry);
1580                 goto done;
1581         }
1582
1583         /* Now send firmware */
1584
1585         fw_len = fw_entry->size;
1586
1587         if (fw_len % sizeof(u32)) {
1588                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1589                            "size of %s firmware"
1590                            " must be a multiple of %zu bytes",
1591                            fw_files[fwidx],sizeof(u32));
1592                 release_firmware(fw_entry);
1593                 ret = -EINVAL;
1594                 goto done;
1595         }
1596
1597         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1598         if (fw_ptr == NULL){
1599                 release_firmware(fw_entry);
1600                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1601                            "failed to allocate memory for firmware2 upload");
1602                 ret = -ENOMEM;
1603                 goto done;
1604         }
1605
1606         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1607
1608         fw_done = 0;
1609         for (fw_done = 0; fw_done < fw_len;) {
1610                 bcnt = fw_len - fw_done;
1611                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1612                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1613                 /* Usbsnoop log shows that we must swap bytes... */
1614                 /* Some background info: The data being swapped here is a
1615                    firmware image destined for the mpeg encoder chip that
1616                    lives at the other end of a USB endpoint.  The encoder
1617                    chip always talks in 32 bit chunks and its storage is
1618                    organized into 32 bit words.  However from the file
1619                    system to the encoder chip everything is purely a byte
1620                    stream.  The firmware file's contents are always 32 bit
1621                    swapped from what the encoder expects.  Thus the need
1622                    always exists to swap the bytes regardless of the endian
1623                    type of the host processor and therefore swab32() makes
1624                    the most sense. */
1625                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1626                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1627
1628                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1629                                     &actual_length, HZ);
1630                 ret |= (actual_length != bcnt);
1631                 if (ret) break;
1632                 fw_done += bcnt;
1633         }
1634
1635         trace_firmware("upload of %s : %i / %i ",
1636                        fw_files[fwidx],fw_done,fw_len);
1637
1638         kfree(fw_ptr);
1639         release_firmware(fw_entry);
1640
1641         if (ret) {
1642                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1643                            "firmware2 upload transfer failure");
1644                 goto done;
1645         }
1646
1647         /* Finish upload */
1648
1649         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1650         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1651         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1652
1653         if (ret) {
1654                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1655                            "firmware2 upload post-proc failure");
1656         }
1657
1658  done:
1659         if (hdw->hdw_desc->signal_routing_scheme ==
1660             PVR2_ROUTING_SCHEME_GOTVIEW) {
1661                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1662                    hardware. */
1663                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1664         }
1665         return ret;
1666 }
1667
1668
1669 static const char *pvr2_get_state_name(unsigned int st)
1670 {
1671         if (st < ARRAY_SIZE(pvr2_state_names)) {
1672                 return pvr2_state_names[st];
1673         }
1674         return "???";
1675 }
1676
1677 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1678 {
1679         /* Even though we really only care about the video decoder chip at
1680            this point, we'll broadcast stream on/off to all sub-devices
1681            anyway, just in case somebody else wants to hear the
1682            command... */
1683         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1684                    (enablefl ? "on" : "off"));
1685         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1686         if (hdw->decoder_client_id) {
1687                 /* We get here if the encoder has been noticed.  Otherwise
1688                    we'll issue a warning to the user (which should
1689                    normally never happen). */
1690                 return 0;
1691         }
1692         if (!hdw->flag_decoder_missed) {
1693                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694                            "WARNING: No decoder present");
1695                 hdw->flag_decoder_missed = !0;
1696                 trace_stbit("flag_decoder_missed",
1697                             hdw->flag_decoder_missed);
1698         }
1699         return -EIO;
1700 }
1701
1702
1703 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1704 {
1705         return hdw->master_state;
1706 }
1707
1708
1709 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1710 {
1711         if (!hdw->flag_tripped) return 0;
1712         hdw->flag_tripped = 0;
1713         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1714                    "Clearing driver error statuss");
1715         return !0;
1716 }
1717
1718
1719 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1720 {
1721         int fl;
1722         LOCK_TAKE(hdw->big_lock); do {
1723                 fl = pvr2_hdw_untrip_unlocked(hdw);
1724         } while (0); LOCK_GIVE(hdw->big_lock);
1725         if (fl) pvr2_hdw_state_sched(hdw);
1726         return 0;
1727 }
1728
1729
1730
1731
1732 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1733 {
1734         return hdw->state_pipeline_req != 0;
1735 }
1736
1737
1738 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1739 {
1740         int ret,st;
1741         LOCK_TAKE(hdw->big_lock); do {
1742                 pvr2_hdw_untrip_unlocked(hdw);
1743                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1744                         hdw->state_pipeline_req = enable_flag != 0;
1745                         pvr2_trace(PVR2_TRACE_START_STOP,
1746                                    "/*--TRACE_STREAM--*/ %s",
1747                                    enable_flag ? "enable" : "disable");
1748                 }
1749                 pvr2_hdw_state_sched(hdw);
1750         } while (0); LOCK_GIVE(hdw->big_lock);
1751         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1752         if (enable_flag) {
1753                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1754                         if (st != PVR2_STATE_READY) return -EIO;
1755                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1756                 }
1757         }
1758         return 0;
1759 }
1760
1761
1762 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1763 {
1764         int fl;
1765         LOCK_TAKE(hdw->big_lock);
1766         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1767                 hdw->desired_stream_type = config;
1768                 hdw->state_pipeline_config = 0;
1769                 trace_stbit("state_pipeline_config",
1770                             hdw->state_pipeline_config);
1771                 pvr2_hdw_state_sched(hdw);
1772         }
1773         LOCK_GIVE(hdw->big_lock);
1774         if (fl) return 0;
1775         return pvr2_hdw_wait(hdw,0);
1776 }
1777
1778
1779 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1780 {
1781         int unit_number = hdw->unit_number;
1782         int tp = -1;
1783         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1784                 tp = tuner[unit_number];
1785         }
1786         if (tp < 0) return -EINVAL;
1787         hdw->tuner_type = tp;
1788         hdw->tuner_updated = !0;
1789         return 0;
1790 }
1791
1792
1793 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1794 {
1795         int unit_number = hdw->unit_number;
1796         int tp = 0;
1797         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1798                 tp = video_std[unit_number];
1799                 if (tp) return tp;
1800         }
1801         return 0;
1802 }
1803
1804
1805 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1806 {
1807         int unit_number = hdw->unit_number;
1808         int tp = 0;
1809         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810                 tp = tolerance[unit_number];
1811         }
1812         return tp;
1813 }
1814
1815
1816 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1817 {
1818         /* Try a harmless request to fetch the eeprom's address over
1819            endpoint 1.  See what happens.  Only the full FX2 image can
1820            respond to this.  If this probe fails then likely the FX2
1821            firmware needs be loaded. */
1822         int result;
1823         LOCK_TAKE(hdw->ctl_lock); do {
1824                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1825                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1826                                            hdw->cmd_buffer,1,
1827                                            hdw->cmd_buffer,1);
1828                 if (result < 0) break;
1829         } while(0); LOCK_GIVE(hdw->ctl_lock);
1830         if (result) {
1831                 pvr2_trace(PVR2_TRACE_INIT,
1832                            "Probe of device endpoint 1 result status %d",
1833                            result);
1834         } else {
1835                 pvr2_trace(PVR2_TRACE_INIT,
1836                            "Probe of device endpoint 1 succeeded");
1837         }
1838         return result == 0;
1839 }
1840
1841 struct pvr2_std_hack {
1842         v4l2_std_id pat;  /* Pattern to match */
1843         v4l2_std_id msk;  /* Which bits we care about */
1844         v4l2_std_id std;  /* What additional standards or default to set */
1845 };
1846
1847 /* This data structure labels specific combinations of standards from
1848    tveeprom that we'll try to recognize.  If we recognize one, then assume
1849    a specified default standard to use.  This is here because tveeprom only
1850    tells us about available standards not the intended default standard (if
1851    any) for the device in question.  We guess the default based on what has
1852    been reported as available.  Note that this is only for guessing a
1853    default - which can always be overridden explicitly - and if the user
1854    has otherwise named a default then that default will always be used in
1855    place of this table. */
1856 static const struct pvr2_std_hack std_eeprom_maps[] = {
1857         {       /* PAL(B/G) */
1858                 .pat = V4L2_STD_B|V4L2_STD_GH,
1859                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1860         },
1861         {       /* NTSC(M) */
1862                 .pat = V4L2_STD_MN,
1863                 .std = V4L2_STD_NTSC_M,
1864         },
1865         {       /* PAL(I) */
1866                 .pat = V4L2_STD_PAL_I,
1867                 .std = V4L2_STD_PAL_I,
1868         },
1869         {       /* SECAM(L/L') */
1870                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1871                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1872         },
1873         {       /* PAL(D/D1/K) */
1874                 .pat = V4L2_STD_DK,
1875                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1876         },
1877 };
1878
1879 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1880 {
1881         char buf[40];
1882         unsigned int bcnt;
1883         v4l2_std_id std1,std2,std3;
1884
1885         std1 = get_default_standard(hdw);
1886         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1887
1888         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1889         pvr2_trace(PVR2_TRACE_STD,
1890                    "Supported video standard(s) reported available"
1891                    " in hardware: %.*s",
1892                    bcnt,buf);
1893
1894         hdw->std_mask_avail = hdw->std_mask_eeprom;
1895
1896         std2 = (std1|std3) & ~hdw->std_mask_avail;
1897         if (std2) {
1898                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1899                 pvr2_trace(PVR2_TRACE_STD,
1900                            "Expanding supported video standards"
1901                            " to include: %.*s",
1902                            bcnt,buf);
1903                 hdw->std_mask_avail |= std2;
1904         }
1905
1906         pvr2_hdw_internal_set_std_avail(hdw);
1907
1908         if (std1) {
1909                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1910                 pvr2_trace(PVR2_TRACE_STD,
1911                            "Initial video standard forced to %.*s",
1912                            bcnt,buf);
1913                 hdw->std_mask_cur = std1;
1914                 hdw->std_dirty = !0;
1915                 pvr2_hdw_internal_find_stdenum(hdw);
1916                 return;
1917         }
1918         if (std3) {
1919                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1920                 pvr2_trace(PVR2_TRACE_STD,
1921                            "Initial video standard"
1922                            " (determined by device type): %.*s",bcnt,buf);
1923                 hdw->std_mask_cur = std3;
1924                 hdw->std_dirty = !0;
1925                 pvr2_hdw_internal_find_stdenum(hdw);
1926                 return;
1927         }
1928
1929         {
1930                 unsigned int idx;
1931                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1932                         if (std_eeprom_maps[idx].msk ?
1933                             ((std_eeprom_maps[idx].pat ^
1934                              hdw->std_mask_eeprom) &
1935                              std_eeprom_maps[idx].msk) :
1936                             (std_eeprom_maps[idx].pat !=
1937                              hdw->std_mask_eeprom)) continue;
1938                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1939                                                   std_eeprom_maps[idx].std);
1940                         pvr2_trace(PVR2_TRACE_STD,
1941                                    "Initial video standard guessed as %.*s",
1942                                    bcnt,buf);
1943                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1944                         hdw->std_dirty = !0;
1945                         pvr2_hdw_internal_find_stdenum(hdw);
1946                         return;
1947                 }
1948         }
1949
1950         if (hdw->std_enum_cnt > 1) {
1951                 // Autoselect the first listed standard
1952                 hdw->std_enum_cur = 1;
1953                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1954                 hdw->std_dirty = !0;
1955                 pvr2_trace(PVR2_TRACE_STD,
1956                            "Initial video standard auto-selected to %s",
1957                            hdw->std_defs[hdw->std_enum_cur-1].name);
1958                 return;
1959         }
1960
1961         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1962                    "Unable to select a viable initial video standard");
1963 }
1964
1965
1966 static unsigned int pvr2_copy_i2c_addr_list(
1967         unsigned short *dst, const unsigned char *src,
1968         unsigned int dst_max)
1969 {
1970         unsigned int cnt = 0;
1971         if (!src) return 0;
1972         while (src[cnt] && (cnt + 1) < dst_max) {
1973                 dst[cnt] = src[cnt];
1974                 cnt++;
1975         }
1976         dst[cnt] = I2C_CLIENT_END;
1977         return cnt;
1978 }
1979
1980
1981 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1982                                 const struct pvr2_device_client_desc *cd)
1983 {
1984         const char *fname;
1985         unsigned char mid;
1986         struct v4l2_subdev *sd;
1987         unsigned int i2ccnt;
1988         const unsigned char *p;
1989         /* Arbitrary count - max # i2c addresses we will probe */
1990         unsigned short i2caddr[25];
1991
1992         mid = cd->module_id;
1993         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1994         if (!fname) {
1995                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1996                            "Module ID %u for device %s has no name",
1997                            mid,
1998                            hdw->hdw_desc->description);
1999                 return -EINVAL;
2000         }
2001         pvr2_trace(PVR2_TRACE_INIT,
2002                    "Module ID %u (%s) for device %s being loaded...",
2003                    mid, fname,
2004                    hdw->hdw_desc->description);
2005
2006         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2007                                          ARRAY_SIZE(i2caddr));
2008         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2009                          module_i2c_addresses[mid] : NULL) != NULL)) {
2010                 /* Second chance: Try default i2c address list */
2011                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2012                                                  ARRAY_SIZE(i2caddr));
2013                 if (i2ccnt) {
2014                         pvr2_trace(PVR2_TRACE_INIT,
2015                                    "Module ID %u:"
2016                                    " Using default i2c address list",
2017                                    mid);
2018                 }
2019         }
2020
2021         if (!i2ccnt) {
2022                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2023                            "Module ID %u (%s) for device %s:"
2024                            " No i2c addresses",
2025                            mid, fname, hdw->hdw_desc->description);
2026                 return -EINVAL;
2027         }
2028
2029         /* Note how the 2nd and 3rd arguments are the same for both
2030          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2031          * Well the 2nd argument is the module name to load, while the 3rd
2032          * argument is documented in the framework as being the "chipid" -
2033          * and every other place where I can find examples of this, the
2034          * "chipid" appears to just be the module name again.  So here we
2035          * just do the same thing. */
2036         if (i2ccnt == 1) {
2037                 pvr2_trace(PVR2_TRACE_INIT,
2038                            "Module ID %u:"
2039                            " Setting up with specified i2c address 0x%x",
2040                            mid, i2caddr[0]);
2041                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2042                                          fname, fname,
2043                                          i2caddr[0]);
2044         } else {
2045                 pvr2_trace(PVR2_TRACE_INIT,
2046                            "Module ID %u:"
2047                            " Setting up with address probe list",
2048                            mid);
2049                 sd = v4l2_i2c_new_probed_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2050                                                 fname, fname,
2051                                                 i2caddr);
2052         }
2053
2054         if (!sd) {
2055                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2056                            "Module ID %u (%s) for device %s failed to load",
2057                            mid, fname, hdw->hdw_desc->description);
2058                 return -EIO;
2059         }
2060
2061         /* Tag this sub-device instance with the module ID we know about.
2062            In other places we'll use that tag to determine if the instance
2063            requires special handling. */
2064         sd->grp_id = mid;
2065
2066         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2067
2068
2069         /* client-specific setup... */
2070         switch (mid) {
2071         case PVR2_CLIENT_ID_CX25840:
2072                 hdw->decoder_client_id = mid;
2073                 {
2074                         /*
2075                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2076                           bit of nuttiness for cx25840 causes that module
2077                           to correctly set up its video scaling.  This is
2078                           really a problem in the cx25840 module itself,
2079                           but we work around it here.  The problem has not
2080                           been seen in ivtv because there VBI is supported
2081                           and set up.  We don't do VBI here (at least not
2082                           yet) and thus we never attempted to even set it
2083                           up.
2084                         */
2085                         struct v4l2_format fmt;
2086                         pvr2_trace(PVR2_TRACE_INIT,
2087                                    "Module ID %u:"
2088                                    " Executing cx25840 VBI hack",
2089                                    mid);
2090                         memset(&fmt, 0, sizeof(fmt));
2091                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2092                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2093                                              video, s_fmt, &fmt);
2094                 }
2095                 break;
2096         case PVR2_CLIENT_ID_SAA7115:
2097                 hdw->decoder_client_id = mid;
2098                 break;
2099         default: break;
2100         }
2101
2102         return 0;
2103 }
2104
2105
2106 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2107 {
2108         unsigned int idx;
2109         const struct pvr2_string_table *cm;
2110         const struct pvr2_device_client_table *ct;
2111         int okFl = !0;
2112
2113         cm = &hdw->hdw_desc->client_modules;
2114         for (idx = 0; idx < cm->cnt; idx++) {
2115                 request_module(cm->lst[idx]);
2116         }
2117
2118         ct = &hdw->hdw_desc->client_table;
2119         for (idx = 0; idx < ct->cnt; idx++) {
2120                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2121         }
2122         if (!okFl) pvr2_hdw_render_useless(hdw);
2123 }
2124
2125
2126 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2127 {
2128         int ret;
2129         unsigned int idx;
2130         struct pvr2_ctrl *cptr;
2131         int reloadFl = 0;
2132         if (hdw->hdw_desc->fx2_firmware.cnt) {
2133                 if (!reloadFl) {
2134                         reloadFl =
2135                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2136                                  == 0);
2137                         if (reloadFl) {
2138                                 pvr2_trace(PVR2_TRACE_INIT,
2139                                            "USB endpoint config looks strange"
2140                                            "; possibly firmware needs to be"
2141                                            " loaded");
2142                         }
2143                 }
2144                 if (!reloadFl) {
2145                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2146                         if (reloadFl) {
2147                                 pvr2_trace(PVR2_TRACE_INIT,
2148                                            "Check for FX2 firmware failed"
2149                                            "; possibly firmware needs to be"
2150                                            " loaded");
2151                         }
2152                 }
2153                 if (reloadFl) {
2154                         if (pvr2_upload_firmware1(hdw) != 0) {
2155                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2156                                            "Failure uploading firmware1");
2157                         }
2158                         return;
2159                 }
2160         }
2161         hdw->fw1_state = FW1_STATE_OK;
2162
2163         if (!pvr2_hdw_dev_ok(hdw)) return;
2164
2165         hdw->force_dirty = !0;
2166
2167         if (!hdw->hdw_desc->flag_no_powerup) {
2168                 pvr2_hdw_cmd_powerup(hdw);
2169                 if (!pvr2_hdw_dev_ok(hdw)) return;
2170         }
2171
2172         /* Take the IR chip out of reset, if appropriate */
2173         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2174                 pvr2_issue_simple_cmd(hdw,
2175                                       FX2CMD_HCW_ZILOG_RESET |
2176                                       (1 << 8) |
2177                                       ((0) << 16));
2178         }
2179
2180         // This step MUST happen after the earlier powerup step.
2181         pvr2_i2c_core_init(hdw);
2182         if (!pvr2_hdw_dev_ok(hdw)) return;
2183
2184         pvr2_hdw_load_modules(hdw);
2185         if (!pvr2_hdw_dev_ok(hdw)) return;
2186
2187         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2188
2189         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2190                 cptr = hdw->controls + idx;
2191                 if (cptr->info->skip_init) continue;
2192                 if (!cptr->info->set_value) continue;
2193                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2194         }
2195
2196         /* Set up special default values for the television and radio
2197            frequencies here.  It's not really important what these defaults
2198            are, but I set them to something usable in the Chicago area just
2199            to make driver testing a little easier. */
2200
2201         hdw->freqValTelevision = default_tv_freq;
2202         hdw->freqValRadio = default_radio_freq;
2203
2204         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2205         // thread-safe against the normal pvr2_send_request() mechanism.
2206         // (We should make it thread safe).
2207
2208         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2209                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2210                 if (!pvr2_hdw_dev_ok(hdw)) return;
2211                 if (ret < 0) {
2212                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2213                                    "Unable to determine location of eeprom,"
2214                                    " skipping");
2215                 } else {
2216                         hdw->eeprom_addr = ret;
2217                         pvr2_eeprom_analyze(hdw);
2218                         if (!pvr2_hdw_dev_ok(hdw)) return;
2219                 }
2220         } else {
2221                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2222                 hdw->tuner_updated = !0;
2223                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2224         }
2225
2226         if (hdw->serial_number) {
2227                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2228                                 "sn-%lu", hdw->serial_number);
2229         } else if (hdw->unit_number >= 0) {
2230                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2231                                 "unit-%c",
2232                                 hdw->unit_number + 'a');
2233         } else {
2234                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2235                                 "unit-??");
2236         }
2237         hdw->identifier[idx] = 0;
2238
2239         pvr2_hdw_setup_std(hdw);
2240
2241         if (!get_default_tuner_type(hdw)) {
2242                 pvr2_trace(PVR2_TRACE_INIT,
2243                            "pvr2_hdw_setup: Tuner type overridden to %d",
2244                            hdw->tuner_type);
2245         }
2246
2247
2248         if (!pvr2_hdw_dev_ok(hdw)) return;
2249
2250         if (hdw->hdw_desc->signal_routing_scheme ==
2251             PVR2_ROUTING_SCHEME_GOTVIEW) {
2252                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2253                    hardware. */
2254                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2255         }
2256
2257         pvr2_hdw_commit_setup(hdw);
2258
2259         hdw->vid_stream = pvr2_stream_create();
2260         if (!pvr2_hdw_dev_ok(hdw)) return;
2261         pvr2_trace(PVR2_TRACE_INIT,
2262                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2263         if (hdw->vid_stream) {
2264                 idx = get_default_error_tolerance(hdw);
2265                 if (idx) {
2266                         pvr2_trace(PVR2_TRACE_INIT,
2267                                    "pvr2_hdw_setup: video stream %p"
2268                                    " setting tolerance %u",
2269                                    hdw->vid_stream,idx);
2270                 }
2271                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2272                                   PVR2_VID_ENDPOINT,idx);
2273         }
2274
2275         if (!pvr2_hdw_dev_ok(hdw)) return;
2276
2277         hdw->flag_init_ok = !0;
2278
2279         pvr2_hdw_state_sched(hdw);
2280 }
2281
2282
2283 /* Set up the structure and attempt to put the device into a usable state.
2284    This can be a time-consuming operation, which is why it is not done
2285    internally as part of the create() step. */
2286 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2287 {
2288         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2289         do {
2290                 pvr2_hdw_setup_low(hdw);
2291                 pvr2_trace(PVR2_TRACE_INIT,
2292                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2293                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2294                 if (pvr2_hdw_dev_ok(hdw)) {
2295                         if (hdw->flag_init_ok) {
2296                                 pvr2_trace(
2297                                         PVR2_TRACE_INFO,
2298                                         "Device initialization"
2299                                         " completed successfully.");
2300                                 break;
2301                         }
2302                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2303                                 pvr2_trace(
2304                                         PVR2_TRACE_INFO,
2305                                         "Device microcontroller firmware"
2306                                         " (re)loaded; it should now reset"
2307                                         " and reconnect.");
2308                                 break;
2309                         }
2310                         pvr2_trace(
2311                                 PVR2_TRACE_ERROR_LEGS,
2312                                 "Device initialization was not successful.");
2313                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2314                                 pvr2_trace(
2315                                         PVR2_TRACE_ERROR_LEGS,
2316                                         "Giving up since device"
2317                                         " microcontroller firmware"
2318                                         " appears to be missing.");
2319                                 break;
2320                         }
2321                 }
2322                 if (procreload) {
2323                         pvr2_trace(
2324                                 PVR2_TRACE_ERROR_LEGS,
2325                                 "Attempting pvrusb2 recovery by reloading"
2326                                 " primary firmware.");
2327                         pvr2_trace(
2328                                 PVR2_TRACE_ERROR_LEGS,
2329                                 "If this works, device should disconnect"
2330                                 " and reconnect in a sane state.");
2331                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2332                         pvr2_upload_firmware1(hdw);
2333                 } else {
2334                         pvr2_trace(
2335                                 PVR2_TRACE_ERROR_LEGS,
2336                                 "***WARNING*** pvrusb2 device hardware"
2337                                 " appears to be jammed"
2338                                 " and I can't clear it.");
2339                         pvr2_trace(
2340                                 PVR2_TRACE_ERROR_LEGS,
2341                                 "You might need to power cycle"
2342                                 " the pvrusb2 device"
2343                                 " in order to recover.");
2344                 }
2345         } while (0);
2346         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2347 }
2348
2349
2350 /* Perform second stage initialization.  Set callback pointer first so that
2351    we can avoid a possible initialization race (if the kernel thread runs
2352    before the callback has been set). */
2353 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2354                         void (*callback_func)(void *),
2355                         void *callback_data)
2356 {
2357         LOCK_TAKE(hdw->big_lock); do {
2358                 if (hdw->flag_disconnected) {
2359                         /* Handle a race here: If we're already
2360                            disconnected by this point, then give up.  If we
2361                            get past this then we'll remain connected for
2362                            the duration of initialization since the entire
2363                            initialization sequence is now protected by the
2364                            big_lock. */
2365                         break;
2366                 }
2367                 hdw->state_data = callback_data;
2368                 hdw->state_func = callback_func;
2369                 pvr2_hdw_setup(hdw);
2370         } while (0); LOCK_GIVE(hdw->big_lock);
2371         return hdw->flag_init_ok;
2372 }
2373
2374
2375 /* Create, set up, and return a structure for interacting with the
2376    underlying hardware.  */
2377 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2378                                  const struct usb_device_id *devid)
2379 {
2380         unsigned int idx,cnt1,cnt2,m;
2381         struct pvr2_hdw *hdw = NULL;
2382         int valid_std_mask;
2383         struct pvr2_ctrl *cptr;
2384         struct usb_device *usb_dev;
2385         const struct pvr2_device_desc *hdw_desc;
2386         __u8 ifnum;
2387         struct v4l2_queryctrl qctrl;
2388         struct pvr2_ctl_info *ciptr;
2389
2390         usb_dev = interface_to_usbdev(intf);
2391
2392         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2393
2394         if (hdw_desc == NULL) {
2395                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2396                            " No device description pointer,"
2397                            " unable to continue.");
2398                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2399                            " please contact Mike Isely <isely@pobox.com>"
2400                            " to get it included in the driver\n");
2401                 goto fail;
2402         }
2403
2404         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2405         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2406                    hdw,hdw_desc->description);
2407         if (!hdw) goto fail;
2408
2409         init_timer(&hdw->quiescent_timer);
2410         hdw->quiescent_timer.data = (unsigned long)hdw;
2411         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2412
2413         init_timer(&hdw->encoder_wait_timer);
2414         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2415         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2416
2417         init_timer(&hdw->encoder_run_timer);
2418         hdw->encoder_run_timer.data = (unsigned long)hdw;
2419         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2420
2421         hdw->master_state = PVR2_STATE_DEAD;
2422
2423         init_waitqueue_head(&hdw->state_wait_data);
2424
2425         hdw->tuner_signal_stale = !0;
2426         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2427
2428         /* Calculate which inputs are OK */
2429         m = 0;
2430         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2431         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2432                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2433         }
2434         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2435         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2436         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2437         hdw->input_avail_mask = m;
2438         hdw->input_allowed_mask = hdw->input_avail_mask;
2439
2440         /* If not a hybrid device, pathway_state never changes.  So
2441            initialize it here to what it should forever be. */
2442         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2443                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2444         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2445                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2446         }
2447
2448         hdw->control_cnt = CTRLDEF_COUNT;
2449         hdw->control_cnt += MPEGDEF_COUNT;
2450         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2451                                 GFP_KERNEL);
2452         if (!hdw->controls) goto fail;
2453         hdw->hdw_desc = hdw_desc;
2454         for (idx = 0; idx < hdw->control_cnt; idx++) {
2455                 cptr = hdw->controls + idx;
2456                 cptr->hdw = hdw;
2457         }
2458         for (idx = 0; idx < 32; idx++) {
2459                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2460         }
2461         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2462                 cptr = hdw->controls + idx;
2463                 cptr->info = control_defs+idx;
2464         }
2465
2466         /* Ensure that default input choice is a valid one. */
2467         m = hdw->input_avail_mask;
2468         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2469                 if (!((1 << idx) & m)) continue;
2470                 hdw->input_val = idx;
2471                 break;
2472         }
2473
2474         /* Define and configure additional controls from cx2341x module. */
2475         hdw->mpeg_ctrl_info = kzalloc(
2476                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2477         if (!hdw->mpeg_ctrl_info) goto fail;
2478         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2479                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2480                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2481                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2482                 ciptr->name = mpeg_ids[idx].strid;
2483                 ciptr->v4l_id = mpeg_ids[idx].id;
2484                 ciptr->skip_init = !0;
2485                 ciptr->get_value = ctrl_cx2341x_get;
2486                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2487                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2488                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2489                 qctrl.id = ciptr->v4l_id;
2490                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2491                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2492                         ciptr->set_value = ctrl_cx2341x_set;
2493                 }
2494                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2495                         PVR2_CTLD_INFO_DESC_SIZE);
2496                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2497                 ciptr->default_value = qctrl.default_value;
2498                 switch (qctrl.type) {
2499                 default:
2500                 case V4L2_CTRL_TYPE_INTEGER:
2501                         ciptr->type = pvr2_ctl_int;
2502                         ciptr->def.type_int.min_value = qctrl.minimum;
2503                         ciptr->def.type_int.max_value = qctrl.maximum;
2504                         break;
2505                 case V4L2_CTRL_TYPE_BOOLEAN:
2506                         ciptr->type = pvr2_ctl_bool;
2507                         break;
2508                 case V4L2_CTRL_TYPE_MENU:
2509                         ciptr->type = pvr2_ctl_enum;
2510                         ciptr->def.type_enum.value_names =
2511                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2512                                                                 ciptr->v4l_id);
2513                         for (cnt1 = 0;
2514                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2515                              cnt1++) { }
2516                         ciptr->def.type_enum.count = cnt1;
2517                         break;
2518                 }
2519                 cptr->info = ciptr;
2520         }
2521
2522         // Initialize video standard enum dynamic control
2523         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2524         if (cptr) {
2525                 memcpy(&hdw->std_info_enum,cptr->info,
2526                        sizeof(hdw->std_info_enum));
2527                 cptr->info = &hdw->std_info_enum;
2528
2529         }
2530         // Initialize control data regarding video standard masks
2531         valid_std_mask = pvr2_std_get_usable();
2532         for (idx = 0; idx < 32; idx++) {
2533                 if (!(valid_std_mask & (1 << idx))) continue;
2534                 cnt1 = pvr2_std_id_to_str(
2535                         hdw->std_mask_names[idx],
2536                         sizeof(hdw->std_mask_names[idx])-1,
2537                         1 << idx);
2538                 hdw->std_mask_names[idx][cnt1] = 0;
2539         }
2540         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2541         if (cptr) {
2542                 memcpy(&hdw->std_info_avail,cptr->info,
2543                        sizeof(hdw->std_info_avail));
2544                 cptr->info = &hdw->std_info_avail;
2545                 hdw->std_info_avail.def.type_bitmask.bit_names =
2546                         hdw->std_mask_ptrs;
2547                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2548                         valid_std_mask;
2549         }
2550         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2551         if (cptr) {
2552                 memcpy(&hdw->std_info_cur,cptr->info,
2553                        sizeof(hdw->std_info_cur));
2554                 cptr->info = &hdw->std_info_cur;
2555                 hdw->std_info_cur.def.type_bitmask.bit_names =
2556                         hdw->std_mask_ptrs;
2557                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2558                         valid_std_mask;
2559         }
2560
2561         hdw->cropcap_stale = !0;
2562         hdw->eeprom_addr = -1;
2563         hdw->unit_number = -1;
2564         hdw->v4l_minor_number_video = -1;
2565         hdw->v4l_minor_number_vbi = -1;
2566         hdw->v4l_minor_number_radio = -1;
2567         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2568         if (!hdw->ctl_write_buffer) goto fail;
2569         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2570         if (!hdw->ctl_read_buffer) goto fail;
2571         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2572         if (!hdw->ctl_write_urb) goto fail;
2573         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2574         if (!hdw->ctl_read_urb) goto fail;
2575
2576         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2577                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2578                            "Error registering with v4l core, giving up");
2579                 goto fail;
2580         }
2581         mutex_lock(&pvr2_unit_mtx); do {
2582                 for (idx = 0; idx < PVR_NUM; idx++) {
2583                         if (unit_pointers[idx]) continue;
2584                         hdw->unit_number = idx;
2585                         unit_pointers[idx] = hdw;
2586                         break;
2587                 }
2588         } while (0); mutex_unlock(&pvr2_unit_mtx);
2589
2590         cnt1 = 0;
2591         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2592         cnt1 += cnt2;
2593         if (hdw->unit_number >= 0) {
2594                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2595                                  ('a' + hdw->unit_number));
2596                 cnt1 += cnt2;
2597         }
2598         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2599         hdw->name[cnt1] = 0;
2600
2601         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2602         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2603
2604         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2605                    hdw->unit_number,hdw->name);
2606
2607         hdw->tuner_type = -1;
2608         hdw->flag_ok = !0;
2609
2610         hdw->usb_intf = intf;
2611         hdw->usb_dev = usb_dev;
2612
2613         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2614
2615         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2616         usb_set_interface(hdw->usb_dev,ifnum,0);
2617
2618         mutex_init(&hdw->ctl_lock_mutex);
2619         mutex_init(&hdw->big_lock_mutex);
2620
2621         return hdw;
2622  fail:
2623         if (hdw) {
2624                 del_timer_sync(&hdw->quiescent_timer);
2625                 del_timer_sync(&hdw->encoder_run_timer);
2626                 del_timer_sync(&hdw->encoder_wait_timer);
2627                 if (hdw->workqueue) {
2628                         flush_workqueue(hdw->workqueue);
2629                         destroy_workqueue(hdw->workqueue);
2630                         hdw->workqueue = NULL;
2631                 }
2632                 usb_free_urb(hdw->ctl_read_urb);
2633                 usb_free_urb(hdw->ctl_write_urb);
2634                 kfree(hdw->ctl_read_buffer);
2635                 kfree(hdw->ctl_write_buffer);
2636                 kfree(hdw->controls);
2637                 kfree(hdw->mpeg_ctrl_info);
2638                 kfree(hdw->std_defs);
2639                 kfree(hdw->std_enum_names);
2640                 kfree(hdw);
2641         }
2642         return NULL;
2643 }
2644
2645
2646 /* Remove _all_ associations between this driver and the underlying USB
2647    layer. */
2648 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2649 {
2650         if (hdw->flag_disconnected) return;
2651         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2652         if (hdw->ctl_read_urb) {
2653                 usb_kill_urb(hdw->ctl_read_urb);
2654                 usb_free_urb(hdw->ctl_read_urb);
2655                 hdw->ctl_read_urb = NULL;
2656         }
2657         if (hdw->ctl_write_urb) {
2658                 usb_kill_urb(hdw->ctl_write_urb);
2659                 usb_free_urb(hdw->ctl_write_urb);
2660                 hdw->ctl_write_urb = NULL;
2661         }
2662         if (hdw->ctl_read_buffer) {
2663                 kfree(hdw->ctl_read_buffer);
2664                 hdw->ctl_read_buffer = NULL;
2665         }
2666         if (hdw->ctl_write_buffer) {
2667                 kfree(hdw->ctl_write_buffer);
2668                 hdw->ctl_write_buffer = NULL;
2669         }
2670         hdw->flag_disconnected = !0;
2671         /* If we don't do this, then there will be a dangling struct device
2672            reference to our disappearing device persisting inside the V4L
2673            core... */
2674         v4l2_device_disconnect(&hdw->v4l2_dev);
2675         hdw->usb_dev = NULL;
2676         hdw->usb_intf = NULL;
2677         pvr2_hdw_render_useless(hdw);
2678 }
2679
2680
2681 /* Destroy hardware interaction structure */
2682 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2683 {
2684         if (!hdw) return;
2685         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2686         if (hdw->workqueue) {
2687                 flush_workqueue(hdw->workqueue);
2688                 destroy_workqueue(hdw->workqueue);
2689                 hdw->workqueue = NULL;
2690         }
2691         del_timer_sync(&hdw->quiescent_timer);
2692         del_timer_sync(&hdw->encoder_run_timer);
2693         del_timer_sync(&hdw->encoder_wait_timer);
2694         if (hdw->fw_buffer) {
2695                 kfree(hdw->fw_buffer);
2696                 hdw->fw_buffer = NULL;
2697         }
2698         if (hdw->vid_stream) {
2699                 pvr2_stream_destroy(hdw->vid_stream);
2700                 hdw->vid_stream = NULL;
2701         }
2702         pvr2_i2c_core_done(hdw);
2703         v4l2_device_unregister(&hdw->v4l2_dev);
2704         pvr2_hdw_remove_usb_stuff(hdw);
2705         mutex_lock(&pvr2_unit_mtx); do {
2706                 if ((hdw->unit_number >= 0) &&
2707                     (hdw->unit_number < PVR_NUM) &&
2708                     (unit_pointers[hdw->unit_number] == hdw)) {
2709                         unit_pointers[hdw->unit_number] = NULL;
2710                 }
2711         } while (0); mutex_unlock(&pvr2_unit_mtx);
2712         kfree(hdw->controls);
2713         kfree(hdw->mpeg_ctrl_info);
2714         kfree(hdw->std_defs);
2715         kfree(hdw->std_enum_names);
2716         kfree(hdw);
2717 }
2718
2719
2720 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2721 {
2722         return (hdw && hdw->flag_ok);
2723 }
2724
2725
2726 /* Called when hardware has been unplugged */
2727 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2728 {
2729         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2730         LOCK_TAKE(hdw->big_lock);
2731         LOCK_TAKE(hdw->ctl_lock);
2732         pvr2_hdw_remove_usb_stuff(hdw);
2733         LOCK_GIVE(hdw->ctl_lock);
2734         LOCK_GIVE(hdw->big_lock);
2735 }
2736
2737
2738 // Attempt to autoselect an appropriate value for std_enum_cur given
2739 // whatever is currently in std_mask_cur
2740 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2741 {
2742         unsigned int idx;
2743         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2744                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2745                         hdw->std_enum_cur = idx;
2746                         return;
2747                 }
2748         }
2749         hdw->std_enum_cur = 0;
2750 }
2751
2752
2753 // Calculate correct set of enumerated standards based on currently known
2754 // set of available standards bits.
2755 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2756 {
2757         struct v4l2_standard *newstd;
2758         unsigned int std_cnt;
2759         unsigned int idx;
2760
2761         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2762
2763         if (hdw->std_defs) {
2764                 kfree(hdw->std_defs);
2765                 hdw->std_defs = NULL;
2766         }
2767         hdw->std_enum_cnt = 0;
2768         if (hdw->std_enum_names) {
2769                 kfree(hdw->std_enum_names);
2770                 hdw->std_enum_names = NULL;
2771         }
2772
2773         if (!std_cnt) {
2774                 pvr2_trace(
2775                         PVR2_TRACE_ERROR_LEGS,
2776                         "WARNING: Failed to identify any viable standards");
2777         }
2778         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2779         hdw->std_enum_names[0] = "none";
2780         for (idx = 0; idx < std_cnt; idx++) {
2781                 hdw->std_enum_names[idx+1] =
2782                         newstd[idx].name;
2783         }
2784         // Set up the dynamic control for this standard
2785         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2786         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2787         hdw->std_defs = newstd;
2788         hdw->std_enum_cnt = std_cnt+1;
2789         hdw->std_enum_cur = 0;
2790         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2791 }
2792
2793
2794 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2795                                struct v4l2_standard *std,
2796                                unsigned int idx)
2797 {
2798         int ret = -EINVAL;
2799         if (!idx) return ret;
2800         LOCK_TAKE(hdw->big_lock); do {
2801                 if (idx >= hdw->std_enum_cnt) break;
2802                 idx--;
2803                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2804                 ret = 0;
2805         } while (0); LOCK_GIVE(hdw->big_lock);
2806         return ret;
2807 }
2808
2809
2810 /* Get the number of defined controls */
2811 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2812 {
2813         return hdw->control_cnt;
2814 }
2815
2816
2817 /* Retrieve a control handle given its index (0..count-1) */
2818 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2819                                              unsigned int idx)
2820 {
2821         if (idx >= hdw->control_cnt) return NULL;
2822         return hdw->controls + idx;
2823 }
2824
2825
2826 /* Retrieve a control handle given its index (0..count-1) */
2827 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2828                                           unsigned int ctl_id)
2829 {
2830         struct pvr2_ctrl *cptr;
2831         unsigned int idx;
2832         int i;
2833
2834         /* This could be made a lot more efficient, but for now... */
2835         for (idx = 0; idx < hdw->control_cnt; idx++) {
2836                 cptr = hdw->controls + idx;
2837                 i = cptr->info->internal_id;
2838                 if (i && (i == ctl_id)) return cptr;
2839         }
2840         return NULL;
2841 }
2842
2843
2844 /* Given a V4L ID, retrieve the control structure associated with it. */
2845 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2846 {
2847         struct pvr2_ctrl *cptr;
2848         unsigned int idx;
2849         int i;
2850
2851         /* This could be made a lot more efficient, but for now... */
2852         for (idx = 0; idx < hdw->control_cnt; idx++) {
2853                 cptr = hdw->controls + idx;
2854                 i = cptr->info->v4l_id;
2855                 if (i && (i == ctl_id)) return cptr;
2856         }
2857         return NULL;
2858 }
2859
2860
2861 /* Given a V4L ID for its immediate predecessor, retrieve the control
2862    structure associated with it. */
2863 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2864                                             unsigned int ctl_id)
2865 {
2866         struct pvr2_ctrl *cptr,*cp2;
2867         unsigned int idx;
2868         int i;
2869
2870         /* This could be made a lot more efficient, but for now... */
2871         cp2 = NULL;
2872         for (idx = 0; idx < hdw->control_cnt; idx++) {
2873                 cptr = hdw->controls + idx;
2874                 i = cptr->info->v4l_id;
2875                 if (!i) continue;
2876                 if (i <= ctl_id) continue;
2877                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2878                 cp2 = cptr;
2879         }
2880         return cp2;
2881         return NULL;
2882 }
2883
2884
2885 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2886 {
2887         switch (tp) {
2888         case pvr2_ctl_int: return "integer";
2889         case pvr2_ctl_enum: return "enum";
2890         case pvr2_ctl_bool: return "boolean";
2891         case pvr2_ctl_bitmask: return "bitmask";
2892         }
2893         return "";
2894 }
2895
2896
2897 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2898                                     const char *name, int val)
2899 {
2900         struct v4l2_control ctrl;
2901         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2902         memset(&ctrl, 0, sizeof(ctrl));
2903         ctrl.id = id;
2904         ctrl.value = val;
2905         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2906 }
2907
2908 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2909         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2910                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2911         }
2912
2913 /* Execute whatever commands are required to update the state of all the
2914    sub-devices so that they match our current control values. */
2915 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2916 {
2917         struct v4l2_subdev *sd;
2918         unsigned int id;
2919         pvr2_subdev_update_func fp;
2920
2921         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2922
2923         if (hdw->tuner_updated || hdw->force_dirty) {
2924                 struct tuner_setup setup;
2925                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2926                            hdw->tuner_type);
2927                 if (((int)(hdw->tuner_type)) >= 0) {
2928                         memset(&setup, 0, sizeof(setup));
2929                         setup.addr = ADDR_UNSET;
2930                         setup.type = hdw->tuner_type;
2931                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
2932                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2933                                              tuner, s_type_addr, &setup);
2934                 }
2935         }
2936
2937         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2938                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2939                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2940                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2941                                              tuner, s_radio);
2942                 } else {
2943                         v4l2_std_id vs;
2944                         vs = hdw->std_mask_cur;
2945                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2946                                              core, s_std, vs);
2947                 }
2948                 hdw->tuner_signal_stale = !0;
2949                 hdw->cropcap_stale = !0;
2950         }
2951
2952         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2953         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2954         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2955         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2956         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2957         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2958         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2959         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2960         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2961
2962         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2963                 struct v4l2_tuner vt;
2964                 memset(&vt, 0, sizeof(vt));
2965                 vt.audmode = hdw->audiomode_val;
2966                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2967         }
2968
2969         if (hdw->freqDirty || hdw->force_dirty) {
2970                 unsigned long fv;
2971                 struct v4l2_frequency freq;
2972                 fv = pvr2_hdw_get_cur_freq(hdw);
2973                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2974                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2975                 memset(&freq, 0, sizeof(freq));
2976                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2977                         /* ((fv * 1000) / 62500) */
2978                         freq.frequency = (fv * 2) / 125;
2979                 } else {
2980                         freq.frequency = fv / 62500;
2981                 }
2982                 /* tuner-core currently doesn't seem to care about this, but
2983                    let's set it anyway for completeness. */
2984                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2985                         freq.type = V4L2_TUNER_RADIO;
2986                 } else {
2987                         freq.type = V4L2_TUNER_ANALOG_TV;
2988                 }
2989                 freq.tuner = 0;
2990                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2991                                      s_frequency, &freq);
2992         }
2993
2994         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2995                 struct v4l2_format fmt;
2996                 memset(&fmt, 0, sizeof(fmt));
2997                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2998                 fmt.fmt.pix.width = hdw->res_hor_val;
2999                 fmt.fmt.pix.height = hdw->res_ver_val;
3000                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3001                            fmt.fmt.pix.width, fmt.fmt.pix.height);
3002                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3003         }
3004
3005         if (hdw->srate_dirty || hdw->force_dirty) {
3006                 u32 val;
3007                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3008                            hdw->srate_val);
3009                 switch (hdw->srate_val) {
3010                 default:
3011                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3012                         val = 48000;
3013                         break;
3014                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3015                         val = 44100;
3016                         break;
3017                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3018                         val = 32000;
3019                         break;
3020                 }
3021                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3022                                      audio, s_clock_freq, val);
3023         }
3024
3025         /* Unable to set crop parameters; there is apparently no equivalent
3026            for VIDIOC_S_CROP */
3027
3028         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3029                 id = sd->grp_id;
3030                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3031                 fp = pvr2_module_update_functions[id];
3032                 if (!fp) continue;
3033                 (*fp)(hdw, sd);
3034         }
3035
3036         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3037                 pvr2_hdw_status_poll(hdw);
3038         }
3039 }
3040
3041
3042 /* Figure out if we need to commit control changes.  If so, mark internal
3043    state flags to indicate this fact and return true.  Otherwise do nothing
3044    else and return false. */
3045 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3046 {
3047         unsigned int idx;
3048         struct pvr2_ctrl *cptr;
3049         int value;
3050         int commit_flag = hdw->force_dirty;
3051         char buf[100];
3052         unsigned int bcnt,ccnt;
3053
3054         for (idx = 0; idx < hdw->control_cnt; idx++) {
3055                 cptr = hdw->controls + idx;
3056                 if (!cptr->info->is_dirty) continue;
3057                 if (!cptr->info->is_dirty(cptr)) continue;
3058                 commit_flag = !0;
3059
3060                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3061                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3062                                  cptr->info->name);
3063                 value = 0;
3064                 cptr->info->get_value(cptr,&value);
3065                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3066                                                 buf+bcnt,
3067                                                 sizeof(buf)-bcnt,&ccnt);
3068                 bcnt += ccnt;
3069                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3070                                   get_ctrl_typename(cptr->info->type));
3071                 pvr2_trace(PVR2_TRACE_CTL,
3072                            "/*--TRACE_COMMIT--*/ %.*s",
3073                            bcnt,buf);
3074         }
3075
3076         if (!commit_flag) {
3077                 /* Nothing has changed */
3078                 return 0;
3079         }
3080
3081         hdw->state_pipeline_config = 0;
3082         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3083         pvr2_hdw_state_sched(hdw);
3084
3085         return !0;
3086 }
3087
3088
3089 /* Perform all operations needed to commit all control changes.  This must
3090    be performed in synchronization with the pipeline state and is thus
3091    expected to be called as part of the driver's worker thread.  Return
3092    true if commit successful, otherwise return false to indicate that
3093    commit isn't possible at this time. */
3094 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3095 {
3096         unsigned int idx;
3097         struct pvr2_ctrl *cptr;
3098         int disruptive_change;
3099
3100         /* Handle some required side effects when the video standard is
3101            changed.... */
3102         if (hdw->std_dirty) {
3103                 int nvres;
3104                 int gop_size;
3105                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3106                         nvres = 480;
3107                         gop_size = 15;
3108                 } else {
3109                         nvres = 576;
3110                         gop_size = 12;
3111                 }
3112                 /* Rewrite the vertical resolution to be appropriate to the
3113                    video standard that has been selected. */
3114                 if (nvres != hdw->res_ver_val) {
3115                         hdw->res_ver_val = nvres;
3116                         hdw->res_ver_dirty = !0;
3117                 }
3118                 /* Rewrite the GOP size to be appropriate to the video
3119                    standard that has been selected. */
3120                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3121                         struct v4l2_ext_controls cs;
3122                         struct v4l2_ext_control c1;
3123                         memset(&cs, 0, sizeof(cs));
3124                         memset(&c1, 0, sizeof(c1));
3125                         cs.controls = &c1;
3126                         cs.count = 1;
3127                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3128                         c1.value = gop_size;
3129                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3130                                           VIDIOC_S_EXT_CTRLS);
3131                 }
3132         }
3133
3134         if (hdw->input_dirty && hdw->state_pathway_ok &&
3135             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3136               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3137              hdw->pathway_state)) {
3138                 /* Change of mode being asked for... */
3139                 hdw->state_pathway_ok = 0;
3140                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3141         }
3142         if (!hdw->state_pathway_ok) {
3143                 /* Can't commit anything until pathway is ok. */
3144                 return 0;
3145         }
3146         /* The broadcast decoder can only scale down, so if
3147          * res_*_dirty && crop window < output format ==> enlarge crop.
3148          *
3149          * The mpeg encoder receives fields of res_hor_val dots and
3150          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3151          */
3152         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3153                 hdw->cropw_val = hdw->res_hor_val;
3154                 hdw->cropw_dirty = !0;
3155         } else if (hdw->cropw_dirty) {
3156                 hdw->res_hor_dirty = !0;           /* must rescale */
3157                 hdw->res_hor_val = min(720, hdw->cropw_val);
3158         }
3159         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3160                 hdw->croph_val = hdw->res_ver_val;
3161                 hdw->croph_dirty = !0;
3162         } else if (hdw->croph_dirty) {
3163                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3164                 hdw->res_ver_dirty = !0;
3165                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3166         }
3167
3168         /* If any of the below has changed, then we can't do the update
3169            while the pipeline is running.  Pipeline must be paused first
3170            and decoder -> encoder connection be made quiescent before we
3171            can proceed. */
3172         disruptive_change =
3173                 (hdw->std_dirty ||
3174                  hdw->enc_unsafe_stale ||
3175                  hdw->srate_dirty ||
3176                  hdw->res_ver_dirty ||
3177                  hdw->res_hor_dirty ||
3178                  hdw->cropw_dirty ||
3179                  hdw->croph_dirty ||
3180                  hdw->input_dirty ||
3181                  (hdw->active_stream_type != hdw->desired_stream_type));
3182         if (disruptive_change && !hdw->state_pipeline_idle) {
3183                 /* Pipeline is not idle; we can't proceed.  Arrange to
3184                    cause pipeline to stop so that we can try this again
3185                    later.... */
3186                 hdw->state_pipeline_pause = !0;
3187                 return 0;
3188         }
3189
3190         if (hdw->srate_dirty) {
3191                 /* Write new sample rate into control structure since
3192                  * the master copy is stale.  We must track srate
3193                  * separate from the mpeg control structure because
3194                  * other logic also uses this value. */
3195                 struct v4l2_ext_controls cs;
3196                 struct v4l2_ext_control c1;
3197                 memset(&cs,0,sizeof(cs));
3198                 memset(&c1,0,sizeof(c1));
3199                 cs.controls = &c1;
3200                 cs.count = 1;
3201                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3202                 c1.value = hdw->srate_val;
3203                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3204         }
3205
3206         if (hdw->active_stream_type != hdw->desired_stream_type) {
3207                 /* Handle any side effects of stream config here */
3208                 hdw->active_stream_type = hdw->desired_stream_type;
3209         }
3210
3211         if (hdw->hdw_desc->signal_routing_scheme ==
3212             PVR2_ROUTING_SCHEME_GOTVIEW) {
3213                 u32 b;
3214                 /* Handle GOTVIEW audio switching */
3215                 pvr2_hdw_gpio_get_out(hdw,&b);
3216                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3217                         /* Set GPIO 11 */
3218                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3219                 } else {
3220                         /* Clear GPIO 11 */
3221                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3222                 }
3223         }
3224
3225         /* Check and update state for all sub-devices. */
3226         pvr2_subdev_update(hdw);
3227
3228         hdw->tuner_updated = 0;
3229         hdw->force_dirty = 0;
3230         for (idx = 0; idx < hdw->control_cnt; idx++) {
3231                 cptr = hdw->controls + idx;
3232                 if (!cptr->info->clear_dirty) continue;
3233                 cptr->info->clear_dirty(cptr);
3234         }
3235
3236         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3237             hdw->state_encoder_run) {
3238                 /* If encoder isn't running or it can't be touched, then
3239                    this will get worked out later when we start the
3240                    encoder. */
3241                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3242         }
3243
3244         hdw->state_pipeline_config = !0;
3245         /* Hardware state may have changed in a way to cause the cropping
3246            capabilities to have changed.  So mark it stale, which will
3247            cause a later re-fetch. */
3248         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3249         return !0;
3250 }
3251
3252
3253 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3254 {
3255         int fl;
3256         LOCK_TAKE(hdw->big_lock);
3257         fl = pvr2_hdw_commit_setup(hdw);
3258         LOCK_GIVE(hdw->big_lock);
3259         if (!fl) return 0;
3260         return pvr2_hdw_wait(hdw,0);
3261 }
3262
3263
3264 static void pvr2_hdw_worker_poll(struct work_struct *work)
3265 {
3266         int fl = 0;
3267         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3268         LOCK_TAKE(hdw->big_lock); do {
3269                 fl = pvr2_hdw_state_eval(hdw);
3270         } while (0); LOCK_GIVE(hdw->big_lock);
3271         if (fl && hdw->state_func) {
3272                 hdw->state_func(hdw->state_data);
3273         }
3274 }
3275
3276
3277 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3278 {
3279         return wait_event_interruptible(
3280                 hdw->state_wait_data,
3281                 (hdw->state_stale == 0) &&
3282                 (!state || (hdw->master_state != state)));
3283 }
3284
3285
3286 /* Return name for this driver instance */
3287 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3288 {
3289         return hdw->name;
3290 }
3291
3292
3293 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3294 {
3295         return hdw->hdw_desc->description;
3296 }
3297
3298
3299 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3300 {
3301         return hdw->hdw_desc->shortname;
3302 }
3303
3304
3305 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3306 {
3307         int result;
3308         LOCK_TAKE(hdw->ctl_lock); do {
3309                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3310                 result = pvr2_send_request(hdw,
3311                                            hdw->cmd_buffer,1,
3312                                            hdw->cmd_buffer,1);
3313                 if (result < 0) break;
3314                 result = (hdw->cmd_buffer[0] != 0);
3315         } while(0); LOCK_GIVE(hdw->ctl_lock);
3316         return result;
3317 }
3318
3319
3320 /* Execute poll of tuner status */
3321 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3322 {
3323         LOCK_TAKE(hdw->big_lock); do {
3324                 pvr2_hdw_status_poll(hdw);
3325         } while (0); LOCK_GIVE(hdw->big_lock);
3326 }
3327
3328
3329 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3330 {
3331         if (!hdw->cropcap_stale) {
3332                 return 0;
3333         }
3334         pvr2_hdw_status_poll(hdw);
3335         if (hdw->cropcap_stale) {
3336                 return -EIO;
3337         }
3338         return 0;
3339 }
3340
3341
3342 /* Return information about cropping capabilities */
3343 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3344 {
3345         int stat = 0;
3346         LOCK_TAKE(hdw->big_lock);
3347         stat = pvr2_hdw_check_cropcap(hdw);
3348         if (!stat) {
3349                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3350         }
3351         LOCK_GIVE(hdw->big_lock);
3352         return stat;
3353 }
3354
3355
3356 /* Return information about the tuner */
3357 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3358 {
3359         LOCK_TAKE(hdw->big_lock); do {
3360                 if (hdw->tuner_signal_stale) {
3361                         pvr2_hdw_status_poll(hdw);
3362                 }
3363                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3364         } while (0); LOCK_GIVE(hdw->big_lock);
3365         return 0;
3366 }
3367
3368
3369 /* Get handle to video output stream */
3370 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3371 {
3372         return hp->vid_stream;
3373 }
3374
3375
3376 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3377 {
3378         int nr = pvr2_hdw_get_unit_number(hdw);
3379         LOCK_TAKE(hdw->big_lock); do {
3380                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3381                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3382                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3383                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3384                 pvr2_hdw_state_log_state(hdw);
3385                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3386         } while (0); LOCK_GIVE(hdw->big_lock);
3387 }
3388
3389
3390 /* Grab EEPROM contents, needed for direct method. */
3391 #define EEPROM_SIZE 8192
3392 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3393 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3394 {
3395         struct i2c_msg msg[2];
3396         u8 *eeprom;
3397         u8 iadd[2];
3398         u8 addr;
3399         u16 eepromSize;
3400         unsigned int offs;
3401         int ret;
3402         int mode16 = 0;
3403         unsigned pcnt,tcnt;
3404         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3405         if (!eeprom) {
3406                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3407                            "Failed to allocate memory"
3408                            " required to read eeprom");
3409                 return NULL;
3410         }
3411
3412         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3413                      hdw->eeprom_addr);
3414         addr = hdw->eeprom_addr;
3415         /* Seems that if the high bit is set, then the *real* eeprom
3416            address is shifted right now bit position (noticed this in
3417            newer PVR USB2 hardware) */
3418         if (addr & 0x80) addr >>= 1;
3419
3420         /* FX2 documentation states that a 16bit-addressed eeprom is
3421            expected if the I2C address is an odd number (yeah, this is
3422            strange but it's what they do) */
3423         mode16 = (addr & 1);
3424         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3425         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3426                      " using %d bit addressing",eepromSize,addr,
3427                      mode16 ? 16 : 8);
3428
3429         msg[0].addr = addr;
3430         msg[0].flags = 0;
3431         msg[0].len = mode16 ? 2 : 1;
3432         msg[0].buf = iadd;
3433         msg[1].addr = addr;
3434         msg[1].flags = I2C_M_RD;
3435
3436         /* We have to do the actual eeprom data fetch ourselves, because
3437            (1) we're only fetching part of the eeprom, and (2) if we were
3438            getting the whole thing our I2C driver can't grab it in one
3439            pass - which is what tveeprom is otherwise going to attempt */
3440         memset(eeprom,0,EEPROM_SIZE);
3441         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3442                 pcnt = 16;
3443                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3444                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3445                 if (mode16) {
3446                         iadd[0] = offs >> 8;
3447                         iadd[1] = offs;
3448                 } else {
3449                         iadd[0] = offs;
3450                 }
3451                 msg[1].len = pcnt;
3452                 msg[1].buf = eeprom+tcnt;
3453                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3454                                         msg,ARRAY_SIZE(msg))) != 2) {
3455                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3456                                    "eeprom fetch set offs err=%d",ret);
3457                         kfree(eeprom);
3458                         return NULL;
3459                 }
3460         }
3461         return eeprom;
3462 }
3463
3464
3465 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3466                                 int prom_flag,
3467                                 int enable_flag)
3468 {
3469         int ret;
3470         u16 address;
3471         unsigned int pipe;
3472         LOCK_TAKE(hdw->big_lock); do {
3473                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3474
3475                 if (!enable_flag) {
3476                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3477                                    "Cleaning up after CPU firmware fetch");
3478                         kfree(hdw->fw_buffer);
3479                         hdw->fw_buffer = NULL;
3480                         hdw->fw_size = 0;
3481                         if (hdw->fw_cpu_flag) {
3482                                 /* Now release the CPU.  It will disconnect
3483                                    and reconnect later. */
3484                                 pvr2_hdw_cpureset_assert(hdw,0);
3485                         }
3486                         break;
3487                 }
3488
3489                 hdw->fw_cpu_flag = (prom_flag == 0);
3490                 if (hdw->fw_cpu_flag) {
3491                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3492                                    "Preparing to suck out CPU firmware");
3493                         hdw->fw_size = 0x2000;
3494                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3495                         if (!hdw->fw_buffer) {
3496                                 hdw->fw_size = 0;
3497                                 break;
3498                         }
3499
3500                         /* We have to hold the CPU during firmware upload. */
3501                         pvr2_hdw_cpureset_assert(hdw,1);
3502
3503                         /* download the firmware from address 0000-1fff in 2048
3504                            (=0x800) bytes chunk. */
3505
3506                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3507                                    "Grabbing CPU firmware");
3508                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3509                         for(address = 0; address < hdw->fw_size;
3510                             address += 0x800) {
3511                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3512                                                       0xa0,0xc0,
3513                                                       address,0,
3514                                                       hdw->fw_buffer+address,
3515                                                       0x800,HZ);
3516                                 if (ret < 0) break;
3517                         }
3518
3519                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3520                                    "Done grabbing CPU firmware");
3521                 } else {
3522                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3523                                    "Sucking down EEPROM contents");
3524                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3525                         if (!hdw->fw_buffer) {
3526                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3527                                            "EEPROM content suck failed.");
3528                                 break;
3529                         }
3530                         hdw->fw_size = EEPROM_SIZE;
3531                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3532                                    "Done sucking down EEPROM contents");
3533                 }
3534
3535         } while (0); LOCK_GIVE(hdw->big_lock);
3536 }
3537
3538
3539 /* Return true if we're in a mode for retrieval CPU firmware */
3540 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3541 {
3542         return hdw->fw_buffer != NULL;
3543 }
3544
3545
3546 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3547                        char *buf,unsigned int cnt)
3548 {
3549         int ret = -EINVAL;
3550         LOCK_TAKE(hdw->big_lock); do {
3551                 if (!buf) break;
3552                 if (!cnt) break;
3553
3554                 if (!hdw->fw_buffer) {
3555                         ret = -EIO;
3556                         break;
3557                 }
3558
3559                 if (offs >= hdw->fw_size) {
3560                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3561                                    "Read firmware data offs=%d EOF",
3562                                    offs);
3563                         ret = 0;
3564                         break;
3565                 }
3566
3567                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3568
3569                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3570
3571                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3572                            "Read firmware data offs=%d cnt=%d",
3573                            offs,cnt);
3574                 ret = cnt;
3575         } while (0); LOCK_GIVE(hdw->big_lock);
3576
3577         return ret;
3578 }
3579
3580
3581 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3582                                   enum pvr2_v4l_type index)
3583 {
3584         switch (index) {
3585         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3586         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3587         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3588         default: return -1;
3589         }
3590 }
3591
3592
3593 /* Store a v4l minor device number */
3594 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3595                                      enum pvr2_v4l_type index,int v)
3596 {
3597         switch (index) {
3598         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3599         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3600         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3601         default: break;
3602         }
3603 }
3604
3605
3606 static void pvr2_ctl_write_complete(struct urb *urb)
3607 {
3608         struct pvr2_hdw *hdw = urb->context;
3609         hdw->ctl_write_pend_flag = 0;
3610         if (hdw->ctl_read_pend_flag) return;
3611         complete(&hdw->ctl_done);
3612 }
3613
3614
3615 static void pvr2_ctl_read_complete(struct urb *urb)
3616 {
3617         struct pvr2_hdw *hdw = urb->context;
3618         hdw->ctl_read_pend_flag = 0;
3619         if (hdw->ctl_write_pend_flag) return;
3620         complete(&hdw->ctl_done);
3621 }
3622
3623
3624 static void pvr2_ctl_timeout(unsigned long data)
3625 {
3626         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3627         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3628                 hdw->ctl_timeout_flag = !0;
3629                 if (hdw->ctl_write_pend_flag)
3630                         usb_unlink_urb(hdw->ctl_write_urb);
3631                 if (hdw->ctl_read_pend_flag)
3632                         usb_unlink_urb(hdw->ctl_read_urb);
3633         }
3634 }
3635
3636
3637 /* Issue a command and get a response from the device.  This extended
3638    version includes a probe flag (which if set means that device errors
3639    should not be logged or treated as fatal) and a timeout in jiffies.
3640    This can be used to non-lethally probe the health of endpoint 1. */
3641 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3642                                 unsigned int timeout,int probe_fl,
3643                                 void *write_data,unsigned int write_len,
3644                                 void *read_data,unsigned int read_len)
3645 {
3646         unsigned int idx;
3647         int status = 0;
3648         struct timer_list timer;
3649         if (!hdw->ctl_lock_held) {
3650                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3651                            "Attempted to execute control transfer"
3652                            " without lock!!");
3653                 return -EDEADLK;
3654         }
3655         if (!hdw->flag_ok && !probe_fl) {
3656                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3657                            "Attempted to execute control transfer"
3658                            " when device not ok");
3659                 return -EIO;
3660         }
3661         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3662                 if (!probe_fl) {
3663                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3664                                    "Attempted to execute control transfer"
3665                                    " when USB is disconnected");
3666                 }
3667                 return -ENOTTY;
3668         }
3669
3670         /* Ensure that we have sane parameters */
3671         if (!write_data) write_len = 0;
3672         if (!read_data) read_len = 0;
3673         if (write_len > PVR2_CTL_BUFFSIZE) {
3674                 pvr2_trace(
3675                         PVR2_TRACE_ERROR_LEGS,
3676                         "Attempted to execute %d byte"
3677                         " control-write transfer (limit=%d)",
3678                         write_len,PVR2_CTL_BUFFSIZE);
3679                 return -EINVAL;
3680         }
3681         if (read_len > PVR2_CTL_BUFFSIZE) {
3682                 pvr2_trace(
3683                         PVR2_TRACE_ERROR_LEGS,
3684                         "Attempted to execute %d byte"
3685                         " control-read transfer (limit=%d)",
3686                         write_len,PVR2_CTL_BUFFSIZE);
3687                 return -EINVAL;
3688         }
3689         if ((!write_len) && (!read_len)) {
3690                 pvr2_trace(
3691                         PVR2_TRACE_ERROR_LEGS,
3692                         "Attempted to execute null control transfer?");
3693                 return -EINVAL;
3694         }
3695
3696
3697         hdw->cmd_debug_state = 1;
3698         if (write_len) {
3699                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3700         } else {
3701                 hdw->cmd_debug_code = 0;
3702         }
3703         hdw->cmd_debug_write_len = write_len;
3704         hdw->cmd_debug_read_len = read_len;
3705
3706         /* Initialize common stuff */
3707         init_completion(&hdw->ctl_done);
3708         hdw->ctl_timeout_flag = 0;
3709         hdw->ctl_write_pend_flag = 0;
3710         hdw->ctl_read_pend_flag = 0;
3711         init_timer(&timer);
3712         timer.expires = jiffies + timeout;
3713         timer.data = (unsigned long)hdw;
3714         timer.function = pvr2_ctl_timeout;
3715
3716         if (write_len) {
3717                 hdw->cmd_debug_state = 2;
3718                 /* Transfer write data to internal buffer */
3719                 for (idx = 0; idx < write_len; idx++) {
3720                         hdw->ctl_write_buffer[idx] =
3721                                 ((unsigned char *)write_data)[idx];
3722                 }
3723                 /* Initiate a write request */
3724                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3725                                   hdw->usb_dev,
3726                                   usb_sndbulkpipe(hdw->usb_dev,
3727                                                   PVR2_CTL_WRITE_ENDPOINT),
3728                                   hdw->ctl_write_buffer,
3729                                   write_len,
3730                                   pvr2_ctl_write_complete,
3731                                   hdw);
3732                 hdw->ctl_write_urb->actual_length = 0;
3733                 hdw->ctl_write_pend_flag = !0;
3734                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3735                 if (status < 0) {
3736                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3737                                    "Failed to submit write-control"
3738                                    " URB status=%d",status);
3739                         hdw->ctl_write_pend_flag = 0;
3740                         goto done;
3741                 }
3742         }
3743
3744         if (read_len) {
3745                 hdw->cmd_debug_state = 3;
3746                 memset(hdw->ctl_read_buffer,0x43,read_len);
3747                 /* Initiate a read request */
3748                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3749                                   hdw->usb_dev,
3750                                   usb_rcvbulkpipe(hdw->usb_dev,
3751                                                   PVR2_CTL_READ_ENDPOINT),
3752                                   hdw->ctl_read_buffer,
3753                                   read_len,
3754                                   pvr2_ctl_read_complete,
3755                                   hdw);
3756                 hdw->ctl_read_urb->actual_length = 0;
3757                 hdw->ctl_read_pend_flag = !0;
3758                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3759                 if (status < 0) {
3760                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3761                                    "Failed to submit read-control"
3762                                    " URB status=%d",status);
3763                         hdw->ctl_read_pend_flag = 0;
3764                         goto done;
3765                 }
3766         }
3767
3768         /* Start timer */
3769         add_timer(&timer);
3770
3771         /* Now wait for all I/O to complete */
3772         hdw->cmd_debug_state = 4;
3773         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3774                 wait_for_completion(&hdw->ctl_done);
3775         }
3776         hdw->cmd_debug_state = 5;
3777
3778         /* Stop timer */
3779         del_timer_sync(&timer);
3780
3781         hdw->cmd_debug_state = 6;
3782         status = 0;
3783
3784         if (hdw->ctl_timeout_flag) {
3785                 status = -ETIMEDOUT;
3786                 if (!probe_fl) {
3787                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3788                                    "Timed out control-write");
3789                 }
3790                 goto done;
3791         }
3792
3793         if (write_len) {
3794                 /* Validate results of write request */
3795                 if ((hdw->ctl_write_urb->status != 0) &&
3796                     (hdw->ctl_write_urb->status != -ENOENT) &&
3797                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3798                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3799                         /* USB subsystem is reporting some kind of failure
3800                            on the write */
3801                         status = hdw->ctl_write_urb->status;
3802                         if (!probe_fl) {
3803                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3804                                            "control-write URB failure,"
3805                                            " status=%d",
3806                                            status);
3807                         }
3808                         goto done;
3809                 }
3810                 if (hdw->ctl_write_urb->actual_length < write_len) {
3811                         /* Failed to write enough data */
3812                         status = -EIO;
3813                         if (!probe_fl) {
3814                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3815                                            "control-write URB short,"
3816                                            " expected=%d got=%d",
3817                                            write_len,
3818                                            hdw->ctl_write_urb->actual_length);
3819                         }
3820                         goto done;
3821                 }
3822         }
3823         if (read_len) {
3824                 /* Validate results of read request */
3825                 if ((hdw->ctl_read_urb->status != 0) &&
3826                     (hdw->ctl_read_urb->status != -ENOENT) &&
3827                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3828                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3829                         /* USB subsystem is reporting some kind of failure
3830                            on the read */
3831                         status = hdw->ctl_read_urb->status;
3832                         if (!probe_fl) {
3833                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3834                                            "control-read URB failure,"
3835                                            " status=%d",
3836                                            status);
3837                         }
3838                         goto done;
3839                 }
3840                 if (hdw->ctl_read_urb->actual_length < read_len) {
3841                         /* Failed to read enough data */
3842                         status = -EIO;
3843                         if (!probe_fl) {
3844                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3845                                            "control-read URB short,"
3846                                            " expected=%d got=%d",
3847                                            read_len,
3848                                            hdw->ctl_read_urb->actual_length);
3849                         }
3850                         goto done;
3851                 }
3852                 /* Transfer retrieved data out from internal buffer */
3853                 for (idx = 0; idx < read_len; idx++) {
3854                         ((unsigned char *)read_data)[idx] =
3855                                 hdw->ctl_read_buffer[idx];
3856                 }
3857         }
3858
3859  done:
3860
3861         hdw->cmd_debug_state = 0;
3862         if ((status < 0) && (!probe_fl)) {
3863                 pvr2_hdw_render_useless(hdw);
3864         }
3865         return status;
3866 }
3867
3868
3869 int pvr2_send_request(struct pvr2_hdw *hdw,
3870                       void *write_data,unsigned int write_len,
3871                       void *read_data,unsigned int read_len)
3872 {
3873         return pvr2_send_request_ex(hdw,HZ*4,0,
3874                                     write_data,write_len,
3875                                     read_data,read_len);
3876 }
3877
3878
3879 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3880 {
3881         int ret;
3882         unsigned int cnt = 1;
3883         unsigned int args = 0;
3884         LOCK_TAKE(hdw->ctl_lock);
3885         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3886         args = (cmdcode >> 8) & 0xffu;
3887         args = (args > 2) ? 2 : args;
3888         if (args) {
3889                 cnt += args;
3890                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3891                 if (args > 1) {
3892                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3893                 }
3894         }
3895         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3896                 unsigned int idx;
3897                 unsigned int ccnt,bcnt;
3898                 char tbuf[50];
3899                 cmdcode &= 0xffu;
3900                 bcnt = 0;
3901                 ccnt = scnprintf(tbuf+bcnt,
3902                                  sizeof(tbuf)-bcnt,
3903                                  "Sending FX2 command 0x%x",cmdcode);
3904                 bcnt += ccnt;
3905                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3906                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3907                                 ccnt = scnprintf(tbuf+bcnt,
3908                                                  sizeof(tbuf)-bcnt,
3909                                                  " \"%s\"",
3910                                                  pvr2_fx2cmd_desc[idx].desc);
3911                                 bcnt += ccnt;
3912                                 break;
3913                         }
3914                 }
3915                 if (args) {
3916                         ccnt = scnprintf(tbuf+bcnt,
3917                                          sizeof(tbuf)-bcnt,
3918                                          " (%u",hdw->cmd_buffer[1]);
3919                         bcnt += ccnt;
3920                         if (args > 1) {
3921                                 ccnt = scnprintf(tbuf+bcnt,
3922                                                  sizeof(tbuf)-bcnt,
3923                                                  ",%u",hdw->cmd_buffer[2]);
3924                                 bcnt += ccnt;
3925                         }
3926                         ccnt = scnprintf(tbuf+bcnt,
3927                                          sizeof(tbuf)-bcnt,
3928                                          ")");
3929                         bcnt += ccnt;
3930                 }
3931                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3932         }
3933         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3934         LOCK_GIVE(hdw->ctl_lock);
3935         return ret;
3936 }
3937
3938
3939 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3940 {
3941         int ret;
3942
3943         LOCK_TAKE(hdw->ctl_lock);
3944
3945         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3946         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3947         hdw->cmd_buffer[5] = 0;
3948         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3949         hdw->cmd_buffer[7] = reg & 0xff;
3950
3951
3952         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3953
3954         LOCK_GIVE(hdw->ctl_lock);
3955
3956         return ret;
3957 }
3958
3959
3960 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3961 {
3962         int ret = 0;
3963
3964         LOCK_TAKE(hdw->ctl_lock);
3965
3966         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3967         hdw->cmd_buffer[1] = 0;
3968         hdw->cmd_buffer[2] = 0;
3969         hdw->cmd_buffer[3] = 0;
3970         hdw->cmd_buffer[4] = 0;
3971         hdw->cmd_buffer[5] = 0;
3972         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3973         hdw->cmd_buffer[7] = reg & 0xff;
3974
3975         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3976         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3977
3978         LOCK_GIVE(hdw->ctl_lock);
3979
3980         return ret;
3981 }
3982
3983
3984 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3985 {
3986         if (!hdw->flag_ok) return;
3987         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3988                    "Device being rendered inoperable");
3989         if (hdw->vid_stream) {
3990                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3991         }
3992         hdw->flag_ok = 0;
3993         trace_stbit("flag_ok",hdw->flag_ok);
3994         pvr2_hdw_state_sched(hdw);
3995 }
3996
3997
3998 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3999 {
4000         int ret;
4001         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4002         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4003         if (ret == 0) {
4004                 ret = usb_reset_device(hdw->usb_dev);
4005                 usb_unlock_device(hdw->usb_dev);
4006         } else {
4007                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4008                            "Failed to lock USB device ret=%d",ret);
4009         }
4010         if (init_pause_msec) {
4011                 pvr2_trace(PVR2_TRACE_INFO,
4012                            "Waiting %u msec for hardware to settle",
4013                            init_pause_msec);
4014                 msleep(init_pause_msec);
4015         }
4016
4017 }
4018
4019
4020 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4021 {
4022         char da[1];
4023         unsigned int pipe;
4024         int ret;
4025
4026         if (!hdw->usb_dev) return;
4027
4028         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4029
4030         da[0] = val ? 0x01 : 0x00;
4031
4032         /* Write the CPUCS register on the 8051.  The lsb of the register
4033            is the reset bit; a 1 asserts reset while a 0 clears it. */
4034         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4035         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4036         if (ret < 0) {
4037                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4038                            "cpureset_assert(%d) error=%d",val,ret);
4039                 pvr2_hdw_render_useless(hdw);
4040         }
4041 }
4042
4043
4044 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4045 {
4046         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4047 }
4048
4049
4050 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4051 {
4052         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4053 }
4054
4055
4056 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4057 {
4058         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4059 }
4060
4061
4062 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4063 {
4064         pvr2_trace(PVR2_TRACE_INIT,
4065                    "Requesting decoder reset");
4066         if (hdw->decoder_client_id) {
4067                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4068                                      core, reset, 0);
4069                 return 0;
4070         }
4071         pvr2_trace(PVR2_TRACE_INIT,
4072                    "Unable to reset decoder: nothing attached");
4073         return -ENOTTY;
4074 }
4075
4076
4077 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4078 {
4079         hdw->flag_ok = !0;
4080         return pvr2_issue_simple_cmd(hdw,
4081                                      FX2CMD_HCW_DEMOD_RESETIN |
4082                                      (1 << 8) |
4083                                      ((onoff ? 1 : 0) << 16));
4084 }
4085
4086
4087 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4088 {
4089         hdw->flag_ok = !0;
4090         return pvr2_issue_simple_cmd(hdw,(onoff ?
4091                                           FX2CMD_ONAIR_DTV_POWER_ON :
4092                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4093 }
4094
4095
4096 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4097                                                 int onoff)
4098 {
4099         return pvr2_issue_simple_cmd(hdw,(onoff ?
4100                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4101                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4102 }
4103
4104
4105 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4106 {
4107         int cmode;
4108         /* Compare digital/analog desired setting with current setting.  If
4109            they don't match, fix it... */
4110         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4111         if (cmode == hdw->pathway_state) {
4112                 /* They match; nothing to do */
4113                 return;
4114         }
4115
4116         switch (hdw->hdw_desc->digital_control_scheme) {
4117         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4118                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4119                 if (cmode == PVR2_PATHWAY_ANALOG) {
4120                         /* If moving to analog mode, also force the decoder
4121                            to reset.  If no decoder is attached, then it's
4122                            ok to ignore this because if/when the decoder
4123                            attaches, it will reset itself at that time. */
4124                         pvr2_hdw_cmd_decoder_reset(hdw);
4125                 }
4126                 break;
4127         case PVR2_DIGITAL_SCHEME_ONAIR:
4128                 /* Supposedly we should always have the power on whether in
4129                    digital or analog mode.  But for now do what appears to
4130                    work... */
4131                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4132                 break;
4133         default: break;
4134         }
4135
4136         pvr2_hdw_untrip_unlocked(hdw);
4137         hdw->pathway_state = cmode;
4138 }
4139
4140
4141 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4142 {
4143         /* change some GPIO data
4144          *
4145          * note: bit d7 of dir appears to control the LED,
4146          * so we shut it off here.
4147          *
4148          */
4149         if (onoff) {
4150                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4151         } else {
4152                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4153         }
4154         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4155 }
4156
4157
4158 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4159
4160 static led_method_func led_methods[] = {
4161         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4162 };
4163
4164
4165 /* Toggle LED */
4166 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4167 {
4168         unsigned int scheme_id;
4169         led_method_func fp;
4170
4171         if ((!onoff) == (!hdw->led_on)) return;
4172
4173         hdw->led_on = onoff != 0;
4174
4175         scheme_id = hdw->hdw_desc->led_scheme;
4176         if (scheme_id < ARRAY_SIZE(led_methods)) {
4177                 fp = led_methods[scheme_id];
4178         } else {
4179                 fp = NULL;
4180         }
4181
4182         if (fp) (*fp)(hdw,onoff);
4183 }
4184
4185
4186 /* Stop / start video stream transport */
4187 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4188 {
4189         int ret;
4190
4191         /* If we're in analog mode, then just issue the usual analog
4192            command. */
4193         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4194                 return pvr2_issue_simple_cmd(hdw,
4195                                              (runFl ?
4196                                               FX2CMD_STREAMING_ON :
4197                                               FX2CMD_STREAMING_OFF));
4198                 /*Note: Not reached */
4199         }
4200
4201         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4202                 /* Whoops, we don't know what mode we're in... */
4203                 return -EINVAL;
4204         }
4205
4206         /* To get here we have to be in digital mode.  The mechanism here
4207            is unfortunately different for different vendors.  So we switch
4208            on the device's digital scheme attribute in order to figure out
4209            what to do. */
4210         switch (hdw->hdw_desc->digital_control_scheme) {
4211         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4212                 return pvr2_issue_simple_cmd(hdw,
4213                                              (runFl ?
4214                                               FX2CMD_HCW_DTV_STREAMING_ON :
4215                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4216         case PVR2_DIGITAL_SCHEME_ONAIR:
4217                 ret = pvr2_issue_simple_cmd(hdw,
4218                                             (runFl ?
4219                                              FX2CMD_STREAMING_ON :
4220                                              FX2CMD_STREAMING_OFF));
4221                 if (ret) return ret;
4222                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4223         default:
4224                 return -EINVAL;
4225         }
4226 }
4227
4228
4229 /* Evaluate whether or not state_pathway_ok can change */
4230 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4231 {
4232         if (hdw->state_pathway_ok) {
4233                 /* Nothing to do if pathway is already ok */
4234                 return 0;
4235         }
4236         if (!hdw->state_pipeline_idle) {
4237                 /* Not allowed to change anything if pipeline is not idle */
4238                 return 0;
4239         }
4240         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4241         hdw->state_pathway_ok = !0;
4242         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4243         return !0;
4244 }
4245
4246
4247 /* Evaluate whether or not state_encoder_ok can change */
4248 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4249 {
4250         if (hdw->state_encoder_ok) return 0;
4251         if (hdw->flag_tripped) return 0;
4252         if (hdw->state_encoder_run) return 0;
4253         if (hdw->state_encoder_config) return 0;
4254         if (hdw->state_decoder_run) return 0;
4255         if (hdw->state_usbstream_run) return 0;
4256         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4257                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4258         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4259                 return 0;
4260         }
4261
4262         if (pvr2_upload_firmware2(hdw) < 0) {
4263                 hdw->flag_tripped = !0;
4264                 trace_stbit("flag_tripped",hdw->flag_tripped);
4265                 return !0;
4266         }
4267         hdw->state_encoder_ok = !0;
4268         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4269         return !0;
4270 }
4271
4272
4273 /* Evaluate whether or not state_encoder_config can change */
4274 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4275 {
4276         if (hdw->state_encoder_config) {
4277                 if (hdw->state_encoder_ok) {
4278                         if (hdw->state_pipeline_req &&
4279                             !hdw->state_pipeline_pause) return 0;
4280                 }
4281                 hdw->state_encoder_config = 0;
4282                 hdw->state_encoder_waitok = 0;
4283                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4284                 /* paranoia - solve race if timer just completed */
4285                 del_timer_sync(&hdw->encoder_wait_timer);
4286         } else {
4287                 if (!hdw->state_pathway_ok ||
4288                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4289                     !hdw->state_encoder_ok ||
4290                     !hdw->state_pipeline_idle ||
4291                     hdw->state_pipeline_pause ||
4292                     !hdw->state_pipeline_req ||
4293                     !hdw->state_pipeline_config) {
4294                         /* We must reset the enforced wait interval if
4295                            anything has happened that might have disturbed
4296                            the encoder.  This should be a rare case. */
4297                         if (timer_pending(&hdw->encoder_wait_timer)) {
4298                                 del_timer_sync(&hdw->encoder_wait_timer);
4299                         }
4300                         if (hdw->state_encoder_waitok) {
4301                                 /* Must clear the state - therefore we did
4302                                    something to a state bit and must also
4303                                    return true. */
4304                                 hdw->state_encoder_waitok = 0;
4305                                 trace_stbit("state_encoder_waitok",
4306                                             hdw->state_encoder_waitok);
4307                                 return !0;
4308                         }
4309                         return 0;
4310                 }
4311                 if (!hdw->state_encoder_waitok) {
4312                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4313                                 /* waitok flag wasn't set and timer isn't
4314                                    running.  Check flag once more to avoid
4315                                    a race then start the timer.  This is
4316                                    the point when we measure out a minimal
4317                                    quiet interval before doing something to
4318                                    the encoder. */
4319                                 if (!hdw->state_encoder_waitok) {
4320                                         hdw->encoder_wait_timer.expires =
4321                                                 jiffies +
4322                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4323                                                  / 1000);
4324                                         add_timer(&hdw->encoder_wait_timer);
4325                                 }
4326                         }
4327                         /* We can't continue until we know we have been
4328                            quiet for the interval measured by this
4329                            timer. */
4330                         return 0;
4331                 }
4332                 pvr2_encoder_configure(hdw);
4333                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4334         }
4335         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4336         return !0;
4337 }
4338
4339
4340 /* Return true if the encoder should not be running. */
4341 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4342 {
4343         if (!hdw->state_encoder_ok) {
4344                 /* Encoder isn't healthy at the moment, so stop it. */
4345                 return !0;
4346         }
4347         if (!hdw->state_pathway_ok) {
4348                 /* Mode is not understood at the moment (i.e. it wants to
4349                    change), so encoder must be stopped. */
4350                 return !0;
4351         }
4352
4353         switch (hdw->pathway_state) {
4354         case PVR2_PATHWAY_ANALOG:
4355                 if (!hdw->state_decoder_run) {
4356                         /* We're in analog mode and the decoder is not
4357                            running; thus the encoder should be stopped as
4358                            well. */
4359                         return !0;
4360                 }
4361                 break;
4362         case PVR2_PATHWAY_DIGITAL:
4363                 if (hdw->state_encoder_runok) {
4364                         /* This is a funny case.  We're in digital mode so
4365                            really the encoder should be stopped.  However
4366                            if it really is running, only kill it after
4367                            runok has been set.  This gives a chance for the
4368                            onair quirk to function (encoder must run
4369                            briefly first, at least once, before onair
4370                            digital streaming can work). */
4371                         return !0;
4372                 }
4373                 break;
4374         default:
4375                 /* Unknown mode; so encoder should be stopped. */
4376                 return !0;
4377         }
4378
4379         /* If we get here, we haven't found a reason to stop the
4380            encoder. */
4381         return 0;
4382 }
4383
4384
4385 /* Return true if the encoder should be running. */
4386 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4387 {
4388         if (!hdw->state_encoder_ok) {
4389                 /* Don't run the encoder if it isn't healthy... */
4390                 return 0;
4391         }
4392         if (!hdw->state_pathway_ok) {
4393                 /* Don't run the encoder if we don't (yet) know what mode
4394                    we need to be in... */
4395                 return 0;
4396         }
4397
4398         switch (hdw->pathway_state) {
4399         case PVR2_PATHWAY_ANALOG:
4400                 if (hdw->state_decoder_run) {
4401                         /* In analog mode, if the decoder is running, then
4402                            run the encoder. */
4403                         return !0;
4404                 }
4405                 break;
4406         case PVR2_PATHWAY_DIGITAL:
4407                 if ((hdw->hdw_desc->digital_control_scheme ==
4408                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4409                     !hdw->state_encoder_runok) {
4410                         /* This is a quirk.  OnAir hardware won't stream
4411                            digital until the encoder has been run at least
4412                            once, for a minimal period of time (empiricially
4413                            measured to be 1/4 second).  So if we're on
4414                            OnAir hardware and the encoder has never been
4415                            run at all, then start the encoder.  Normal
4416                            state machine logic in the driver will
4417                            automatically handle the remaining bits. */
4418                         return !0;
4419                 }
4420                 break;
4421         default:
4422                 /* For completeness (unknown mode; encoder won't run ever) */
4423                 break;
4424         }
4425         /* If we get here, then we haven't found any reason to run the
4426            encoder, so don't run it. */
4427         return 0;
4428 }
4429
4430
4431 /* Evaluate whether or not state_encoder_run can change */
4432 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4433 {
4434         if (hdw->state_encoder_run) {
4435                 if (!state_check_disable_encoder_run(hdw)) return 0;
4436                 if (hdw->state_encoder_ok) {
4437                         del_timer_sync(&hdw->encoder_run_timer);
4438                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4439                 }
4440                 hdw->state_encoder_run = 0;
4441         } else {
4442                 if (!state_check_enable_encoder_run(hdw)) return 0;
4443                 if (pvr2_encoder_start(hdw) < 0) return !0;
4444                 hdw->state_encoder_run = !0;
4445                 if (!hdw->state_encoder_runok) {
4446                         hdw->encoder_run_timer.expires =
4447                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4448                         add_timer(&hdw->encoder_run_timer);
4449                 }
4450         }
4451         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4452         return !0;
4453 }
4454
4455
4456 /* Timeout function for quiescent timer. */
4457 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4458 {
4459         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4460         hdw->state_decoder_quiescent = !0;
4461         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4462         hdw->state_stale = !0;
4463         queue_work(hdw->workqueue,&hdw->workpoll);
4464 }
4465
4466
4467 /* Timeout function for encoder wait timer. */
4468 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4469 {
4470         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4471         hdw->state_encoder_waitok = !0;
4472         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4473         hdw->state_stale = !0;
4474         queue_work(hdw->workqueue,&hdw->workpoll);
4475 }
4476
4477
4478 /* Timeout function for encoder run timer. */
4479 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4480 {
4481         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4482         if (!hdw->state_encoder_runok) {
4483                 hdw->state_encoder_runok = !0;
4484                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4485                 hdw->state_stale = !0;
4486                 queue_work(hdw->workqueue,&hdw->workpoll);
4487         }
4488 }
4489
4490
4491 /* Evaluate whether or not state_decoder_run can change */
4492 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4493 {
4494         if (hdw->state_decoder_run) {
4495                 if (hdw->state_encoder_ok) {
4496                         if (hdw->state_pipeline_req &&
4497                             !hdw->state_pipeline_pause &&
4498                             hdw->state_pathway_ok) return 0;
4499                 }
4500                 if (!hdw->flag_decoder_missed) {
4501                         pvr2_decoder_enable(hdw,0);
4502                 }
4503                 hdw->state_decoder_quiescent = 0;
4504                 hdw->state_decoder_run = 0;
4505                 /* paranoia - solve race if timer just completed */
4506                 del_timer_sync(&hdw->quiescent_timer);
4507         } else {
4508                 if (!hdw->state_decoder_quiescent) {
4509                         if (!timer_pending(&hdw->quiescent_timer)) {
4510                                 /* We don't do something about the
4511                                    quiescent timer until right here because
4512                                    we also want to catch cases where the
4513                                    decoder was already not running (like
4514                                    after initialization) as opposed to
4515                                    knowing that we had just stopped it.
4516                                    The second flag check is here to cover a
4517                                    race - the timer could have run and set
4518                                    this flag just after the previous check
4519                                    but before we did the pending check. */
4520                                 if (!hdw->state_decoder_quiescent) {
4521                                         hdw->quiescent_timer.expires =
4522                                                 jiffies +
4523                                                 (HZ * TIME_MSEC_DECODER_WAIT
4524                                                  / 1000);
4525                                         add_timer(&hdw->quiescent_timer);
4526                                 }
4527                         }
4528                         /* Don't allow decoder to start again until it has
4529                            been quiesced first.  This little detail should
4530                            hopefully further stabilize the encoder. */
4531                         return 0;
4532                 }
4533                 if (!hdw->state_pathway_ok ||
4534                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4535                     !hdw->state_pipeline_req ||
4536                     hdw->state_pipeline_pause ||
4537                     !hdw->state_pipeline_config ||
4538                     !hdw->state_encoder_config ||
4539                     !hdw->state_encoder_ok) return 0;
4540                 del_timer_sync(&hdw->quiescent_timer);
4541                 if (hdw->flag_decoder_missed) return 0;
4542                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4543                 hdw->state_decoder_quiescent = 0;
4544                 hdw->state_decoder_run = !0;
4545         }
4546         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4547         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4548         return !0;
4549 }
4550
4551
4552 /* Evaluate whether or not state_usbstream_run can change */
4553 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4554 {
4555         if (hdw->state_usbstream_run) {
4556                 int fl = !0;
4557                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4558                         fl = (hdw->state_encoder_ok &&
4559                               hdw->state_encoder_run);
4560                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4561                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4562                         fl = hdw->state_encoder_ok;
4563                 }
4564                 if (fl &&
4565                     hdw->state_pipeline_req &&
4566                     !hdw->state_pipeline_pause &&
4567                     hdw->state_pathway_ok) {
4568                         return 0;
4569                 }
4570                 pvr2_hdw_cmd_usbstream(hdw,0);
4571                 hdw->state_usbstream_run = 0;
4572         } else {
4573                 if (!hdw->state_pipeline_req ||
4574                     hdw->state_pipeline_pause ||
4575                     !hdw->state_pathway_ok) return 0;
4576                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4577                         if (!hdw->state_encoder_ok ||
4578                             !hdw->state_encoder_run) return 0;
4579                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4580                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4581                         if (!hdw->state_encoder_ok) return 0;
4582                         if (hdw->state_encoder_run) return 0;
4583                         if (hdw->hdw_desc->digital_control_scheme ==
4584                             PVR2_DIGITAL_SCHEME_ONAIR) {
4585                                 /* OnAir digital receivers won't stream
4586                                    unless the analog encoder has run first.
4587                                    Why?  I have no idea.  But don't even
4588                                    try until we know the analog side is
4589                                    known to have run. */
4590                                 if (!hdw->state_encoder_runok) return 0;
4591                         }
4592                 }
4593                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4594                 hdw->state_usbstream_run = !0;
4595         }
4596         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4597         return !0;
4598 }
4599
4600
4601 /* Attempt to configure pipeline, if needed */
4602 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4603 {
4604         if (hdw->state_pipeline_config ||
4605             hdw->state_pipeline_pause) return 0;
4606         pvr2_hdw_commit_execute(hdw);
4607         return !0;
4608 }
4609
4610
4611 /* Update pipeline idle and pipeline pause tracking states based on other
4612    inputs.  This must be called whenever the other relevant inputs have
4613    changed. */
4614 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4615 {
4616         unsigned int st;
4617         int updatedFl = 0;
4618         /* Update pipeline state */
4619         st = !(hdw->state_encoder_run ||
4620                hdw->state_decoder_run ||
4621                hdw->state_usbstream_run ||
4622                (!hdw->state_decoder_quiescent));
4623         if (!st != !hdw->state_pipeline_idle) {
4624                 hdw->state_pipeline_idle = st;
4625                 updatedFl = !0;
4626         }
4627         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4628                 hdw->state_pipeline_pause = 0;
4629                 updatedFl = !0;
4630         }
4631         return updatedFl;
4632 }
4633
4634
4635 typedef int (*state_eval_func)(struct pvr2_hdw *);
4636
4637 /* Set of functions to be run to evaluate various states in the driver. */
4638 static const state_eval_func eval_funcs[] = {
4639         state_eval_pathway_ok,
4640         state_eval_pipeline_config,
4641         state_eval_encoder_ok,
4642         state_eval_encoder_config,
4643         state_eval_decoder_run,
4644         state_eval_encoder_run,
4645         state_eval_usbstream_run,
4646 };
4647
4648
4649 /* Process various states and return true if we did anything interesting. */
4650 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4651 {
4652         unsigned int i;
4653         int state_updated = 0;
4654         int check_flag;
4655
4656         if (!hdw->state_stale) return 0;
4657         if ((hdw->fw1_state != FW1_STATE_OK) ||
4658             !hdw->flag_ok) {
4659                 hdw->state_stale = 0;
4660                 return !0;
4661         }
4662         /* This loop is the heart of the entire driver.  It keeps trying to
4663            evaluate various bits of driver state until nothing changes for
4664            one full iteration.  Each "bit of state" tracks some global
4665            aspect of the driver, e.g. whether decoder should run, if
4666            pipeline is configured, usb streaming is on, etc.  We separately
4667            evaluate each of those questions based on other driver state to
4668            arrive at the correct running configuration. */
4669         do {
4670                 check_flag = 0;
4671                 state_update_pipeline_state(hdw);
4672                 /* Iterate over each bit of state */
4673                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4674                         if ((*eval_funcs[i])(hdw)) {
4675                                 check_flag = !0;
4676                                 state_updated = !0;
4677                                 state_update_pipeline_state(hdw);
4678                         }
4679                 }
4680         } while (check_flag && hdw->flag_ok);
4681         hdw->state_stale = 0;
4682         trace_stbit("state_stale",hdw->state_stale);
4683         return state_updated;
4684 }
4685
4686
4687 static unsigned int print_input_mask(unsigned int msk,
4688                                      char *buf,unsigned int acnt)
4689 {
4690         unsigned int idx,ccnt;
4691         unsigned int tcnt = 0;
4692         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4693                 if (!((1 << idx) & msk)) continue;
4694                 ccnt = scnprintf(buf+tcnt,
4695                                  acnt-tcnt,
4696                                  "%s%s",
4697                                  (tcnt ? ", " : ""),
4698                                  control_values_input[idx]);
4699                 tcnt += ccnt;
4700         }
4701         return tcnt;
4702 }
4703
4704
4705 static const char *pvr2_pathway_state_name(int id)
4706 {
4707         switch (id) {
4708         case PVR2_PATHWAY_ANALOG: return "analog";
4709         case PVR2_PATHWAY_DIGITAL: return "digital";
4710         default: return "unknown";
4711         }
4712 }
4713
4714
4715 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4716                                              char *buf,unsigned int acnt)
4717 {
4718         switch (which) {
4719         case 0:
4720                 return scnprintf(
4721                         buf,acnt,
4722                         "driver:%s%s%s%s%s <mode=%s>",
4723                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4724                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4725                         (hdw->flag_disconnected ? " <disconnected>" :
4726                          " <connected>"),
4727                         (hdw->flag_tripped ? " <tripped>" : ""),
4728                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4729                         pvr2_pathway_state_name(hdw->pathway_state));
4730
4731         case 1:
4732                 return scnprintf(
4733                         buf,acnt,
4734                         "pipeline:%s%s%s%s",
4735                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4736                         (hdw->state_pipeline_config ?
4737                          " <configok>" : " <stale>"),
4738                         (hdw->state_pipeline_req ? " <req>" : ""),
4739                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4740         case 2:
4741                 return scnprintf(
4742                         buf,acnt,
4743                         "worker:%s%s%s%s%s%s%s",
4744                         (hdw->state_decoder_run ?
4745                          " <decode:run>" :
4746                          (hdw->state_decoder_quiescent ?
4747                           "" : " <decode:stop>")),
4748                         (hdw->state_decoder_quiescent ?
4749                          " <decode:quiescent>" : ""),
4750                         (hdw->state_encoder_ok ?
4751                          "" : " <encode:init>"),
4752                         (hdw->state_encoder_run ?
4753                          (hdw->state_encoder_runok ?
4754                           " <encode:run>" :
4755                           " <encode:firstrun>") :
4756                          (hdw->state_encoder_runok ?
4757                           " <encode:stop>" :
4758                           " <encode:virgin>")),
4759                         (hdw->state_encoder_config ?
4760                          " <encode:configok>" :
4761                          (hdw->state_encoder_waitok ?
4762                           "" : " <encode:waitok>")),
4763                         (hdw->state_usbstream_run ?
4764                          " <usb:run>" : " <usb:stop>"),
4765                         (hdw->state_pathway_ok ?
4766                          " <pathway:ok>" : ""));
4767         case 3:
4768                 return scnprintf(
4769                         buf,acnt,
4770                         "state: %s",
4771                         pvr2_get_state_name(hdw->master_state));
4772         case 4: {
4773                 unsigned int tcnt = 0;
4774                 unsigned int ccnt;
4775
4776                 ccnt = scnprintf(buf,
4777                                  acnt,
4778                                  "Hardware supported inputs: ");
4779                 tcnt += ccnt;
4780                 tcnt += print_input_mask(hdw->input_avail_mask,
4781                                          buf+tcnt,
4782                                          acnt-tcnt);
4783                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4784                         ccnt = scnprintf(buf+tcnt,
4785                                          acnt-tcnt,
4786                                          "; allowed inputs: ");
4787                         tcnt += ccnt;
4788                         tcnt += print_input_mask(hdw->input_allowed_mask,
4789                                                  buf+tcnt,
4790                                                  acnt-tcnt);
4791                 }
4792                 return tcnt;
4793         }
4794         case 5: {
4795                 struct pvr2_stream_stats stats;
4796                 if (!hdw->vid_stream) break;
4797                 pvr2_stream_get_stats(hdw->vid_stream,
4798                                       &stats,
4799                                       0);
4800                 return scnprintf(
4801                         buf,acnt,
4802                         "Bytes streamed=%u"
4803                         " URBs: queued=%u idle=%u ready=%u"
4804                         " processed=%u failed=%u",
4805                         stats.bytes_processed,
4806                         stats.buffers_in_queue,
4807                         stats.buffers_in_idle,
4808                         stats.buffers_in_ready,
4809                         stats.buffers_processed,
4810                         stats.buffers_failed);
4811         }
4812         default: break;
4813         }
4814         return 0;
4815 }
4816
4817
4818 /* Generate report containing info about attached sub-devices and attached
4819    i2c clients, including an indication of which attached i2c clients are
4820    actually sub-devices. */
4821 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4822                                             char *buf, unsigned int acnt)
4823 {
4824         struct v4l2_subdev *sd;
4825         unsigned int tcnt = 0;
4826         unsigned int ccnt;
4827         struct i2c_client *client;
4828         struct list_head *item;
4829         void *cd;
4830         const char *p;
4831         unsigned int id;
4832
4833         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers:");
4834         tcnt += ccnt;
4835         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4836                 id = sd->grp_id;
4837                 p = NULL;
4838                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4839                 if (p) {
4840                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s", p);
4841                         tcnt += ccnt;
4842                 } else {
4843                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4844                                          " (unknown id=%u)", id);
4845                         tcnt += ccnt;
4846                 }
4847         }
4848         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
4849         tcnt += ccnt;
4850
4851         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "I2C clients:\n");
4852         tcnt += ccnt;
4853
4854         mutex_lock(&hdw->i2c_adap.clist_lock);
4855         list_for_each(item, &hdw->i2c_adap.clients) {
4856                 client = list_entry(item, struct i2c_client, list);
4857                 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4858                                  "  %s: i2c=%02x", client->name, client->addr);
4859                 tcnt += ccnt;
4860                 cd = i2c_get_clientdata(client);
4861                 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4862                         if (cd == sd) {
4863                                 id = sd->grp_id;
4864                                 p = NULL;
4865                                 if (id < ARRAY_SIZE(module_names)) {
4866                                         p = module_names[id];
4867                                 }
4868                                 if (p) {
4869                                         ccnt = scnprintf(buf + tcnt,
4870                                                          acnt - tcnt,
4871                                                          " subdev=%s", p);
4872                                         tcnt += ccnt;
4873                                 } else {
4874                                         ccnt = scnprintf(buf + tcnt,
4875                                                          acnt - tcnt,
4876                                                          " subdev= id %u)",
4877                                                          id);
4878                                         tcnt += ccnt;
4879                                 }
4880                                 break;
4881                         }
4882                 }
4883                 ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
4884                 tcnt += ccnt;
4885         }
4886         mutex_unlock(&hdw->i2c_adap.clist_lock);
4887         return tcnt;
4888 }
4889
4890
4891 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4892                                    char *buf,unsigned int acnt)
4893 {
4894         unsigned int bcnt,ccnt,idx;
4895         bcnt = 0;
4896         LOCK_TAKE(hdw->big_lock);
4897         for (idx = 0; ; idx++) {
4898                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4899                 if (!ccnt) break;
4900                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4901                 if (!acnt) break;
4902                 buf[0] = '\n'; ccnt = 1;
4903                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4904         }
4905         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4906         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4907         LOCK_GIVE(hdw->big_lock);
4908         return bcnt;
4909 }
4910
4911
4912 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4913 {
4914         char buf[256];
4915         unsigned int idx, ccnt;
4916         unsigned int lcnt, ucnt;
4917
4918         for (idx = 0; ; idx++) {
4919                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4920                 if (!ccnt) break;
4921                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4922         }
4923         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4924         ucnt = 0;
4925         while (ucnt < ccnt) {
4926                 lcnt = 0;
4927                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4928                         lcnt++;
4929                 }
4930                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4931                 ucnt += lcnt + 1;
4932         }
4933 }
4934
4935
4936 /* Evaluate and update the driver's current state, taking various actions
4937    as appropriate for the update. */
4938 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4939 {
4940         unsigned int st;
4941         int state_updated = 0;
4942         int callback_flag = 0;
4943         int analog_mode;
4944
4945         pvr2_trace(PVR2_TRACE_STBITS,
4946                    "Drive state check START");
4947         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4948                 pvr2_hdw_state_log_state(hdw);
4949         }
4950
4951         /* Process all state and get back over disposition */
4952         state_updated = pvr2_hdw_state_update(hdw);
4953
4954         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4955
4956         /* Update master state based upon all other states. */
4957         if (!hdw->flag_ok) {
4958                 st = PVR2_STATE_DEAD;
4959         } else if (hdw->fw1_state != FW1_STATE_OK) {
4960                 st = PVR2_STATE_COLD;
4961         } else if ((analog_mode ||
4962                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4963                    !hdw->state_encoder_ok) {
4964                 st = PVR2_STATE_WARM;
4965         } else if (hdw->flag_tripped ||
4966                    (analog_mode && hdw->flag_decoder_missed)) {
4967                 st = PVR2_STATE_ERROR;
4968         } else if (hdw->state_usbstream_run &&
4969                    (!analog_mode ||
4970                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4971                 st = PVR2_STATE_RUN;
4972         } else {
4973                 st = PVR2_STATE_READY;
4974         }
4975         if (hdw->master_state != st) {
4976                 pvr2_trace(PVR2_TRACE_STATE,
4977                            "Device state change from %s to %s",
4978                            pvr2_get_state_name(hdw->master_state),
4979                            pvr2_get_state_name(st));
4980                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4981                 hdw->master_state = st;
4982                 state_updated = !0;
4983                 callback_flag = !0;
4984         }
4985         if (state_updated) {
4986                 /* Trigger anyone waiting on any state changes here. */
4987                 wake_up(&hdw->state_wait_data);
4988         }
4989
4990         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4991                 pvr2_hdw_state_log_state(hdw);
4992         }
4993         pvr2_trace(PVR2_TRACE_STBITS,
4994                    "Drive state check DONE callback=%d",callback_flag);
4995
4996         return callback_flag;
4997 }
4998
4999
5000 /* Cause kernel thread to check / update driver state */
5001 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5002 {
5003         if (hdw->state_stale) return;
5004         hdw->state_stale = !0;
5005         trace_stbit("state_stale",hdw->state_stale);
5006         queue_work(hdw->workqueue,&hdw->workpoll);
5007 }
5008
5009
5010 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5011 {
5012         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5013 }
5014
5015
5016 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5017 {
5018         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5019 }
5020
5021
5022 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5023 {
5024         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5025 }
5026
5027
5028 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5029 {
5030         u32 cval,nval;
5031         int ret;
5032         if (~msk) {
5033                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5034                 if (ret) return ret;
5035                 nval = (cval & ~msk) | (val & msk);
5036                 pvr2_trace(PVR2_TRACE_GPIO,
5037                            "GPIO direction changing 0x%x:0x%x"
5038                            " from 0x%x to 0x%x",
5039                            msk,val,cval,nval);
5040         } else {
5041                 nval = val;
5042                 pvr2_trace(PVR2_TRACE_GPIO,
5043                            "GPIO direction changing to 0x%x",nval);
5044         }
5045         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5046 }
5047
5048
5049 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5050 {
5051         u32 cval,nval;
5052         int ret;
5053         if (~msk) {
5054                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5055                 if (ret) return ret;
5056                 nval = (cval & ~msk) | (val & msk);
5057                 pvr2_trace(PVR2_TRACE_GPIO,
5058                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5059                            msk,val,cval,nval);
5060         } else {
5061                 nval = val;
5062                 pvr2_trace(PVR2_TRACE_GPIO,
5063                            "GPIO output changing to 0x%x",nval);
5064         }
5065         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5066 }
5067
5068
5069 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5070 {
5071         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5072         memset(vtp, 0, sizeof(*vtp));
5073         hdw->tuner_signal_stale = 0;
5074         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5075            using v4l2-subdev - therefore we can't support that AT ALL right
5076            now.  (Of course, no sub-drivers seem to implement it either.
5077            But now it's a a chicken and egg problem...) */
5078         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5079                              &hdw->tuner_signal_info);
5080         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5081                    " type=%u strength=%u audio=0x%x cap=0x%x"
5082                    " low=%u hi=%u",
5083                    vtp->type,
5084                    vtp->signal, vtp->rxsubchans, vtp->capability,
5085                    vtp->rangelow, vtp->rangehigh);
5086
5087         /* We have to do this to avoid getting into constant polling if
5088            there's nobody to answer a poll of cropcap info. */
5089         hdw->cropcap_stale = 0;
5090 }
5091
5092
5093 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5094 {
5095         return hdw->input_avail_mask;
5096 }
5097
5098
5099 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5100 {
5101         return hdw->input_allowed_mask;
5102 }
5103
5104
5105 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5106 {
5107         if (hdw->input_val != v) {
5108                 hdw->input_val = v;
5109                 hdw->input_dirty = !0;
5110         }
5111
5112         /* Handle side effects - if we switch to a mode that needs the RF
5113            tuner, then select the right frequency choice as well and mark
5114            it dirty. */
5115         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5116                 hdw->freqSelector = 0;
5117                 hdw->freqDirty = !0;
5118         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5119                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5120                 hdw->freqSelector = 1;
5121                 hdw->freqDirty = !0;
5122         }
5123         return 0;
5124 }
5125
5126
5127 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5128                                unsigned int change_mask,
5129                                unsigned int change_val)
5130 {
5131         int ret = 0;
5132         unsigned int nv,m,idx;
5133         LOCK_TAKE(hdw->big_lock);
5134         do {
5135                 nv = hdw->input_allowed_mask & ~change_mask;
5136                 nv |= (change_val & change_mask);
5137                 nv &= hdw->input_avail_mask;
5138                 if (!nv) {
5139                         /* No legal modes left; return error instead. */
5140                         ret = -EPERM;
5141                         break;
5142                 }
5143                 hdw->input_allowed_mask = nv;
5144                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5145                         /* Current mode is still in the allowed mask, so
5146                            we're done. */
5147                         break;
5148                 }
5149                 /* Select and switch to a mode that is still in the allowed
5150                    mask */
5151                 if (!hdw->input_allowed_mask) {
5152                         /* Nothing legal; give up */
5153                         break;
5154                 }
5155                 m = hdw->input_allowed_mask;
5156                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5157                         if (!((1 << idx) & m)) continue;
5158                         pvr2_hdw_set_input(hdw,idx);
5159                         break;
5160                 }
5161         } while (0);
5162         LOCK_GIVE(hdw->big_lock);
5163         return ret;
5164 }
5165
5166
5167 /* Find I2C address of eeprom */
5168 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5169 {
5170         int result;
5171         LOCK_TAKE(hdw->ctl_lock); do {
5172                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5173                 result = pvr2_send_request(hdw,
5174                                            hdw->cmd_buffer,1,
5175                                            hdw->cmd_buffer,1);
5176                 if (result < 0) break;
5177                 result = hdw->cmd_buffer[0];
5178         } while(0); LOCK_GIVE(hdw->ctl_lock);
5179         return result;
5180 }
5181
5182
5183 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5184                              struct v4l2_dbg_match *match, u64 reg_id,
5185                              int setFl, u64 *val_ptr)
5186 {
5187 #ifdef CONFIG_VIDEO_ADV_DEBUG
5188         struct v4l2_dbg_register req;
5189         int stat = 0;
5190         int okFl = 0;
5191
5192         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5193
5194         req.match = *match;
5195         req.reg = reg_id;
5196         if (setFl) req.val = *val_ptr;
5197         /* It would be nice to know if a sub-device answered the request */
5198         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5199         if (!setFl) *val_ptr = req.val;
5200         if (okFl) {
5201                 return stat;
5202         }
5203         return -EINVAL;
5204 #else
5205         return -ENOSYS;
5206 #endif
5207 }
5208
5209
5210 /*
5211   Stuff for Emacs to see, in order to encourage consistent editing style:
5212   *** Local Variables: ***
5213   *** mode: c ***
5214   *** fill-column: 75 ***
5215   *** tab-width: 8 ***
5216   *** c-basic-offset: 8 ***
5217   *** End: ***
5218   */