3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 #include <linux/pci.h>
19 #include <linux/kthread.h>
20 #include <linux/interrupt.h>
26 #include "hw-me-regs.h"
29 * mei_me_reg_read - Reads 32bit data from the mei device
31 * @dev: the device structure
32 * @offset: offset from which to read the data
34 * returns register value (u32)
36 static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
39 return ioread32(hw->mem_addr + offset);
44 * mei_me_reg_write - Writes 32bit data to the mei device
46 * @dev: the device structure
47 * @offset: offset from which to write the data
48 * @value: register value to write (u32)
50 static inline void mei_me_reg_write(const struct mei_me_hw *hw,
51 unsigned long offset, u32 value)
53 iowrite32(value, hw->mem_addr + offset);
57 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
58 * read window register
60 * @dev: the device structure
62 * returns ME_CB_RW register value (u32)
64 static u32 mei_me_mecbrw_read(const struct mei_device *dev)
66 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
69 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
71 * @dev: the device structure
73 * returns ME_CSR_HA register value (u32)
75 static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw)
77 return mei_me_reg_read(hw, ME_CSR_HA);
81 * mei_hcsr_read - Reads 32bit data from the host CSR
83 * @dev: the device structure
85 * returns H_CSR register value (u32)
87 static inline u32 mei_hcsr_read(const struct mei_me_hw *hw)
89 return mei_me_reg_read(hw, H_CSR);
93 * mei_hcsr_set - writes H_CSR register to the mei device,
94 * and ignores the H_IS bit for it is write-one-to-zero.
96 * @dev: the device structure
98 static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr)
101 mei_me_reg_write(hw, H_CSR, hcsr);
106 * mei_me_hw_config - configure hw dependent settings
110 static void mei_me_hw_config(struct mei_device *dev)
112 u32 hcsr = mei_hcsr_read(to_me_hw(dev));
113 /* Doesn't change in runtime */
114 dev->hbuf_depth = (hcsr & H_CBD) >> 24;
118 * mei_me_pg_state - translate internal pg state
119 * to the mei power gating state
122 * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
124 static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
130 * mei_clear_interrupts - clear and stop interrupts
132 * @dev: the device structure
134 static void mei_me_intr_clear(struct mei_device *dev)
136 struct mei_me_hw *hw = to_me_hw(dev);
137 u32 hcsr = mei_hcsr_read(hw);
138 if ((hcsr & H_IS) == H_IS)
139 mei_me_reg_write(hw, H_CSR, hcsr);
142 * mei_me_intr_enable - enables mei device interrupts
144 * @dev: the device structure
146 static void mei_me_intr_enable(struct mei_device *dev)
148 struct mei_me_hw *hw = to_me_hw(dev);
149 u32 hcsr = mei_hcsr_read(hw);
151 mei_hcsr_set(hw, hcsr);
155 * mei_disable_interrupts - disables mei device interrupts
157 * @dev: the device structure
159 static void mei_me_intr_disable(struct mei_device *dev)
161 struct mei_me_hw *hw = to_me_hw(dev);
162 u32 hcsr = mei_hcsr_read(hw);
164 mei_hcsr_set(hw, hcsr);
168 * mei_me_hw_reset_release - release device from the reset
170 * @dev: the device structure
172 static void mei_me_hw_reset_release(struct mei_device *dev)
174 struct mei_me_hw *hw = to_me_hw(dev);
175 u32 hcsr = mei_hcsr_read(hw);
179 mei_hcsr_set(hw, hcsr);
182 * mei_me_hw_reset - resets fw via mei csr register.
184 * @dev: the device structure
185 * @intr_enable: if interrupt should be enabled after reset.
187 static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
189 struct mei_me_hw *hw = to_me_hw(dev);
190 u32 hcsr = mei_hcsr_read(hw);
192 hcsr |= H_RST | H_IG | H_IS;
199 mei_me_reg_write(hw, H_CSR, hcsr);
201 if (intr_enable == false)
202 mei_me_hw_reset_release(dev);
208 * mei_me_host_set_ready - enable device
214 static void mei_me_host_set_ready(struct mei_device *dev)
216 struct mei_me_hw *hw = to_me_hw(dev);
217 hw->host_hw_state |= H_IE | H_IG | H_RDY;
218 mei_hcsr_set(hw, hw->host_hw_state);
221 * mei_me_host_is_ready - check whether the host has turned ready
226 static bool mei_me_host_is_ready(struct mei_device *dev)
228 struct mei_me_hw *hw = to_me_hw(dev);
229 hw->host_hw_state = mei_hcsr_read(hw);
230 return (hw->host_hw_state & H_RDY) == H_RDY;
234 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
239 static bool mei_me_hw_is_ready(struct mei_device *dev)
241 struct mei_me_hw *hw = to_me_hw(dev);
242 hw->me_hw_state = mei_me_mecsr_read(hw);
243 return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA;
246 static int mei_me_hw_ready_wait(struct mei_device *dev)
249 if (mei_me_hw_is_ready(dev))
252 dev->recvd_hw_ready = false;
253 mutex_unlock(&dev->device_lock);
254 err = wait_event_interruptible_timeout(dev->wait_hw_ready,
256 mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
257 mutex_lock(&dev->device_lock);
258 if (!err && !dev->recvd_hw_ready) {
261 dev_err(&dev->pdev->dev,
262 "wait hw ready failed. status = %d\n", err);
266 dev->recvd_hw_ready = false;
270 static int mei_me_hw_start(struct mei_device *dev)
272 int ret = mei_me_hw_ready_wait(dev);
275 dev_dbg(&dev->pdev->dev, "hw is ready\n");
277 mei_me_host_set_ready(dev);
283 * mei_hbuf_filled_slots - gets number of device filled buffer slots
285 * @dev: the device structure
287 * returns number of filled slots
289 static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
291 struct mei_me_hw *hw = to_me_hw(dev);
292 char read_ptr, write_ptr;
294 hw->host_hw_state = mei_hcsr_read(hw);
296 read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8);
297 write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16);
299 return (unsigned char) (write_ptr - read_ptr);
303 * mei_me_hbuf_is_empty - checks if host buffer is empty.
305 * @dev: the device structure
307 * returns true if empty, false - otherwise.
309 static bool mei_me_hbuf_is_empty(struct mei_device *dev)
311 return mei_hbuf_filled_slots(dev) == 0;
315 * mei_me_hbuf_empty_slots - counts write empty slots.
317 * @dev: the device structure
319 * returns -EOVERFLOW if overflow, otherwise empty slots count
321 static int mei_me_hbuf_empty_slots(struct mei_device *dev)
323 unsigned char filled_slots, empty_slots;
325 filled_slots = mei_hbuf_filled_slots(dev);
326 empty_slots = dev->hbuf_depth - filled_slots;
328 /* check for overflow */
329 if (filled_slots > dev->hbuf_depth)
335 static size_t mei_me_hbuf_max_len(const struct mei_device *dev)
337 return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr);
342 * mei_me_write_message - writes a message to mei device.
344 * @dev: the device structure
345 * @header: mei HECI header of message
346 * @buf: message payload will be written
348 * This function returns -EIO if write has failed
350 static int mei_me_write_message(struct mei_device *dev,
351 struct mei_msg_hdr *header,
354 struct mei_me_hw *hw = to_me_hw(dev);
356 unsigned long length = header->length;
357 u32 *reg_buf = (u32 *)buf;
363 dev_dbg(&dev->pdev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
365 empty_slots = mei_hbuf_empty_slots(dev);
366 dev_dbg(&dev->pdev->dev, "empty slots = %hu.\n", empty_slots);
368 dw_cnt = mei_data2slots(length);
369 if (empty_slots < 0 || dw_cnt > empty_slots)
372 mei_me_reg_write(hw, H_CB_WW, *((u32 *) header));
374 for (i = 0; i < length / 4; i++)
375 mei_me_reg_write(hw, H_CB_WW, reg_buf[i]);
380 memcpy(®, &buf[length - rem], rem);
381 mei_me_reg_write(hw, H_CB_WW, reg);
384 hcsr = mei_hcsr_read(hw) | H_IG;
385 mei_hcsr_set(hw, hcsr);
386 if (!mei_me_hw_is_ready(dev))
393 * mei_me_count_full_read_slots - counts read full slots.
395 * @dev: the device structure
397 * returns -EOVERFLOW if overflow, otherwise filled slots count
399 static int mei_me_count_full_read_slots(struct mei_device *dev)
401 struct mei_me_hw *hw = to_me_hw(dev);
402 char read_ptr, write_ptr;
403 unsigned char buffer_depth, filled_slots;
405 hw->me_hw_state = mei_me_mecsr_read(hw);
406 buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24);
407 read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8);
408 write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16);
409 filled_slots = (unsigned char) (write_ptr - read_ptr);
411 /* check for overflow */
412 if (filled_slots > buffer_depth)
415 dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
416 return (int)filled_slots;
420 * mei_me_read_slots - reads a message from mei device.
422 * @dev: the device structure
423 * @buffer: message buffer will be written
424 * @buffer_length: message size will be read
426 static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
427 unsigned long buffer_length)
429 struct mei_me_hw *hw = to_me_hw(dev);
430 u32 *reg_buf = (u32 *)buffer;
433 for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32))
434 *reg_buf++ = mei_me_mecbrw_read(dev);
436 if (buffer_length > 0) {
437 u32 reg = mei_me_mecbrw_read(dev);
438 memcpy(reg_buf, ®, buffer_length);
441 hcsr = mei_hcsr_read(hw) | H_IG;
442 mei_hcsr_set(hw, hcsr);
447 * mei_me_pg_enter - write pg enter register to mei device.
449 * @dev: the device structure
451 static void mei_me_pg_enter(struct mei_device *dev)
453 struct mei_me_hw *hw = to_me_hw(dev);
454 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
455 reg |= H_HPG_CSR_PGI;
456 mei_me_reg_write(hw, H_HPG_CSR, reg);
460 * mei_me_pg_enter - write pg enter register to mei device.
462 * @dev: the device structure
464 static void mei_me_pg_exit(struct mei_device *dev)
466 struct mei_me_hw *hw = to_me_hw(dev);
467 u32 reg = mei_me_reg_read(hw, H_HPG_CSR);
469 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
471 reg |= H_HPG_CSR_PGIHEXR;
472 mei_me_reg_write(hw, H_HPG_CSR, reg);
476 * mei_me_pg_is_enabled - detect if PG is supported by HW
478 * @dev: the device structure
480 * returns: true is pg supported, false otherwise
482 static bool mei_me_pg_is_enabled(struct mei_device *dev)
484 struct mei_me_hw *hw = to_me_hw(dev);
485 u32 reg = mei_me_reg_read(hw, ME_CSR_HA);
487 if ((reg & ME_PGIC_HRA) == 0)
490 if (dev->version.major_version < HBM_MAJOR_VERSION_PGI)
493 if (dev->version.major_version == HBM_MAJOR_VERSION_PGI &&
494 dev->version.minor_version < HBM_MINOR_VERSION_PGI)
500 dev_dbg(&dev->pdev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n",
501 !!(reg & ME_PGIC_HRA),
502 dev->version.major_version,
503 dev->version.minor_version,
504 HBM_MAJOR_VERSION_PGI,
505 HBM_MINOR_VERSION_PGI);
511 * mei_me_irq_quick_handler - The ISR of the MEI device
513 * @irq: The irq number
514 * @dev_id: pointer to the device structure
516 * returns irqreturn_t
519 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
521 struct mei_device *dev = (struct mei_device *) dev_id;
522 struct mei_me_hw *hw = to_me_hw(dev);
523 u32 csr_reg = mei_hcsr_read(hw);
525 if ((csr_reg & H_IS) != H_IS)
528 /* clear H_IS bit in H_CSR */
529 mei_me_reg_write(hw, H_CSR, csr_reg);
531 return IRQ_WAKE_THREAD;
535 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
538 * @irq: The irq number
539 * @dev_id: pointer to the device structure
541 * returns irqreturn_t
544 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
546 struct mei_device *dev = (struct mei_device *) dev_id;
547 struct mei_cl_cb complete_list;
551 dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
552 /* initialize our complete list */
553 mutex_lock(&dev->device_lock);
554 mei_io_list_init(&complete_list);
556 /* Ack the interrupt here
557 * In case of MSI we don't go through the quick handler */
558 if (pci_dev_msi_enabled(dev->pdev))
559 mei_clear_interrupts(dev);
561 /* check if ME wants a reset */
562 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
563 dev_warn(&dev->pdev->dev, "FW not ready: resetting.\n");
564 schedule_work(&dev->reset_work);
568 /* check if we need to start the dev */
569 if (!mei_host_is_ready(dev)) {
570 if (mei_hw_is_ready(dev)) {
571 dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
573 dev->recvd_hw_ready = true;
574 wake_up_interruptible(&dev->wait_hw_ready);
577 dev_dbg(&dev->pdev->dev, "Reset Completed.\n");
578 mei_me_hw_reset_release(dev);
582 /* check slots available for reading */
583 slots = mei_count_full_read_slots(dev);
585 dev_dbg(&dev->pdev->dev, "slots to read = %08x\n", slots);
586 rets = mei_irq_read_handler(dev, &complete_list, &slots);
587 /* There is a race between ME write and interrupt delivery:
588 * Not all data is always available immediately after the
589 * interrupt, so try to read again on the next interrupt.
591 if (rets == -ENODATA)
594 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
595 dev_err(&dev->pdev->dev, "mei_irq_read_handler ret = %d.\n",
597 schedule_work(&dev->reset_work);
602 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
604 rets = mei_irq_write_handler(dev, &complete_list);
606 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
608 mei_irq_compl_handler(dev, &complete_list);
611 dev_dbg(&dev->pdev->dev, "interrupt thread end ret = %d\n", rets);
612 mutex_unlock(&dev->device_lock);
615 static const struct mei_hw_ops mei_me_hw_ops = {
617 .pg_state = mei_me_pg_state,
619 .host_is_ready = mei_me_host_is_ready,
621 .hw_is_ready = mei_me_hw_is_ready,
622 .hw_reset = mei_me_hw_reset,
623 .hw_config = mei_me_hw_config,
624 .hw_start = mei_me_hw_start,
626 .pg_is_enabled = mei_me_pg_is_enabled,
628 .intr_clear = mei_me_intr_clear,
629 .intr_enable = mei_me_intr_enable,
630 .intr_disable = mei_me_intr_disable,
632 .hbuf_free_slots = mei_me_hbuf_empty_slots,
633 .hbuf_is_ready = mei_me_hbuf_is_empty,
634 .hbuf_max_len = mei_me_hbuf_max_len,
636 .write = mei_me_write_message,
638 .rdbuf_full_slots = mei_me_count_full_read_slots,
639 .read_hdr = mei_me_mecbrw_read,
640 .read = mei_me_read_slots
644 * mei_me_dev_init - allocates and initializes the mei device structure
646 * @pdev: The pci device structure
648 * returns The mei_device_device pointer on success, NULL on failure.
650 struct mei_device *mei_me_dev_init(struct pci_dev *pdev)
652 struct mei_device *dev;
654 dev = kzalloc(sizeof(struct mei_device) +
655 sizeof(struct mei_me_hw), GFP_KERNEL);
659 mei_device_init(dev);
661 dev->ops = &mei_me_hw_ops;