drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/mmc/dw_mmc.h>
  33 #include <linux/bitops.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of.h>
  37 #include <linux/of_gpio.h>
  38
  39 #include "dw_mmc.h"
  40
  41 /* Common flag combinations */
  42 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  43                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  44                                  SDMMC_INT_EBE)
  45 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  46                                  SDMMC_INT_RESP_ERR)
  47 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  48                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  49 #define DW_MCI_SEND_STATUS      1
  50 #define DW_MCI_RECV_STATUS      2
  51 #define DW_MCI_DMA_THRESHOLD    16
  52
  53 #ifdef CONFIG_MMC_DW_IDMAC
  54 struct idmac_desc {
  55         u32             des0;   /* Control Descriptor */
  56 #define IDMAC_DES0_DIC  BIT(1)
  57 #define IDMAC_DES0_LD   BIT(2)
  58 #define IDMAC_DES0_FD   BIT(3)
  59 #define IDMAC_DES0_CH   BIT(4)
  60 #define IDMAC_DES0_ER   BIT(5)
  61 #define IDMAC_DES0_CES  BIT(30)
  62 #define IDMAC_DES0_OWN  BIT(31)
  63
  64         u32             des1;   /* Buffer sizes */
  65 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  66         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  67
  68         u32             des2;   /* buffer 1 physical address */
  69
  70         u32             des3;   /* buffer 2 physical address */
  71 };
  72 #endif /* CONFIG_MMC_DW_IDMAC */
  73
  74 /**
  75  * struct dw_mci_slot - MMC slot state
  76  * @mmc: The mmc_host representing this slot.
  77  * @host: The MMC controller this slot is using.
  78  * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
  79  * @wp_gpio: If gpio_is_valid() we'll use this to read write protect.
  80  * @ctype: Card type for this slot.
  81  * @mrq: mmc_request currently being processed or waiting to be
  82  *      processed, or NULL when the slot is idle.
  83  * @queue_node: List node for placing this node in the @queue list of
  84  *      &struct dw_mci.
  85  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  86  * @flags: Random state bits associated with the slot.
  87  * @id: Number of this slot.
  88  * @last_detect_state: Most recently observed card detect state.
  89  */
  90 struct dw_mci_slot {
  91         struct mmc_host         *mmc;
  92         struct dw_mci           *host;
  93
  94         int                     quirks;
  95         int                     wp_gpio;
  96
  97         u32                     ctype;
  98
  99         struct mmc_request      *mrq;
 100         struct list_head        queue_node;
 101
 102         unsigned int            clock;
 103         unsigned long           flags;
 104 #define DW_MMC_CARD_PRESENT     0
 105 #define DW_MMC_CARD_NEED_INIT   1
 106         int                     id;
 107         int                     last_detect_state;
 108 };
 109
 110 #if defined(CONFIG_DEBUG_FS)
 111 static int dw_mci_req_show(struct seq_file *s, void *v)
 112 {
 113         struct dw_mci_slot *slot = s->private;
 114         struct mmc_request *mrq;
 115         struct mmc_command *cmd;
 116         struct mmc_command *stop;
 117         struct mmc_data *data;
 118
 119         /* Make sure we get a consistent snapshot */
 120         spin_lock_bh(&slot->host->lock);
 121         mrq = slot->mrq;
 122
 123         if (mrq) {
 124                 cmd = mrq->cmd;
 125                 data = mrq->data;
 126                 stop = mrq->stop;
 127
 128                 if (cmd)
 129                         seq_printf(s,
 130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 131                                    cmd->opcode, cmd->arg, cmd->flags,
 132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 133                                    cmd->resp[2], cmd->error);
 134                 if (data)
 135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 136                                    data->bytes_xfered, data->blocks,
 137                                    data->blksz, data->flags, data->error);
 138                 if (stop)
 139                         seq_printf(s,
 140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 141                                    stop->opcode, stop->arg, stop->flags,
 142                                    stop->resp[0], stop->resp[1], stop->resp[2],
 143                                    stop->resp[2], stop->error);
 144         }
 145
 146         spin_unlock_bh(&slot->host->lock);
 147
 148         return 0;
 149 }
 150
 151 static int dw_mci_req_open(struct inode *inode, struct file *file)
 152 {
 153         return single_open(file, dw_mci_req_show, inode->i_private);
 154 }
 155
 156 static const struct file_operations dw_mci_req_fops = {
 157         .owner          = THIS_MODULE,
 158         .open           = dw_mci_req_open,
 159         .read           = seq_read,
 160         .llseek         = seq_lseek,
 161         .release        = single_release,
 162 };
 163
 164 static int dw_mci_regs_show(struct seq_file *s, void *v)
 165 {
 166         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 167         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 168         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 169         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 170         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 171         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 172
 173         return 0;
 174 }
 175
 176 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 177 {
 178         return single_open(file, dw_mci_regs_show, inode->i_private);
 179 }
 180
 181 static const struct file_operations dw_mci_regs_fops = {
 182         .owner          = THIS_MODULE,
 183         .open           = dw_mci_regs_open,
 184         .read           = seq_read,
 185         .llseek         = seq_lseek,
 186         .release        = single_release,
 187 };
 188
 189 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 190 {
 191         struct mmc_host *mmc = slot->mmc;
 192         struct dw_mci *host = slot->host;
 193         struct dentry *root;
 194         struct dentry *node;
 195
 196         root = mmc->debugfs_root;
 197         if (!root)
 198                 return;
 199
 200         node = debugfs_create_file("regs", S_IRUSR, root, host,
 201                                    &dw_mci_regs_fops);
 202         if (!node)
 203                 goto err;
 204
 205         node = debugfs_create_file("req", S_IRUSR, root, slot,
 206                                    &dw_mci_req_fops);
 207         if (!node)
 208                 goto err;
 209
 210         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 211         if (!node)
 212                 goto err;
 213
 214         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 215                                   (u32 *)&host->pending_events);
 216         if (!node)
 217                 goto err;
 218
 219         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 220                                   (u32 *)&host->completed_events);
 221         if (!node)
 222                 goto err;
 223
 224         return;
 225
 226 err:
 227         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 228 }
 229 #endif /* defined(CONFIG_DEBUG_FS) */
 230
 231 static void dw_mci_set_timeout(struct dw_mci *host)
 232 {
 233         /* timeout (maximum) */
 234         mci_writel(host, TMOUT, 0xffffffff);
 235 }
 236
 237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 238 {
 239         struct mmc_data *data;
 240         struct dw_mci_slot *slot = mmc_priv(mmc);
 241         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 242         u32 cmdr;
 243         cmd->error = -EINPROGRESS;
 244
 245         cmdr = cmd->opcode;
 246
 247         if (cmdr == MMC_STOP_TRANSMISSION)
 248                 cmdr |= SDMMC_CMD_STOP;
 249         else
 250                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 251
 252         if (cmd->flags & MMC_RSP_PRESENT) {
 253                 /* We expect a response, so set this bit */
 254                 cmdr |= SDMMC_CMD_RESP_EXP;
 255                 if (cmd->flags & MMC_RSP_136)
 256                         cmdr |= SDMMC_CMD_RESP_LONG;
 257         }
 258
 259         if (cmd->flags & MMC_RSP_CRC)
 260                 cmdr |= SDMMC_CMD_RESP_CRC;
 261
 262         data = cmd->data;
 263         if (data) {
 264                 cmdr |= SDMMC_CMD_DAT_EXP;
 265                 if (data->flags & MMC_DATA_STREAM)
 266                         cmdr |= SDMMC_CMD_STRM_MODE;
 267                 if (data->flags & MMC_DATA_WRITE)
 268                         cmdr |= SDMMC_CMD_DAT_WR;
 269         }
 270
 271         if (drv_data && drv_data->prepare_command)
 272                 drv_data->prepare_command(slot->host, &cmdr);
 273
 274         return cmdr;
 275 }
 276
 277 static void dw_mci_start_command(struct dw_mci *host,
 278                                  struct mmc_command *cmd, u32 cmd_flags)
 279 {
 280         host->cmd = cmd;
 281         dev_vdbg(host->dev,
 282                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 283                  cmd->arg, cmd_flags);
 284
 285         mci_writel(host, CMDARG, cmd->arg);
 286         wmb();
 287
 288         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 289 }
 290
 291 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 292 {
 293         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 294 }
 295
 296 /* DMA interface functions */
 297 static void dw_mci_stop_dma(struct dw_mci *host)
 298 {
 299         if (host->using_dma) {
 300                 host->dma_ops->stop(host);
 301                 host->dma_ops->cleanup(host);
 302         } else {
 303                 /* Data transfer was stopped by the interrupt handler */
 304                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 305         }
 306 }
 307
 308 static int dw_mci_get_dma_dir(struct mmc_data *data)
 309 {
 310         if (data->flags & MMC_DATA_WRITE)
 311                 return DMA_TO_DEVICE;
 312         else
 313                 return DMA_FROM_DEVICE;
 314 }
 315
 316 #ifdef CONFIG_MMC_DW_IDMAC
 317 static void dw_mci_dma_cleanup(struct dw_mci *host)
 318 {
 319         struct mmc_data *data = host->data;
 320
 321         if (data)
 322                 if (!data->host_cookie)
 323                         dma_unmap_sg(host->dev,
 324                                      data->sg,
 325                                      data->sg_len,
 326                                      dw_mci_get_dma_dir(data));
 327 }
 328
 329 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 330 {
 331         u32 temp;
 332
 333         /* Disable and reset the IDMAC interface */
 334         temp = mci_readl(host, CTRL);
 335         temp &= ~SDMMC_CTRL_USE_IDMAC;
 336         temp |= SDMMC_CTRL_DMA_RESET;
 337         mci_writel(host, CTRL, temp);
 338
 339         /* Stop the IDMAC running */
 340         temp = mci_readl(host, BMOD);
 341         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 342         mci_writel(host, BMOD, temp);
 343 }
 344
 345 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 346 {
 347         struct mmc_data *data = host->data;
 348
 349         dev_vdbg(host->dev, "DMA complete\n");
 350
 351         host->dma_ops->cleanup(host);
 352
 353         /*
 354          * If the card was removed, data will be NULL. No point in trying to
 355          * send the stop command or waiting for NBUSY in this case.
 356          */
 357         if (data) {
 358                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 359                 tasklet_schedule(&host->tasklet);
 360         }
 361 }
 362
 363 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 364                                     unsigned int sg_len)
 365 {
 366         int i;
 367         struct idmac_desc *desc = host->sg_cpu;
 368
 369         for (i = 0; i < sg_len; i++, desc++) {
 370                 unsigned int length = sg_dma_len(&data->sg[i]);
 371                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 372
 373                 /* Set the OWN bit and disable interrupts for this descriptor */
 374                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 375
 376                 /* Buffer length */
 377                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 378
 379                 /* Physical address to DMA to/from */
 380                 desc->des2 = mem_addr;
 381         }
 382
 383         /* Set first descriptor */
 384         desc = host->sg_cpu;
 385         desc->des0 |= IDMAC_DES0_FD;
 386
 387         /* Set last descriptor */
 388         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 389         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 390         desc->des0 |= IDMAC_DES0_LD;
 391
 392         wmb();
 393 }
 394
 395 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 396 {
 397         u32 temp;
 398
 399         dw_mci_translate_sglist(host, host->data, sg_len);
 400
 401         /* Select IDMAC interface */
 402         temp = mci_readl(host, CTRL);
 403         temp |= SDMMC_CTRL_USE_IDMAC;
 404         mci_writel(host, CTRL, temp);
 405
 406         wmb();
 407
 408         /* Enable the IDMAC */
 409         temp = mci_readl(host, BMOD);
 410         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 411         mci_writel(host, BMOD, temp);
 412
 413         /* Start it running */
 414         mci_writel(host, PLDMND, 1);
 415 }
 416
 417 static int dw_mci_idmac_init(struct dw_mci *host)
 418 {
 419         struct idmac_desc *p;
 420         int i;
 421
 422         /* Number of descriptors in the ring buffer */
 423         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 424
 425         /* Forward link the descriptor list */
 426         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 427                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 428
 429         /* Set the last descriptor as the end-of-ring descriptor */
 430         p->des3 = host->sg_dma;
 431         p->des0 = IDMAC_DES0_ER;
 432
 433         mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
 434
 435         /* Mask out interrupts - get Tx & Rx complete only */
 436         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 437                    SDMMC_IDMAC_INT_TI);
 438
 439         /* Set the descriptor base address */
 440         mci_writel(host, DBADDR, host->sg_dma);
 441         return 0;
 442 }
 443
 444 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 445         .init = dw_mci_idmac_init,
 446         .start = dw_mci_idmac_start_dma,
 447         .stop = dw_mci_idmac_stop_dma,
 448         .complete = dw_mci_idmac_complete_dma,
 449         .cleanup = dw_mci_dma_cleanup,
 450 };
 451 #endif /* CONFIG_MMC_DW_IDMAC */
 452
 453 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 454                                    struct mmc_data *data,
 455                                    bool next)
 456 {
 457         struct scatterlist *sg;
 458         unsigned int i, sg_len;
 459
 460         if (!next && data->host_cookie)
 461                 return data->host_cookie;
 462
 463         /*
 464          * We don't do DMA on "complex" transfers, i.e. with
 465          * non-word-aligned buffers or lengths. Also, we don't bother
 466          * with all the DMA setup overhead for short transfers.
 467          */
 468         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 469                 return -EINVAL;
 470
 471         if (data->blksz & 3)
 472                 return -EINVAL;
 473
 474         for_each_sg(data->sg, sg, data->sg_len, i) {
 475                 if (sg->offset & 3 || sg->length & 3)
 476                         return -EINVAL;
 477         }
 478
 479         sg_len = dma_map_sg(host->dev,
 480                             data->sg,
 481                             data->sg_len,
 482                             dw_mci_get_dma_dir(data));
 483         if (sg_len == 0)
 484                 return -EINVAL;
 485
 486         if (next)
 487                 data->host_cookie = sg_len;
 488
 489         return sg_len;
 490 }
 491
 492 static void dw_mci_pre_req(struct mmc_host *mmc,
 493                            struct mmc_request *mrq,
 494                            bool is_first_req)
 495 {
 496         struct dw_mci_slot *slot = mmc_priv(mmc);
 497         struct mmc_data *data = mrq->data;
 498
 499         if (!slot->host->use_dma || !data)
 500                 return;
 501
 502         if (data->host_cookie) {
 503                 data->host_cookie = 0;
 504                 return;
 505         }
 506
 507         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 508                 data->host_cookie = 0;
 509 }
 510
 511 static void dw_mci_post_req(struct mmc_host *mmc,
 512                             struct mmc_request *mrq,
 513                             int err)
 514 {
 515         struct dw_mci_slot *slot = mmc_priv(mmc);
 516         struct mmc_data *data = mrq->data;
 517
 518         if (!slot->host->use_dma || !data)
 519                 return;
 520
 521         if (data->host_cookie)
 522                 dma_unmap_sg(slot->host->dev,
 523                              data->sg,
 524                              data->sg_len,
 525                              dw_mci_get_dma_dir(data));
 526         data->host_cookie = 0;
 527 }
 528
 529 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 530 {
 531         int sg_len;
 532         u32 temp;
 533
 534         host->using_dma = 0;
 535
 536         /* If we don't have a channel, we can't do DMA */
 537         if (!host->use_dma)
 538                 return -ENODEV;
 539
 540         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 541         if (sg_len < 0) {
 542                 host->dma_ops->stop(host);
 543                 return sg_len;
 544         }
 545
 546         host->using_dma = 1;
 547
 548         dev_vdbg(host->dev,
 549                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 550                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 551                  sg_len);
 552
 553         /* Enable the DMA interface */
 554         temp = mci_readl(host, CTRL);
 555         temp |= SDMMC_CTRL_DMA_ENABLE;
 556         mci_writel(host, CTRL, temp);
 557
 558         /* Disable RX/TX IRQs, let DMA handle it */
 559         temp = mci_readl(host, INTMASK);
 560         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 561         mci_writel(host, INTMASK, temp);
 562
 563         host->dma_ops->start(host, sg_len);
 564
 565         return 0;
 566 }
 567
 568 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 569 {
 570         u32 temp;
 571
 572         data->error = -EINPROGRESS;
 573
 574         WARN_ON(host->data);
 575         host->sg = NULL;
 576         host->data = data;
 577
 578         if (data->flags & MMC_DATA_READ)
 579                 host->dir_status = DW_MCI_RECV_STATUS;
 580         else
 581                 host->dir_status = DW_MCI_SEND_STATUS;
 582
 583         if (dw_mci_submit_data_dma(host, data)) {
 584                 int flags = SG_MITER_ATOMIC;
 585                 if (host->data->flags & MMC_DATA_READ)
 586                         flags |= SG_MITER_TO_SG;
 587                 else
 588                         flags |= SG_MITER_FROM_SG;
 589
 590                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 591                 host->sg = data->sg;
 592                 host->part_buf_start = 0;
 593                 host->part_buf_count = 0;
 594
 595                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 596                 temp = mci_readl(host, INTMASK);
 597                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 598                 mci_writel(host, INTMASK, temp);
 599
 600                 temp = mci_readl(host, CTRL);
 601                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 602                 mci_writel(host, CTRL, temp);
 603         }
 604 }
 605
 606 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 607 {
 608         struct dw_mci *host = slot->host;
 609         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 610         unsigned int cmd_status = 0;
 611
 612         mci_writel(host, CMDARG, arg);
 613         wmb();
 614         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 615
 616         while (time_before(jiffies, timeout)) {
 617                 cmd_status = mci_readl(host, CMD);
 618                 if (!(cmd_status & SDMMC_CMD_START))
 619                         return;
 620         }
 621         dev_err(&slot->mmc->class_dev,
 622                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 623                 cmd, arg, cmd_status);
 624 }
 625
 626 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
 627 {
 628         struct dw_mci *host = slot->host;
 629         u32 div;
 630         u32 clk_en_a;
 631
 632         if (slot->clock != host->current_speed || force_clkinit) {
 633                 div = host->bus_hz / slot->clock;
 634                 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
 635                         /*
 636                          * move the + 1 after the divide to prevent
 637                          * over-clocking the card.
 638                          */
 639                         div += 1;
 640
 641                 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
 642
 643                 dev_info(&slot->mmc->class_dev,
 644                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 645                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 646                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 647
 648                 /* disable clock */
 649                 mci_writel(host, CLKENA, 0);
 650                 mci_writel(host, CLKSRC, 0);
 651
 652                 /* inform CIU */
 653                 mci_send_cmd(slot,
 654                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 655
 656                 /* set clock to desired speed */
 657                 mci_writel(host, CLKDIV, div);
 658
 659                 /* inform CIU */
 660                 mci_send_cmd(slot,
 661                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 662
 663                 /* enable clock; only low power if no SDIO */
 664                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
 665                 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
 666                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
 667                 mci_writel(host, CLKENA, clk_en_a);
 668
 669                 /* inform CIU */
 670                 mci_send_cmd(slot,
 671                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 672
 673                 host->current_speed = slot->clock;
 674         }
 675
 676         /* Set the current slot bus width */
 677         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 678 }
 679
 680 static void __dw_mci_start_request(struct dw_mci *host,
 681                                    struct dw_mci_slot *slot,
 682                                    struct mmc_command *cmd)
 683 {
 684         struct mmc_request *mrq;
 685         struct mmc_data *data;
 686         u32 cmdflags;
 687
 688         mrq = slot->mrq;
 689         if (host->pdata->select_slot)
 690                 host->pdata->select_slot(slot->id);
 691
 692         host->cur_slot = slot;
 693         host->mrq = mrq;
 694
 695         host->pending_events = 0;
 696         host->completed_events = 0;
 697         host->data_status = 0;
 698
 699         data = cmd->data;
 700         if (data) {
 701                 dw_mci_set_timeout(host);
 702                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 703                 mci_writel(host, BLKSIZ, data->blksz);
 704         }
 705
 706         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 707
 708         /* this is the first command, send the initialization clock */
 709         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 710                 cmdflags |= SDMMC_CMD_INIT;
 711
 712         if (data) {
 713                 dw_mci_submit_data(host, data);
 714                 wmb();
 715         }
 716
 717         dw_mci_start_command(host, cmd, cmdflags);
 718
 719         if (mrq->stop)
 720                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 721 }
 722
 723 static void dw_mci_start_request(struct dw_mci *host,
 724                                  struct dw_mci_slot *slot)
 725 {
 726         struct mmc_request *mrq = slot->mrq;
 727         struct mmc_command *cmd;
 728
 729         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 730         __dw_mci_start_request(host, slot, cmd);
 731 }
 732
 733 /* must be called with host->lock held */
 734 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 735                                  struct mmc_request *mrq)
 736 {
 737         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 738                  host->state);
 739
 740         slot->mrq = mrq;
 741
 742         if (host->state == STATE_IDLE) {
 743                 host->state = STATE_SENDING_CMD;
 744                 dw_mci_start_request(host, slot);
 745         } else {
 746                 list_add_tail(&slot->queue_node, &host->queue);
 747         }
 748 }
 749
 750 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 751 {
 752         struct dw_mci_slot *slot = mmc_priv(mmc);
 753         struct dw_mci *host = slot->host;
 754
 755         WARN_ON(slot->mrq);
 756
 757         /*
 758          * The check for card presence and queueing of the request must be
 759          * atomic, otherwise the card could be removed in between and the
 760          * request wouldn't fail until another card was inserted.
 761          */
 762         spin_lock_bh(&host->lock);
 763
 764         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 765                 spin_unlock_bh(&host->lock);
 766                 mrq->cmd->error = -ENOMEDIUM;
 767                 mmc_request_done(mmc, mrq);
 768                 return;
 769         }
 770
 771         dw_mci_queue_request(host, slot, mrq);
 772
 773         spin_unlock_bh(&host->lock);
 774 }
 775
 776 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 777 {
 778         struct dw_mci_slot *slot = mmc_priv(mmc);
 779         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
 780         u32 regs;
 781
 782         switch (ios->bus_width) {
 783         case MMC_BUS_WIDTH_4:
 784                 slot->ctype = SDMMC_CTYPE_4BIT;
 785                 break;
 786         case MMC_BUS_WIDTH_8:
 787                 slot->ctype = SDMMC_CTYPE_8BIT;
 788                 break;
 789         default:
 790                 /* set default 1 bit mode */
 791                 slot->ctype = SDMMC_CTYPE_1BIT;
 792         }
 793
 794         regs = mci_readl(slot->host, UHS_REG);
 795
 796         /* DDR mode set */
 797         if (ios->timing == MMC_TIMING_UHS_DDR50)
 798                 regs |= ((0x1 << slot->id) << 16);
 799         else
 800                 regs &= ~((0x1 << slot->id) << 16);
 801
 802         mci_writel(slot->host, UHS_REG, regs);
 803
 804         if (ios->clock) {
 805                 /*
 806                  * Use mirror of ios->clock to prevent race with mmc
 807                  * core ios update when finding the minimum.
 808                  */
 809                 slot->clock = ios->clock;
 810         }
 811
 812         if (drv_data && drv_data->set_ios)
 813                 drv_data->set_ios(slot->host, ios);
 814
 815         /* Slot specific timing and width adjustment */
 816         dw_mci_setup_bus(slot, false);
 817
 818         switch (ios->power_mode) {
 819         case MMC_POWER_UP:
 820                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 821                 /* Power up slot */
 822                 if (slot->host->pdata->setpower)
 823                         slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
 824                 break;
 825         case MMC_POWER_OFF:
 826                 /* Power down slot */
 827                 if (slot->host->pdata->setpower)
 828                         slot->host->pdata->setpower(slot->id, 0);
 829                 break;
 830         default:
 831                 break;
 832         }
 833 }
 834
 835 static int dw_mci_get_ro(struct mmc_host *mmc)
 836 {
 837         int read_only;
 838         struct dw_mci_slot *slot = mmc_priv(mmc);
 839         struct dw_mci_board *brd = slot->host->pdata;
 840
 841         /* Use platform get_ro function, else try on board write protect */
 842         if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
 843                 read_only = 0;
 844         else if (brd->get_ro)
 845                 read_only = brd->get_ro(slot->id);
 846         else if (gpio_is_valid(slot->wp_gpio))
 847                 read_only = gpio_get_value(slot->wp_gpio);
 848         else
 849                 read_only =
 850                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 851
 852         dev_dbg(&mmc->class_dev, "card is %s\n",
 853                 read_only ? "read-only" : "read-write");
 854
 855         return read_only;
 856 }
 857
 858 static int dw_mci_get_cd(struct mmc_host *mmc)
 859 {
 860         int present;
 861         struct dw_mci_slot *slot = mmc_priv(mmc);
 862         struct dw_mci_board *brd = slot->host->pdata;
 863
 864         /* Use platform get_cd function, else try onboard card detect */
 865         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 866                 present = 1;
 867         else if (brd->get_cd)
 868                 present = !brd->get_cd(slot->id);
 869         else
 870                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 871                         == 0 ? 1 : 0;
 872
 873         if (present)
 874                 dev_dbg(&mmc->class_dev, "card is present\n");
 875         else
 876                 dev_dbg(&mmc->class_dev, "card is not present\n");
 877
 878         return present;
 879 }
 880
 881 /*
 882  * Disable lower power mode.
 883  *
 884  * Low power mode will stop the card clock when idle.  According to the
 885  * description of the CLKENA register we should disable low power mode
 886  * for SDIO cards if we need SDIO interrupts to work.
 887  *
 888  * This function is fast if low power mode is already disabled.
 889  */
 890 static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
 891 {
 892         struct dw_mci *host = slot->host;
 893         u32 clk_en_a;
 894         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
 895
 896         clk_en_a = mci_readl(host, CLKENA);
 897
 898         if (clk_en_a & clken_low_pwr) {
 899                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
 900                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 901                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 902         }
 903 }
 904
 905 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 906 {
 907         struct dw_mci_slot *slot = mmc_priv(mmc);
 908         struct dw_mci *host = slot->host;
 909         u32 int_mask;
 910
 911         /* Enable/disable Slot Specific SDIO interrupt */
 912         int_mask = mci_readl(host, INTMASK);
 913         if (enb) {
 914                 /*
 915                  * Turn off low power mode if it was enabled.  This is a bit of
 916                  * a heavy operation and we disable / enable IRQs a lot, so
 917                  * we'll leave low power mode disabled and it will get
 918                  * re-enabled again in dw_mci_setup_bus().
 919                  */
 920                 dw_mci_disable_low_power(slot);
 921
 922                 mci_writel(host, INTMASK,
 923                            (int_mask | SDMMC_INT_SDIO(slot->id)));
 924         } else {
 925                 mci_writel(host, INTMASK,
 926                            (int_mask & ~SDMMC_INT_SDIO(slot->id)));
 927         }
 928 }
 929
 930 static const struct mmc_host_ops dw_mci_ops = {
 931         .request                = dw_mci_request,
 932         .pre_req                = dw_mci_pre_req,
 933         .post_req               = dw_mci_post_req,
 934         .set_ios                = dw_mci_set_ios,
 935         .get_ro                 = dw_mci_get_ro,
 936         .get_cd                 = dw_mci_get_cd,
 937         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 938 };
 939
 940 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 941         __releases(&host->lock)
 942         __acquires(&host->lock)
 943 {
 944         struct dw_mci_slot *slot;
 945         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 946
 947         WARN_ON(host->cmd || host->data);
 948
 949         host->cur_slot->mrq = NULL;
 950         host->mrq = NULL;
 951         if (!list_empty(&host->queue)) {
 952                 slot = list_entry(host->queue.next,
 953                                   struct dw_mci_slot, queue_node);
 954                 list_del(&slot->queue_node);
 955                 dev_vdbg(host->dev, "list not empty: %s is next\n",
 956                          mmc_hostname(slot->mmc));
 957                 host->state = STATE_SENDING_CMD;
 958                 dw_mci_start_request(host, slot);
 959         } else {
 960                 dev_vdbg(host->dev, "list empty\n");
 961                 host->state = STATE_IDLE;
 962         }
 963
 964         spin_unlock(&host->lock);
 965         mmc_request_done(prev_mmc, mrq);
 966         spin_lock(&host->lock);
 967 }
 968
 969 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 970 {
 971         u32 status = host->cmd_status;
 972
 973         host->cmd_status = 0;
 974
 975         /* Read the response from the card (up to 16 bytes) */
 976         if (cmd->flags & MMC_RSP_PRESENT) {
 977                 if (cmd->flags & MMC_RSP_136) {
 978                         cmd->resp[3] = mci_readl(host, RESP0);
 979                         cmd->resp[2] = mci_readl(host, RESP1);
 980                         cmd->resp[1] = mci_readl(host, RESP2);
 981                         cmd->resp[0] = mci_readl(host, RESP3);
 982                 } else {
 983                         cmd->resp[0] = mci_readl(host, RESP0);
 984                         cmd->resp[1] = 0;
 985                         cmd->resp[2] = 0;
 986                         cmd->resp[3] = 0;
 987                 }
 988         }
 989
 990         if (status & SDMMC_INT_RTO)
 991                 cmd->error = -ETIMEDOUT;
 992         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 993                 cmd->error = -EILSEQ;
 994         else if (status & SDMMC_INT_RESP_ERR)
 995                 cmd->error = -EIO;
 996         else
 997                 cmd->error = 0;
 998
 999         if (cmd->error) {
1000                 /* newer ip versions need a delay between retries */
1001                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1002                         mdelay(20);
1003
1004                 if (cmd->data) {
1005                         dw_mci_stop_dma(host);
1006                         host->data = NULL;
1007                 }
1008         }
1009 }
1010
1011 static void dw_mci_tasklet_func(unsigned long priv)
1012 {
1013         struct dw_mci *host = (struct dw_mci *)priv;
1014         struct mmc_data *data;
1015         struct mmc_command *cmd;
1016         enum dw_mci_state state;
1017         enum dw_mci_state prev_state;
1018         u32 status, ctrl;
1019
1020         spin_lock(&host->lock);
1021
1022         state = host->state;
1023         data = host->data;
1024
1025         do {
1026                 prev_state = state;
1027
1028                 switch (state) {
1029                 case STATE_IDLE:
1030                         break;
1031
1032                 case STATE_SENDING_CMD:
1033                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1034                                                 &host->pending_events))
1035                                 break;
1036
1037                         cmd = host->cmd;
1038                         host->cmd = NULL;
1039                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1040                         dw_mci_command_complete(host, cmd);
1041                         if (cmd == host->mrq->sbc && !cmd->error) {
1042                                 prev_state = state = STATE_SENDING_CMD;
1043                                 __dw_mci_start_request(host, host->cur_slot,
1044                                                        host->mrq->cmd);
1045                                 goto unlock;
1046                         }
1047
1048                         if (!host->mrq->data || cmd->error) {
1049                                 dw_mci_request_end(host, host->mrq);
1050                                 goto unlock;
1051                         }
1052
1053                         prev_state = state = STATE_SENDING_DATA;
1054                         /* fall through */
1055
1056                 case STATE_SENDING_DATA:
1057                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1058                                                &host->pending_events)) {
1059                                 dw_mci_stop_dma(host);
1060                                 if (data->stop)
1061                                         send_stop_cmd(host, data);
1062                                 state = STATE_DATA_ERROR;
1063                                 break;
1064                         }
1065
1066                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1067                                                 &host->pending_events))
1068                                 break;
1069
1070                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1071                         prev_state = state = STATE_DATA_BUSY;
1072                         /* fall through */
1073
1074                 case STATE_DATA_BUSY:
1075                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1076                                                 &host->pending_events))
1077                                 break;
1078
1079                         host->data = NULL;
1080                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1081                         status = host->data_status;
1082
1083                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1084                                 if (status & SDMMC_INT_DTO) {
1085                                         data->error = -ETIMEDOUT;
1086                                 } else if (status & SDMMC_INT_DCRC) {
1087                                         data->error = -EILSEQ;
1088                                 } else if (status & SDMMC_INT_EBE &&
1089                                            host->dir_status ==
1090                                                         DW_MCI_SEND_STATUS) {
1091                                         /*
1092                                          * No data CRC status was returned.
1093                                          * The number of bytes transferred will
1094                                          * be exaggerated in PIO mode.
1095                                          */
1096                                         data->bytes_xfered = 0;
1097                                         data->error = -ETIMEDOUT;
1098                                 } else {
1099                                         dev_err(host->dev,
1100                                                 "data FIFO error "
1101                                                 "(status=%08x)\n",
1102                                                 status);
1103                                         data->error = -EIO;
1104                                 }
1105                                 /*
1106                                  * After an error, there may be data lingering
1107                                  * in the FIFO, so reset it - doing so
1108                                  * generates a block interrupt, hence setting
1109                                  * the scatter-gather pointer to NULL.
1110                                  */
1111                                 sg_miter_stop(&host->sg_miter);
1112                                 host->sg = NULL;
1113                                 ctrl = mci_readl(host, CTRL);
1114                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1115                                 mci_writel(host, CTRL, ctrl);
1116                         } else {
1117                                 data->bytes_xfered = data->blocks * data->blksz;
1118                                 data->error = 0;
1119                         }
1120
1121                         if (!data->stop) {
1122                                 dw_mci_request_end(host, host->mrq);
1123                                 goto unlock;
1124                         }
1125
1126                         if (host->mrq->sbc && !data->error) {
1127                                 data->stop->error = 0;
1128                                 dw_mci_request_end(host, host->mrq);
1129                                 goto unlock;
1130                         }
1131
1132                         prev_state = state = STATE_SENDING_STOP;
1133                         if (!data->error)
1134                                 send_stop_cmd(host, data);
1135                         /* fall through */
1136
1137                 case STATE_SENDING_STOP:
1138                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1139                                                 &host->pending_events))
1140                                 break;
1141
1142                         host->cmd = NULL;
1143                         dw_mci_command_complete(host, host->mrq->stop);
1144                         dw_mci_request_end(host, host->mrq);
1145                         goto unlock;
1146
1147                 case STATE_DATA_ERROR:
1148                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1149                                                 &host->pending_events))
1150                                 break;
1151
1152                         state = STATE_DATA_BUSY;
1153                         break;
1154                 }
1155         } while (state != prev_state);
1156
1157         host->state = state;
1158 unlock:
1159         spin_unlock(&host->lock);
1160
1161 }
1162
1163 /* push final bytes to part_buf, only use during push */
1164 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1165 {
1166         memcpy((void *)&host->part_buf, buf, cnt);
1167         host->part_buf_count = cnt;
1168 }
1169
1170 /* append bytes to part_buf, only use during push */
1171 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1172 {
1173         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1174         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1175         host->part_buf_count += cnt;
1176         return cnt;
1177 }
1178
1179 /* pull first bytes from part_buf, only use during pull */
1180 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1181 {
1182         cnt = min(cnt, (int)host->part_buf_count);
1183         if (cnt) {
1184                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1185                        cnt);
1186                 host->part_buf_count -= cnt;
1187                 host->part_buf_start += cnt;
1188         }
1189         return cnt;
1190 }
1191
1192 /* pull final bytes from the part_buf, assuming it's just been filled */
1193 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1194 {
1195         memcpy(buf, &host->part_buf, cnt);
1196         host->part_buf_start = cnt;
1197         host->part_buf_count = (1 << host->data_shift) - cnt;
1198 }
1199
1200 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1201 {
1202         struct mmc_data *data = host->data;
1203         int init_cnt = cnt;
1204
1205         /* try and push anything in the part_buf */
1206         if (unlikely(host->part_buf_count)) {
1207                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1208                 buf += len;
1209                 cnt -= len;
1210                 if (host->part_buf_count == 2) {
1211                         mci_writew(host, DATA(host->data_offset),
1212                                         host->part_buf16);
1213                         host->part_buf_count = 0;
1214                 }
1215         }
1216 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1217         if (unlikely((unsigned long)buf & 0x1)) {
1218                 while (cnt >= 2) {
1219                         u16 aligned_buf[64];
1220                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1221                         int items = len >> 1;
1222                         int i;
1223                         /* memcpy from input buffer into aligned buffer */
1224                         memcpy(aligned_buf, buf, len);
1225                         buf += len;
1226                         cnt -= len;
1227                         /* push data from aligned buffer into fifo */
1228                         for (i = 0; i < items; ++i)
1229                                 mci_writew(host, DATA(host->data_offset),
1230                                                 aligned_buf[i]);
1231                 }
1232         } else
1233 #endif
1234         {
1235                 u16 *pdata = buf;
1236                 for (; cnt >= 2; cnt -= 2)
1237                         mci_writew(host, DATA(host->data_offset), *pdata++);
1238                 buf = pdata;
1239         }
1240         /* put anything remaining in the part_buf */
1241         if (cnt) {
1242                 dw_mci_set_part_bytes(host, buf, cnt);
1243                  /* Push data if we have reached the expected data length */
1244                 if ((data->bytes_xfered + init_cnt) ==
1245                     (data->blksz * data->blocks))
1246                         mci_writew(host, DATA(host->data_offset),
1247                                    host->part_buf16);
1248         }
1249 }
1250
1251 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1252 {
1253 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1254         if (unlikely((unsigned long)buf & 0x1)) {
1255                 while (cnt >= 2) {
1256                         /* pull data from fifo into aligned buffer */
1257                         u16 aligned_buf[64];
1258                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1259                         int items = len >> 1;
1260                         int i;
1261                         for (i = 0; i < items; ++i)
1262                                 aligned_buf[i] = mci_readw(host,
1263                                                 DATA(host->data_offset));
1264                         /* memcpy from aligned buffer into output buffer */
1265                         memcpy(buf, aligned_buf, len);
1266                         buf += len;
1267                         cnt -= len;
1268                 }
1269         } else
1270 #endif
1271         {
1272                 u16 *pdata = buf;
1273                 for (; cnt >= 2; cnt -= 2)
1274                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1275                 buf = pdata;
1276         }
1277         if (cnt) {
1278                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1279                 dw_mci_pull_final_bytes(host, buf, cnt);
1280         }
1281 }
1282
1283 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1284 {
1285         struct mmc_data *data = host->data;
1286         int init_cnt = cnt;
1287
1288         /* try and push anything in the part_buf */
1289         if (unlikely(host->part_buf_count)) {
1290                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1291                 buf += len;
1292                 cnt -= len;
1293                 if (host->part_buf_count == 4) {
1294                         mci_writel(host, DATA(host->data_offset),
1295                                         host->part_buf32);
1296                         host->part_buf_count = 0;
1297                 }
1298         }
1299 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1300         if (unlikely((unsigned long)buf & 0x3)) {
1301                 while (cnt >= 4) {
1302                         u32 aligned_buf[32];
1303                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1304                         int items = len >> 2;
1305                         int i;
1306                         /* memcpy from input buffer into aligned buffer */
1307                         memcpy(aligned_buf, buf, len);
1308                         buf += len;
1309                         cnt -= len;
1310                         /* push data from aligned buffer into fifo */
1311                         for (i = 0; i < items; ++i)
1312                                 mci_writel(host, DATA(host->data_offset),
1313                                                 aligned_buf[i]);
1314                 }
1315         } else
1316 #endif
1317         {
1318                 u32 *pdata = buf;
1319                 for (; cnt >= 4; cnt -= 4)
1320                         mci_writel(host, DATA(host->data_offset), *pdata++);
1321                 buf = pdata;
1322         }
1323         /* put anything remaining in the part_buf */
1324         if (cnt) {
1325                 dw_mci_set_part_bytes(host, buf, cnt);
1326                  /* Push data if we have reached the expected data length */
1327                 if ((data->bytes_xfered + init_cnt) ==
1328                     (data->blksz * data->blocks))
1329                         mci_writel(host, DATA(host->data_offset),
1330                                    host->part_buf32);
1331         }
1332 }
1333
1334 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1335 {
1336 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1337         if (unlikely((unsigned long)buf & 0x3)) {
1338                 while (cnt >= 4) {
1339                         /* pull data from fifo into aligned buffer */
1340                         u32 aligned_buf[32];
1341                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1342                         int items = len >> 2;
1343                         int i;
1344                         for (i = 0; i < items; ++i)
1345                                 aligned_buf[i] = mci_readl(host,
1346                                                 DATA(host->data_offset));
1347                         /* memcpy from aligned buffer into output buffer */
1348                         memcpy(buf, aligned_buf, len);
1349                         buf += len;
1350                         cnt -= len;
1351                 }
1352         } else
1353 #endif
1354         {
1355                 u32 *pdata = buf;
1356                 for (; cnt >= 4; cnt -= 4)
1357                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1358                 buf = pdata;
1359         }
1360         if (cnt) {
1361                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1362                 dw_mci_pull_final_bytes(host, buf, cnt);
1363         }
1364 }
1365
1366 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1367 {
1368         struct mmc_data *data = host->data;
1369         int init_cnt = cnt;
1370
1371         /* try and push anything in the part_buf */
1372         if (unlikely(host->part_buf_count)) {
1373                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1374                 buf += len;
1375                 cnt -= len;
1376
1377                 if (host->part_buf_count == 8) {
1378                         mci_writeq(host, DATA(host->data_offset),
1379                                         host->part_buf);
1380                         host->part_buf_count = 0;
1381                 }
1382         }
1383 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1384         if (unlikely((unsigned long)buf & 0x7)) {
1385                 while (cnt >= 8) {
1386                         u64 aligned_buf[16];
1387                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1388                         int items = len >> 3;
1389                         int i;
1390                         /* memcpy from input buffer into aligned buffer */
1391                         memcpy(aligned_buf, buf, len);
1392                         buf += len;
1393                         cnt -= len;
1394                         /* push data from aligned buffer into fifo */
1395                         for (i = 0; i < items; ++i)
1396                                 mci_writeq(host, DATA(host->data_offset),
1397                                                 aligned_buf[i]);
1398                 }
1399         } else
1400 #endif
1401         {
1402                 u64 *pdata = buf;
1403                 for (; cnt >= 8; cnt -= 8)
1404                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1405                 buf = pdata;
1406         }
1407         /* put anything remaining in the part_buf */
1408         if (cnt) {
1409                 dw_mci_set_part_bytes(host, buf, cnt);
1410                 /* Push data if we have reached the expected data length */
1411                 if ((data->bytes_xfered + init_cnt) ==
1412                     (data->blksz * data->blocks))
1413                         mci_writeq(host, DATA(host->data_offset),
1414                                    host->part_buf);
1415         }
1416 }
1417
1418 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1419 {
1420 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1421         if (unlikely((unsigned long)buf & 0x7)) {
1422                 while (cnt >= 8) {
1423                         /* pull data from fifo into aligned buffer */
1424                         u64 aligned_buf[16];
1425                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1426                         int items = len >> 3;
1427                         int i;
1428                         for (i = 0; i < items; ++i)
1429                                 aligned_buf[i] = mci_readq(host,
1430                                                 DATA(host->data_offset));
1431                         /* memcpy from aligned buffer into output buffer */
1432                         memcpy(buf, aligned_buf, len);
1433                         buf += len;
1434                         cnt -= len;
1435                 }
1436         } else
1437 #endif
1438         {
1439                 u64 *pdata = buf;
1440                 for (; cnt >= 8; cnt -= 8)
1441                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1442                 buf = pdata;
1443         }
1444         if (cnt) {
1445                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1446                 dw_mci_pull_final_bytes(host, buf, cnt);
1447         }
1448 }
1449
1450 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1451 {
1452         int len;
1453
1454         /* get remaining partial bytes */
1455         len = dw_mci_pull_part_bytes(host, buf, cnt);
1456         if (unlikely(len == cnt))
1457                 return;
1458         buf += len;
1459         cnt -= len;
1460
1461         /* get the rest of the data */
1462         host->pull_data(host, buf, cnt);
1463 }
1464
1465 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
1466 {
1467         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1468         void *buf;
1469         unsigned int offset;
1470         struct mmc_data *data = host->data;
1471         int shift = host->data_shift;
1472         u32 status;
1473         unsigned int len;
1474         unsigned int remain, fcnt;
1475
1476         do {
1477                 if (!sg_miter_next(sg_miter))
1478                         goto done;
1479
1480                 host->sg = sg_miter->piter.sg;
1481                 buf = sg_miter->addr;
1482                 remain = sg_miter->length;
1483                 offset = 0;
1484
1485                 do {
1486                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1487                                         << shift) + host->part_buf_count;
1488                         len = min(remain, fcnt);
1489                         if (!len)
1490                                 break;
1491                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1492                         data->bytes_xfered += len;
1493                         offset += len;
1494                         remain -= len;
1495                 } while (remain);
1496
1497                 sg_miter->consumed = offset;
1498                 status = mci_readl(host, MINTSTS);
1499                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1500         /* if the RXDR is ready read again */
1501         } while ((status & SDMMC_INT_RXDR) ||
1502                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
1503
1504         if (!remain) {
1505                 if (!sg_miter_next(sg_miter))
1506                         goto done;
1507                 sg_miter->consumed = 0;
1508         }
1509         sg_miter_stop(sg_miter);
1510         return;
1511
1512 done:
1513         sg_miter_stop(sg_miter);
1514         host->sg = NULL;
1515         smp_wmb();
1516         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1517 }
1518
1519 static void dw_mci_write_data_pio(struct dw_mci *host)
1520 {
1521         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1522         void *buf;
1523         unsigned int offset;
1524         struct mmc_data *data = host->data;
1525         int shift = host->data_shift;
1526         u32 status;
1527         unsigned int len;
1528         unsigned int fifo_depth = host->fifo_depth;
1529         unsigned int remain, fcnt;
1530
1531         do {
1532                 if (!sg_miter_next(sg_miter))
1533                         goto done;
1534
1535                 host->sg = sg_miter->piter.sg;
1536                 buf = sg_miter->addr;
1537                 remain = sg_miter->length;
1538                 offset = 0;
1539
1540                 do {
1541                         fcnt = ((fifo_depth -
1542                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1543                                         << shift) - host->part_buf_count;
1544                         len = min(remain, fcnt);
1545                         if (!len)
1546                                 break;
1547                         host->push_data(host, (void *)(buf + offset), len);
1548                         data->bytes_xfered += len;
1549                         offset += len;
1550                         remain -= len;
1551                 } while (remain);
1552
1553                 sg_miter->consumed = offset;
1554                 status = mci_readl(host, MINTSTS);
1555                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1556         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1557
1558         if (!remain) {
1559                 if (!sg_miter_next(sg_miter))
1560                         goto done;
1561                 sg_miter->consumed = 0;
1562         }
1563         sg_miter_stop(sg_miter);
1564         return;
1565
1566 done:
1567         sg_miter_stop(sg_miter);
1568         host->sg = NULL;
1569         smp_wmb();
1570         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1571 }
1572
1573 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1574 {
1575         if (!host->cmd_status)
1576                 host->cmd_status = status;
1577
1578         smp_wmb();
1579
1580         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1581         tasklet_schedule(&host->tasklet);
1582 }
1583
1584 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1585 {
1586         struct dw_mci *host = dev_id;
1587         u32 pending;
1588         int i;
1589
1590         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1591
1592         if (pending) {
1593
1594                 /*
1595                  * DTO fix - version 2.10a and below, and only if internal DMA
1596                  * is configured.
1597                  */
1598                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1599                         if (!pending &&
1600                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1601                                 pending |= SDMMC_INT_DATA_OVER;
1602                 }
1603
1604                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1605                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1606                         host->cmd_status = pending;
1607                         smp_wmb();
1608                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1609                 }
1610
1611                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1612                         /* if there is an error report DATA_ERROR */
1613                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1614                         host->data_status = pending;
1615                         smp_wmb();
1616                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1617                         tasklet_schedule(&host->tasklet);
1618                 }
1619
1620                 if (pending & SDMMC_INT_DATA_OVER) {
1621                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1622                         if (!host->data_status)
1623                                 host->data_status = pending;
1624                         smp_wmb();
1625                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1626                                 if (host->sg != NULL)
1627                                         dw_mci_read_data_pio(host, true);
1628                         }
1629                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1630                         tasklet_schedule(&host->tasklet);
1631                 }
1632
1633                 if (pending & SDMMC_INT_RXDR) {
1634                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1635                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1636                                 dw_mci_read_data_pio(host, false);
1637                 }
1638
1639                 if (pending & SDMMC_INT_TXDR) {
1640                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1641                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1642                                 dw_mci_write_data_pio(host);
1643                 }
1644
1645                 if (pending & SDMMC_INT_CMD_DONE) {
1646                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1647                         dw_mci_cmd_interrupt(host, pending);
1648                 }
1649
1650                 if (pending & SDMMC_INT_CD) {
1651                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1652                         queue_work(host->card_workqueue, &host->card_work);
1653                 }
1654
1655                 /* Handle SDIO Interrupts */
1656                 for (i = 0; i < host->num_slots; i++) {
1657                         struct dw_mci_slot *slot = host->slot[i];
1658                         if (pending & SDMMC_INT_SDIO(i)) {
1659                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1660                                 mmc_signal_sdio_irq(slot->mmc);
1661                         }
1662                 }
1663
1664         }
1665
1666 #ifdef CONFIG_MMC_DW_IDMAC
1667         /* Handle DMA interrupts */
1668         pending = mci_readl(host, IDSTS);
1669         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1670                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1671                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1672                 host->dma_ops->complete(host);
1673         }
1674 #endif
1675
1676         return IRQ_HANDLED;
1677 }
1678
1679 static void dw_mci_work_routine_card(struct work_struct *work)
1680 {
1681         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1682         int i;
1683
1684         for (i = 0; i < host->num_slots; i++) {
1685                 struct dw_mci_slot *slot = host->slot[i];
1686                 struct mmc_host *mmc = slot->mmc;
1687                 struct mmc_request *mrq;
1688                 int present;
1689                 u32 ctrl;
1690
1691                 present = dw_mci_get_cd(mmc);
1692                 while (present != slot->last_detect_state) {
1693                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1694                                 present ? "inserted" : "removed");
1695
1696                         spin_lock_bh(&host->lock);
1697
1698                         /* Card change detected */
1699                         slot->last_detect_state = present;
1700
1701                         /* Mark card as present if applicable */
1702                         if (present != 0)
1703                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1704
1705                         /* Clean up queue if present */
1706                         mrq = slot->mrq;
1707                         if (mrq) {
1708                                 if (mrq == host->mrq) {
1709                                         host->data = NULL;
1710                                         host->cmd = NULL;
1711
1712                                         switch (host->state) {
1713                                         case STATE_IDLE:
1714                                                 break;
1715                                         case STATE_SENDING_CMD:
1716                                                 mrq->cmd->error = -ENOMEDIUM;
1717                                                 if (!mrq->data)
1718                                                         break;
1719                                                 /* fall through */
1720                                         case STATE_SENDING_DATA:
1721                                                 mrq->data->error = -ENOMEDIUM;
1722                                                 dw_mci_stop_dma(host);
1723                                                 break;
1724                                         case STATE_DATA_BUSY:
1725                                         case STATE_DATA_ERROR:
1726                                                 if (mrq->data->error == -EINPROGRESS)
1727                                                         mrq->data->error = -ENOMEDIUM;
1728                                                 if (!mrq->stop)
1729                                                         break;
1730                                                 /* fall through */
1731                                         case STATE_SENDING_STOP:
1732                                                 mrq->stop->error = -ENOMEDIUM;
1733                                                 break;
1734                                         }
1735
1736                                         dw_mci_request_end(host, mrq);
1737                                 } else {
1738                                         list_del(&slot->queue_node);
1739                                         mrq->cmd->error = -ENOMEDIUM;
1740                                         if (mrq->data)
1741                                                 mrq->data->error = -ENOMEDIUM;
1742                                         if (mrq->stop)
1743                                                 mrq->stop->error = -ENOMEDIUM;
1744
1745                                         spin_unlock(&host->lock);
1746                                         mmc_request_done(slot->mmc, mrq);
1747                                         spin_lock(&host->lock);
1748                                 }
1749                         }
1750
1751                         /* Power down slot */
1752                         if (present == 0) {
1753                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1754
1755                                 /*
1756                                  * Clear down the FIFO - doing so generates a
1757                                  * block interrupt, hence setting the
1758                                  * scatter-gather pointer to NULL.
1759                                  */
1760                                 sg_miter_stop(&host->sg_miter);
1761                                 host->sg = NULL;
1762
1763                                 ctrl = mci_readl(host, CTRL);
1764                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1765                                 mci_writel(host, CTRL, ctrl);
1766
1767 #ifdef CONFIG_MMC_DW_IDMAC
1768                                 ctrl = mci_readl(host, BMOD);
1769                                 /* Software reset of DMA */
1770                                 ctrl |= SDMMC_IDMAC_SWRESET;
1771                                 mci_writel(host, BMOD, ctrl);
1772 #endif
1773
1774                         }
1775
1776                         spin_unlock_bh(&host->lock);
1777
1778                         present = dw_mci_get_cd(mmc);
1779                 }
1780
1781                 mmc_detect_change(slot->mmc,
1782                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1783         }
1784 }
1785
1786 #ifdef CONFIG_OF
1787 /* given a slot id, find out the device node representing that slot */
1788 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1789 {
1790         struct device_node *np;
1791         const __be32 *addr;
1792         int len;
1793
1794         if (!dev || !dev->of_node)
1795                 return NULL;
1796
1797         for_each_child_of_node(dev->of_node, np) {
1798                 addr = of_get_property(np, "reg", &len);
1799                 if (!addr || (len < sizeof(int)))
1800                         continue;
1801                 if (be32_to_cpup(addr) == slot)
1802                         return np;
1803         }
1804         return NULL;
1805 }
1806
1807 static struct dw_mci_of_slot_quirks {
1808         char *quirk;
1809         int id;
1810 } of_slot_quirks[] = {
1811         {
1812                 .quirk  = "disable-wp",
1813                 .id     = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
1814         },
1815 };
1816
1817 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1818 {
1819         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1820         int quirks = 0;
1821         int idx;
1822
1823         /* get quirks */
1824         for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
1825                 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
1826                         quirks |= of_slot_quirks[idx].id;
1827
1828         return quirks;
1829 }
1830
1831 /* find out bus-width for a given slot */
1832 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1833 {
1834         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1835         u32 bus_wd = 1;
1836
1837         if (!np)
1838                 return 1;
1839
1840         if (of_property_read_u32(np, "bus-width", &bus_wd))
1841                 dev_err(dev, "bus-width property not found, assuming width"
1842                                " as 1\n");
1843         return bus_wd;
1844 }
1845
1846 /* find the write protect gpio for a given slot; or -1 if none specified */
1847 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
1848 {
1849         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1850         int gpio;
1851
1852         if (!np)
1853                 return -EINVAL;
1854
1855         gpio = of_get_named_gpio(np, "wp-gpios", 0);
1856
1857         /* Having a missing entry is valid; return silently */
1858         if (!gpio_is_valid(gpio))
1859                 return -EINVAL;
1860
1861         if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
1862                 dev_warn(dev, "gpio [%d] request failed\n", gpio);
1863                 return -EINVAL;
1864         }
1865
1866         return gpio;
1867 }
1868 #else /* CONFIG_OF */
1869 static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
1870 {
1871         return 0;
1872 }
1873 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1874 {
1875         return 1;
1876 }
1877 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1878 {
1879         return NULL;
1880 }
1881 static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
1882 {
1883         return -EINVAL;
1884 }
1885 #endif /* CONFIG_OF */
1886
1887 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1888 {
1889         struct mmc_host *mmc;
1890         struct dw_mci_slot *slot;
1891         const struct dw_mci_drv_data *drv_data = host->drv_data;
1892         int ctrl_id, ret;
1893         u8 bus_width;
1894
1895         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
1896         if (!mmc)
1897                 return -ENOMEM;
1898
1899         slot = mmc_priv(mmc);
1900         slot->id = id;
1901         slot->mmc = mmc;
1902         slot->host = host;
1903         host->slot[id] = slot;
1904
1905         slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
1906
1907         mmc->ops = &dw_mci_ops;
1908         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1909         mmc->f_max = host->bus_hz;
1910
1911         if (host->pdata->get_ocr)
1912                 mmc->ocr_avail = host->pdata->get_ocr(id);
1913         else
1914                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1915
1916         /*
1917          * Start with slot power disabled, it will be enabled when a card
1918          * is detected.
1919          */
1920         if (host->pdata->setpower)
1921                 host->pdata->setpower(id, 0);
1922
1923         if (host->pdata->caps)
1924                 mmc->caps = host->pdata->caps;
1925
1926         if (host->pdata->pm_caps)
1927                 mmc->pm_caps = host->pdata->pm_caps;
1928
1929         if (host->dev->of_node) {
1930                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1931                 if (ctrl_id < 0)
1932                         ctrl_id = 0;
1933         } else {
1934                 ctrl_id = to_platform_device(host->dev)->id;
1935         }
1936         if (drv_data && drv_data->caps)
1937                 mmc->caps |= drv_data->caps[ctrl_id];
1938
1939         if (host->pdata->caps2)
1940                 mmc->caps2 = host->pdata->caps2;
1941
1942         if (host->pdata->get_bus_wd)
1943                 bus_width = host->pdata->get_bus_wd(slot->id);
1944         else if (host->dev->of_node)
1945                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1946         else
1947                 bus_width = 1;
1948
1949         if (drv_data && drv_data->setup_bus) {
1950                 struct device_node *slot_np;
1951                 slot_np = dw_mci_of_find_slot_node(host->dev, slot->id);
1952                 ret = drv_data->setup_bus(host, slot_np, bus_width);
1953                 if (ret)
1954                         goto err_setup_bus;
1955         }
1956
1957         switch (bus_width) {
1958         case 8:
1959                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1960         case 4:
1961                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1962         }
1963
1964         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1965                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1966
1967         if (host->pdata->blk_settings) {
1968                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1969                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1970                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1971                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1972                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1973         } else {
1974                 /* Useful defaults if platform data is unset. */
1975 #ifdef CONFIG_MMC_DW_IDMAC
1976                 mmc->max_segs = host->ring_size;
1977                 mmc->max_blk_size = 65536;
1978                 mmc->max_blk_count = host->ring_size;
1979                 mmc->max_seg_size = 0x1000;
1980                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1981 #else
1982                 mmc->max_segs = 64;
1983                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1984                 mmc->max_blk_count = 512;
1985                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1986                 mmc->max_seg_size = mmc->max_req_size;
1987 #endif /* CONFIG_MMC_DW_IDMAC */
1988         }
1989
1990         host->vmmc = devm_regulator_get(mmc_dev(mmc), "vmmc");
1991         if (IS_ERR(host->vmmc)) {
1992                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1993                 host->vmmc = NULL;
1994         } else
1995                 regulator_enable(host->vmmc);
1996
1997         if (dw_mci_get_cd(mmc))
1998                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1999         else
2000                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2001
2002         slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
2003
2004         ret = mmc_add_host(mmc);
2005         if (ret)
2006                 goto err_setup_bus;
2007
2008 #if defined(CONFIG_DEBUG_FS)
2009         dw_mci_init_debugfs(slot);
2010 #endif
2011
2012         /* Card initially undetected */
2013         slot->last_detect_state = 0;
2014
2015         /*
2016          * Card may have been plugged in prior to boot so we
2017          * need to run the detect tasklet
2018          */
2019         queue_work(host->card_workqueue, &host->card_work);
2020
2021         return 0;
2022
2023 err_setup_bus:
2024         mmc_free_host(mmc);
2025         return -EINVAL;
2026 }
2027
2028 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2029 {
2030         /* Shutdown detect IRQ */
2031         if (slot->host->pdata->exit)
2032                 slot->host->pdata->exit(id);
2033
2034         /* Debugfs stuff is cleaned up by mmc core */
2035         mmc_remove_host(slot->mmc);
2036         slot->host->slot[id] = NULL;
2037         mmc_free_host(slot->mmc);
2038 }
2039
2040 static void dw_mci_init_dma(struct dw_mci *host)
2041 {
2042         /* Alloc memory for sg translation */
2043         host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2044                                           &host->sg_dma, GFP_KERNEL);
2045         if (!host->sg_cpu) {
2046                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2047                         __func__);
2048                 goto no_dma;
2049         }
2050
2051         /* Determine which DMA interface to use */
2052 #ifdef CONFIG_MMC_DW_IDMAC
2053         host->dma_ops = &dw_mci_idmac_ops;
2054         dev_info(host->dev, "Using internal DMA controller.\n");
2055 #endif
2056
2057         if (!host->dma_ops)
2058                 goto no_dma;
2059
2060         if (host->dma_ops->init && host->dma_ops->start &&
2061             host->dma_ops->stop && host->dma_ops->cleanup) {
2062                 if (host->dma_ops->init(host)) {
2063                         dev_err(host->dev, "%s: Unable to initialize "
2064                                 "DMA Controller.\n", __func__);
2065                         goto no_dma;
2066                 }
2067         } else {
2068                 dev_err(host->dev, "DMA initialization not found.\n");
2069                 goto no_dma;
2070         }
2071
2072         host->use_dma = 1;
2073         return;
2074
2075 no_dma:
2076         dev_info(host->dev, "Using PIO mode.\n");
2077         host->use_dma = 0;
2078         return;
2079 }
2080
2081 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2082 {
2083         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2084         unsigned int ctrl;
2085
2086         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2087                                 SDMMC_CTRL_DMA_RESET));
2088
2089         /* wait till resets clear */
2090         do {
2091                 ctrl = mci_readl(host, CTRL);
2092                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2093                               SDMMC_CTRL_DMA_RESET)))
2094                         return true;
2095         } while (time_before(jiffies, timeout));
2096
2097         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2098
2099         return false;
2100 }
2101
2102 #ifdef CONFIG_OF
2103 static struct dw_mci_of_quirks {
2104         char *quirk;
2105         int id;
2106 } of_quirks[] = {
2107         {
2108                 .quirk  = "supports-highspeed",
2109                 .id     = DW_MCI_QUIRK_HIGHSPEED,
2110         }, {
2111                 .quirk  = "broken-cd",
2112                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2113         },
2114 };
2115
2116 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2117 {
2118         struct dw_mci_board *pdata;
2119         struct device *dev = host->dev;
2120         struct device_node *np = dev->of_node;
2121         const struct dw_mci_drv_data *drv_data = host->drv_data;
2122         int idx, ret;
2123
2124         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2125         if (!pdata) {
2126                 dev_err(dev, "could not allocate memory for pdata\n");
2127                 return ERR_PTR(-ENOMEM);
2128         }
2129
2130         /* find out number of slots supported */
2131         if (of_property_read_u32(dev->of_node, "num-slots",
2132                                 &pdata->num_slots)) {
2133                 dev_info(dev, "num-slots property not found, "
2134                                 "assuming 1 slot is available\n");
2135                 pdata->num_slots = 1;
2136         }
2137
2138         /* get quirks */
2139         for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2140                 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2141                         pdata->quirks |= of_quirks[idx].id;
2142
2143         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2144                 dev_info(dev, "fifo-depth property not found, using "
2145                                 "value of FIFOTH register as default\n");
2146
2147         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2148
2149         if (drv_data && drv_data->parse_dt) {
2150                 ret = drv_data->parse_dt(host);
2151                 if (ret)
2152                         return ERR_PTR(ret);
2153         }
2154
2155         if (of_find_property(np, "keep-power-in-suspend", NULL))
2156                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2157
2158         if (of_find_property(np, "enable-sdio-wakeup", NULL))
2159                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2160
2161         return pdata;
2162 }
2163
2164 #else /* CONFIG_OF */
2165 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2166 {
2167         return ERR_PTR(-EINVAL);
2168 }
2169 #endif /* CONFIG_OF */
2170
2171 int dw_mci_probe(struct dw_mci *host)
2172 {
2173         const struct dw_mci_drv_data *drv_data = host->drv_data;
2174         int width, i, ret = 0;
2175         u32 fifo_size;
2176         int init_slots = 0;
2177
2178         if (!host->pdata) {
2179                 host->pdata = dw_mci_parse_dt(host);
2180                 if (IS_ERR(host->pdata)) {
2181                         dev_err(host->dev, "platform data not available\n");
2182                         return -EINVAL;
2183                 }
2184         }
2185
2186         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
2187                 dev_err(host->dev,
2188                         "Platform data must supply select_slot function\n");
2189                 return -ENODEV;
2190         }
2191
2192         host->biu_clk = devm_clk_get(host->dev, "biu");
2193         if (IS_ERR(host->biu_clk)) {
2194                 dev_dbg(host->dev, "biu clock not available\n");
2195         } else {
2196                 ret = clk_prepare_enable(host->biu_clk);
2197                 if (ret) {
2198                         dev_err(host->dev, "failed to enable biu clock\n");
2199                         return ret;
2200                 }
2201         }
2202
2203         host->ciu_clk = devm_clk_get(host->dev, "ciu");
2204         if (IS_ERR(host->ciu_clk)) {
2205                 dev_dbg(host->dev, "ciu clock not available\n");
2206         } else {
2207                 ret = clk_prepare_enable(host->ciu_clk);
2208                 if (ret) {
2209                         dev_err(host->dev, "failed to enable ciu clock\n");
2210                         goto err_clk_biu;
2211                 }
2212         }
2213
2214         if (IS_ERR(host->ciu_clk))
2215                 host->bus_hz = host->pdata->bus_hz;
2216         else
2217                 host->bus_hz = clk_get_rate(host->ciu_clk);
2218
2219         if (drv_data && drv_data->setup_clock) {
2220                 ret = drv_data->setup_clock(host);
2221                 if (ret) {
2222                         dev_err(host->dev,
2223                                 "implementation specific clock setup failed\n");
2224                         goto err_clk_ciu;
2225                 }
2226         }
2227
2228         if (!host->bus_hz) {
2229                 dev_err(host->dev,
2230                         "Platform data must supply bus speed\n");
2231                 ret = -ENODEV;
2232                 goto err_clk_ciu;
2233         }
2234
2235         host->quirks = host->pdata->quirks;
2236
2237         spin_lock_init(&host->lock);
2238         INIT_LIST_HEAD(&host->queue);
2239
2240         /*
2241          * Get the host data width - this assumes that HCON has been set with
2242          * the correct values.
2243          */
2244         i = (mci_readl(host, HCON) >> 7) & 0x7;
2245         if (!i) {
2246                 host->push_data = dw_mci_push_data16;
2247                 host->pull_data = dw_mci_pull_data16;
2248                 width = 16;
2249                 host->data_shift = 1;
2250         } else if (i == 2) {
2251                 host->push_data = dw_mci_push_data64;
2252                 host->pull_data = dw_mci_pull_data64;
2253                 width = 64;
2254                 host->data_shift = 3;
2255         } else {
2256                 /* Check for a reserved value, and warn if it is */
2257                 WARN((i != 1),
2258                      "HCON reports a reserved host data width!\n"
2259                      "Defaulting to 32-bit access.\n");
2260                 host->push_data = dw_mci_push_data32;
2261                 host->pull_data = dw_mci_pull_data32;
2262                 width = 32;
2263                 host->data_shift = 2;
2264         }
2265
2266         /* Reset all blocks */
2267         if (!mci_wait_reset(host->dev, host))
2268                 return -ENODEV;
2269
2270         host->dma_ops = host->pdata->dma_ops;
2271         dw_mci_init_dma(host);
2272
2273         /* Clear the interrupts for the host controller */
2274         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2275         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2276
2277         /* Put in max timeout */
2278         mci_writel(host, TMOUT, 0xFFFFFFFF);
2279
2280         /*
2281          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2282          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2283          */
2284         if (!host->pdata->fifo_depth) {
2285                 /*
2286                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2287                  * have been overwritten by the bootloader, just like we're
2288                  * about to do, so if you know the value for your hardware, you
2289                  * should put it in the platform data.
2290                  */
2291                 fifo_size = mci_readl(host, FIFOTH);
2292                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2293         } else {
2294                 fifo_size = host->pdata->fifo_depth;
2295         }
2296         host->fifo_depth = fifo_size;
2297         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2298                         ((fifo_size/2) << 0));
2299         mci_writel(host, FIFOTH, host->fifoth_val);
2300
2301         /* disable clock to CIU */
2302         mci_writel(host, CLKENA, 0);
2303         mci_writel(host, CLKSRC, 0);
2304
2305         /*
2306          * In 2.40a spec, Data offset is changed.
2307          * Need to check the version-id and set data-offset for DATA register.
2308          */
2309         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2310         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2311
2312         if (host->verid < DW_MMC_240A)
2313                 host->data_offset = DATA_OFFSET;
2314         else
2315                 host->data_offset = DATA_240A_OFFSET;
2316
2317         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2318         host->card_workqueue = alloc_workqueue("dw-mci-card",
2319                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2320         if (!host->card_workqueue)
2321                 goto err_dmaunmap;
2322         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2323         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2324                                host->irq_flags, "dw-mci", host);
2325         if (ret)
2326                 goto err_workqueue;
2327
2328         if (host->pdata->num_slots)
2329                 host->num_slots = host->pdata->num_slots;
2330         else
2331                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2332
2333         /*
2334          * Enable interrupts for command done, data over, data empty, card det,
2335          * receive ready and error such as transmit, receive timeout, crc error
2336          */
2337         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2338         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2339                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2340                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2341         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2342
2343         dev_info(host->dev, "DW MMC controller at irq %d, "
2344                  "%d bit host data width, "
2345                  "%u deep fifo\n",
2346                  host->irq, width, fifo_size);
2347
2348         /* We need at least one slot to succeed */
2349         for (i = 0; i < host->num_slots; i++) {
2350                 ret = dw_mci_init_slot(host, i);
2351                 if (ret)
2352                         dev_dbg(host->dev, "slot %d init failed\n", i);
2353                 else
2354                         init_slots++;
2355         }
2356
2357         if (init_slots) {
2358                 dev_info(host->dev, "%d slots initialized\n", init_slots);
2359         } else {
2360                 dev_dbg(host->dev, "attempted to initialize %d slots, "
2361                                         "but failed on all\n", host->num_slots);
2362                 goto err_workqueue;
2363         }
2364
2365         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2366                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2367
2368         return 0;
2369
2370 err_workqueue:
2371         destroy_workqueue(host->card_workqueue);
2372
2373 err_dmaunmap:
2374         if (host->use_dma && host->dma_ops->exit)
2375                 host->dma_ops->exit(host);
2376
2377         if (host->vmmc)
2378                 regulator_disable(host->vmmc);
2379
2380 err_clk_ciu:
2381         if (!IS_ERR(host->ciu_clk))
2382                 clk_disable_unprepare(host->ciu_clk);
2383
2384 err_clk_biu:
2385         if (!IS_ERR(host->biu_clk))
2386                 clk_disable_unprepare(host->biu_clk);
2387
2388         return ret;
2389 }
2390 EXPORT_SYMBOL(dw_mci_probe);
2391
2392 void dw_mci_remove(struct dw_mci *host)
2393 {
2394         int i;
2395
2396         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2397         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2398
2399         for (i = 0; i < host->num_slots; i++) {
2400                 dev_dbg(host->dev, "remove slot %d\n", i);
2401                 if (host->slot[i])
2402                         dw_mci_cleanup_slot(host->slot[i], i);
2403         }
2404
2405         /* disable clock to CIU */
2406         mci_writel(host, CLKENA, 0);
2407         mci_writel(host, CLKSRC, 0);
2408
2409         destroy_workqueue(host->card_workqueue);
2410
2411         if (host->use_dma && host->dma_ops->exit)
2412                 host->dma_ops->exit(host);
2413
2414         if (host->vmmc)
2415                 regulator_disable(host->vmmc);
2416
2417         if (!IS_ERR(host->ciu_clk))
2418                 clk_disable_unprepare(host->ciu_clk);
2419
2420         if (!IS_ERR(host->biu_clk))
2421                 clk_disable_unprepare(host->biu_clk);
2422 }
2423 EXPORT_SYMBOL(dw_mci_remove);
2424
2425
2426
2427 #ifdef CONFIG_PM_SLEEP
2428 /*
2429  * TODO: we should probably disable the clock to the card in the suspend path.
2430  */
2431 int dw_mci_suspend(struct dw_mci *host)
2432 {
2433         int i, ret = 0;
2434
2435         for (i = 0; i < host->num_slots; i++) {
2436                 struct dw_mci_slot *slot = host->slot[i];
2437                 if (!slot)
2438                         continue;
2439                 ret = mmc_suspend_host(slot->mmc);
2440                 if (ret < 0) {
2441                         while (--i >= 0) {
2442                                 slot = host->slot[i];
2443                                 if (slot)
2444                                         mmc_resume_host(host->slot[i]->mmc);
2445                         }
2446                         return ret;
2447                 }
2448         }
2449
2450         if (host->vmmc)
2451                 regulator_disable(host->vmmc);
2452
2453         return 0;
2454 }
2455 EXPORT_SYMBOL(dw_mci_suspend);
2456
2457 int dw_mci_resume(struct dw_mci *host)
2458 {
2459         int i, ret;
2460
2461         if (host->vmmc)
2462                 regulator_enable(host->vmmc);
2463
2464         if (!mci_wait_reset(host->dev, host)) {
2465                 ret = -ENODEV;
2466                 return ret;
2467         }
2468
2469         if (host->use_dma && host->dma_ops->init)
2470                 host->dma_ops->init(host);
2471
2472         /* Restore the old value at FIFOTH register */
2473         mci_writel(host, FIFOTH, host->fifoth_val);
2474
2475         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2476         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2477                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2478                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2479         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2480
2481         for (i = 0; i < host->num_slots; i++) {
2482                 struct dw_mci_slot *slot = host->slot[i];
2483                 if (!slot)
2484                         continue;
2485                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2486                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2487                         dw_mci_setup_bus(slot, true);
2488                 }
2489
2490                 ret = mmc_resume_host(host->slot[i]->mmc);
2491                 if (ret < 0)
2492                         return ret;
2493         }
2494         return 0;
2495 }
2496 EXPORT_SYMBOL(dw_mci_resume);
2497 #endif /* CONFIG_PM_SLEEP */
2498
2499 static int __init dw_mci_init(void)
2500 {
2501         printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2502         return 0;
2503 }
2504
2505 static void __exit dw_mci_exit(void)
2506 {
2507 }
2508
2509 module_init(dw_mci_init);
2510 module_exit(dw_mci_exit);
2511
2512 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2513 MODULE_AUTHOR("NXP Semiconductor VietNam");
2514 MODULE_AUTHOR("Imagination Technologies Ltd");
2515 MODULE_LICENSE("GPL v2");