2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/ioport.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/highmem.h>
19 #include <linux/log2.h>
20 #include <linux/mmc/host.h>
21 #include <linux/amba/bus.h>
22 #include <linux/clk.h>
23 #include <linux/scatterlist.h>
24 #include <linux/gpio.h>
26 #include <asm/cacheflush.h>
27 #include <asm/div64.h>
29 #include <asm/sizes.h>
30 #include <asm/mach/mmc.h>
34 #define DRIVER_NAME "mmci-pl18x"
36 #define DBG(host,fmt,args...) \
37 pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
39 static unsigned int fmax = 515633;
42 * This must be called with host->lock held
44 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
49 if (desired >= host->mclk) {
51 host->cclk = host->mclk;
53 clk = host->mclk / (2 * desired) - 1;
56 host->cclk = host->mclk / (2 * (clk + 1));
58 if (host->hw_designer == 0x80)
59 clk |= MCI_FCEN; /* Bug fix in ST IP block */
60 clk |= MCI_CLK_ENABLE;
61 /* This hasn't proven to be worthwhile */
62 /* clk |= MCI_CLK_PWRSAVE; */
65 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
68 writel(clk, host->base + MMCICLOCK);
72 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
74 writel(0, host->base + MMCICOMMAND);
82 mrq->data->bytes_xfered = host->data_xfered;
85 * Need to drop the host lock here; mmc_request_done may call
86 * back into the driver...
88 spin_unlock(&host->lock);
89 mmc_request_done(host->mmc, mrq);
90 spin_lock(&host->lock);
93 static void mmci_stop_data(struct mmci_host *host)
95 writel(0, host->base + MMCIDATACTRL);
96 writel(0, host->base + MMCIMASK1);
100 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
102 unsigned int datactrl, timeout, irqmask;
103 unsigned long long clks;
107 DBG(host, "blksz %04x blks %04x flags %08x\n",
108 data->blksz, data->blocks, data->flags);
111 host->size = data->blksz;
112 host->data_xfered = 0;
114 mmci_init_sg(host, data);
116 clks = (unsigned long long)data->timeout_ns * host->cclk;
117 do_div(clks, 1000000000UL);
119 timeout = data->timeout_clks + (unsigned int)clks;
122 writel(timeout, base + MMCIDATATIMER);
123 writel(host->size, base + MMCIDATALENGTH);
125 blksz_bits = ffs(data->blksz) - 1;
126 BUG_ON(1 << blksz_bits != data->blksz);
128 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
129 if (data->flags & MMC_DATA_READ) {
130 datactrl |= MCI_DPSM_DIRECTION;
131 irqmask = MCI_RXFIFOHALFFULLMASK;
134 * If we have less than a FIFOSIZE of bytes to transfer,
135 * trigger a PIO interrupt as soon as any data is available.
137 if (host->size < MCI_FIFOSIZE)
138 irqmask |= MCI_RXDATAAVLBLMASK;
141 * We don't actually need to include "FIFO empty" here
142 * since its implicit in "FIFO half empty".
144 irqmask = MCI_TXFIFOHALFEMPTYMASK;
147 writel(datactrl, base + MMCIDATACTRL);
148 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
149 writel(irqmask, base + MMCIMASK1);
153 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
155 void __iomem *base = host->base;
157 DBG(host, "op %02x arg %08x flags %08x\n",
158 cmd->opcode, cmd->arg, cmd->flags);
160 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
161 writel(0, base + MMCICOMMAND);
165 c |= cmd->opcode | MCI_CPSM_ENABLE;
166 if (cmd->flags & MMC_RSP_PRESENT) {
167 if (cmd->flags & MMC_RSP_136)
168 c |= MCI_CPSM_LONGRSP;
169 c |= MCI_CPSM_RESPONSE;
172 c |= MCI_CPSM_INTERRUPT;
176 writel(cmd->arg, base + MMCIARGUMENT);
177 writel(c, base + MMCICOMMAND);
181 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
184 if (status & MCI_DATABLOCKEND) {
185 host->data_xfered += data->blksz;
187 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
188 if (status & MCI_DATACRCFAIL)
189 data->error = -EILSEQ;
190 else if (status & MCI_DATATIMEOUT)
191 data->error = -ETIMEDOUT;
192 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
194 status |= MCI_DATAEND;
197 * We hit an error condition. Ensure that any data
198 * partially written to a page is properly coherent.
200 if (host->sg_len && data->flags & MMC_DATA_READ)
201 flush_dcache_page(sg_page(host->sg_ptr));
203 if (status & MCI_DATAEND) {
204 mmci_stop_data(host);
207 mmci_request_end(host, data->mrq);
209 mmci_start_command(host, data->stop, 0);
215 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
218 void __iomem *base = host->base;
222 cmd->resp[0] = readl(base + MMCIRESPONSE0);
223 cmd->resp[1] = readl(base + MMCIRESPONSE1);
224 cmd->resp[2] = readl(base + MMCIRESPONSE2);
225 cmd->resp[3] = readl(base + MMCIRESPONSE3);
227 if (status & MCI_CMDTIMEOUT) {
228 cmd->error = -ETIMEDOUT;
229 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
230 cmd->error = -EILSEQ;
233 if (!cmd->data || cmd->error) {
235 mmci_stop_data(host);
236 mmci_request_end(host, cmd->mrq);
237 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
238 mmci_start_data(host, cmd->data);
242 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
244 void __iomem *base = host->base;
247 int host_remain = host->size;
250 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
258 readsl(base + MMCIFIFO, ptr, count >> 2);
262 host_remain -= count;
267 status = readl(base + MMCISTATUS);
268 } while (status & MCI_RXDATAAVLBL);
273 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
275 void __iomem *base = host->base;
279 unsigned int count, maxcnt;
281 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
282 count = min(remain, maxcnt);
284 writesl(base + MMCIFIFO, ptr, count >> 2);
292 status = readl(base + MMCISTATUS);
293 } while (status & MCI_TXFIFOHALFEMPTY);
299 * PIO data transfer IRQ handler.
301 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
303 struct mmci_host *host = dev_id;
304 void __iomem *base = host->base;
307 status = readl(base + MMCISTATUS);
309 DBG(host, "irq1 %08x\n", status);
313 unsigned int remain, len;
317 * For write, we only need to test the half-empty flag
318 * here - if the FIFO is completely empty, then by
319 * definition it is more than half empty.
321 * For read, check for data available.
323 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
327 * Map the current scatter buffer.
329 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
330 remain = host->sg_ptr->length - host->sg_off;
333 if (status & MCI_RXACTIVE)
334 len = mmci_pio_read(host, buffer, remain);
335 if (status & MCI_TXACTIVE)
336 len = mmci_pio_write(host, buffer, remain, status);
341 mmci_kunmap_atomic(host, buffer, &flags);
351 * If we were reading, and we have completed this
352 * page, ensure that the data cache is coherent.
354 if (status & MCI_RXACTIVE)
355 flush_dcache_page(sg_page(host->sg_ptr));
357 if (!mmci_next_sg(host))
360 status = readl(base + MMCISTATUS);
364 * If we're nearing the end of the read, switch to
365 * "any data available" mode.
367 if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
368 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
371 * If we run out of data, disable the data IRQs; this
372 * prevents a race where the FIFO becomes empty before
373 * the chip itself has disabled the data path, and
374 * stops us racing with our data end IRQ.
376 if (host->size == 0) {
377 writel(0, base + MMCIMASK1);
378 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
385 * Handle completion of command and data transfers.
387 static irqreturn_t mmci_irq(int irq, void *dev_id)
389 struct mmci_host *host = dev_id;
393 spin_lock(&host->lock);
396 struct mmc_command *cmd;
397 struct mmc_data *data;
399 status = readl(host->base + MMCISTATUS);
400 status &= readl(host->base + MMCIMASK0);
401 writel(status, host->base + MMCICLEAR);
403 DBG(host, "irq0 %08x\n", status);
406 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
407 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
408 mmci_data_irq(host, data, status);
411 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
412 mmci_cmd_irq(host, cmd, status);
417 spin_unlock(&host->lock);
419 return IRQ_RETVAL(ret);
422 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
424 struct mmci_host *host = mmc_priv(mmc);
427 WARN_ON(host->mrq != NULL);
429 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
430 printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n",
431 mmc_hostname(mmc), mrq->data->blksz);
432 mrq->cmd->error = -EINVAL;
433 mmc_request_done(mmc, mrq);
437 spin_lock_irqsave(&host->lock, flags);
441 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
442 mmci_start_data(host, mrq->data);
444 mmci_start_command(host, mrq->cmd, 0);
446 spin_unlock_irqrestore(&host->lock, flags);
449 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
451 struct mmci_host *host = mmc_priv(mmc);
455 if (host->plat->translate_vdd)
456 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
458 switch (ios->power_mode) {
462 /* The ST version does not have this, fall through to POWER_ON */
463 if (host->hw_designer != AMBA_VENDOR_ST) {
472 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
473 if (host->hw_designer != AMBA_VENDOR_ST)
477 * The ST Micro variant use the ROD bit for something
478 * else and only has OD (Open Drain).
484 spin_lock_irqsave(&host->lock, flags);
486 mmci_set_clkreg(host, ios->clock);
488 if (host->pwr != pwr) {
490 writel(pwr, host->base + MMCIPOWER);
493 spin_unlock_irqrestore(&host->lock, flags);
496 static int mmci_get_ro(struct mmc_host *mmc)
498 struct mmci_host *host = mmc_priv(mmc);
500 if (host->gpio_wp == -ENOSYS)
503 return gpio_get_value(host->gpio_wp);
506 static int mmci_get_cd(struct mmc_host *mmc)
508 struct mmci_host *host = mmc_priv(mmc);
511 if (host->gpio_cd == -ENOSYS)
512 status = host->plat->status(mmc_dev(host->mmc));
514 status = gpio_get_value(host->gpio_cd);
519 static const struct mmc_host_ops mmci_ops = {
520 .request = mmci_request,
521 .set_ios = mmci_set_ios,
522 .get_ro = mmci_get_ro,
523 .get_cd = mmci_get_cd,
526 static void mmci_check_status(unsigned long data)
528 struct mmci_host *host = (struct mmci_host *)data;
529 unsigned int status = mmci_get_cd(host->mmc);
531 if (status ^ host->oldstat)
532 mmc_detect_change(host->mmc, 0);
534 host->oldstat = status;
535 mod_timer(&host->timer, jiffies + HZ);
538 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
540 struct mmc_platform_data *plat = dev->dev.platform_data;
541 struct mmci_host *host;
542 struct mmc_host *mmc;
545 /* must have platform data */
551 ret = amba_request_regions(dev, DRIVER_NAME);
555 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
561 host = mmc_priv(mmc);
564 host->gpio_wp = -ENOSYS;
565 host->gpio_cd = -ENOSYS;
567 host->hw_designer = amba_manf(dev);
568 host->hw_revision = amba_rev(dev);
569 DBG(host, "designer ID = 0x%02x\n", host->hw_designer);
570 DBG(host, "revision = 0x%01x\n", host->hw_revision);
572 host->clk = clk_get(&dev->dev, NULL);
573 if (IS_ERR(host->clk)) {
574 ret = PTR_ERR(host->clk);
579 ret = clk_enable(host->clk);
584 host->mclk = clk_get_rate(host->clk);
586 * According to the spec, mclk is max 100 MHz,
587 * so we try to adjust the clock down to this,
590 if (host->mclk > 100000000) {
591 ret = clk_set_rate(host->clk, 100000000);
594 host->mclk = clk_get_rate(host->clk);
595 DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
597 host->base = ioremap(dev->res.start, resource_size(&dev->res));
603 mmc->ops = &mmci_ops;
604 mmc->f_min = (host->mclk + 511) / 512;
605 mmc->f_max = min(host->mclk, fmax);
606 mmc->ocr_avail = plat->ocr_mask;
607 mmc->caps = plat->capabilities;
612 mmc->max_hw_segs = 16;
613 mmc->max_phys_segs = NR_SG;
616 * Since we only have a 16-bit data length register, we must
617 * ensure that we don't exceed 2^16-1 bytes in a single request.
619 mmc->max_req_size = 65535;
622 * Set the maximum segment size. Since we aren't doing DMA
623 * (yet) we are only limited by the data length register.
625 mmc->max_seg_size = mmc->max_req_size;
628 * Block size can be up to 2048 bytes, but must be a power of two.
630 mmc->max_blk_size = 2048;
633 * No limit on the number of blocks transferred.
635 mmc->max_blk_count = mmc->max_req_size;
637 spin_lock_init(&host->lock);
639 writel(0, host->base + MMCIMASK0);
640 writel(0, host->base + MMCIMASK1);
641 writel(0xfff, host->base + MMCICLEAR);
643 #ifdef CONFIG_GPIOLIB
644 if (gpio_is_valid(plat->gpio_cd)) {
645 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
647 ret = gpio_direction_input(plat->gpio_cd);
649 host->gpio_cd = plat->gpio_cd;
650 else if (ret != -ENOSYS)
653 if (gpio_is_valid(plat->gpio_wp)) {
654 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
656 ret = gpio_direction_input(plat->gpio_wp);
658 host->gpio_wp = plat->gpio_wp;
659 else if (ret != -ENOSYS)
664 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
668 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
672 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
674 amba_set_drvdata(dev, mmc);
675 host->oldstat = mmci_get_cd(host->mmc);
679 printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
680 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
681 (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
683 init_timer(&host->timer);
684 host->timer.data = (unsigned long)host;
685 host->timer.function = mmci_check_status;
686 host->timer.expires = jiffies + HZ;
687 add_timer(&host->timer);
692 free_irq(dev->irq[0], host);
694 if (host->gpio_wp != -ENOSYS)
695 gpio_free(host->gpio_wp);
697 if (host->gpio_cd != -ENOSYS)
698 gpio_free(host->gpio_cd);
702 clk_disable(host->clk);
708 amba_release_regions(dev);
713 static int __devexit mmci_remove(struct amba_device *dev)
715 struct mmc_host *mmc = amba_get_drvdata(dev);
717 amba_set_drvdata(dev, NULL);
720 struct mmci_host *host = mmc_priv(mmc);
722 del_timer_sync(&host->timer);
724 mmc_remove_host(mmc);
726 writel(0, host->base + MMCIMASK0);
727 writel(0, host->base + MMCIMASK1);
729 writel(0, host->base + MMCICOMMAND);
730 writel(0, host->base + MMCIDATACTRL);
732 free_irq(dev->irq[0], host);
733 free_irq(dev->irq[1], host);
735 if (host->gpio_wp != -ENOSYS)
736 gpio_free(host->gpio_wp);
737 if (host->gpio_cd != -ENOSYS)
738 gpio_free(host->gpio_cd);
741 clk_disable(host->clk);
746 amba_release_regions(dev);
753 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
755 struct mmc_host *mmc = amba_get_drvdata(dev);
759 struct mmci_host *host = mmc_priv(mmc);
761 ret = mmc_suspend_host(mmc, state);
763 writel(0, host->base + MMCIMASK0);
769 static int mmci_resume(struct amba_device *dev)
771 struct mmc_host *mmc = amba_get_drvdata(dev);
775 struct mmci_host *host = mmc_priv(mmc);
777 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
779 ret = mmc_resume_host(mmc);
785 #define mmci_suspend NULL
786 #define mmci_resume NULL
789 static struct amba_id mmci_ids[] = {
798 /* ST Micro variants */
810 static struct amba_driver mmci_driver = {
815 .remove = __devexit_p(mmci_remove),
816 .suspend = mmci_suspend,
817 .resume = mmci_resume,
818 .id_table = mmci_ids,
821 static int __init mmci_init(void)
823 return amba_driver_register(&mmci_driver);
826 static void __exit mmci_exit(void)
828 amba_driver_unregister(&mmci_driver);
831 module_init(mmci_init);
832 module_exit(mmci_exit);
833 module_param(fmax, uint, 0444);
835 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
836 MODULE_LICENSE("GPL");