2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
39 #include <asm/sizes.h>
44 #define DRIVER_NAME "mxc-mmc"
46 #define MMC_REG_STR_STP_CLK 0x00
47 #define MMC_REG_STATUS 0x04
48 #define MMC_REG_CLK_RATE 0x08
49 #define MMC_REG_CMD_DAT_CONT 0x0C
50 #define MMC_REG_RES_TO 0x10
51 #define MMC_REG_READ_TO 0x14
52 #define MMC_REG_BLK_LEN 0x18
53 #define MMC_REG_NOB 0x1C
54 #define MMC_REG_REV_NO 0x20
55 #define MMC_REG_INT_CNTR 0x24
56 #define MMC_REG_CMD 0x28
57 #define MMC_REG_ARG 0x2C
58 #define MMC_REG_RES_FIFO 0x34
59 #define MMC_REG_BUFFER_ACCESS 0x38
61 #define STR_STP_CLK_RESET (1 << 3)
62 #define STR_STP_CLK_START_CLK (1 << 1)
63 #define STR_STP_CLK_STOP_CLK (1 << 0)
65 #define STATUS_CARD_INSERTION (1 << 31)
66 #define STATUS_CARD_REMOVAL (1 << 30)
67 #define STATUS_YBUF_EMPTY (1 << 29)
68 #define STATUS_XBUF_EMPTY (1 << 28)
69 #define STATUS_YBUF_FULL (1 << 27)
70 #define STATUS_XBUF_FULL (1 << 26)
71 #define STATUS_BUF_UND_RUN (1 << 25)
72 #define STATUS_BUF_OVFL (1 << 24)
73 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
74 #define STATUS_END_CMD_RESP (1 << 13)
75 #define STATUS_WRITE_OP_DONE (1 << 12)
76 #define STATUS_DATA_TRANS_DONE (1 << 11)
77 #define STATUS_READ_OP_DONE (1 << 11)
78 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
79 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
80 #define STATUS_BUF_READ_RDY (1 << 7)
81 #define STATUS_BUF_WRITE_RDY (1 << 6)
82 #define STATUS_RESP_CRC_ERR (1 << 5)
83 #define STATUS_CRC_READ_ERR (1 << 3)
84 #define STATUS_CRC_WRITE_ERR (1 << 2)
85 #define STATUS_TIME_OUT_RESP (1 << 1)
86 #define STATUS_TIME_OUT_READ (1 << 0)
87 #define STATUS_ERR_MASK 0x2f
89 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
90 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
91 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
92 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
93 #define CMD_DAT_CONT_INIT (1 << 7)
94 #define CMD_DAT_CONT_WRITE (1 << 4)
95 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
96 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
97 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
98 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
100 #define INT_SDIO_INT_WKP_EN (1 << 18)
101 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
102 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
103 #define INT_CARD_INSERTION_EN (1 << 15)
104 #define INT_CARD_REMOVAL_EN (1 << 14)
105 #define INT_SDIO_IRQ_EN (1 << 13)
106 #define INT_DAT0_EN (1 << 12)
107 #define INT_BUF_READ_EN (1 << 4)
108 #define INT_BUF_WRITE_EN (1 << 3)
109 #define INT_END_CMD_RES_EN (1 << 2)
110 #define INT_WRITE_OP_DONE_EN (1 << 1)
111 #define INT_READ_OP_EN (1 << 0)
114 struct mmc_host *mmc;
115 struct resource *res;
119 struct dma_chan *dma;
120 struct dma_async_tx_descriptor *desc;
122 int default_irq_mask;
124 unsigned int power_mode;
125 struct imxmmc_platform_data *pdata;
127 struct mmc_request *req;
128 struct mmc_command *cmd;
129 struct mmc_data *data;
131 unsigned int datasize;
132 unsigned int dma_dir;
141 struct work_struct datawork;
144 struct regulator *vcc;
148 struct dma_slave_config dma_slave_config;
149 struct imx_dma_data dma_data;
152 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
154 static inline void mxcmci_init_ocr(struct mxcmci_host *host)
156 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
158 if (IS_ERR(host->vcc)) {
161 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
162 if (host->pdata && host->pdata->ocr_avail)
163 dev_warn(mmc_dev(host->mmc),
164 "pdata->ocr_avail will not be used\n");
167 if (host->vcc == NULL) {
168 /* fall-back to platform data */
169 if (host->pdata && host->pdata->ocr_avail)
170 host->mmc->ocr_avail = host->pdata->ocr_avail;
172 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
176 static inline void mxcmci_set_power(struct mxcmci_host *host,
177 unsigned char power_mode,
181 if (power_mode == MMC_POWER_UP)
182 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
183 else if (power_mode == MMC_POWER_OFF)
184 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
187 if (host->pdata && host->pdata->setpower)
188 host->pdata->setpower(mmc_dev(host->mmc), vdd);
191 static inline int mxcmci_use_dma(struct mxcmci_host *host)
196 static void mxcmci_softreset(struct mxcmci_host *host)
200 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
203 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
204 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
205 host->base + MMC_REG_STR_STP_CLK);
207 for (i = 0; i < 8; i++)
208 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
210 writew(0xff, host->base + MMC_REG_RES_TO);
212 static int mxcmci_setup_dma(struct mmc_host *mmc);
214 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
216 unsigned int nob = data->blocks;
217 unsigned int blksz = data->blksz;
218 unsigned int datasize = nob * blksz;
219 struct scatterlist *sg;
220 enum dma_transfer_direction slave_dirn;
223 if (data->flags & MMC_DATA_STREAM)
227 data->bytes_xfered = 0;
229 writew(nob, host->base + MMC_REG_NOB);
230 writew(blksz, host->base + MMC_REG_BLK_LEN);
231 host->datasize = datasize;
233 if (!mxcmci_use_dma(host))
236 for_each_sg(data->sg, sg, data->sg_len, i) {
237 if (sg->offset & 3 || sg->length & 3) {
243 if (data->flags & MMC_DATA_READ) {
244 host->dma_dir = DMA_FROM_DEVICE;
245 slave_dirn = DMA_DEV_TO_MEM;
247 host->dma_dir = DMA_TO_DEVICE;
248 slave_dirn = DMA_MEM_TO_DEV;
251 nents = dma_map_sg(host->dma->device->dev, data->sg,
252 data->sg_len, host->dma_dir);
253 if (nents != data->sg_len)
256 host->desc = host->dma->device->device_prep_slave_sg(host->dma,
257 data->sg, data->sg_len, slave_dirn,
258 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
261 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
264 return 0; /* Fall back to PIO */
268 dmaengine_submit(host->desc);
273 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
276 u32 int_cntr = host->default_irq_mask;
279 WARN_ON(host->cmd != NULL);
282 switch (mmc_resp_type(cmd)) {
283 case MMC_RSP_R1: /* short CRC, OPCODE */
284 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
285 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
287 case MMC_RSP_R2: /* long 136 bit + CRC */
288 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
290 case MMC_RSP_R3: /* short */
291 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
296 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
298 cmd->error = -EINVAL;
302 int_cntr = INT_END_CMD_RES_EN;
304 if (mxcmci_use_dma(host))
305 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN;
307 spin_lock_irqsave(&host->lock, flags);
309 int_cntr |= INT_SDIO_IRQ_EN;
310 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
311 spin_unlock_irqrestore(&host->lock, flags);
313 writew(cmd->opcode, host->base + MMC_REG_CMD);
314 writel(cmd->arg, host->base + MMC_REG_ARG);
315 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
320 static void mxcmci_finish_request(struct mxcmci_host *host,
321 struct mmc_request *req)
323 u32 int_cntr = host->default_irq_mask;
326 spin_lock_irqsave(&host->lock, flags);
328 int_cntr |= INT_SDIO_IRQ_EN;
329 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
330 spin_unlock_irqrestore(&host->lock, flags);
336 mmc_request_done(host->mmc, req);
339 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
341 struct mmc_data *data = host->data;
344 if (mxcmci_use_dma(host)) {
345 dmaengine_terminate_all(host->dma);
346 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
350 if (stat & STATUS_ERR_MASK) {
351 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
353 if (stat & STATUS_CRC_READ_ERR) {
354 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
355 data->error = -EILSEQ;
356 } else if (stat & STATUS_CRC_WRITE_ERR) {
357 u32 err_code = (stat >> 9) & 0x3;
358 if (err_code == 2) { /* No CRC response */
359 dev_err(mmc_dev(host->mmc),
360 "%s: No CRC -ETIMEDOUT\n", __func__);
361 data->error = -ETIMEDOUT;
363 dev_err(mmc_dev(host->mmc),
364 "%s: -EILSEQ\n", __func__);
365 data->error = -EILSEQ;
367 } else if (stat & STATUS_TIME_OUT_READ) {
368 dev_err(mmc_dev(host->mmc),
369 "%s: read -ETIMEDOUT\n", __func__);
370 data->error = -ETIMEDOUT;
372 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
376 data->bytes_xfered = host->datasize;
379 data_error = data->error;
386 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
388 struct mmc_command *cmd = host->cmd;
395 if (stat & STATUS_TIME_OUT_RESP) {
396 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
397 cmd->error = -ETIMEDOUT;
398 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
399 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
400 cmd->error = -EILSEQ;
403 if (cmd->flags & MMC_RSP_PRESENT) {
404 if (cmd->flags & MMC_RSP_136) {
405 for (i = 0; i < 4; i++) {
406 a = readw(host->base + MMC_REG_RES_FIFO);
407 b = readw(host->base + MMC_REG_RES_FIFO);
408 cmd->resp[i] = a << 16 | b;
411 a = readw(host->base + MMC_REG_RES_FIFO);
412 b = readw(host->base + MMC_REG_RES_FIFO);
413 c = readw(host->base + MMC_REG_RES_FIFO);
414 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
419 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
422 unsigned long timeout = jiffies + HZ;
425 stat = readl(host->base + MMC_REG_STATUS);
426 if (stat & STATUS_ERR_MASK)
428 if (time_after(jiffies, timeout)) {
429 mxcmci_softreset(host);
430 mxcmci_set_clk_rate(host, host->clock);
431 return STATUS_TIME_OUT_READ;
439 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
445 stat = mxcmci_poll_status(host,
446 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
449 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
457 stat = mxcmci_poll_status(host,
458 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
461 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
462 memcpy(b, &tmp, bytes);
468 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
474 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
477 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
485 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
489 memcpy(&tmp, b, bytes);
490 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
493 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
500 static int mxcmci_transfer_data(struct mxcmci_host *host)
502 struct mmc_data *data = host->req->data;
503 struct scatterlist *sg;
509 if (data->flags & MMC_DATA_READ) {
510 for_each_sg(data->sg, sg, data->sg_len, i) {
511 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
514 host->datasize += sg->length;
517 for_each_sg(data->sg, sg, data->sg_len, i) {
518 stat = mxcmci_push(host, sg_virt(sg), sg->length);
521 host->datasize += sg->length;
523 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
530 static void mxcmci_datawork(struct work_struct *work)
532 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
534 int datastat = mxcmci_transfer_data(host);
536 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
537 host->base + MMC_REG_STATUS);
538 mxcmci_finish_data(host, datastat);
540 if (host->req->stop) {
541 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
542 mxcmci_finish_request(host, host->req);
546 mxcmci_finish_request(host, host->req);
550 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
552 struct mmc_data *data = host->data;
558 data_error = mxcmci_finish_data(host, stat);
560 mxcmci_read_response(host, stat);
563 if (host->req->stop) {
564 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
565 mxcmci_finish_request(host, host->req);
569 mxcmci_finish_request(host, host->req);
573 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
575 mxcmci_read_response(host, stat);
578 if (!host->data && host->req) {
579 mxcmci_finish_request(host, host->req);
583 /* For the DMA case the DMA engine handles the data transfer
584 * automatically. For non DMA we have to do it ourselves.
585 * Don't do it in interrupt context though.
587 if (!mxcmci_use_dma(host) && host->data)
588 schedule_work(&host->datawork);
592 static irqreturn_t mxcmci_irq(int irq, void *devid)
594 struct mxcmci_host *host = devid;
599 stat = readl(host->base + MMC_REG_STATUS);
600 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
601 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
603 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
605 spin_lock_irqsave(&host->lock, flags);
606 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
607 spin_unlock_irqrestore(&host->lock, flags);
609 if (mxcmci_use_dma(host) &&
610 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
611 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
612 host->base + MMC_REG_STATUS);
615 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
616 mmc_signal_sdio_irq(host->mmc);
619 if (stat & STATUS_END_CMD_RESP)
620 mxcmci_cmd_done(host, stat);
622 if (mxcmci_use_dma(host) &&
623 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE)))
624 mxcmci_data_done(host, stat);
626 if (host->default_irq_mask &&
627 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
628 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
633 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
635 struct mxcmci_host *host = mmc_priv(mmc);
636 unsigned int cmdat = host->cmdat;
639 WARN_ON(host->req != NULL);
642 host->cmdat &= ~CMD_DAT_CONT_INIT;
648 error = mxcmci_setup_data(host, req->data);
650 req->cmd->error = error;
655 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
657 if (req->data->flags & MMC_DATA_WRITE)
658 cmdat |= CMD_DAT_CONT_WRITE;
661 error = mxcmci_start_cmd(host, req->cmd, cmdat);
665 mxcmci_finish_request(host, req);
668 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
670 unsigned int divider;
672 unsigned int clk_in = clk_get_rate(host->clk);
674 while (prescaler <= 0x800) {
675 for (divider = 1; divider <= 0xF; divider++) {
678 x = (clk_in / (divider + 1));
681 x /= (prescaler * 2);
695 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
697 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
698 prescaler, divider, clk_in, clk_ios);
701 static int mxcmci_setup_dma(struct mmc_host *mmc)
703 struct mxcmci_host *host = mmc_priv(mmc);
704 struct dma_slave_config *config = &host->dma_slave_config;
706 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
707 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
708 config->dst_addr_width = 4;
709 config->src_addr_width = 4;
710 config->dst_maxburst = host->burstlen;
711 config->src_maxburst = host->burstlen;
713 return dmaengine_slave_config(host->dma, config);
716 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
718 struct mxcmci_host *host = mmc_priv(mmc);
722 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
723 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
725 if (ios->bus_width == MMC_BUS_WIDTH_4)
730 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
731 host->burstlen = burstlen;
732 ret = mxcmci_setup_dma(mmc);
734 dev_err(mmc_dev(host->mmc),
735 "failed to config DMA channel. Falling back to PIO\n");
736 dma_release_channel(host->dma);
741 if (ios->bus_width == MMC_BUS_WIDTH_4)
742 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
744 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
746 if (host->power_mode != ios->power_mode) {
747 mxcmci_set_power(host, ios->power_mode, ios->vdd);
748 host->power_mode = ios->power_mode;
750 if (ios->power_mode == MMC_POWER_ON)
751 host->cmdat |= CMD_DAT_CONT_INIT;
755 mxcmci_set_clk_rate(host, ios->clock);
756 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
758 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
761 host->clock = ios->clock;
764 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
766 struct mmc_host *mmc = data;
768 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
770 mmc_detect_change(mmc, msecs_to_jiffies(250));
774 static int mxcmci_get_ro(struct mmc_host *mmc)
776 struct mxcmci_host *host = mmc_priv(mmc);
778 if (host->pdata && host->pdata->get_ro)
779 return !!host->pdata->get_ro(mmc_dev(mmc));
781 * Board doesn't support read only detection; let the mmc core
787 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
789 struct mxcmci_host *host = mmc_priv(mmc);
793 spin_lock_irqsave(&host->lock, flags);
794 host->use_sdio = enable;
795 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
798 int_cntr |= INT_SDIO_IRQ_EN;
800 int_cntr &= ~INT_SDIO_IRQ_EN;
802 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
803 spin_unlock_irqrestore(&host->lock, flags);
806 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
809 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
810 * multi-block transfers when connected SDIO peripheral doesn't
811 * drive the BUSY line as required by the specs.
812 * One way to prevent this is to only allow 1-bit transfers.
815 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO)
816 host->caps &= ~MMC_CAP_4_BIT_DATA;
818 host->caps |= MMC_CAP_4_BIT_DATA;
821 static bool filter(struct dma_chan *chan, void *param)
823 struct mxcmci_host *host = param;
825 if (!imx_dma_is_general_purpose(chan))
828 chan->private = &host->dma_data;
833 static const struct mmc_host_ops mxcmci_ops = {
834 .request = mxcmci_request,
835 .set_ios = mxcmci_set_ios,
836 .get_ro = mxcmci_get_ro,
837 .enable_sdio_irq = mxcmci_enable_sdio_irq,
838 .init_card = mxcmci_init_card,
841 static int mxcmci_probe(struct platform_device *pdev)
843 struct mmc_host *mmc;
844 struct mxcmci_host *host = NULL;
845 struct resource *iores, *r;
849 printk(KERN_INFO "i.MX SDHC driver\n");
851 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852 irq = platform_get_irq(pdev, 0);
853 if (!iores || irq < 0)
856 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
860 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
863 goto out_release_mem;
866 mmc->ops = &mxcmci_ops;
867 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
869 /* MMC core transfer sizes tunable parameters */
871 mmc->max_blk_size = 2048;
872 mmc->max_blk_count = 65535;
873 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
874 mmc->max_seg_size = mmc->max_req_size;
876 host = mmc_priv(mmc);
877 host->base = ioremap(r->start, resource_size(r));
884 host->pdata = pdev->dev.platform_data;
885 spin_lock_init(&host->lock);
887 mxcmci_init_ocr(host);
889 if (host->pdata && host->pdata->dat3_card_detect)
890 host->default_irq_mask =
891 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
893 host->default_irq_mask = 0;
898 host->clk = clk_get(&pdev->dev, NULL);
899 if (IS_ERR(host->clk)) {
900 ret = PTR_ERR(host->clk);
903 clk_enable(host->clk);
905 mxcmci_softreset(host);
907 host->rev_no = readw(host->base + MMC_REG_REV_NO);
908 if (host->rev_no != 0x400) {
910 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
915 mmc->f_min = clk_get_rate(host->clk) >> 16;
916 mmc->f_max = clk_get_rate(host->clk) >> 1;
918 /* recommended in data sheet */
919 writew(0x2db4, host->base + MMC_REG_READ_TO);
921 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
923 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
925 host->dmareq = r->start;
926 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
927 host->dma_data.priority = DMA_PRIO_LOW;
928 host->dma_data.dma_request = host->dmareq;
930 dma_cap_set(DMA_SLAVE, mask);
931 host->dma = dma_request_channel(mask, filter, host);
933 mmc->max_seg_size = dma_get_max_seg_size(
934 host->dma->device->dev);
938 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
940 INIT_WORK(&host->datawork, mxcmci_datawork);
942 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
946 platform_set_drvdata(pdev, mmc);
948 if (host->pdata && host->pdata->init) {
949 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
960 free_irq(host->irq, host);
963 dma_release_channel(host->dma);
965 clk_disable(host->clk);
972 release_mem_region(iores->start, resource_size(iores));
976 static int mxcmci_remove(struct platform_device *pdev)
978 struct mmc_host *mmc = platform_get_drvdata(pdev);
979 struct mxcmci_host *host = mmc_priv(mmc);
981 platform_set_drvdata(pdev, NULL);
983 mmc_remove_host(mmc);
986 regulator_put(host->vcc);
988 if (host->pdata && host->pdata->exit)
989 host->pdata->exit(&pdev->dev, mmc);
991 free_irq(host->irq, host);
995 dma_release_channel(host->dma);
997 clk_disable(host->clk);
1000 release_mem_region(host->res->start, resource_size(host->res));
1008 static int mxcmci_suspend(struct device *dev)
1010 struct mmc_host *mmc = dev_get_drvdata(dev);
1011 struct mxcmci_host *host = mmc_priv(mmc);
1015 ret = mmc_suspend_host(mmc);
1016 clk_disable(host->clk);
1021 static int mxcmci_resume(struct device *dev)
1023 struct mmc_host *mmc = dev_get_drvdata(dev);
1024 struct mxcmci_host *host = mmc_priv(mmc);
1027 clk_enable(host->clk);
1029 ret = mmc_resume_host(mmc);
1034 static const struct dev_pm_ops mxcmci_pm_ops = {
1035 .suspend = mxcmci_suspend,
1036 .resume = mxcmci_resume,
1040 static struct platform_driver mxcmci_driver = {
1041 .probe = mxcmci_probe,
1042 .remove = mxcmci_remove,
1044 .name = DRIVER_NAME,
1045 .owner = THIS_MODULE,
1047 .pm = &mxcmci_pm_ops,
1052 static int __init mxcmci_init(void)
1054 return platform_driver_register(&mxcmci_driver);
1057 static void __exit mxcmci_exit(void)
1059 platform_driver_unregister(&mxcmci_driver);
1062 module_init(mxcmci_init);
1063 module_exit(mxcmci_exit);
1065 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1066 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1067 MODULE_LICENSE("GPL");
1068 MODULE_ALIAS("platform:imx-mmc");