drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/omap-dmaengine.h>
  36 #include <linux/mmc/host.h>
  37 #include <linux/mmc/core.h>
  38 #include <linux/mmc/mmc.h>
  39 #include <linux/io.h>
  40 #include <linux/irq.h>
  41 #include <linux/gpio.h>
  42 #include <linux/regulator/consumer.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/platform_data/hsmmc-omap.h>
  46
  47 /* OMAP HSMMC Host Controller Registers */
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_SDMASA       0x0100
  51 #define OMAP_HSMMC_BLK          0x0104
  52 #define OMAP_HSMMC_ARG          0x0108
  53 #define OMAP_HSMMC_CMD          0x010C
  54 #define OMAP_HSMMC_RSP10        0x0110
  55 #define OMAP_HSMMC_RSP32        0x0114
  56 #define OMAP_HSMMC_RSP54        0x0118
  57 #define OMAP_HSMMC_RSP76        0x011C
  58 #define OMAP_HSMMC_DATA         0x0120
  59 #define OMAP_HSMMC_PSTATE       0x0124
  60 #define OMAP_HSMMC_HCTL         0x0128
  61 #define OMAP_HSMMC_SYSCTL       0x012C
  62 #define OMAP_HSMMC_STAT         0x0130
  63 #define OMAP_HSMMC_IE           0x0134
  64 #define OMAP_HSMMC_ISE          0x0138
  65 #define OMAP_HSMMC_AC12         0x013C
  66 #define OMAP_HSMMC_CAPA         0x0140
  67
  68 #define VS18                    (1 << 26)
  69 #define VS30                    (1 << 25)
  70 #define HSS                     (1 << 21)
  71 #define SDVS18                  (0x5 << 9)
  72 #define SDVS30                  (0x6 << 9)
  73 #define SDVS33                  (0x7 << 9)
  74 #define SDVS_MASK               0x00000E00
  75 #define SDVSCLR                 0xFFFFF1FF
  76 #define SDVSDET                 0x00000400
  77 #define AUTOIDLE                0x1
  78 #define SDBP                    (1 << 8)
  79 #define DTO                     0xe
  80 #define ICE                     0x1
  81 #define ICS                     0x2
  82 #define CEN                     (1 << 2)
  83 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  84 #define CLKD_MASK               0x0000FFC0
  85 #define CLKD_SHIFT              6
  86 #define DTO_MASK                0x000F0000
  87 #define DTO_SHIFT               16
  88 #define INIT_STREAM             (1 << 1)
  89 #define ACEN_ACMD23             (2 << 2)
  90 #define DP_SELECT               (1 << 21)
  91 #define DDIR                    (1 << 4)
  92 #define DMAE                    0x1
  93 #define MSBS                    (1 << 5)
  94 #define BCE                     (1 << 1)
  95 #define FOUR_BIT                (1 << 1)
  96 #define HSPE                    (1 << 2)
  97 #define IWE                     (1 << 24)
  98 #define DDR                     (1 << 19)
  99 #define CLKEXTFREE              (1 << 16)
 100 #define CTPL                    (1 << 11)
 101 #define DW8                     (1 << 5)
 102 #define OD                      0x1
 103 #define STAT_CLEAR              0xFFFFFFFF
 104 #define INIT_STREAM_CMD         0x00000000
 105 #define DUAL_VOLT_OCR_BIT       7
 106 #define SRC                     (1 << 25)
 107 #define SRD                     (1 << 26)
 108 #define SOFTRESET               (1 << 1)
 109
 110 /* PSTATE */
 111 #define DLEV_DAT(x)             (1 << (20 + (x)))
 112
 113 /* Interrupt masks for IE and ISE register */
 114 #define CC_EN                   (1 << 0)
 115 #define TC_EN                   (1 << 1)
 116 #define BWR_EN                  (1 << 4)
 117 #define BRR_EN                  (1 << 5)
 118 #define CIRQ_EN                 (1 << 8)
 119 #define ERR_EN                  (1 << 15)
 120 #define CTO_EN                  (1 << 16)
 121 #define CCRC_EN                 (1 << 17)
 122 #define CEB_EN                  (1 << 18)
 123 #define CIE_EN                  (1 << 19)
 124 #define DTO_EN                  (1 << 20)
 125 #define DCRC_EN                 (1 << 21)
 126 #define DEB_EN                  (1 << 22)
 127 #define ACE_EN                  (1 << 24)
 128 #define CERR_EN                 (1 << 28)
 129 #define BADA_EN                 (1 << 29)
 130
 131 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
 132                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 133                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 134
 135 #define CNI     (1 << 7)
 136 #define ACIE    (1 << 4)
 137 #define ACEB    (1 << 3)
 138 #define ACCE    (1 << 2)
 139 #define ACTO    (1 << 1)
 140 #define ACNE    (1 << 0)
 141
 142 #define MMC_AUTOSUSPEND_DELAY   100
 143 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 144 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 145 #define OMAP_MMC_MIN_CLOCK      400000
 146 #define OMAP_MMC_MAX_CLOCK      52000000
 147 #define DRIVER_NAME             "omap_hsmmc"
 148
 149 #define VDD_1V8                 1800000         /* 180000 uV */
 150 #define VDD_3V0                 3000000         /* 300000 uV */
 151 #define VDD_165_195             (ffs(MMC_VDD_165_195) - 1)
 152
 153 /*
 154  * One controller can have multiple slots, like on some omap boards using
 155  * omap.c controller driver. Luckily this is not currently done on any known
 156  * omap_hsmmc.c device.
 157  */
 158 #define mmc_pdata(host)         host->pdata
 159
 160 /*
 161  * MMC Host controller read/write API's
 162  */
 163 #define OMAP_HSMMC_READ(base, reg)      \
 164         __raw_readl((base) + OMAP_HSMMC_##reg)
 165
 166 #define OMAP_HSMMC_WRITE(base, reg, val) \
 167         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 168
 169 struct omap_hsmmc_next {
 170         unsigned int    dma_len;
 171         s32             cookie;
 172 };
 173
 174 struct omap_hsmmc_host {
 175         struct  device          *dev;
 176         struct  mmc_host        *mmc;
 177         struct  mmc_request     *mrq;
 178         struct  mmc_command     *cmd;
 179         struct  mmc_data        *data;
 180         struct  clk             *fclk;
 181         struct  clk             *dbclk;
 182         /*
 183          * vcc == configured supply
 184          * vcc_aux == optional
 185          *   -  MMC1, supply for DAT4..DAT7
 186          *   -  MMC2/MMC2, external level shifter voltage supply, for
 187          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 188          */
 189         struct  regulator       *vcc;
 190         struct  regulator       *vcc_aux;
 191         struct  regulator       *pbias;
 192         bool                    pbias_enabled;
 193         void    __iomem         *base;
 194         resource_size_t         mapbase;
 195         spinlock_t              irq_lock; /* Prevent races with irq handler */
 196         unsigned int            dma_len;
 197         unsigned int            dma_sg_idx;
 198         unsigned char           bus_mode;
 199         unsigned char           power_mode;
 200         int                     suspended;
 201         u32                     con;
 202         u32                     hctl;
 203         u32                     sysctl;
 204         u32                     capa;
 205         int                     irq;
 206         int                     wake_irq;
 207         int                     use_dma, dma_ch;
 208         struct dma_chan         *tx_chan;
 209         struct dma_chan         *rx_chan;
 210         int                     slot_id;
 211         int                     response_busy;
 212         int                     context_loss;
 213         int                     protect_card;
 214         int                     reqs_blocked;
 215         int                     use_reg;
 216         int                     req_in_progress;
 217         unsigned long           clk_rate;
 218         unsigned int            flags;
 219 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
 220 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
 221 #define HSMMC_WAKE_IRQ_ENABLED  (1 << 2)
 222         struct omap_hsmmc_next  next_data;
 223         struct  omap_hsmmc_platform_data        *pdata;
 224 };
 225
 226 struct omap_mmc_of_data {
 227         u32 reg_offset;
 228         u8 controller_flags;
 229 };
 230
 231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 232
 233 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 234 {
 235         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 236         struct omap_hsmmc_platform_data *mmc = host->pdata;
 237
 238         /* NOTE: assumes card detect signal is active-low */
 239         return !gpio_get_value_cansleep(mmc->switch_pin);
 240 }
 241
 242 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 243 {
 244         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 245         struct omap_hsmmc_platform_data *mmc = host->pdata;
 246
 247         /* NOTE: assumes write protect signal is active-high */
 248         return gpio_get_value_cansleep(mmc->gpio_wp);
 249 }
 250
 251 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 252 {
 253         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 254         struct omap_hsmmc_platform_data *mmc = host->pdata;
 255
 256         /* NOTE: assumes card detect signal is active-low */
 257         return !gpio_get_value_cansleep(mmc->switch_pin);
 258 }
 259
 260 #ifdef CONFIG_PM
 261
 262 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 263 {
 264         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 265         struct omap_hsmmc_platform_data *mmc = host->pdata;
 266
 267         disable_irq(mmc->card_detect_irq);
 268         return 0;
 269 }
 270
 271 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 272 {
 273         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 274         struct omap_hsmmc_platform_data *mmc = host->pdata;
 275
 276         enable_irq(mmc->card_detect_irq);
 277         return 0;
 278 }
 279
 280 #else
 281
 282 #define omap_hsmmc_suspend_cdirq        NULL
 283 #define omap_hsmmc_resume_cdirq         NULL
 284
 285 #endif
 286
 287 #ifdef CONFIG_REGULATOR
 288
 289 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 290                                    int vdd)
 291 {
 292         struct omap_hsmmc_host *host =
 293                 platform_get_drvdata(to_platform_device(dev));
 294         int ret = 0;
 295
 296         /*
 297          * If we don't see a Vcc regulator, assume it's a fixed
 298          * voltage always-on regulator.
 299          */
 300         if (!host->vcc)
 301                 return 0;
 302
 303         if (mmc_pdata(host)->before_set_reg)
 304                 mmc_pdata(host)->before_set_reg(dev, slot, power_on, vdd);
 305
 306         if (host->pbias) {
 307                 if (host->pbias_enabled == 1) {
 308                         ret = regulator_disable(host->pbias);
 309                         if (!ret)
 310                                 host->pbias_enabled = 0;
 311                 }
 312                 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
 313         }
 314
 315         /*
 316          * Assume Vcc regulator is used only to power the card ... OMAP
 317          * VDDS is used to power the pins, optionally with a transceiver to
 318          * support cards using voltages other than VDDS (1.8V nominal).  When a
 319          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 320          *
 321          * In some cases this regulator won't support enable/disable;
 322          * e.g. it's a fixed rail for a WLAN chip.
 323          *
 324          * In other cases vcc_aux switches interface power.  Example, for
 325          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 326          * chips/cards need an interface voltage rail too.
 327          */
 328         if (power_on) {
 329                 if (host->vcc)
 330                         ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 331                 /* Enable interface voltage rail, if needed */
 332                 if (ret == 0 && host->vcc_aux) {
 333                         ret = regulator_enable(host->vcc_aux);
 334                         if (ret < 0 && host->vcc)
 335                                 ret = mmc_regulator_set_ocr(host->mmc,
 336                                                         host->vcc, 0);
 337                 }
 338         } else {
 339                 /* Shut down the rail */
 340                 if (host->vcc_aux)
 341                         ret = regulator_disable(host->vcc_aux);
 342                 if (host->vcc) {
 343                         /* Then proceed to shut down the local regulator */
 344                         ret = mmc_regulator_set_ocr(host->mmc,
 345                                                 host->vcc, 0);
 346                 }
 347         }
 348
 349         if (host->pbias) {
 350                 if (vdd <= VDD_165_195)
 351                         ret = regulator_set_voltage(host->pbias, VDD_1V8,
 352                                                                 VDD_1V8);
 353                 else
 354                         ret = regulator_set_voltage(host->pbias, VDD_3V0,
 355                                                                 VDD_3V0);
 356                 if (ret < 0)
 357                         goto error_set_power;
 358
 359                 if (host->pbias_enabled == 0) {
 360                         ret = regulator_enable(host->pbias);
 361                         if (!ret)
 362                                 host->pbias_enabled = 1;
 363                 }
 364         }
 365
 366         if (mmc_pdata(host)->after_set_reg)
 367                 mmc_pdata(host)->after_set_reg(dev, slot, power_on, vdd);
 368
 369 error_set_power:
 370         return ret;
 371 }
 372
 373 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 374 {
 375         struct regulator *reg;
 376         int ocr_value = 0;
 377
 378         reg = devm_regulator_get(host->dev, "vmmc");
 379         if (IS_ERR(reg)) {
 380                 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
 381                         PTR_ERR(reg));
 382                 return PTR_ERR(reg);
 383         } else {
 384                 host->vcc = reg;
 385                 ocr_value = mmc_regulator_get_ocrmask(reg);
 386                 if (!mmc_pdata(host)->ocr_mask) {
 387                         mmc_pdata(host)->ocr_mask = ocr_value;
 388                 } else {
 389                         if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
 390                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 391                                         mmc_pdata(host)->ocr_mask);
 392                                 mmc_pdata(host)->ocr_mask = 0;
 393                                 return -EINVAL;
 394                         }
 395                 }
 396         }
 397         mmc_pdata(host)->set_power = omap_hsmmc_set_power;
 398
 399         /* Allow an aux regulator */
 400         reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
 401         host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 402
 403         reg = devm_regulator_get_optional(host->dev, "pbias");
 404         host->pbias = IS_ERR(reg) ? NULL : reg;
 405
 406         /* For eMMC do not power off when not in sleep state */
 407         if (mmc_pdata(host)->no_regulator_off_init)
 408                 return 0;
 409         /*
 410          * To disable boot_on regulator, enable regulator
 411          * to increase usecount and then disable it.
 412          */
 413         if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
 414             (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 415                 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
 416
 417                 mmc_pdata(host)->set_power(host->dev, host->slot_id, 1, vdd);
 418                 mmc_pdata(host)->set_power(host->dev, host->slot_id, 0, 0);
 419         }
 420
 421         return 0;
 422 }
 423
 424 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 425 {
 426         mmc_pdata(host)->set_power = NULL;
 427 }
 428
 429 static inline int omap_hsmmc_have_reg(void)
 430 {
 431         return 1;
 432 }
 433
 434 #else
 435
 436 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 437 {
 438         return -EINVAL;
 439 }
 440
 441 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 442 {
 443 }
 444
 445 static inline int omap_hsmmc_have_reg(void)
 446 {
 447         return 0;
 448 }
 449
 450 #endif
 451
 452 static int omap_hsmmc_gpio_init(struct omap_hsmmc_platform_data *pdata)
 453 {
 454         int ret;
 455
 456         if (gpio_is_valid(pdata->switch_pin)) {
 457                 if (pdata->cover)
 458                         pdata->get_cover_state =
 459                                         omap_hsmmc_get_cover_state;
 460                 else
 461                         pdata->card_detect = omap_hsmmc_card_detect;
 462                 pdata->card_detect_irq =
 463                                 gpio_to_irq(pdata->switch_pin);
 464                 ret = gpio_request(pdata->switch_pin, "mmc_cd");
 465                 if (ret)
 466                         return ret;
 467                 ret = gpio_direction_input(pdata->switch_pin);
 468                 if (ret)
 469                         goto err_free_sp;
 470         } else {
 471                 pdata->switch_pin = -EINVAL;
 472         }
 473
 474         if (gpio_is_valid(pdata->gpio_wp)) {
 475                 pdata->get_ro = omap_hsmmc_get_wp;
 476                 ret = gpio_request(pdata->gpio_wp, "mmc_wp");
 477                 if (ret)
 478                         goto err_free_cd;
 479                 ret = gpio_direction_input(pdata->gpio_wp);
 480                 if (ret)
 481                         goto err_free_wp;
 482         } else {
 483                 pdata->gpio_wp = -EINVAL;
 484         }
 485
 486         return 0;
 487
 488 err_free_wp:
 489         gpio_free(pdata->gpio_wp);
 490 err_free_cd:
 491         if (gpio_is_valid(pdata->switch_pin))
 492 err_free_sp:
 493                 gpio_free(pdata->switch_pin);
 494         return ret;
 495 }
 496
 497 static void omap_hsmmc_gpio_free(struct omap_hsmmc_platform_data *pdata)
 498 {
 499         if (gpio_is_valid(pdata->gpio_wp))
 500                 gpio_free(pdata->gpio_wp);
 501         if (gpio_is_valid(pdata->switch_pin))
 502                 gpio_free(pdata->switch_pin);
 503 }
 504
 505 /*
 506  * Start clock to the card
 507  */
 508 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 509 {
 510         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 511                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 512 }
 513
 514 /*
 515  * Stop clock to the card
 516  */
 517 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 518 {
 519         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 520                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 521         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 522                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 523 }
 524
 525 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 526                                   struct mmc_command *cmd)
 527 {
 528         u32 irq_mask = INT_EN_MASK;
 529         unsigned long flags;
 530
 531         if (host->use_dma)
 532                 irq_mask &= ~(BRR_EN | BWR_EN);
 533
 534         /* Disable timeout for erases */
 535         if (cmd->opcode == MMC_ERASE)
 536                 irq_mask &= ~DTO_EN;
 537
 538         spin_lock_irqsave(&host->irq_lock, flags);
 539         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 540         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 541
 542         /* latch pending CIRQ, but don't signal MMC core */
 543         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 544                 irq_mask |= CIRQ_EN;
 545         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 546         spin_unlock_irqrestore(&host->irq_lock, flags);
 547 }
 548
 549 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 550 {
 551         u32 irq_mask = 0;
 552         unsigned long flags;
 553
 554         spin_lock_irqsave(&host->irq_lock, flags);
 555         /* no transfer running but need to keep cirq if enabled */
 556         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 557                 irq_mask |= CIRQ_EN;
 558         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 559         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 560         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 561         spin_unlock_irqrestore(&host->irq_lock, flags);
 562 }
 563
 564 /* Calculate divisor for the given clock frequency */
 565 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 566 {
 567         u16 dsor = 0;
 568
 569         if (ios->clock) {
 570                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 571                 if (dsor > CLKD_MAX)
 572                         dsor = CLKD_MAX;
 573         }
 574
 575         return dsor;
 576 }
 577
 578 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 579 {
 580         struct mmc_ios *ios = &host->mmc->ios;
 581         unsigned long regval;
 582         unsigned long timeout;
 583         unsigned long clkdiv;
 584
 585         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 586
 587         omap_hsmmc_stop_clock(host);
 588
 589         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 590         regval = regval & ~(CLKD_MASK | DTO_MASK);
 591         clkdiv = calc_divisor(host, ios);
 592         regval = regval | (clkdiv << 6) | (DTO << 16);
 593         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 594         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 595                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 596
 597         /* Wait till the ICS bit is set */
 598         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 599         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 600                 && time_before(jiffies, timeout))
 601                 cpu_relax();
 602
 603         /*
 604          * Enable High-Speed Support
 605          * Pre-Requisites
 606          *      - Controller should support High-Speed-Enable Bit
 607          *      - Controller should not be using DDR Mode
 608          *      - Controller should advertise that it supports High Speed
 609          *        in capabilities register
 610          *      - MMC/SD clock coming out of controller > 25MHz
 611          */
 612         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
 613             (ios->timing != MMC_TIMING_MMC_DDR52) &&
 614             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 615                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 616                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 617                         regval |= HSPE;
 618                 else
 619                         regval &= ~HSPE;
 620
 621                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 622         }
 623
 624         omap_hsmmc_start_clock(host);
 625 }
 626
 627 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 628 {
 629         struct mmc_ios *ios = &host->mmc->ios;
 630         u32 con;
 631
 632         con = OMAP_HSMMC_READ(host->base, CON);
 633         if (ios->timing == MMC_TIMING_MMC_DDR52)
 634                 con |= DDR;     /* configure in DDR mode */
 635         else
 636                 con &= ~DDR;
 637         switch (ios->bus_width) {
 638         case MMC_BUS_WIDTH_8:
 639                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 640                 break;
 641         case MMC_BUS_WIDTH_4:
 642                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 643                 OMAP_HSMMC_WRITE(host->base, HCTL,
 644                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 645                 break;
 646         case MMC_BUS_WIDTH_1:
 647                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 648                 OMAP_HSMMC_WRITE(host->base, HCTL,
 649                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 650                 break;
 651         }
 652 }
 653
 654 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 655 {
 656         struct mmc_ios *ios = &host->mmc->ios;
 657         u32 con;
 658
 659         con = OMAP_HSMMC_READ(host->base, CON);
 660         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 661                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 662         else
 663                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 664 }
 665
 666 #ifdef CONFIG_PM
 667
 668 /*
 669  * Restore the MMC host context, if it was lost as result of a
 670  * power state change.
 671  */
 672 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 673 {
 674         struct mmc_ios *ios = &host->mmc->ios;
 675         u32 hctl, capa;
 676         unsigned long timeout;
 677
 678         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 679             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 680             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 681             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 682                 return 0;
 683
 684         host->context_loss++;
 685
 686         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 687                 if (host->power_mode != MMC_POWER_OFF &&
 688                     (1 << ios->vdd) <= MMC_VDD_23_24)
 689                         hctl = SDVS18;
 690                 else
 691                         hctl = SDVS30;
 692                 capa = VS30 | VS18;
 693         } else {
 694                 hctl = SDVS18;
 695                 capa = VS18;
 696         }
 697
 698         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
 699                 hctl |= IWE;
 700
 701         OMAP_HSMMC_WRITE(host->base, HCTL,
 702                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 703
 704         OMAP_HSMMC_WRITE(host->base, CAPA,
 705                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 706
 707         OMAP_HSMMC_WRITE(host->base, HCTL,
 708                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 709
 710         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 711         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 712                 && time_before(jiffies, timeout))
 713                 ;
 714
 715         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 716         OMAP_HSMMC_WRITE(host->base, IE, 0);
 717         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 718
 719         /* Do not initialize card-specific things if the power is off */
 720         if (host->power_mode == MMC_POWER_OFF)
 721                 goto out;
 722
 723         omap_hsmmc_set_bus_width(host);
 724
 725         omap_hsmmc_set_clock(host);
 726
 727         omap_hsmmc_set_bus_mode(host);
 728
 729 out:
 730         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 731                 host->context_loss);
 732         return 0;
 733 }
 734
 735 /*
 736  * Save the MMC host context (store the number of power state changes so far).
 737  */
 738 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 739 {
 740         host->con =  OMAP_HSMMC_READ(host->base, CON);
 741         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 742         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 743         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 744 }
 745
 746 #else
 747
 748 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 749 {
 750         return 0;
 751 }
 752
 753 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 754 {
 755 }
 756
 757 #endif
 758
 759 /*
 760  * Send init stream sequence to card
 761  * before sending IDLE command
 762  */
 763 static void send_init_stream(struct omap_hsmmc_host *host)
 764 {
 765         int reg = 0;
 766         unsigned long timeout;
 767
 768         if (host->protect_card)
 769                 return;
 770
 771         disable_irq(host->irq);
 772
 773         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 774         OMAP_HSMMC_WRITE(host->base, CON,
 775                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 776         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 777
 778         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 779         while ((reg != CC_EN) && time_before(jiffies, timeout))
 780                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 781
 782         OMAP_HSMMC_WRITE(host->base, CON,
 783                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 784
 785         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 786         OMAP_HSMMC_READ(host->base, STAT);
 787
 788         enable_irq(host->irq);
 789 }
 790
 791 static inline
 792 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 793 {
 794         int r = 1;
 795
 796         if (mmc_pdata(host)->get_cover_state)
 797                 r = mmc_pdata(host)->get_cover_state(host->dev, host->slot_id);
 798         return r;
 799 }
 800
 801 static ssize_t
 802 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 803                            char *buf)
 804 {
 805         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 806         struct omap_hsmmc_host *host = mmc_priv(mmc);
 807
 808         return sprintf(buf, "%s\n",
 809                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 810 }
 811
 812 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 813
 814 static ssize_t
 815 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 816                         char *buf)
 817 {
 818         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 819         struct omap_hsmmc_host *host = mmc_priv(mmc);
 820
 821         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
 822 }
 823
 824 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 825
 826 /*
 827  * Configure the response type and send the cmd.
 828  */
 829 static void
 830 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 831         struct mmc_data *data)
 832 {
 833         int cmdreg = 0, resptype = 0, cmdtype = 0;
 834
 835         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 836                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 837         host->cmd = cmd;
 838
 839         omap_hsmmc_enable_irq(host, cmd);
 840
 841         host->response_busy = 0;
 842         if (cmd->flags & MMC_RSP_PRESENT) {
 843                 if (cmd->flags & MMC_RSP_136)
 844                         resptype = 1;
 845                 else if (cmd->flags & MMC_RSP_BUSY) {
 846                         resptype = 3;
 847                         host->response_busy = 1;
 848                 } else
 849                         resptype = 2;
 850         }
 851
 852         /*
 853          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 854          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 855          * a val of 0x3, rest 0x0.
 856          */
 857         if (cmd == host->mrq->stop)
 858                 cmdtype = 0x3;
 859
 860         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 861
 862         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 863             host->mrq->sbc) {
 864                 cmdreg |= ACEN_ACMD23;
 865                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
 866         }
 867         if (data) {
 868                 cmdreg |= DP_SELECT | MSBS | BCE;
 869                 if (data->flags & MMC_DATA_READ)
 870                         cmdreg |= DDIR;
 871                 else
 872                         cmdreg &= ~(DDIR);
 873         }
 874
 875         if (host->use_dma)
 876                 cmdreg |= DMAE;
 877
 878         host->req_in_progress = 1;
 879
 880         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 881         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 882 }
 883
 884 static int
 885 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 886 {
 887         if (data->flags & MMC_DATA_WRITE)
 888                 return DMA_TO_DEVICE;
 889         else
 890                 return DMA_FROM_DEVICE;
 891 }
 892
 893 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 894         struct mmc_data *data)
 895 {
 896         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 897 }
 898
 899 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 900 {
 901         int dma_ch;
 902         unsigned long flags;
 903
 904         spin_lock_irqsave(&host->irq_lock, flags);
 905         host->req_in_progress = 0;
 906         dma_ch = host->dma_ch;
 907         spin_unlock_irqrestore(&host->irq_lock, flags);
 908
 909         omap_hsmmc_disable_irq(host);
 910         /* Do not complete the request if DMA is still in progress */
 911         if (mrq->data && host->use_dma && dma_ch != -1)
 912                 return;
 913         host->mrq = NULL;
 914         mmc_request_done(host->mmc, mrq);
 915 }
 916
 917 /*
 918  * Notify the transfer complete to MMC core
 919  */
 920 static void
 921 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 922 {
 923         if (!data) {
 924                 struct mmc_request *mrq = host->mrq;
 925
 926                 /* TC before CC from CMD6 - don't know why, but it happens */
 927                 if (host->cmd && host->cmd->opcode == 6 &&
 928                     host->response_busy) {
 929                         host->response_busy = 0;
 930                         return;
 931                 }
 932
 933                 omap_hsmmc_request_done(host, mrq);
 934                 return;
 935         }
 936
 937         host->data = NULL;
 938
 939         if (!data->error)
 940                 data->bytes_xfered += data->blocks * (data->blksz);
 941         else
 942                 data->bytes_xfered = 0;
 943
 944         if (data->stop && (data->error || !host->mrq->sbc))
 945                 omap_hsmmc_start_command(host, data->stop, NULL);
 946         else
 947                 omap_hsmmc_request_done(host, data->mrq);
 948 }
 949
 950 /*
 951  * Notify the core about command completion
 952  */
 953 static void
 954 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 955 {
 956         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
 957             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
 958                 host->cmd = NULL;
 959                 omap_hsmmc_start_dma_transfer(host);
 960                 omap_hsmmc_start_command(host, host->mrq->cmd,
 961                                                 host->mrq->data);
 962                 return;
 963         }
 964
 965         host->cmd = NULL;
 966
 967         if (cmd->flags & MMC_RSP_PRESENT) {
 968                 if (cmd->flags & MMC_RSP_136) {
 969                         /* response type 2 */
 970                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 971                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 972                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 973                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 974                 } else {
 975                         /* response types 1, 1b, 3, 4, 5, 6 */
 976                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 977                 }
 978         }
 979         if ((host->data == NULL && !host->response_busy) || cmd->error)
 980                 omap_hsmmc_request_done(host, host->mrq);
 981 }
 982
 983 /*
 984  * DMA clean up for command errors
 985  */
 986 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 987 {
 988         int dma_ch;
 989         unsigned long flags;
 990
 991         host->data->error = errno;
 992
 993         spin_lock_irqsave(&host->irq_lock, flags);
 994         dma_ch = host->dma_ch;
 995         host->dma_ch = -1;
 996         spin_unlock_irqrestore(&host->irq_lock, flags);
 997
 998         if (host->use_dma && dma_ch != -1) {
 999                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1000
1001                 dmaengine_terminate_all(chan);
1002                 dma_unmap_sg(chan->device->dev,
1003                         host->data->sg, host->data->sg_len,
1004                         omap_hsmmc_get_dma_dir(host, host->data));
1005
1006                 host->data->host_cookie = 0;
1007         }
1008         host->data = NULL;
1009 }
1010
1011 /*
1012  * Readable error output
1013  */
1014 #ifdef CONFIG_MMC_DEBUG
1015 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1016 {
1017         /* --- means reserved bit without definition at documentation */
1018         static const char *omap_hsmmc_status_bits[] = {
1019                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1020                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1021                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1022                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1023         };
1024         char res[256];
1025         char *buf = res;
1026         int len, i;
1027
1028         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1029         buf += len;
1030
1031         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1032                 if (status & (1 << i)) {
1033                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1034                         buf += len;
1035                 }
1036
1037         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1038 }
1039 #else
1040 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1041                                              u32 status)
1042 {
1043 }
1044 #endif  /* CONFIG_MMC_DEBUG */
1045
1046 /*
1047  * MMC controller internal state machines reset
1048  *
1049  * Used to reset command or data internal state machines, using respectively
1050  *  SRC or SRD bit of SYSCTL register
1051  * Can be called from interrupt context
1052  */
1053 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1054                                                    unsigned long bit)
1055 {
1056         unsigned long i = 0;
1057         unsigned long limit = MMC_TIMEOUT_US;
1058
1059         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1060                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1061
1062         /*
1063          * OMAP4 ES2 and greater has an updated reset logic.
1064          * Monitor a 0->1 transition first
1065          */
1066         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1067                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1068                                         && (i++ < limit))
1069                         udelay(1);
1070         }
1071         i = 0;
1072
1073         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1074                 (i++ < limit))
1075                 udelay(1);
1076
1077         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1078                 dev_err(mmc_dev(host->mmc),
1079                         "Timeout waiting on controller reset in %s\n",
1080                         __func__);
1081 }
1082
1083 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1084                                         int err, int end_cmd)
1085 {
1086         if (end_cmd) {
1087                 omap_hsmmc_reset_controller_fsm(host, SRC);
1088                 if (host->cmd)
1089                         host->cmd->error = err;
1090         }
1091
1092         if (host->data) {
1093                 omap_hsmmc_reset_controller_fsm(host, SRD);
1094                 omap_hsmmc_dma_cleanup(host, err);
1095         } else if (host->mrq && host->mrq->cmd)
1096                 host->mrq->cmd->error = err;
1097 }
1098
1099 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1100 {
1101         struct mmc_data *data;
1102         int end_cmd = 0, end_trans = 0;
1103         int error = 0;
1104
1105         data = host->data;
1106         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1107
1108         if (status & ERR_EN) {
1109                 omap_hsmmc_dbg_report_irq(host, status);
1110
1111                 if (status & (CTO_EN | CCRC_EN))
1112                         end_cmd = 1;
1113                 if (status & (CTO_EN | DTO_EN))
1114                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1115                 else if (status & (CCRC_EN | DCRC_EN))
1116                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1117
1118                 if (status & ACE_EN) {
1119                         u32 ac12;
1120                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1121                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1122                                 end_cmd = 1;
1123                                 if (ac12 & ACTO)
1124                                         error =  -ETIMEDOUT;
1125                                 else if (ac12 & (ACCE | ACEB | ACIE))
1126                                         error = -EILSEQ;
1127                                 host->mrq->sbc->error = error;
1128                                 hsmmc_command_incomplete(host, error, end_cmd);
1129                         }
1130                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1131                 }
1132                 if (host->data || host->response_busy) {
1133                         end_trans = !end_cmd;
1134                         host->response_busy = 0;
1135                 }
1136         }
1137
1138         OMAP_HSMMC_WRITE(host->base, STAT, status);
1139         if (end_cmd || ((status & CC_EN) && host->cmd))
1140                 omap_hsmmc_cmd_done(host, host->cmd);
1141         if ((end_trans || (status & TC_EN)) && host->mrq)
1142                 omap_hsmmc_xfer_done(host, data);
1143 }
1144
1145 /*
1146  * MMC controller IRQ handler
1147  */
1148 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1149 {
1150         struct omap_hsmmc_host *host = dev_id;
1151         int status;
1152
1153         status = OMAP_HSMMC_READ(host->base, STAT);
1154         while (status & (INT_EN_MASK | CIRQ_EN)) {
1155                 if (host->req_in_progress)
1156                         omap_hsmmc_do_irq(host, status);
1157
1158                 if (status & CIRQ_EN)
1159                         mmc_signal_sdio_irq(host->mmc);
1160
1161                 /* Flush posted write */
1162                 status = OMAP_HSMMC_READ(host->base, STAT);
1163         }
1164
1165         return IRQ_HANDLED;
1166 }
1167
1168 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1169 {
1170         struct omap_hsmmc_host *host = dev_id;
1171
1172         /* cirq is level triggered, disable to avoid infinite loop */
1173         spin_lock(&host->irq_lock);
1174         if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1175                 disable_irq_nosync(host->wake_irq);
1176                 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1177         }
1178         spin_unlock(&host->irq_lock);
1179         pm_request_resume(host->dev); /* no use counter */
1180
1181         return IRQ_HANDLED;
1182 }
1183
1184 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1185 {
1186         unsigned long i;
1187
1188         OMAP_HSMMC_WRITE(host->base, HCTL,
1189                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1190         for (i = 0; i < loops_per_jiffy; i++) {
1191                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1192                         break;
1193                 cpu_relax();
1194         }
1195 }
1196
1197 /*
1198  * Switch MMC interface voltage ... only relevant for MMC1.
1199  *
1200  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1201  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1202  * Some chips, like eMMC ones, use internal transceivers.
1203  */
1204 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1205 {
1206         u32 reg_val = 0;
1207         int ret;
1208
1209         /* Disable the clocks */
1210         pm_runtime_put_sync(host->dev);
1211         if (host->dbclk)
1212                 clk_disable_unprepare(host->dbclk);
1213
1214         /* Turn the power off */
1215         ret = mmc_pdata(host)->set_power(host->dev, host->slot_id, 0, 0);
1216
1217         /* Turn the power ON with given VDD 1.8 or 3.0v */
1218         if (!ret)
1219                 ret = mmc_pdata(host)->set_power(host->dev, host->slot_id, 1,
1220                                                  vdd);
1221         pm_runtime_get_sync(host->dev);
1222         if (host->dbclk)
1223                 clk_prepare_enable(host->dbclk);
1224
1225         if (ret != 0)
1226                 goto err;
1227
1228         OMAP_HSMMC_WRITE(host->base, HCTL,
1229                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1230         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1231
1232         /*
1233          * If a MMC dual voltage card is detected, the set_ios fn calls
1234          * this fn with VDD bit set for 1.8V. Upon card removal from the
1235          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1236          *
1237          * Cope with a bit of slop in the range ... per data sheets:
1238          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1239          *    but recommended values are 1.71V to 1.89V
1240          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1241          *    but recommended values are 2.7V to 3.3V
1242          *
1243          * Board setup code shouldn't permit anything very out-of-range.
1244          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1245          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1246          */
1247         if ((1 << vdd) <= MMC_VDD_23_24)
1248                 reg_val |= SDVS18;
1249         else
1250                 reg_val |= SDVS30;
1251
1252         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1253         set_sd_bus_power(host);
1254
1255         return 0;
1256 err:
1257         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1258         return ret;
1259 }
1260
1261 /* Protect the card while the cover is open */
1262 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1263 {
1264         if (!mmc_pdata(host)->get_cover_state)
1265                 return;
1266
1267         host->reqs_blocked = 0;
1268         if (mmc_pdata(host)->get_cover_state(host->dev, host->slot_id)) {
1269                 if (host->protect_card) {
1270                         dev_info(host->dev, "%s: cover is closed, "
1271                                          "card is now accessible\n",
1272                                          mmc_hostname(host->mmc));
1273                         host->protect_card = 0;
1274                 }
1275         } else {
1276                 if (!host->protect_card) {
1277                         dev_info(host->dev, "%s: cover is open, "
1278                                          "card is now inaccessible\n",
1279                                          mmc_hostname(host->mmc));
1280                         host->protect_card = 1;
1281                 }
1282         }
1283 }
1284
1285 /*
1286  * irq handler to notify the core about card insertion/removal
1287  */
1288 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1289 {
1290         struct omap_hsmmc_host *host = dev_id;
1291         struct omap_hsmmc_platform_data *pdata = host->pdata;
1292         int carddetect;
1293
1294         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1295
1296         if (pdata->card_detect)
1297                 carddetect = pdata->card_detect(host->dev, host->slot_id);
1298         else {
1299                 omap_hsmmc_protect_card(host);
1300                 carddetect = -ENOSYS;
1301         }
1302
1303         if (carddetect)
1304                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1305         else
1306                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1307         return IRQ_HANDLED;
1308 }
1309
1310 static void omap_hsmmc_dma_callback(void *param)
1311 {
1312         struct omap_hsmmc_host *host = param;
1313         struct dma_chan *chan;
1314         struct mmc_data *data;
1315         int req_in_progress;
1316
1317         spin_lock_irq(&host->irq_lock);
1318         if (host->dma_ch < 0) {
1319                 spin_unlock_irq(&host->irq_lock);
1320                 return;
1321         }
1322
1323         data = host->mrq->data;
1324         chan = omap_hsmmc_get_dma_chan(host, data);
1325         if (!data->host_cookie)
1326                 dma_unmap_sg(chan->device->dev,
1327                              data->sg, data->sg_len,
1328                              omap_hsmmc_get_dma_dir(host, data));
1329
1330         req_in_progress = host->req_in_progress;
1331         host->dma_ch = -1;
1332         spin_unlock_irq(&host->irq_lock);
1333
1334         /* If DMA has finished after TC, complete the request */
1335         if (!req_in_progress) {
1336                 struct mmc_request *mrq = host->mrq;
1337
1338                 host->mrq = NULL;
1339                 mmc_request_done(host->mmc, mrq);
1340         }
1341 }
1342
1343 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1344                                        struct mmc_data *data,
1345                                        struct omap_hsmmc_next *next,
1346                                        struct dma_chan *chan)
1347 {
1348         int dma_len;
1349
1350         if (!next && data->host_cookie &&
1351             data->host_cookie != host->next_data.cookie) {
1352                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1353                        " host->next_data.cookie %d\n",
1354                        __func__, data->host_cookie, host->next_data.cookie);
1355                 data->host_cookie = 0;
1356         }
1357
1358         /* Check if next job is already prepared */
1359         if (next || data->host_cookie != host->next_data.cookie) {
1360                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1361                                      omap_hsmmc_get_dma_dir(host, data));
1362
1363         } else {
1364                 dma_len = host->next_data.dma_len;
1365                 host->next_data.dma_len = 0;
1366         }
1367
1368
1369         if (dma_len == 0)
1370                 return -EINVAL;
1371
1372         if (next) {
1373                 next->dma_len = dma_len;
1374                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1375         } else
1376                 host->dma_len = dma_len;
1377
1378         return 0;
1379 }
1380
1381 /*
1382  * Routine to configure and start DMA for the MMC card
1383  */
1384 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1385                                         struct mmc_request *req)
1386 {
1387         struct dma_slave_config cfg;
1388         struct dma_async_tx_descriptor *tx;
1389         int ret = 0, i;
1390         struct mmc_data *data = req->data;
1391         struct dma_chan *chan;
1392
1393         /* Sanity check: all the SG entries must be aligned by block size. */
1394         for (i = 0; i < data->sg_len; i++) {
1395                 struct scatterlist *sgl;
1396
1397                 sgl = data->sg + i;
1398                 if (sgl->length % data->blksz)
1399                         return -EINVAL;
1400         }
1401         if ((data->blksz % 4) != 0)
1402                 /* REVISIT: The MMC buffer increments only when MSB is written.
1403                  * Return error for blksz which is non multiple of four.
1404                  */
1405                 return -EINVAL;
1406
1407         BUG_ON(host->dma_ch != -1);
1408
1409         chan = omap_hsmmc_get_dma_chan(host, data);
1410
1411         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1412         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1413         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1414         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1415         cfg.src_maxburst = data->blksz / 4;
1416         cfg.dst_maxburst = data->blksz / 4;
1417
1418         ret = dmaengine_slave_config(chan, &cfg);
1419         if (ret)
1420                 return ret;
1421
1422         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1423         if (ret)
1424                 return ret;
1425
1426         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1427                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1428                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1429         if (!tx) {
1430                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1431                 /* FIXME: cleanup */
1432                 return -1;
1433         }
1434
1435         tx->callback = omap_hsmmc_dma_callback;
1436         tx->callback_param = host;
1437
1438         /* Does not fail */
1439         dmaengine_submit(tx);
1440
1441         host->dma_ch = 1;
1442
1443         return 0;
1444 }
1445
1446 static void set_data_timeout(struct omap_hsmmc_host *host,
1447                              unsigned int timeout_ns,
1448                              unsigned int timeout_clks)
1449 {
1450         unsigned int timeout, cycle_ns;
1451         uint32_t reg, clkd, dto = 0;
1452
1453         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1454         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1455         if (clkd == 0)
1456                 clkd = 1;
1457
1458         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1459         timeout = timeout_ns / cycle_ns;
1460         timeout += timeout_clks;
1461         if (timeout) {
1462                 while ((timeout & 0x80000000) == 0) {
1463                         dto += 1;
1464                         timeout <<= 1;
1465                 }
1466                 dto = 31 - dto;
1467                 timeout <<= 1;
1468                 if (timeout && dto)
1469                         dto += 1;
1470                 if (dto >= 13)
1471                         dto -= 13;
1472                 else
1473                         dto = 0;
1474                 if (dto > 14)
1475                         dto = 14;
1476         }
1477
1478         reg &= ~DTO_MASK;
1479         reg |= dto << DTO_SHIFT;
1480         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1481 }
1482
1483 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1484 {
1485         struct mmc_request *req = host->mrq;
1486         struct dma_chan *chan;
1487
1488         if (!req->data)
1489                 return;
1490         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1491                                 | (req->data->blocks << 16));
1492         set_data_timeout(host, req->data->timeout_ns,
1493                                 req->data->timeout_clks);
1494         chan = omap_hsmmc_get_dma_chan(host, req->data);
1495         dma_async_issue_pending(chan);
1496 }
1497
1498 /*
1499  * Configure block length for MMC/SD cards and initiate the transfer.
1500  */
1501 static int
1502 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1503 {
1504         int ret;
1505         host->data = req->data;
1506
1507         if (req->data == NULL) {
1508                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1509                 /*
1510                  * Set an arbitrary 100ms data timeout for commands with
1511                  * busy signal.
1512                  */
1513                 if (req->cmd->flags & MMC_RSP_BUSY)
1514                         set_data_timeout(host, 100000000U, 0);
1515                 return 0;
1516         }
1517
1518         if (host->use_dma) {
1519                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1520                 if (ret != 0) {
1521                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1522                         return ret;
1523                 }
1524         }
1525         return 0;
1526 }
1527
1528 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1529                                 int err)
1530 {
1531         struct omap_hsmmc_host *host = mmc_priv(mmc);
1532         struct mmc_data *data = mrq->data;
1533
1534         if (host->use_dma && data->host_cookie) {
1535                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1536
1537                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1538                              omap_hsmmc_get_dma_dir(host, data));
1539                 data->host_cookie = 0;
1540         }
1541 }
1542
1543 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1544                                bool is_first_req)
1545 {
1546         struct omap_hsmmc_host *host = mmc_priv(mmc);
1547
1548         if (mrq->data->host_cookie) {
1549                 mrq->data->host_cookie = 0;
1550                 return ;
1551         }
1552
1553         if (host->use_dma) {
1554                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1555
1556                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1557                                                 &host->next_data, c))
1558                         mrq->data->host_cookie = 0;
1559         }
1560 }
1561
1562 /*
1563  * Request function. for read/write operation
1564  */
1565 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1566 {
1567         struct omap_hsmmc_host *host = mmc_priv(mmc);
1568         int err;
1569
1570         BUG_ON(host->req_in_progress);
1571         BUG_ON(host->dma_ch != -1);
1572         if (host->protect_card) {
1573                 if (host->reqs_blocked < 3) {
1574                         /*
1575                          * Ensure the controller is left in a consistent
1576                          * state by resetting the command and data state
1577                          * machines.
1578                          */
1579                         omap_hsmmc_reset_controller_fsm(host, SRD);
1580                         omap_hsmmc_reset_controller_fsm(host, SRC);
1581                         host->reqs_blocked += 1;
1582                 }
1583                 req->cmd->error = -EBADF;
1584                 if (req->data)
1585                         req->data->error = -EBADF;
1586                 req->cmd->retries = 0;
1587                 mmc_request_done(mmc, req);
1588                 return;
1589         } else if (host->reqs_blocked)
1590                 host->reqs_blocked = 0;
1591         WARN_ON(host->mrq != NULL);
1592         host->mrq = req;
1593         host->clk_rate = clk_get_rate(host->fclk);
1594         err = omap_hsmmc_prepare_data(host, req);
1595         if (err) {
1596                 req->cmd->error = err;
1597                 if (req->data)
1598                         req->data->error = err;
1599                 host->mrq = NULL;
1600                 mmc_request_done(mmc, req);
1601                 return;
1602         }
1603         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1604                 omap_hsmmc_start_command(host, req->sbc, NULL);
1605                 return;
1606         }
1607
1608         omap_hsmmc_start_dma_transfer(host);
1609         omap_hsmmc_start_command(host, req->cmd, req->data);
1610 }
1611
1612 /* Routine to configure clock values. Exposed API to core */
1613 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1614 {
1615         struct omap_hsmmc_host *host = mmc_priv(mmc);
1616         int do_send_init_stream = 0;
1617
1618         pm_runtime_get_sync(host->dev);
1619
1620         if (ios->power_mode != host->power_mode) {
1621                 switch (ios->power_mode) {
1622                 case MMC_POWER_OFF:
1623                         mmc_pdata(host)->set_power(host->dev, host->slot_id,
1624                                                    0, 0);
1625                         break;
1626                 case MMC_POWER_UP:
1627                         mmc_pdata(host)->set_power(host->dev, host->slot_id,
1628                                                    1, ios->vdd);
1629                         break;
1630                 case MMC_POWER_ON:
1631                         do_send_init_stream = 1;
1632                         break;
1633                 }
1634                 host->power_mode = ios->power_mode;
1635         }
1636
1637         /* FIXME: set registers based only on changes to ios */
1638
1639         omap_hsmmc_set_bus_width(host);
1640
1641         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1642                 /* Only MMC1 can interface at 3V without some flavor
1643                  * of external transceiver; but they all handle 1.8V.
1644                  */
1645                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1646                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1647                                 /*
1648                                  * The mmc_select_voltage fn of the core does
1649                                  * not seem to set the power_mode to
1650                                  * MMC_POWER_UP upon recalculating the voltage.
1651                                  * vdd 1.8v.
1652                                  */
1653                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1654                                 dev_dbg(mmc_dev(host->mmc),
1655                                                 "Switch operation failed\n");
1656                 }
1657         }
1658
1659         omap_hsmmc_set_clock(host);
1660
1661         if (do_send_init_stream)
1662                 send_init_stream(host);
1663
1664         omap_hsmmc_set_bus_mode(host);
1665
1666         pm_runtime_put_autosuspend(host->dev);
1667 }
1668
1669 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1670 {
1671         struct omap_hsmmc_host *host = mmc_priv(mmc);
1672
1673         if (!mmc_pdata(host)->card_detect)
1674                 return -ENOSYS;
1675         return mmc_pdata(host)->card_detect(host->dev, host->slot_id);
1676 }
1677
1678 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1679 {
1680         struct omap_hsmmc_host *host = mmc_priv(mmc);
1681
1682         if (!mmc_pdata(host)->get_ro)
1683                 return -ENOSYS;
1684         return mmc_pdata(host)->get_ro(host->dev, 0);
1685 }
1686
1687 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1688 {
1689         struct omap_hsmmc_host *host = mmc_priv(mmc);
1690
1691         if (mmc_pdata(host)->init_card)
1692                 mmc_pdata(host)->init_card(card);
1693 }
1694
1695 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1696 {
1697         struct omap_hsmmc_host *host = mmc_priv(mmc);
1698         u32 irq_mask, con;
1699         unsigned long flags;
1700
1701         spin_lock_irqsave(&host->irq_lock, flags);
1702
1703         con = OMAP_HSMMC_READ(host->base, CON);
1704         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1705         if (enable) {
1706                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1707                 irq_mask |= CIRQ_EN;
1708                 con |= CTPL | CLKEXTFREE;
1709         } else {
1710                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1711                 irq_mask &= ~CIRQ_EN;
1712                 con &= ~(CTPL | CLKEXTFREE);
1713         }
1714         OMAP_HSMMC_WRITE(host->base, CON, con);
1715         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1716
1717         /*
1718          * if enable, piggy back detection on current request
1719          * but always disable immediately
1720          */
1721         if (!host->req_in_progress || !enable)
1722                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1723
1724         /* flush posted write */
1725         OMAP_HSMMC_READ(host->base, IE);
1726
1727         spin_unlock_irqrestore(&host->irq_lock, flags);
1728 }
1729
1730 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1731 {
1732         struct mmc_host *mmc = host->mmc;
1733         int ret;
1734
1735         /*
1736          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1737          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1738          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1739          * with functional clock disabled.
1740          */
1741         if (!host->dev->of_node || !host->wake_irq)
1742                 return -ENODEV;
1743
1744         /* Prevent auto-enabling of IRQ */
1745         irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1746         ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1747                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1748                                mmc_hostname(mmc), host);
1749         if (ret) {
1750                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1751                 goto err;
1752         }
1753
1754         /*
1755          * Some omaps don't have wake-up path from deeper idle states
1756          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1757          */
1758         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1759                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1760                 if (!p) {
1761                         ret = -ENODEV;
1762                         goto err_free_irq;
1763                 }
1764                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1765                         dev_info(host->dev, "missing default pinctrl state\n");
1766                         devm_pinctrl_put(p);
1767                         ret = -EINVAL;
1768                         goto err_free_irq;
1769                 }
1770
1771                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1772                         dev_info(host->dev, "missing idle pinctrl state\n");
1773                         devm_pinctrl_put(p);
1774                         ret = -EINVAL;
1775                         goto err_free_irq;
1776                 }
1777                 devm_pinctrl_put(p);
1778         }
1779
1780         OMAP_HSMMC_WRITE(host->base, HCTL,
1781                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1782         return 0;
1783
1784 err_free_irq:
1785         devm_free_irq(host->dev, host->wake_irq, host);
1786 err:
1787         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1788         host->wake_irq = 0;
1789         return ret;
1790 }
1791
1792 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1793 {
1794         u32 hctl, capa, value;
1795
1796         /* Only MMC1 supports 3.0V */
1797         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1798                 hctl = SDVS30;
1799                 capa = VS30 | VS18;
1800         } else {
1801                 hctl = SDVS18;
1802                 capa = VS18;
1803         }
1804
1805         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1806         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1807
1808         value = OMAP_HSMMC_READ(host->base, CAPA);
1809         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1810
1811         /* Set SD bus power bit */
1812         set_sd_bus_power(host);
1813 }
1814
1815 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1816 {
1817         struct omap_hsmmc_host *host = mmc_priv(mmc);
1818
1819         pm_runtime_get_sync(host->dev);
1820
1821         return 0;
1822 }
1823
1824 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1825 {
1826         struct omap_hsmmc_host *host = mmc_priv(mmc);
1827
1828         pm_runtime_mark_last_busy(host->dev);
1829         pm_runtime_put_autosuspend(host->dev);
1830
1831         return 0;
1832 }
1833
1834 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1835                                      unsigned int direction, int blk_size)
1836 {
1837         /* This controller can't do multiblock reads due to hw bugs */
1838         if (direction == MMC_DATA_READ)
1839                 return 1;
1840
1841         return blk_size;
1842 }
1843
1844 static struct mmc_host_ops omap_hsmmc_ops = {
1845         .enable = omap_hsmmc_enable_fclk,
1846         .disable = omap_hsmmc_disable_fclk,
1847         .post_req = omap_hsmmc_post_req,
1848         .pre_req = omap_hsmmc_pre_req,
1849         .request = omap_hsmmc_request,
1850         .set_ios = omap_hsmmc_set_ios,
1851         .get_cd = omap_hsmmc_get_cd,
1852         .get_ro = omap_hsmmc_get_ro,
1853         .init_card = omap_hsmmc_init_card,
1854         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1855 };
1856
1857 #ifdef CONFIG_DEBUG_FS
1858
1859 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1860 {
1861         struct mmc_host *mmc = s->private;
1862         struct omap_hsmmc_host *host = mmc_priv(mmc);
1863
1864         seq_printf(s, "mmc%d:\n", mmc->index);
1865         seq_printf(s, "sdio irq mode\t%s\n",
1866                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1867
1868         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1869                 seq_printf(s, "sdio irq \t%s\n",
1870                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1871                            : "disabled");
1872         }
1873         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1874
1875         pm_runtime_get_sync(host->dev);
1876         seq_puts(s, "\nregs:\n");
1877         seq_printf(s, "CON:\t\t0x%08x\n",
1878                         OMAP_HSMMC_READ(host->base, CON));
1879         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1880                    OMAP_HSMMC_READ(host->base, PSTATE));
1881         seq_printf(s, "HCTL:\t\t0x%08x\n",
1882                         OMAP_HSMMC_READ(host->base, HCTL));
1883         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1884                         OMAP_HSMMC_READ(host->base, SYSCTL));
1885         seq_printf(s, "IE:\t\t0x%08x\n",
1886                         OMAP_HSMMC_READ(host->base, IE));
1887         seq_printf(s, "ISE:\t\t0x%08x\n",
1888                         OMAP_HSMMC_READ(host->base, ISE));
1889         seq_printf(s, "CAPA:\t\t0x%08x\n",
1890                         OMAP_HSMMC_READ(host->base, CAPA));
1891
1892         pm_runtime_mark_last_busy(host->dev);
1893         pm_runtime_put_autosuspend(host->dev);
1894
1895         return 0;
1896 }
1897
1898 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1899 {
1900         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1901 }
1902
1903 static const struct file_operations mmc_regs_fops = {
1904         .open           = omap_hsmmc_regs_open,
1905         .read           = seq_read,
1906         .llseek         = seq_lseek,
1907         .release        = single_release,
1908 };
1909
1910 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1911 {
1912         if (mmc->debugfs_root)
1913                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1914                         mmc, &mmc_regs_fops);
1915 }
1916
1917 #else
1918
1919 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1920 {
1921 }
1922
1923 #endif
1924
1925 #ifdef CONFIG_OF
1926 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1927         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1928         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1929 };
1930
1931 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1932         .reg_offset = 0x100,
1933 };
1934 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1935         .reg_offset = 0x100,
1936         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1937 };
1938
1939 static const struct of_device_id omap_mmc_of_match[] = {
1940         {
1941                 .compatible = "ti,omap2-hsmmc",
1942         },
1943         {
1944                 .compatible = "ti,omap3-pre-es3-hsmmc",
1945                 .data = &omap3_pre_es3_mmc_of_data,
1946         },
1947         {
1948                 .compatible = "ti,omap3-hsmmc",
1949         },
1950         {
1951                 .compatible = "ti,omap4-hsmmc",
1952                 .data = &omap4_mmc_of_data,
1953         },
1954         {
1955                 .compatible = "ti,am33xx-hsmmc",
1956                 .data = &am33xx_mmc_of_data,
1957         },
1958         {},
1959 };
1960 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1961
1962 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1963 {
1964         struct omap_hsmmc_platform_data *pdata;
1965         struct device_node *np = dev->of_node;
1966         u32 bus_width, max_freq;
1967         int cd_gpio, wp_gpio;
1968
1969         cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1970         wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1971         if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1972                 return ERR_PTR(-EPROBE_DEFER);
1973
1974         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1975         if (!pdata)
1976                 return ERR_PTR(-ENOMEM); /* out of memory */
1977
1978         if (of_find_property(np, "ti,dual-volt", NULL))
1979                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1980
1981         /* This driver only supports 1 slot */
1982         pdata->nr_slots = 1;
1983         pdata->switch_pin = cd_gpio;
1984         pdata->gpio_wp = wp_gpio;
1985
1986         if (of_find_property(np, "ti,non-removable", NULL)) {
1987                 pdata->nonremovable = true;
1988                 pdata->no_regulator_off_init = true;
1989         }
1990         of_property_read_u32(np, "bus-width", &bus_width);
1991         if (bus_width == 4)
1992                 pdata->caps |= MMC_CAP_4_BIT_DATA;
1993         else if (bus_width == 8)
1994                 pdata->caps |= MMC_CAP_8_BIT_DATA;
1995
1996         if (of_find_property(np, "ti,needs-special-reset", NULL))
1997                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1998
1999         if (!of_property_read_u32(np, "max-frequency", &max_freq))
2000                 pdata->max_freq = max_freq;
2001
2002         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
2003                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
2004
2005         if (of_find_property(np, "keep-power-in-suspend", NULL))
2006                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2007
2008         if (of_find_property(np, "enable-sdio-wakeup", NULL))
2009                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2010
2011         return pdata;
2012 }
2013 #else
2014 static inline struct omap_hsmmc_platform_data
2015                         *of_get_hsmmc_pdata(struct device *dev)
2016 {
2017         return ERR_PTR(-EINVAL);
2018 }
2019 #endif
2020
2021 static int omap_hsmmc_probe(struct platform_device *pdev)
2022 {
2023         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
2024         struct mmc_host *mmc;
2025         struct omap_hsmmc_host *host = NULL;
2026         struct resource *res;
2027         int ret, irq;
2028         const struct of_device_id *match;
2029         dma_cap_mask_t mask;
2030         unsigned tx_req, rx_req;
2031         const struct omap_mmc_of_data *data;
2032         void __iomem *base;
2033
2034         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2035         if (match) {
2036                 pdata = of_get_hsmmc_pdata(&pdev->dev);
2037
2038                 if (IS_ERR(pdata))
2039                         return PTR_ERR(pdata);
2040
2041                 if (match->data) {
2042                         data = match->data;
2043                         pdata->reg_offset = data->reg_offset;
2044                         pdata->controller_flags |= data->controller_flags;
2045                 }
2046         }
2047
2048         if (pdata == NULL) {
2049                 dev_err(&pdev->dev, "Platform Data is missing\n");
2050                 return -ENXIO;
2051         }
2052
2053         if (pdata->nr_slots == 0) {
2054                 dev_err(&pdev->dev, "No Slots\n");
2055                 return -ENXIO;
2056         }
2057
2058         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2059         irq = platform_get_irq(pdev, 0);
2060         if (res == NULL || irq < 0)
2061                 return -ENXIO;
2062
2063         base = devm_ioremap_resource(&pdev->dev, res);
2064         if (IS_ERR(base))
2065                 return PTR_ERR(base);
2066
2067         ret = omap_hsmmc_gpio_init(pdata);
2068         if (ret)
2069                 goto err;
2070
2071         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2072         if (!mmc) {
2073                 ret = -ENOMEM;
2074                 goto err_alloc;
2075         }
2076
2077         host            = mmc_priv(mmc);
2078         host->mmc       = mmc;
2079         host->pdata     = pdata;
2080         host->dev       = &pdev->dev;
2081         host->use_dma   = 1;
2082         host->dma_ch    = -1;
2083         host->irq       = irq;
2084         host->slot_id   = 0;
2085         host->mapbase   = res->start + pdata->reg_offset;
2086         host->base      = base + pdata->reg_offset;
2087         host->power_mode = MMC_POWER_OFF;
2088         host->next_data.cookie = 1;
2089         host->pbias_enabled = 0;
2090
2091         platform_set_drvdata(pdev, host);
2092
2093         if (pdev->dev.of_node)
2094                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2095
2096         mmc->ops        = &omap_hsmmc_ops;
2097
2098         mmc->f_min = OMAP_MMC_MIN_CLOCK;
2099
2100         if (pdata->max_freq > 0)
2101                 mmc->f_max = pdata->max_freq;
2102         else
2103                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2104
2105         spin_lock_init(&host->irq_lock);
2106
2107         host->fclk = devm_clk_get(&pdev->dev, "fck");
2108         if (IS_ERR(host->fclk)) {
2109                 ret = PTR_ERR(host->fclk);
2110                 host->fclk = NULL;
2111                 goto err1;
2112         }
2113
2114         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2115                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2116                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2117         }
2118
2119         pm_runtime_enable(host->dev);
2120         pm_runtime_get_sync(host->dev);
2121         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2122         pm_runtime_use_autosuspend(host->dev);
2123
2124         omap_hsmmc_context_save(host);
2125
2126         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2127         /*
2128          * MMC can still work without debounce clock.
2129          */
2130         if (IS_ERR(host->dbclk)) {
2131                 host->dbclk = NULL;
2132         } else if (clk_prepare_enable(host->dbclk) != 0) {
2133                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2134                 host->dbclk = NULL;
2135         }
2136
2137         /* Since we do only SG emulation, we can have as many segs
2138          * as we want. */
2139         mmc->max_segs = 1024;
2140
2141         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2142         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2143         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2144         mmc->max_seg_size = mmc->max_req_size;
2145
2146         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2147                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2148
2149         mmc->caps |= mmc_pdata(host)->caps;
2150         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2151                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2152
2153         if (mmc_pdata(host)->nonremovable)
2154                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2155
2156         mmc->pm_caps = mmc_pdata(host)->pm_caps;
2157
2158         omap_hsmmc_conf_bus_power(host);
2159
2160         if (!pdev->dev.of_node) {
2161                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2162                 if (!res) {
2163                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2164                         ret = -ENXIO;
2165                         goto err_irq;
2166                 }
2167                 tx_req = res->start;
2168
2169                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2170                 if (!res) {
2171                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2172                         ret = -ENXIO;
2173                         goto err_irq;
2174                 }
2175                 rx_req = res->start;
2176         }
2177
2178         dma_cap_zero(mask);
2179         dma_cap_set(DMA_SLAVE, mask);
2180
2181         host->rx_chan =
2182                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2183                                                  &rx_req, &pdev->dev, "rx");
2184
2185         if (!host->rx_chan) {
2186                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2187                 ret = -ENXIO;
2188                 goto err_irq;
2189         }
2190
2191         host->tx_chan =
2192                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2193                                                  &tx_req, &pdev->dev, "tx");
2194
2195         if (!host->tx_chan) {
2196                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2197                 ret = -ENXIO;
2198                 goto err_irq;
2199         }
2200
2201         /* Request IRQ for MMC operations */
2202         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2203                         mmc_hostname(mmc), host);
2204         if (ret) {
2205                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2206                 goto err_irq;
2207         }
2208
2209         if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2210                 ret = omap_hsmmc_reg_get(host);
2211                 if (ret)
2212                         goto err_irq;
2213                 host->use_reg = 1;
2214         }
2215
2216         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2217
2218         /* Request IRQ for card detect */
2219         if ((mmc_pdata(host)->card_detect_irq)) {
2220                 ret = devm_request_threaded_irq(&pdev->dev,
2221                                                 mmc_pdata(host)->card_detect_irq,
2222                                                 NULL, omap_hsmmc_detect,
2223                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2224                                            mmc_hostname(mmc), host);
2225                 if (ret) {
2226                         dev_err(mmc_dev(host->mmc),
2227                                 "Unable to grab MMC CD IRQ\n");
2228                         goto err_irq_cd;
2229                 }
2230                 pdata->suspend = omap_hsmmc_suspend_cdirq;
2231                 pdata->resume = omap_hsmmc_resume_cdirq;
2232         }
2233
2234         omap_hsmmc_disable_irq(host);
2235
2236         /*
2237          * For now, only support SDIO interrupt if we have a separate
2238          * wake-up interrupt configured from device tree. This is because
2239          * the wake-up interrupt is needed for idle state and some
2240          * platforms need special quirks. And we don't want to add new
2241          * legacy mux platform init code callbacks any longer as we
2242          * are moving to DT based booting anyways.
2243          */
2244         ret = omap_hsmmc_configure_wake_irq(host);
2245         if (!ret)
2246                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2247
2248         omap_hsmmc_protect_card(host);
2249
2250         mmc_add_host(mmc);
2251
2252         if (mmc_pdata(host)->name != NULL) {
2253                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2254                 if (ret < 0)
2255                         goto err_slot_name;
2256         }
2257         if (mmc_pdata(host)->card_detect_irq &&
2258             mmc_pdata(host)->get_cover_state) {
2259                 ret = device_create_file(&mmc->class_dev,
2260                                         &dev_attr_cover_switch);
2261                 if (ret < 0)
2262                         goto err_slot_name;
2263         }
2264
2265         omap_hsmmc_debugfs(mmc);
2266         pm_runtime_mark_last_busy(host->dev);
2267         pm_runtime_put_autosuspend(host->dev);
2268
2269         return 0;
2270
2271 err_slot_name:
2272         mmc_remove_host(mmc);
2273 err_irq_cd:
2274         if (host->use_reg)
2275                 omap_hsmmc_reg_put(host);
2276 err_irq:
2277         if (host->tx_chan)
2278                 dma_release_channel(host->tx_chan);
2279         if (host->rx_chan)
2280                 dma_release_channel(host->rx_chan);
2281         pm_runtime_put_sync(host->dev);
2282         pm_runtime_disable(host->dev);
2283         if (host->dbclk)
2284                 clk_disable_unprepare(host->dbclk);
2285 err1:
2286         mmc_free_host(mmc);
2287 err_alloc:
2288         omap_hsmmc_gpio_free(pdata);
2289 err:
2290         return ret;
2291 }
2292
2293 static int omap_hsmmc_remove(struct platform_device *pdev)
2294 {
2295         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2296
2297         pm_runtime_get_sync(host->dev);
2298         mmc_remove_host(host->mmc);
2299         if (host->use_reg)
2300                 omap_hsmmc_reg_put(host);
2301
2302         if (host->tx_chan)
2303                 dma_release_channel(host->tx_chan);
2304         if (host->rx_chan)
2305                 dma_release_channel(host->rx_chan);
2306
2307         pm_runtime_put_sync(host->dev);
2308         pm_runtime_disable(host->dev);
2309         if (host->dbclk)
2310                 clk_disable_unprepare(host->dbclk);
2311
2312         omap_hsmmc_gpio_free(host->pdata);
2313         mmc_free_host(host->mmc);
2314
2315         return 0;
2316 }
2317
2318 #ifdef CONFIG_PM
2319 static int omap_hsmmc_prepare(struct device *dev)
2320 {
2321         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2322
2323         if (host->pdata->suspend)
2324                 return host->pdata->suspend(dev, host->slot_id);
2325
2326         return 0;
2327 }
2328
2329 static void omap_hsmmc_complete(struct device *dev)
2330 {
2331         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2332
2333         if (host->pdata->resume)
2334                 host->pdata->resume(dev, host->slot_id);
2335
2336 }
2337
2338 static int omap_hsmmc_suspend(struct device *dev)
2339 {
2340         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2341
2342         if (!host)
2343                 return 0;
2344
2345         pm_runtime_get_sync(host->dev);
2346
2347         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2348                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2349                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2350                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2351                 OMAP_HSMMC_WRITE(host->base, HCTL,
2352                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2353         }
2354
2355         /* do not wake up due to sdio irq */
2356         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2357             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2358                 disable_irq(host->wake_irq);
2359
2360         if (host->dbclk)
2361                 clk_disable_unprepare(host->dbclk);
2362
2363         pm_runtime_put_sync(host->dev);
2364         return 0;
2365 }
2366
2367 /* Routine to resume the MMC device */
2368 static int omap_hsmmc_resume(struct device *dev)
2369 {
2370         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2371
2372         if (!host)
2373                 return 0;
2374
2375         pm_runtime_get_sync(host->dev);
2376
2377         if (host->dbclk)
2378                 clk_prepare_enable(host->dbclk);
2379
2380         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2381                 omap_hsmmc_conf_bus_power(host);
2382
2383         omap_hsmmc_protect_card(host);
2384
2385         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2386             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2387                 enable_irq(host->wake_irq);
2388
2389         pm_runtime_mark_last_busy(host->dev);
2390         pm_runtime_put_autosuspend(host->dev);
2391         return 0;
2392 }
2393
2394 #else
2395 #define omap_hsmmc_prepare      NULL
2396 #define omap_hsmmc_complete     NULL
2397 #define omap_hsmmc_suspend      NULL
2398 #define omap_hsmmc_resume       NULL
2399 #endif
2400
2401 static int omap_hsmmc_runtime_suspend(struct device *dev)
2402 {
2403         struct omap_hsmmc_host *host;
2404         unsigned long flags;
2405         int ret = 0;
2406
2407         host = platform_get_drvdata(to_platform_device(dev));
2408         omap_hsmmc_context_save(host);
2409         dev_dbg(dev, "disabled\n");
2410
2411         spin_lock_irqsave(&host->irq_lock, flags);
2412         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2413             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2414                 /* disable sdio irq handling to prevent race */
2415                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2416                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2417
2418                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2419                         /*
2420                          * dat1 line low, pending sdio irq
2421                          * race condition: possible irq handler running on
2422                          * multi-core, abort
2423                          */
2424                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2425                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2426                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2427                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2428                         pm_runtime_mark_last_busy(dev);
2429                         ret = -EBUSY;
2430                         goto abort;
2431                 }
2432
2433                 pinctrl_pm_select_idle_state(dev);
2434
2435                 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2436                 enable_irq(host->wake_irq);
2437                 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2438         } else {
2439                 pinctrl_pm_select_idle_state(dev);
2440         }
2441
2442 abort:
2443         spin_unlock_irqrestore(&host->irq_lock, flags);
2444         return ret;
2445 }
2446
2447 static int omap_hsmmc_runtime_resume(struct device *dev)
2448 {
2449         struct omap_hsmmc_host *host;
2450         unsigned long flags;
2451
2452         host = platform_get_drvdata(to_platform_device(dev));
2453         omap_hsmmc_context_restore(host);
2454         dev_dbg(dev, "enabled\n");
2455
2456         spin_lock_irqsave(&host->irq_lock, flags);
2457         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2458             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2459                 /* sdio irq flag can't change while in runtime suspend */
2460                 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2461                         disable_irq_nosync(host->wake_irq);
2462                         host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2463                 }
2464
2465                 pinctrl_pm_select_default_state(host->dev);
2466
2467                 /* irq lost, if pinmux incorrect */
2468                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2469                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2470                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2471         } else {
2472                 pinctrl_pm_select_default_state(host->dev);
2473         }
2474         spin_unlock_irqrestore(&host->irq_lock, flags);
2475         return 0;
2476 }
2477
2478 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2479         .suspend        = omap_hsmmc_suspend,
2480         .resume         = omap_hsmmc_resume,
2481         .prepare        = omap_hsmmc_prepare,
2482         .complete       = omap_hsmmc_complete,
2483         .runtime_suspend = omap_hsmmc_runtime_suspend,
2484         .runtime_resume = omap_hsmmc_runtime_resume,
2485 };
2486
2487 static struct platform_driver omap_hsmmc_driver = {
2488         .probe          = omap_hsmmc_probe,
2489         .remove         = omap_hsmmc_remove,
2490         .driver         = {
2491                 .name = DRIVER_NAME,
2492                 .pm = &omap_hsmmc_dev_pm_ops,
2493                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2494         },
2495 };
2496
2497 module_platform_driver(omap_hsmmc_driver);
2498 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2499 MODULE_LICENSE("GPL");
2500 MODULE_ALIAS("platform:" DRIVER_NAME);
2501 MODULE_AUTHOR("Texas Instruments Inc");