2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/omap-dmaengine.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/core.h>
38 #include <linux/mmc/mmc.h>
39 #include <linux/mmc/slot-gpio.h>
41 #include <linux/irq.h>
42 #include <linux/gpio.h>
43 #include <linux/regulator/consumer.h>
44 #include <linux/pinctrl/consumer.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/pm_wakeirq.h>
47 #include <linux/platform_data/hsmmc-omap.h>
49 /* OMAP HSMMC Host Controller Registers */
50 #define OMAP_HSMMC_SYSSTATUS 0x0014
51 #define OMAP_HSMMC_CON 0x002C
52 #define OMAP_HSMMC_SDMASA 0x0100
53 #define OMAP_HSMMC_BLK 0x0104
54 #define OMAP_HSMMC_ARG 0x0108
55 #define OMAP_HSMMC_CMD 0x010C
56 #define OMAP_HSMMC_RSP10 0x0110
57 #define OMAP_HSMMC_RSP32 0x0114
58 #define OMAP_HSMMC_RSP54 0x0118
59 #define OMAP_HSMMC_RSP76 0x011C
60 #define OMAP_HSMMC_DATA 0x0120
61 #define OMAP_HSMMC_PSTATE 0x0124
62 #define OMAP_HSMMC_HCTL 0x0128
63 #define OMAP_HSMMC_SYSCTL 0x012C
64 #define OMAP_HSMMC_STAT 0x0130
65 #define OMAP_HSMMC_IE 0x0134
66 #define OMAP_HSMMC_ISE 0x0138
67 #define OMAP_HSMMC_AC12 0x013C
68 #define OMAP_HSMMC_CAPA 0x0140
70 #define VS18 (1 << 26)
71 #define VS30 (1 << 25)
73 #define SDVS18 (0x5 << 9)
74 #define SDVS30 (0x6 << 9)
75 #define SDVS33 (0x7 << 9)
76 #define SDVS_MASK 0x00000E00
77 #define SDVSCLR 0xFFFFF1FF
78 #define SDVSDET 0x00000400
85 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
86 #define CLKD_MASK 0x0000FFC0
88 #define DTO_MASK 0x000F0000
90 #define INIT_STREAM (1 << 1)
91 #define ACEN_ACMD23 (2 << 2)
92 #define DP_SELECT (1 << 21)
97 #define FOUR_BIT (1 << 1)
100 #define DDR (1 << 19)
101 #define CLKEXTFREE (1 << 16)
102 #define CTPL (1 << 11)
105 #define STAT_CLEAR 0xFFFFFFFF
106 #define INIT_STREAM_CMD 0x00000000
107 #define DUAL_VOLT_OCR_BIT 7
108 #define SRC (1 << 25)
109 #define SRD (1 << 26)
110 #define SOFTRESET (1 << 1)
113 #define DLEV_DAT(x) (1 << (20 + (x)))
115 /* Interrupt masks for IE and ISE register */
116 #define CC_EN (1 << 0)
117 #define TC_EN (1 << 1)
118 #define BWR_EN (1 << 4)
119 #define BRR_EN (1 << 5)
120 #define CIRQ_EN (1 << 8)
121 #define ERR_EN (1 << 15)
122 #define CTO_EN (1 << 16)
123 #define CCRC_EN (1 << 17)
124 #define CEB_EN (1 << 18)
125 #define CIE_EN (1 << 19)
126 #define DTO_EN (1 << 20)
127 #define DCRC_EN (1 << 21)
128 #define DEB_EN (1 << 22)
129 #define ACE_EN (1 << 24)
130 #define CERR_EN (1 << 28)
131 #define BADA_EN (1 << 29)
133 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
134 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
135 BRR_EN | BWR_EN | TC_EN | CC_EN)
138 #define ACIE (1 << 4)
139 #define ACEB (1 << 3)
140 #define ACCE (1 << 2)
141 #define ACTO (1 << 1)
142 #define ACNE (1 << 0)
144 #define MMC_AUTOSUSPEND_DELAY 100
145 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
146 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
147 #define OMAP_MMC_MIN_CLOCK 400000
148 #define OMAP_MMC_MAX_CLOCK 52000000
149 #define DRIVER_NAME "omap_hsmmc"
151 #define VDD_1V8 1800000 /* 180000 uV */
152 #define VDD_3V0 3000000 /* 300000 uV */
153 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
156 * One controller can have multiple slots, like on some omap boards using
157 * omap.c controller driver. Luckily this is not currently done on any known
158 * omap_hsmmc.c device.
160 #define mmc_pdata(host) host->pdata
163 * MMC Host controller read/write API's
165 #define OMAP_HSMMC_READ(base, reg) \
166 __raw_readl((base) + OMAP_HSMMC_##reg)
168 #define OMAP_HSMMC_WRITE(base, reg, val) \
169 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
171 struct omap_hsmmc_next {
172 unsigned int dma_len;
176 struct omap_hsmmc_host {
178 struct mmc_host *mmc;
179 struct mmc_request *mrq;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
184 struct regulator *pbias;
187 resource_size_t mapbase;
188 spinlock_t irq_lock; /* Prevent races with irq handler */
189 unsigned int dma_len;
190 unsigned int dma_sg_idx;
191 unsigned char bus_mode;
192 unsigned char power_mode;
201 struct dma_chan *tx_chan;
202 struct dma_chan *rx_chan;
208 unsigned long clk_rate;
210 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
211 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
212 struct omap_hsmmc_next next_data;
213 struct omap_hsmmc_platform_data *pdata;
215 /* return MMC cover switch state, can be NULL if not supported.
217 * possible return values:
221 int (*get_cover_state)(struct device *dev);
223 int (*card_detect)(struct device *dev);
226 struct omap_mmc_of_data {
231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
233 static int omap_hsmmc_card_detect(struct device *dev)
235 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
237 return mmc_gpio_get_cd(host->mmc);
240 static int omap_hsmmc_get_cover_state(struct device *dev)
242 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
244 return mmc_gpio_get_cd(host->mmc);
247 #ifdef CONFIG_REGULATOR
249 static int omap_hsmmc_enable_supply(struct mmc_host *mmc, int vdd)
253 if (mmc->supply.vmmc) {
254 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
259 /* Enable interface voltage rail, if needed */
260 if (mmc->supply.vqmmc) {
261 ret = regulator_enable(mmc->supply.vqmmc);
263 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
271 if (mmc->supply.vmmc)
272 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
277 static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
282 if (mmc->supply.vqmmc) {
283 ret = regulator_disable(mmc->supply.vqmmc);
285 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
290 if (mmc->supply.vmmc) {
291 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
299 if (mmc->supply.vqmmc) {
300 status = regulator_enable(mmc->supply.vqmmc);
302 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
308 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
317 if (vdd <= VDD_165_195)
318 ret = regulator_set_voltage(host->pbias, VDD_1V8,
321 ret = regulator_set_voltage(host->pbias, VDD_3V0,
324 dev_err(host->dev, "pbias set voltage fail\n");
328 if (host->pbias_enabled == 0) {
329 ret = regulator_enable(host->pbias);
331 dev_err(host->dev, "pbias reg enable fail\n");
334 host->pbias_enabled = 1;
337 if (host->pbias_enabled == 1) {
338 ret = regulator_disable(host->pbias);
340 dev_err(host->dev, "pbias reg disable fail\n");
343 host->pbias_enabled = 0;
350 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
352 struct omap_hsmmc_host *host =
353 platform_get_drvdata(to_platform_device(dev));
354 struct mmc_host *mmc = host->mmc;
357 if (mmc_pdata(host)->set_power)
358 return mmc_pdata(host)->set_power(dev, power_on, vdd);
361 * If we don't see a Vcc regulator, assume it's a fixed
362 * voltage always-on regulator.
364 if (!mmc->supply.vmmc)
367 if (mmc_pdata(host)->before_set_reg)
368 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
370 ret = omap_hsmmc_set_pbias(host, false, 0);
375 * Assume Vcc regulator is used only to power the card ... OMAP
376 * VDDS is used to power the pins, optionally with a transceiver to
377 * support cards using voltages other than VDDS (1.8V nominal). When a
378 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
380 * In some cases this regulator won't support enable/disable;
381 * e.g. it's a fixed rail for a WLAN chip.
383 * In other cases vcc_aux switches interface power. Example, for
384 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
385 * chips/cards need an interface voltage rail too.
388 ret = omap_hsmmc_enable_supply(mmc, vdd);
392 ret = omap_hsmmc_disable_supply(mmc);
397 ret = omap_hsmmc_set_pbias(host, true, vdd);
399 goto err_set_voltage;
401 if (mmc_pdata(host)->after_set_reg)
402 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
407 omap_hsmmc_disable_supply(mmc);
412 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
416 struct mmc_host *mmc = host->mmc;
418 if (mmc_pdata(host)->set_power)
421 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
422 if (IS_ERR(mmc->supply.vmmc)) {
423 ret = PTR_ERR(mmc->supply.vmmc);
426 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
427 PTR_ERR(mmc->supply.vmmc));
428 mmc->supply.vmmc = NULL;
430 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
432 mmc_pdata(host)->ocr_mask = ocr_value;
435 /* Allow an aux regulator */
436 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
437 if (IS_ERR(mmc->supply.vqmmc)) {
438 ret = PTR_ERR(mmc->supply.vqmmc);
441 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
442 PTR_ERR(mmc->supply.vqmmc));
443 mmc->supply.vqmmc = NULL;
446 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
447 if (IS_ERR(host->pbias)) {
448 ret = PTR_ERR(host->pbias);
451 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
452 PTR_ERR(host->pbias));
456 /* For eMMC do not power off when not in sleep state */
457 if (mmc_pdata(host)->no_regulator_off_init)
460 * To disable boot_on regulator, enable regulator
461 * to increase usecount and then disable it.
463 if ((mmc->supply.vmmc && regulator_is_enabled(mmc->supply.vmmc) > 0) ||
464 (mmc->supply.vqmmc && regulator_is_enabled(mmc->supply.vqmmc))) {
465 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
467 omap_hsmmc_set_power(host->dev, 1, vdd);
468 omap_hsmmc_set_power(host->dev, 0, 0);
474 static inline int omap_hsmmc_have_reg(void)
481 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
486 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
491 static inline int omap_hsmmc_have_reg(void)
498 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
500 static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
501 struct omap_hsmmc_host *host,
502 struct omap_hsmmc_platform_data *pdata)
506 if (gpio_is_valid(pdata->gpio_cod)) {
507 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
511 host->get_cover_state = omap_hsmmc_get_cover_state;
512 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
513 } else if (gpio_is_valid(pdata->gpio_cd)) {
514 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
518 host->card_detect = omap_hsmmc_card_detect;
521 if (gpio_is_valid(pdata->gpio_wp)) {
522 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
531 * Start clock to the card
533 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
535 OMAP_HSMMC_WRITE(host->base, SYSCTL,
536 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
540 * Stop clock to the card
542 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
544 OMAP_HSMMC_WRITE(host->base, SYSCTL,
545 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
546 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
547 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
550 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
551 struct mmc_command *cmd)
553 u32 irq_mask = INT_EN_MASK;
557 irq_mask &= ~(BRR_EN | BWR_EN);
559 /* Disable timeout for erases */
560 if (cmd->opcode == MMC_ERASE)
563 spin_lock_irqsave(&host->irq_lock, flags);
564 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
565 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
567 /* latch pending CIRQ, but don't signal MMC core */
568 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
570 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
571 spin_unlock_irqrestore(&host->irq_lock, flags);
574 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
579 spin_lock_irqsave(&host->irq_lock, flags);
580 /* no transfer running but need to keep cirq if enabled */
581 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
583 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
584 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
585 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
586 spin_unlock_irqrestore(&host->irq_lock, flags);
589 /* Calculate divisor for the given clock frequency */
590 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
595 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
603 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
605 struct mmc_ios *ios = &host->mmc->ios;
606 unsigned long regval;
607 unsigned long timeout;
608 unsigned long clkdiv;
610 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
612 omap_hsmmc_stop_clock(host);
614 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
615 regval = regval & ~(CLKD_MASK | DTO_MASK);
616 clkdiv = calc_divisor(host, ios);
617 regval = regval | (clkdiv << 6) | (DTO << 16);
618 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
619 OMAP_HSMMC_WRITE(host->base, SYSCTL,
620 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
622 /* Wait till the ICS bit is set */
623 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
624 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
625 && time_before(jiffies, timeout))
629 * Enable High-Speed Support
631 * - Controller should support High-Speed-Enable Bit
632 * - Controller should not be using DDR Mode
633 * - Controller should advertise that it supports High Speed
634 * in capabilities register
635 * - MMC/SD clock coming out of controller > 25MHz
637 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
638 (ios->timing != MMC_TIMING_MMC_DDR52) &&
639 (ios->timing != MMC_TIMING_UHS_DDR50) &&
640 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
641 regval = OMAP_HSMMC_READ(host->base, HCTL);
642 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
647 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
650 omap_hsmmc_start_clock(host);
653 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
655 struct mmc_ios *ios = &host->mmc->ios;
658 con = OMAP_HSMMC_READ(host->base, CON);
659 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
660 ios->timing == MMC_TIMING_UHS_DDR50)
661 con |= DDR; /* configure in DDR mode */
664 switch (ios->bus_width) {
665 case MMC_BUS_WIDTH_8:
666 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
668 case MMC_BUS_WIDTH_4:
669 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
670 OMAP_HSMMC_WRITE(host->base, HCTL,
671 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
673 case MMC_BUS_WIDTH_1:
674 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
675 OMAP_HSMMC_WRITE(host->base, HCTL,
676 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
681 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
683 struct mmc_ios *ios = &host->mmc->ios;
686 con = OMAP_HSMMC_READ(host->base, CON);
687 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
688 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
690 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
696 * Restore the MMC host context, if it was lost as result of a
697 * power state change.
699 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
701 struct mmc_ios *ios = &host->mmc->ios;
703 unsigned long timeout;
705 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
706 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
707 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
708 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
711 host->context_loss++;
713 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
714 if (host->power_mode != MMC_POWER_OFF &&
715 (1 << ios->vdd) <= MMC_VDD_23_24)
725 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
728 OMAP_HSMMC_WRITE(host->base, HCTL,
729 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
731 OMAP_HSMMC_WRITE(host->base, CAPA,
732 OMAP_HSMMC_READ(host->base, CAPA) | capa);
734 OMAP_HSMMC_WRITE(host->base, HCTL,
735 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
737 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
738 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
739 && time_before(jiffies, timeout))
742 OMAP_HSMMC_WRITE(host->base, ISE, 0);
743 OMAP_HSMMC_WRITE(host->base, IE, 0);
744 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
746 /* Do not initialize card-specific things if the power is off */
747 if (host->power_mode == MMC_POWER_OFF)
750 omap_hsmmc_set_bus_width(host);
752 omap_hsmmc_set_clock(host);
754 omap_hsmmc_set_bus_mode(host);
757 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
763 * Save the MMC host context (store the number of power state changes so far).
765 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
767 host->con = OMAP_HSMMC_READ(host->base, CON);
768 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
769 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
770 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
775 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
780 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
787 * Send init stream sequence to card
788 * before sending IDLE command
790 static void send_init_stream(struct omap_hsmmc_host *host)
793 unsigned long timeout;
795 if (host->protect_card)
798 disable_irq(host->irq);
800 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
801 OMAP_HSMMC_WRITE(host->base, CON,
802 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
803 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
805 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
806 while ((reg != CC_EN) && time_before(jiffies, timeout))
807 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
809 OMAP_HSMMC_WRITE(host->base, CON,
810 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
812 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
813 OMAP_HSMMC_READ(host->base, STAT);
815 enable_irq(host->irq);
819 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
823 if (host->get_cover_state)
824 r = host->get_cover_state(host->dev);
829 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
832 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
833 struct omap_hsmmc_host *host = mmc_priv(mmc);
835 return sprintf(buf, "%s\n",
836 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
839 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
842 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
845 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
846 struct omap_hsmmc_host *host = mmc_priv(mmc);
848 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
851 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
854 * Configure the response type and send the cmd.
857 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
858 struct mmc_data *data)
860 int cmdreg = 0, resptype = 0, cmdtype = 0;
862 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
863 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
866 omap_hsmmc_enable_irq(host, cmd);
868 host->response_busy = 0;
869 if (cmd->flags & MMC_RSP_PRESENT) {
870 if (cmd->flags & MMC_RSP_136)
872 else if (cmd->flags & MMC_RSP_BUSY) {
874 host->response_busy = 1;
880 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
881 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
882 * a val of 0x3, rest 0x0.
884 if (cmd == host->mrq->stop)
887 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
889 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
891 cmdreg |= ACEN_ACMD23;
892 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
895 cmdreg |= DP_SELECT | MSBS | BCE;
896 if (data->flags & MMC_DATA_READ)
905 host->req_in_progress = 1;
907 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
908 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
912 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
914 if (data->flags & MMC_DATA_WRITE)
915 return DMA_TO_DEVICE;
917 return DMA_FROM_DEVICE;
920 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
921 struct mmc_data *data)
923 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
926 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
931 spin_lock_irqsave(&host->irq_lock, flags);
932 host->req_in_progress = 0;
933 dma_ch = host->dma_ch;
934 spin_unlock_irqrestore(&host->irq_lock, flags);
936 omap_hsmmc_disable_irq(host);
937 /* Do not complete the request if DMA is still in progress */
938 if (mrq->data && host->use_dma && dma_ch != -1)
941 mmc_request_done(host->mmc, mrq);
942 pm_runtime_mark_last_busy(host->dev);
943 pm_runtime_put_autosuspend(host->dev);
947 * Notify the transfer complete to MMC core
950 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
953 struct mmc_request *mrq = host->mrq;
955 /* TC before CC from CMD6 - don't know why, but it happens */
956 if (host->cmd && host->cmd->opcode == 6 &&
957 host->response_busy) {
958 host->response_busy = 0;
962 omap_hsmmc_request_done(host, mrq);
969 data->bytes_xfered += data->blocks * (data->blksz);
971 data->bytes_xfered = 0;
973 if (data->stop && (data->error || !host->mrq->sbc))
974 omap_hsmmc_start_command(host, data->stop, NULL);
976 omap_hsmmc_request_done(host, data->mrq);
980 * Notify the core about command completion
983 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
985 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
986 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
988 omap_hsmmc_start_dma_transfer(host);
989 omap_hsmmc_start_command(host, host->mrq->cmd,
996 if (cmd->flags & MMC_RSP_PRESENT) {
997 if (cmd->flags & MMC_RSP_136) {
998 /* response type 2 */
999 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1000 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1001 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1002 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1004 /* response types 1, 1b, 3, 4, 5, 6 */
1005 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1008 if ((host->data == NULL && !host->response_busy) || cmd->error)
1009 omap_hsmmc_request_done(host, host->mrq);
1013 * DMA clean up for command errors
1015 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1018 unsigned long flags;
1020 host->data->error = errno;
1022 spin_lock_irqsave(&host->irq_lock, flags);
1023 dma_ch = host->dma_ch;
1025 spin_unlock_irqrestore(&host->irq_lock, flags);
1027 if (host->use_dma && dma_ch != -1) {
1028 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1030 dmaengine_terminate_all(chan);
1031 dma_unmap_sg(chan->device->dev,
1032 host->data->sg, host->data->sg_len,
1033 omap_hsmmc_get_dma_dir(host, host->data));
1035 host->data->host_cookie = 0;
1041 * Readable error output
1043 #ifdef CONFIG_MMC_DEBUG
1044 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1046 /* --- means reserved bit without definition at documentation */
1047 static const char *omap_hsmmc_status_bits[] = {
1048 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1049 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1050 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1051 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1057 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1060 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1061 if (status & (1 << i)) {
1062 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1066 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1069 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1073 #endif /* CONFIG_MMC_DEBUG */
1076 * MMC controller internal state machines reset
1078 * Used to reset command or data internal state machines, using respectively
1079 * SRC or SRD bit of SYSCTL register
1080 * Can be called from interrupt context
1082 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1085 unsigned long i = 0;
1086 unsigned long limit = MMC_TIMEOUT_US;
1088 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1089 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1092 * OMAP4 ES2 and greater has an updated reset logic.
1093 * Monitor a 0->1 transition first
1095 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1096 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1102 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1106 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1107 dev_err(mmc_dev(host->mmc),
1108 "Timeout waiting on controller reset in %s\n",
1112 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1113 int err, int end_cmd)
1116 omap_hsmmc_reset_controller_fsm(host, SRC);
1118 host->cmd->error = err;
1122 omap_hsmmc_reset_controller_fsm(host, SRD);
1123 omap_hsmmc_dma_cleanup(host, err);
1124 } else if (host->mrq && host->mrq->cmd)
1125 host->mrq->cmd->error = err;
1128 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1130 struct mmc_data *data;
1131 int end_cmd = 0, end_trans = 0;
1135 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1137 if (status & ERR_EN) {
1138 omap_hsmmc_dbg_report_irq(host, status);
1140 if (status & (CTO_EN | CCRC_EN))
1142 if (host->data || host->response_busy) {
1143 end_trans = !end_cmd;
1144 host->response_busy = 0;
1146 if (status & (CTO_EN | DTO_EN))
1147 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1148 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1150 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1152 if (status & ACE_EN) {
1154 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1155 if (!(ac12 & ACNE) && host->mrq->sbc) {
1159 else if (ac12 & (ACCE | ACEB | ACIE))
1161 host->mrq->sbc->error = error;
1162 hsmmc_command_incomplete(host, error, end_cmd);
1164 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1168 OMAP_HSMMC_WRITE(host->base, STAT, status);
1169 if (end_cmd || ((status & CC_EN) && host->cmd))
1170 omap_hsmmc_cmd_done(host, host->cmd);
1171 if ((end_trans || (status & TC_EN)) && host->mrq)
1172 omap_hsmmc_xfer_done(host, data);
1176 * MMC controller IRQ handler
1178 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1180 struct omap_hsmmc_host *host = dev_id;
1183 status = OMAP_HSMMC_READ(host->base, STAT);
1184 while (status & (INT_EN_MASK | CIRQ_EN)) {
1185 if (host->req_in_progress)
1186 omap_hsmmc_do_irq(host, status);
1188 if (status & CIRQ_EN)
1189 mmc_signal_sdio_irq(host->mmc);
1191 /* Flush posted write */
1192 status = OMAP_HSMMC_READ(host->base, STAT);
1198 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1202 OMAP_HSMMC_WRITE(host->base, HCTL,
1203 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1204 for (i = 0; i < loops_per_jiffy; i++) {
1205 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1212 * Switch MMC interface voltage ... only relevant for MMC1.
1214 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1215 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1216 * Some chips, like eMMC ones, use internal transceivers.
1218 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1223 /* Disable the clocks */
1224 pm_runtime_put_sync(host->dev);
1226 clk_disable_unprepare(host->dbclk);
1228 /* Turn the power off */
1229 ret = omap_hsmmc_set_power(host->dev, 0, 0);
1231 /* Turn the power ON with given VDD 1.8 or 3.0v */
1233 ret = omap_hsmmc_set_power(host->dev, 1, vdd);
1234 pm_runtime_get_sync(host->dev);
1236 clk_prepare_enable(host->dbclk);
1241 OMAP_HSMMC_WRITE(host->base, HCTL,
1242 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1243 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1246 * If a MMC dual voltage card is detected, the set_ios fn calls
1247 * this fn with VDD bit set for 1.8V. Upon card removal from the
1248 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1250 * Cope with a bit of slop in the range ... per data sheets:
1251 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1252 * but recommended values are 1.71V to 1.89V
1253 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1254 * but recommended values are 2.7V to 3.3V
1256 * Board setup code shouldn't permit anything very out-of-range.
1257 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1258 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1260 if ((1 << vdd) <= MMC_VDD_23_24)
1265 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1266 set_sd_bus_power(host);
1270 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1274 /* Protect the card while the cover is open */
1275 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1277 if (!host->get_cover_state)
1280 host->reqs_blocked = 0;
1281 if (host->get_cover_state(host->dev)) {
1282 if (host->protect_card) {
1283 dev_info(host->dev, "%s: cover is closed, "
1284 "card is now accessible\n",
1285 mmc_hostname(host->mmc));
1286 host->protect_card = 0;
1289 if (!host->protect_card) {
1290 dev_info(host->dev, "%s: cover is open, "
1291 "card is now inaccessible\n",
1292 mmc_hostname(host->mmc));
1293 host->protect_card = 1;
1299 * irq handler when (cell-phone) cover is mounted/removed
1301 static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1303 struct omap_hsmmc_host *host = dev_id;
1305 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1307 omap_hsmmc_protect_card(host);
1308 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1312 static void omap_hsmmc_dma_callback(void *param)
1314 struct omap_hsmmc_host *host = param;
1315 struct dma_chan *chan;
1316 struct mmc_data *data;
1317 int req_in_progress;
1319 spin_lock_irq(&host->irq_lock);
1320 if (host->dma_ch < 0) {
1321 spin_unlock_irq(&host->irq_lock);
1325 data = host->mrq->data;
1326 chan = omap_hsmmc_get_dma_chan(host, data);
1327 if (!data->host_cookie)
1328 dma_unmap_sg(chan->device->dev,
1329 data->sg, data->sg_len,
1330 omap_hsmmc_get_dma_dir(host, data));
1332 req_in_progress = host->req_in_progress;
1334 spin_unlock_irq(&host->irq_lock);
1336 /* If DMA has finished after TC, complete the request */
1337 if (!req_in_progress) {
1338 struct mmc_request *mrq = host->mrq;
1341 mmc_request_done(host->mmc, mrq);
1342 pm_runtime_mark_last_busy(host->dev);
1343 pm_runtime_put_autosuspend(host->dev);
1347 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1348 struct mmc_data *data,
1349 struct omap_hsmmc_next *next,
1350 struct dma_chan *chan)
1354 if (!next && data->host_cookie &&
1355 data->host_cookie != host->next_data.cookie) {
1356 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1357 " host->next_data.cookie %d\n",
1358 __func__, data->host_cookie, host->next_data.cookie);
1359 data->host_cookie = 0;
1362 /* Check if next job is already prepared */
1363 if (next || data->host_cookie != host->next_data.cookie) {
1364 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1365 omap_hsmmc_get_dma_dir(host, data));
1368 dma_len = host->next_data.dma_len;
1369 host->next_data.dma_len = 0;
1377 next->dma_len = dma_len;
1378 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1380 host->dma_len = dma_len;
1386 * Routine to configure and start DMA for the MMC card
1388 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1389 struct mmc_request *req)
1391 struct dma_slave_config cfg;
1392 struct dma_async_tx_descriptor *tx;
1394 struct mmc_data *data = req->data;
1395 struct dma_chan *chan;
1397 /* Sanity check: all the SG entries must be aligned by block size. */
1398 for (i = 0; i < data->sg_len; i++) {
1399 struct scatterlist *sgl;
1402 if (sgl->length % data->blksz)
1405 if ((data->blksz % 4) != 0)
1406 /* REVISIT: The MMC buffer increments only when MSB is written.
1407 * Return error for blksz which is non multiple of four.
1411 BUG_ON(host->dma_ch != -1);
1413 chan = omap_hsmmc_get_dma_chan(host, data);
1415 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1416 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1417 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1418 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1419 cfg.src_maxburst = data->blksz / 4;
1420 cfg.dst_maxburst = data->blksz / 4;
1422 ret = dmaengine_slave_config(chan, &cfg);
1426 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1430 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1431 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1432 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1434 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1435 /* FIXME: cleanup */
1439 tx->callback = omap_hsmmc_dma_callback;
1440 tx->callback_param = host;
1443 dmaengine_submit(tx);
1450 static void set_data_timeout(struct omap_hsmmc_host *host,
1451 unsigned int timeout_ns,
1452 unsigned int timeout_clks)
1454 unsigned int timeout, cycle_ns;
1455 uint32_t reg, clkd, dto = 0;
1457 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1458 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1462 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1463 timeout = timeout_ns / cycle_ns;
1464 timeout += timeout_clks;
1466 while ((timeout & 0x80000000) == 0) {
1483 reg |= dto << DTO_SHIFT;
1484 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1487 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1489 struct mmc_request *req = host->mrq;
1490 struct dma_chan *chan;
1494 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1495 | (req->data->blocks << 16));
1496 set_data_timeout(host, req->data->timeout_ns,
1497 req->data->timeout_clks);
1498 chan = omap_hsmmc_get_dma_chan(host, req->data);
1499 dma_async_issue_pending(chan);
1503 * Configure block length for MMC/SD cards and initiate the transfer.
1506 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1509 host->data = req->data;
1511 if (req->data == NULL) {
1512 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1514 * Set an arbitrary 100ms data timeout for commands with
1517 if (req->cmd->flags & MMC_RSP_BUSY)
1518 set_data_timeout(host, 100000000U, 0);
1522 if (host->use_dma) {
1523 ret = omap_hsmmc_setup_dma_transfer(host, req);
1525 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1532 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1535 struct omap_hsmmc_host *host = mmc_priv(mmc);
1536 struct mmc_data *data = mrq->data;
1538 if (host->use_dma && data->host_cookie) {
1539 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1541 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1542 omap_hsmmc_get_dma_dir(host, data));
1543 data->host_cookie = 0;
1547 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1550 struct omap_hsmmc_host *host = mmc_priv(mmc);
1552 if (mrq->data->host_cookie) {
1553 mrq->data->host_cookie = 0;
1557 if (host->use_dma) {
1558 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1560 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1561 &host->next_data, c))
1562 mrq->data->host_cookie = 0;
1567 * Request function. for read/write operation
1569 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
1574 BUG_ON(host->req_in_progress);
1575 BUG_ON(host->dma_ch != -1);
1576 pm_runtime_get_sync(host->dev);
1577 if (host->protect_card) {
1578 if (host->reqs_blocked < 3) {
1580 * Ensure the controller is left in a consistent
1581 * state by resetting the command and data state
1584 omap_hsmmc_reset_controller_fsm(host, SRD);
1585 omap_hsmmc_reset_controller_fsm(host, SRC);
1586 host->reqs_blocked += 1;
1588 req->cmd->error = -EBADF;
1590 req->data->error = -EBADF;
1591 req->cmd->retries = 0;
1592 mmc_request_done(mmc, req);
1593 pm_runtime_mark_last_busy(host->dev);
1594 pm_runtime_put_autosuspend(host->dev);
1596 } else if (host->reqs_blocked)
1597 host->reqs_blocked = 0;
1598 WARN_ON(host->mrq != NULL);
1600 host->clk_rate = clk_get_rate(host->fclk);
1601 err = omap_hsmmc_prepare_data(host, req);
1603 req->cmd->error = err;
1605 req->data->error = err;
1607 mmc_request_done(mmc, req);
1608 pm_runtime_mark_last_busy(host->dev);
1609 pm_runtime_put_autosuspend(host->dev);
1612 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1613 omap_hsmmc_start_command(host, req->sbc, NULL);
1617 omap_hsmmc_start_dma_transfer(host);
1618 omap_hsmmc_start_command(host, req->cmd, req->data);
1621 /* Routine to configure clock values. Exposed API to core */
1622 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1624 struct omap_hsmmc_host *host = mmc_priv(mmc);
1625 int do_send_init_stream = 0;
1627 pm_runtime_get_sync(host->dev);
1629 if (ios->power_mode != host->power_mode) {
1630 switch (ios->power_mode) {
1632 omap_hsmmc_set_power(host->dev, 0, 0);
1635 omap_hsmmc_set_power(host->dev, 1, ios->vdd);
1638 do_send_init_stream = 1;
1641 host->power_mode = ios->power_mode;
1644 /* FIXME: set registers based only on changes to ios */
1646 omap_hsmmc_set_bus_width(host);
1648 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1649 /* Only MMC1 can interface at 3V without some flavor
1650 * of external transceiver; but they all handle 1.8V.
1652 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1653 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1655 * The mmc_select_voltage fn of the core does
1656 * not seem to set the power_mode to
1657 * MMC_POWER_UP upon recalculating the voltage.
1660 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1661 dev_dbg(mmc_dev(host->mmc),
1662 "Switch operation failed\n");
1666 omap_hsmmc_set_clock(host);
1668 if (do_send_init_stream)
1669 send_init_stream(host);
1671 omap_hsmmc_set_bus_mode(host);
1673 pm_runtime_put_autosuspend(host->dev);
1676 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1678 struct omap_hsmmc_host *host = mmc_priv(mmc);
1680 if (!host->card_detect)
1682 return host->card_detect(host->dev);
1685 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1687 struct omap_hsmmc_host *host = mmc_priv(mmc);
1689 if (mmc_pdata(host)->init_card)
1690 mmc_pdata(host)->init_card(card);
1693 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1695 struct omap_hsmmc_host *host = mmc_priv(mmc);
1697 unsigned long flags;
1699 spin_lock_irqsave(&host->irq_lock, flags);
1701 con = OMAP_HSMMC_READ(host->base, CON);
1702 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1704 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1705 irq_mask |= CIRQ_EN;
1706 con |= CTPL | CLKEXTFREE;
1708 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1709 irq_mask &= ~CIRQ_EN;
1710 con &= ~(CTPL | CLKEXTFREE);
1712 OMAP_HSMMC_WRITE(host->base, CON, con);
1713 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1716 * if enable, piggy back detection on current request
1717 * but always disable immediately
1719 if (!host->req_in_progress || !enable)
1720 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1722 /* flush posted write */
1723 OMAP_HSMMC_READ(host->base, IE);
1725 spin_unlock_irqrestore(&host->irq_lock, flags);
1728 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1733 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1734 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1735 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1736 * with functional clock disabled.
1738 if (!host->dev->of_node || !host->wake_irq)
1741 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1743 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1748 * Some omaps don't have wake-up path from deeper idle states
1749 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1751 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1752 struct pinctrl *p = devm_pinctrl_get(host->dev);
1757 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1758 dev_info(host->dev, "missing default pinctrl state\n");
1759 devm_pinctrl_put(p);
1764 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1765 dev_info(host->dev, "missing idle pinctrl state\n");
1766 devm_pinctrl_put(p);
1770 devm_pinctrl_put(p);
1773 OMAP_HSMMC_WRITE(host->base, HCTL,
1774 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1778 dev_pm_clear_wake_irq(host->dev);
1780 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1785 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1787 u32 hctl, capa, value;
1789 /* Only MMC1 supports 3.0V */
1790 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1798 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1799 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1801 value = OMAP_HSMMC_READ(host->base, CAPA);
1802 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1804 /* Set SD bus power bit */
1805 set_sd_bus_power(host);
1808 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1809 unsigned int direction, int blk_size)
1811 /* This controller can't do multiblock reads due to hw bugs */
1812 if (direction == MMC_DATA_READ)
1818 static struct mmc_host_ops omap_hsmmc_ops = {
1819 .post_req = omap_hsmmc_post_req,
1820 .pre_req = omap_hsmmc_pre_req,
1821 .request = omap_hsmmc_request,
1822 .set_ios = omap_hsmmc_set_ios,
1823 .get_cd = omap_hsmmc_get_cd,
1824 .get_ro = mmc_gpio_get_ro,
1825 .init_card = omap_hsmmc_init_card,
1826 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1829 #ifdef CONFIG_DEBUG_FS
1831 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1833 struct mmc_host *mmc = s->private;
1834 struct omap_hsmmc_host *host = mmc_priv(mmc);
1836 seq_printf(s, "mmc%d:\n", mmc->index);
1837 seq_printf(s, "sdio irq mode\t%s\n",
1838 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1840 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1841 seq_printf(s, "sdio irq \t%s\n",
1842 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1845 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1847 pm_runtime_get_sync(host->dev);
1848 seq_puts(s, "\nregs:\n");
1849 seq_printf(s, "CON:\t\t0x%08x\n",
1850 OMAP_HSMMC_READ(host->base, CON));
1851 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1852 OMAP_HSMMC_READ(host->base, PSTATE));
1853 seq_printf(s, "HCTL:\t\t0x%08x\n",
1854 OMAP_HSMMC_READ(host->base, HCTL));
1855 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1856 OMAP_HSMMC_READ(host->base, SYSCTL));
1857 seq_printf(s, "IE:\t\t0x%08x\n",
1858 OMAP_HSMMC_READ(host->base, IE));
1859 seq_printf(s, "ISE:\t\t0x%08x\n",
1860 OMAP_HSMMC_READ(host->base, ISE));
1861 seq_printf(s, "CAPA:\t\t0x%08x\n",
1862 OMAP_HSMMC_READ(host->base, CAPA));
1864 pm_runtime_mark_last_busy(host->dev);
1865 pm_runtime_put_autosuspend(host->dev);
1870 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1872 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1875 static const struct file_operations mmc_regs_fops = {
1876 .open = omap_hsmmc_regs_open,
1878 .llseek = seq_lseek,
1879 .release = single_release,
1882 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1884 if (mmc->debugfs_root)
1885 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1886 mmc, &mmc_regs_fops);
1891 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1898 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1899 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1900 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1903 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1904 .reg_offset = 0x100,
1906 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1907 .reg_offset = 0x100,
1908 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1911 static const struct of_device_id omap_mmc_of_match[] = {
1913 .compatible = "ti,omap2-hsmmc",
1916 .compatible = "ti,omap3-pre-es3-hsmmc",
1917 .data = &omap3_pre_es3_mmc_of_data,
1920 .compatible = "ti,omap3-hsmmc",
1923 .compatible = "ti,omap4-hsmmc",
1924 .data = &omap4_mmc_of_data,
1927 .compatible = "ti,am33xx-hsmmc",
1928 .data = &am33xx_mmc_of_data,
1932 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1934 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1936 struct omap_hsmmc_platform_data *pdata;
1937 struct device_node *np = dev->of_node;
1939 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1941 return ERR_PTR(-ENOMEM); /* out of memory */
1943 if (of_find_property(np, "ti,dual-volt", NULL))
1944 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1946 pdata->gpio_cd = -EINVAL;
1947 pdata->gpio_cod = -EINVAL;
1948 pdata->gpio_wp = -EINVAL;
1950 if (of_find_property(np, "ti,non-removable", NULL)) {
1951 pdata->nonremovable = true;
1952 pdata->no_regulator_off_init = true;
1955 if (of_find_property(np, "ti,needs-special-reset", NULL))
1956 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1958 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1959 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1964 static inline struct omap_hsmmc_platform_data
1965 *of_get_hsmmc_pdata(struct device *dev)
1967 return ERR_PTR(-EINVAL);
1971 static int omap_hsmmc_probe(struct platform_device *pdev)
1973 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1974 struct mmc_host *mmc;
1975 struct omap_hsmmc_host *host = NULL;
1976 struct resource *res;
1978 const struct of_device_id *match;
1979 dma_cap_mask_t mask;
1980 unsigned tx_req, rx_req;
1981 const struct omap_mmc_of_data *data;
1984 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1986 pdata = of_get_hsmmc_pdata(&pdev->dev);
1989 return PTR_ERR(pdata);
1993 pdata->reg_offset = data->reg_offset;
1994 pdata->controller_flags |= data->controller_flags;
1998 if (pdata == NULL) {
1999 dev_err(&pdev->dev, "Platform Data is missing\n");
2003 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2004 irq = platform_get_irq(pdev, 0);
2005 if (res == NULL || irq < 0)
2008 base = devm_ioremap_resource(&pdev->dev, res);
2010 return PTR_ERR(base);
2012 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2018 ret = mmc_of_parse(mmc);
2022 host = mmc_priv(mmc);
2024 host->pdata = pdata;
2025 host->dev = &pdev->dev;
2029 host->mapbase = res->start + pdata->reg_offset;
2030 host->base = base + pdata->reg_offset;
2031 host->power_mode = MMC_POWER_OFF;
2032 host->next_data.cookie = 1;
2033 host->pbias_enabled = 0;
2035 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
2039 platform_set_drvdata(pdev, host);
2041 if (pdev->dev.of_node)
2042 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2044 mmc->ops = &omap_hsmmc_ops;
2046 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2048 if (pdata->max_freq > 0)
2049 mmc->f_max = pdata->max_freq;
2050 else if (mmc->f_max == 0)
2051 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2053 spin_lock_init(&host->irq_lock);
2055 host->fclk = devm_clk_get(&pdev->dev, "fck");
2056 if (IS_ERR(host->fclk)) {
2057 ret = PTR_ERR(host->fclk);
2062 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2063 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2064 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2067 device_init_wakeup(&pdev->dev, true);
2068 pm_runtime_enable(host->dev);
2069 pm_runtime_get_sync(host->dev);
2070 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2071 pm_runtime_use_autosuspend(host->dev);
2073 omap_hsmmc_context_save(host);
2075 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2077 * MMC can still work without debounce clock.
2079 if (IS_ERR(host->dbclk)) {
2081 } else if (clk_prepare_enable(host->dbclk) != 0) {
2082 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2086 /* Since we do only SG emulation, we can have as many segs
2088 mmc->max_segs = 1024;
2090 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2091 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2092 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2093 mmc->max_seg_size = mmc->max_req_size;
2095 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2096 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2098 mmc->caps |= mmc_pdata(host)->caps;
2099 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2100 mmc->caps |= MMC_CAP_4_BIT_DATA;
2102 if (mmc_pdata(host)->nonremovable)
2103 mmc->caps |= MMC_CAP_NONREMOVABLE;
2105 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
2107 omap_hsmmc_conf_bus_power(host);
2109 if (!pdev->dev.of_node) {
2110 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2112 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2116 tx_req = res->start;
2118 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2120 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2124 rx_req = res->start;
2128 dma_cap_set(DMA_SLAVE, mask);
2131 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2132 &rx_req, &pdev->dev, "rx");
2134 if (!host->rx_chan) {
2135 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2141 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2142 &tx_req, &pdev->dev, "tx");
2144 if (!host->tx_chan) {
2145 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2150 /* Request IRQ for MMC operations */
2151 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2152 mmc_hostname(mmc), host);
2154 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2158 if (omap_hsmmc_have_reg()) {
2159 ret = omap_hsmmc_reg_get(host);
2164 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2166 omap_hsmmc_disable_irq(host);
2169 * For now, only support SDIO interrupt if we have a separate
2170 * wake-up interrupt configured from device tree. This is because
2171 * the wake-up interrupt is needed for idle state and some
2172 * platforms need special quirks. And we don't want to add new
2173 * legacy mux platform init code callbacks any longer as we
2174 * are moving to DT based booting anyways.
2176 ret = omap_hsmmc_configure_wake_irq(host);
2178 mmc->caps |= MMC_CAP_SDIO_IRQ;
2180 omap_hsmmc_protect_card(host);
2184 if (mmc_pdata(host)->name != NULL) {
2185 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2189 if (host->get_cover_state) {
2190 ret = device_create_file(&mmc->class_dev,
2191 &dev_attr_cover_switch);
2196 omap_hsmmc_debugfs(mmc);
2197 pm_runtime_mark_last_busy(host->dev);
2198 pm_runtime_put_autosuspend(host->dev);
2203 mmc_remove_host(mmc);
2205 device_init_wakeup(&pdev->dev, false);
2207 dma_release_channel(host->tx_chan);
2209 dma_release_channel(host->rx_chan);
2210 pm_runtime_put_sync(host->dev);
2211 pm_runtime_disable(host->dev);
2213 clk_disable_unprepare(host->dbclk);
2221 static int omap_hsmmc_remove(struct platform_device *pdev)
2223 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2225 pm_runtime_get_sync(host->dev);
2226 mmc_remove_host(host->mmc);
2229 dma_release_channel(host->tx_chan);
2231 dma_release_channel(host->rx_chan);
2233 pm_runtime_put_sync(host->dev);
2234 pm_runtime_disable(host->dev);
2235 device_init_wakeup(&pdev->dev, false);
2237 clk_disable_unprepare(host->dbclk);
2239 mmc_free_host(host->mmc);
2244 #ifdef CONFIG_PM_SLEEP
2245 static int omap_hsmmc_suspend(struct device *dev)
2247 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2252 pm_runtime_get_sync(host->dev);
2254 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2255 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2256 OMAP_HSMMC_WRITE(host->base, IE, 0);
2257 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2258 OMAP_HSMMC_WRITE(host->base, HCTL,
2259 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2263 clk_disable_unprepare(host->dbclk);
2265 pm_runtime_put_sync(host->dev);
2269 /* Routine to resume the MMC device */
2270 static int omap_hsmmc_resume(struct device *dev)
2272 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2277 pm_runtime_get_sync(host->dev);
2280 clk_prepare_enable(host->dbclk);
2282 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2283 omap_hsmmc_conf_bus_power(host);
2285 omap_hsmmc_protect_card(host);
2286 pm_runtime_mark_last_busy(host->dev);
2287 pm_runtime_put_autosuspend(host->dev);
2292 static int omap_hsmmc_runtime_suspend(struct device *dev)
2294 struct omap_hsmmc_host *host;
2295 unsigned long flags;
2298 host = platform_get_drvdata(to_platform_device(dev));
2299 omap_hsmmc_context_save(host);
2300 dev_dbg(dev, "disabled\n");
2302 spin_lock_irqsave(&host->irq_lock, flags);
2303 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2304 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2305 /* disable sdio irq handling to prevent race */
2306 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2307 OMAP_HSMMC_WRITE(host->base, IE, 0);
2309 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2311 * dat1 line low, pending sdio irq
2312 * race condition: possible irq handler running on
2315 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2316 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2317 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2318 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2319 pm_runtime_mark_last_busy(dev);
2324 pinctrl_pm_select_idle_state(dev);
2326 pinctrl_pm_select_idle_state(dev);
2330 spin_unlock_irqrestore(&host->irq_lock, flags);
2334 static int omap_hsmmc_runtime_resume(struct device *dev)
2336 struct omap_hsmmc_host *host;
2337 unsigned long flags;
2339 host = platform_get_drvdata(to_platform_device(dev));
2340 omap_hsmmc_context_restore(host);
2341 dev_dbg(dev, "enabled\n");
2343 spin_lock_irqsave(&host->irq_lock, flags);
2344 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2345 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2347 pinctrl_pm_select_default_state(host->dev);
2349 /* irq lost, if pinmux incorrect */
2350 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2351 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2352 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2354 pinctrl_pm_select_default_state(host->dev);
2356 spin_unlock_irqrestore(&host->irq_lock, flags);
2360 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2361 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2362 .runtime_suspend = omap_hsmmc_runtime_suspend,
2363 .runtime_resume = omap_hsmmc_runtime_resume,
2366 static struct platform_driver omap_hsmmc_driver = {
2367 .probe = omap_hsmmc_probe,
2368 .remove = omap_hsmmc_remove,
2370 .name = DRIVER_NAME,
2371 .pm = &omap_hsmmc_dev_pm_ops,
2372 .of_match_table = of_match_ptr(omap_mmc_of_match),
2376 module_platform_driver(omap_hsmmc_driver);
2377 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2378 MODULE_LICENSE("GPL");
2379 MODULE_ALIAS("platform:" DRIVER_NAME);
2380 MODULE_AUTHOR("Texas Instruments Inc");