drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/omap-dmaengine.h>
  36 #include <linux/mmc/host.h>
  37 #include <linux/mmc/core.h>
  38 #include <linux/mmc/mmc.h>
  39 #include <linux/io.h>
  40 #include <linux/irq.h>
  41 #include <linux/gpio.h>
  42 #include <linux/regulator/consumer.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/platform_data/hsmmc-omap.h>
  46
  47 /* OMAP HSMMC Host Controller Registers */
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_SDMASA       0x0100
  51 #define OMAP_HSMMC_BLK          0x0104
  52 #define OMAP_HSMMC_ARG          0x0108
  53 #define OMAP_HSMMC_CMD          0x010C
  54 #define OMAP_HSMMC_RSP10        0x0110
  55 #define OMAP_HSMMC_RSP32        0x0114
  56 #define OMAP_HSMMC_RSP54        0x0118
  57 #define OMAP_HSMMC_RSP76        0x011C
  58 #define OMAP_HSMMC_DATA         0x0120
  59 #define OMAP_HSMMC_PSTATE       0x0124
  60 #define OMAP_HSMMC_HCTL         0x0128
  61 #define OMAP_HSMMC_SYSCTL       0x012C
  62 #define OMAP_HSMMC_STAT         0x0130
  63 #define OMAP_HSMMC_IE           0x0134
  64 #define OMAP_HSMMC_ISE          0x0138
  65 #define OMAP_HSMMC_AC12         0x013C
  66 #define OMAP_HSMMC_CAPA         0x0140
  67
  68 #define VS18                    (1 << 26)
  69 #define VS30                    (1 << 25)
  70 #define HSS                     (1 << 21)
  71 #define SDVS18                  (0x5 << 9)
  72 #define SDVS30                  (0x6 << 9)
  73 #define SDVS33                  (0x7 << 9)
  74 #define SDVS_MASK               0x00000E00
  75 #define SDVSCLR                 0xFFFFF1FF
  76 #define SDVSDET                 0x00000400
  77 #define AUTOIDLE                0x1
  78 #define SDBP                    (1 << 8)
  79 #define DTO                     0xe
  80 #define ICE                     0x1
  81 #define ICS                     0x2
  82 #define CEN                     (1 << 2)
  83 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  84 #define CLKD_MASK               0x0000FFC0
  85 #define CLKD_SHIFT              6
  86 #define DTO_MASK                0x000F0000
  87 #define DTO_SHIFT               16
  88 #define INIT_STREAM             (1 << 1)
  89 #define ACEN_ACMD23             (2 << 2)
  90 #define DP_SELECT               (1 << 21)
  91 #define DDIR                    (1 << 4)
  92 #define DMAE                    0x1
  93 #define MSBS                    (1 << 5)
  94 #define BCE                     (1 << 1)
  95 #define FOUR_BIT                (1 << 1)
  96 #define HSPE                    (1 << 2)
  97 #define IWE                     (1 << 24)
  98 #define DDR                     (1 << 19)
  99 #define CLKEXTFREE              (1 << 16)
 100 #define CTPL                    (1 << 11)
 101 #define DW8                     (1 << 5)
 102 #define OD                      0x1
 103 #define STAT_CLEAR              0xFFFFFFFF
 104 #define INIT_STREAM_CMD         0x00000000
 105 #define DUAL_VOLT_OCR_BIT       7
 106 #define SRC                     (1 << 25)
 107 #define SRD                     (1 << 26)
 108 #define SOFTRESET               (1 << 1)
 109
 110 /* PSTATE */
 111 #define DLEV_DAT(x)             (1 << (20 + (x)))
 112
 113 /* Interrupt masks for IE and ISE register */
 114 #define CC_EN                   (1 << 0)
 115 #define TC_EN                   (1 << 1)
 116 #define BWR_EN                  (1 << 4)
 117 #define BRR_EN                  (1 << 5)
 118 #define CIRQ_EN                 (1 << 8)
 119 #define ERR_EN                  (1 << 15)
 120 #define CTO_EN                  (1 << 16)
 121 #define CCRC_EN                 (1 << 17)
 122 #define CEB_EN                  (1 << 18)
 123 #define CIE_EN                  (1 << 19)
 124 #define DTO_EN                  (1 << 20)
 125 #define DCRC_EN                 (1 << 21)
 126 #define DEB_EN                  (1 << 22)
 127 #define ACE_EN                  (1 << 24)
 128 #define CERR_EN                 (1 << 28)
 129 #define BADA_EN                 (1 << 29)
 130
 131 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
 132                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 133                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 134
 135 #define CNI     (1 << 7)
 136 #define ACIE    (1 << 4)
 137 #define ACEB    (1 << 3)
 138 #define ACCE    (1 << 2)
 139 #define ACTO    (1 << 1)
 140 #define ACNE    (1 << 0)
 141
 142 #define MMC_AUTOSUSPEND_DELAY   100
 143 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 144 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 145 #define OMAP_MMC_MIN_CLOCK      400000
 146 #define OMAP_MMC_MAX_CLOCK      52000000
 147 #define DRIVER_NAME             "omap_hsmmc"
 148
 149 #define VDD_1V8                 1800000         /* 180000 uV */
 150 #define VDD_3V0                 3000000         /* 300000 uV */
 151 #define VDD_165_195             (ffs(MMC_VDD_165_195) - 1)
 152
 153 /*
 154  * One controller can have multiple slots, like on some omap boards using
 155  * omap.c controller driver. Luckily this is not currently done on any known
 156  * omap_hsmmc.c device.
 157  */
 158 #define mmc_pdata(host)         host->pdata
 159
 160 /*
 161  * MMC Host controller read/write API's
 162  */
 163 #define OMAP_HSMMC_READ(base, reg)      \
 164         __raw_readl((base) + OMAP_HSMMC_##reg)
 165
 166 #define OMAP_HSMMC_WRITE(base, reg, val) \
 167         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 168
 169 struct omap_hsmmc_next {
 170         unsigned int    dma_len;
 171         s32             cookie;
 172 };
 173
 174 struct omap_hsmmc_host {
 175         struct  device          *dev;
 176         struct  mmc_host        *mmc;
 177         struct  mmc_request     *mrq;
 178         struct  mmc_command     *cmd;
 179         struct  mmc_data        *data;
 180         struct  clk             *fclk;
 181         struct  clk             *dbclk;
 182         /*
 183          * vcc == configured supply
 184          * vcc_aux == optional
 185          *   -  MMC1, supply for DAT4..DAT7
 186          *   -  MMC2/MMC2, external level shifter voltage supply, for
 187          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 188          */
 189         struct  regulator       *vcc;
 190         struct  regulator       *vcc_aux;
 191         struct  regulator       *pbias;
 192         bool                    pbias_enabled;
 193         void    __iomem         *base;
 194         resource_size_t         mapbase;
 195         spinlock_t              irq_lock; /* Prevent races with irq handler */
 196         unsigned int            dma_len;
 197         unsigned int            dma_sg_idx;
 198         unsigned char           bus_mode;
 199         unsigned char           power_mode;
 200         int                     suspended;
 201         u32                     con;
 202         u32                     hctl;
 203         u32                     sysctl;
 204         u32                     capa;
 205         int                     irq;
 206         int                     wake_irq;
 207         int                     use_dma, dma_ch;
 208         struct dma_chan         *tx_chan;
 209         struct dma_chan         *rx_chan;
 210         int                     response_busy;
 211         int                     context_loss;
 212         int                     protect_card;
 213         int                     reqs_blocked;
 214         int                     use_reg;
 215         int                     req_in_progress;
 216         unsigned long           clk_rate;
 217         unsigned int            flags;
 218 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
 219 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
 220 #define HSMMC_WAKE_IRQ_ENABLED  (1 << 2)
 221         struct omap_hsmmc_next  next_data;
 222         struct  omap_hsmmc_platform_data        *pdata;
 223
 224         /* To handle board related suspend/resume functionality for MMC */
 225         int (*suspend)(struct device *dev);
 226         int (*resume)(struct device *dev);
 227
 228         /* return MMC cover switch state, can be NULL if not supported.
 229          *
 230          * possible return values:
 231          *   0 - closed
 232          *   1 - open
 233          */
 234         int (*get_cover_state)(struct device *dev);
 235
 236         /* Card detection IRQs */
 237         int card_detect_irq;
 238
 239         int (*card_detect)(struct device *dev);
 240         int (*get_ro)(struct device *dev);
 241
 242 };
 243
 244 struct omap_mmc_of_data {
 245         u32 reg_offset;
 246         u8 controller_flags;
 247 };
 248
 249 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 250
 251 static int omap_hsmmc_card_detect(struct device *dev)
 252 {
 253         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 254         struct omap_hsmmc_platform_data *mmc = host->pdata;
 255
 256         /* NOTE: assumes card detect signal is active-low */
 257         return !gpio_get_value_cansleep(mmc->switch_pin);
 258 }
 259
 260 static int omap_hsmmc_get_wp(struct device *dev)
 261 {
 262         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 263         struct omap_hsmmc_platform_data *mmc = host->pdata;
 264
 265         /* NOTE: assumes write protect signal is active-high */
 266         return gpio_get_value_cansleep(mmc->gpio_wp);
 267 }
 268
 269 static int omap_hsmmc_get_cover_state(struct device *dev)
 270 {
 271         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 272         struct omap_hsmmc_platform_data *mmc = host->pdata;
 273
 274         /* NOTE: assumes card detect signal is active-low */
 275         return !gpio_get_value_cansleep(mmc->switch_pin);
 276 }
 277
 278 #ifdef CONFIG_PM
 279
 280 static int omap_hsmmc_suspend_cdirq(struct device *dev)
 281 {
 282         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 283
 284         disable_irq(host->card_detect_irq);
 285         return 0;
 286 }
 287
 288 static int omap_hsmmc_resume_cdirq(struct device *dev)
 289 {
 290         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 291
 292         enable_irq(host->card_detect_irq);
 293         return 0;
 294 }
 295
 296 #else
 297
 298 #define omap_hsmmc_suspend_cdirq        NULL
 299 #define omap_hsmmc_resume_cdirq         NULL
 300
 301 #endif
 302
 303 #ifdef CONFIG_REGULATOR
 304
 305 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
 306 {
 307         struct omap_hsmmc_host *host =
 308                 platform_get_drvdata(to_platform_device(dev));
 309         int ret = 0;
 310
 311         /*
 312          * If we don't see a Vcc regulator, assume it's a fixed
 313          * voltage always-on regulator.
 314          */
 315         if (!host->vcc)
 316                 return 0;
 317
 318         if (mmc_pdata(host)->before_set_reg)
 319                 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
 320
 321         if (host->pbias) {
 322                 if (host->pbias_enabled == 1) {
 323                         ret = regulator_disable(host->pbias);
 324                         if (!ret)
 325                                 host->pbias_enabled = 0;
 326                 }
 327                 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
 328         }
 329
 330         /*
 331          * Assume Vcc regulator is used only to power the card ... OMAP
 332          * VDDS is used to power the pins, optionally with a transceiver to
 333          * support cards using voltages other than VDDS (1.8V nominal).  When a
 334          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 335          *
 336          * In some cases this regulator won't support enable/disable;
 337          * e.g. it's a fixed rail for a WLAN chip.
 338          *
 339          * In other cases vcc_aux switches interface power.  Example, for
 340          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 341          * chips/cards need an interface voltage rail too.
 342          */
 343         if (power_on) {
 344                 if (host->vcc)
 345                         ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 346                 /* Enable interface voltage rail, if needed */
 347                 if (ret == 0 && host->vcc_aux) {
 348                         ret = regulator_enable(host->vcc_aux);
 349                         if (ret < 0 && host->vcc)
 350                                 ret = mmc_regulator_set_ocr(host->mmc,
 351                                                         host->vcc, 0);
 352                 }
 353         } else {
 354                 /* Shut down the rail */
 355                 if (host->vcc_aux)
 356                         ret = regulator_disable(host->vcc_aux);
 357                 if (host->vcc) {
 358                         /* Then proceed to shut down the local regulator */
 359                         ret = mmc_regulator_set_ocr(host->mmc,
 360                                                 host->vcc, 0);
 361                 }
 362         }
 363
 364         if (host->pbias) {
 365                 if (vdd <= VDD_165_195)
 366                         ret = regulator_set_voltage(host->pbias, VDD_1V8,
 367                                                                 VDD_1V8);
 368                 else
 369                         ret = regulator_set_voltage(host->pbias, VDD_3V0,
 370                                                                 VDD_3V0);
 371                 if (ret < 0)
 372                         goto error_set_power;
 373
 374                 if (host->pbias_enabled == 0) {
 375                         ret = regulator_enable(host->pbias);
 376                         if (!ret)
 377                                 host->pbias_enabled = 1;
 378                 }
 379         }
 380
 381         if (mmc_pdata(host)->after_set_reg)
 382                 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
 383
 384 error_set_power:
 385         return ret;
 386 }
 387
 388 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 389 {
 390         struct regulator *reg;
 391         int ocr_value = 0;
 392
 393         reg = devm_regulator_get(host->dev, "vmmc");
 394         if (IS_ERR(reg)) {
 395                 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
 396                         PTR_ERR(reg));
 397                 return PTR_ERR(reg);
 398         } else {
 399                 host->vcc = reg;
 400                 ocr_value = mmc_regulator_get_ocrmask(reg);
 401                 if (!mmc_pdata(host)->ocr_mask) {
 402                         mmc_pdata(host)->ocr_mask = ocr_value;
 403                 } else {
 404                         if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
 405                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 406                                         mmc_pdata(host)->ocr_mask);
 407                                 mmc_pdata(host)->ocr_mask = 0;
 408                                 return -EINVAL;
 409                         }
 410                 }
 411         }
 412         mmc_pdata(host)->set_power = omap_hsmmc_set_power;
 413
 414         /* Allow an aux regulator */
 415         reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
 416         host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 417
 418         reg = devm_regulator_get_optional(host->dev, "pbias");
 419         host->pbias = IS_ERR(reg) ? NULL : reg;
 420
 421         /* For eMMC do not power off when not in sleep state */
 422         if (mmc_pdata(host)->no_regulator_off_init)
 423                 return 0;
 424         /*
 425          * To disable boot_on regulator, enable regulator
 426          * to increase usecount and then disable it.
 427          */
 428         if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
 429             (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 430                 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
 431
 432                 mmc_pdata(host)->set_power(host->dev, 1, vdd);
 433                 mmc_pdata(host)->set_power(host->dev, 0, 0);
 434         }
 435
 436         return 0;
 437 }
 438
 439 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 440 {
 441         mmc_pdata(host)->set_power = NULL;
 442 }
 443
 444 static inline int omap_hsmmc_have_reg(void)
 445 {
 446         return 1;
 447 }
 448
 449 #else
 450
 451 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 452 {
 453         return -EINVAL;
 454 }
 455
 456 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 457 {
 458 }
 459
 460 static inline int omap_hsmmc_have_reg(void)
 461 {
 462         return 0;
 463 }
 464
 465 #endif
 466
 467 static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host,
 468                                 struct omap_hsmmc_platform_data *pdata)
 469 {
 470         int ret;
 471
 472         if (gpio_is_valid(pdata->switch_pin)) {
 473                 if (pdata->cover)
 474                         host->get_cover_state =
 475                                 omap_hsmmc_get_cover_state;
 476                 else
 477                         host->card_detect = omap_hsmmc_card_detect;
 478                 host->card_detect_irq =
 479                                 gpio_to_irq(pdata->switch_pin);
 480                 ret = gpio_request(pdata->switch_pin, "mmc_cd");
 481                 if (ret)
 482                         return ret;
 483                 ret = gpio_direction_input(pdata->switch_pin);
 484                 if (ret)
 485                         goto err_free_sp;
 486         } else {
 487                 pdata->switch_pin = -EINVAL;
 488         }
 489
 490         if (gpio_is_valid(pdata->gpio_wp)) {
 491                 host->get_ro = omap_hsmmc_get_wp;
 492                 ret = gpio_request(pdata->gpio_wp, "mmc_wp");
 493                 if (ret)
 494                         goto err_free_cd;
 495                 ret = gpio_direction_input(pdata->gpio_wp);
 496                 if (ret)
 497                         goto err_free_wp;
 498         } else {
 499                 pdata->gpio_wp = -EINVAL;
 500         }
 501
 502         return 0;
 503
 504 err_free_wp:
 505         gpio_free(pdata->gpio_wp);
 506 err_free_cd:
 507         if (gpio_is_valid(pdata->switch_pin))
 508 err_free_sp:
 509                 gpio_free(pdata->switch_pin);
 510         return ret;
 511 }
 512
 513 static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host,
 514                                  struct omap_hsmmc_platform_data *pdata)
 515 {
 516         if (gpio_is_valid(pdata->gpio_wp))
 517                 gpio_free(pdata->gpio_wp);
 518         if (gpio_is_valid(pdata->switch_pin))
 519                 gpio_free(pdata->switch_pin);
 520 }
 521
 522 /*
 523  * Start clock to the card
 524  */
 525 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 526 {
 527         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 528                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 529 }
 530
 531 /*
 532  * Stop clock to the card
 533  */
 534 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 535 {
 536         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 537                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 538         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 539                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 540 }
 541
 542 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 543                                   struct mmc_command *cmd)
 544 {
 545         u32 irq_mask = INT_EN_MASK;
 546         unsigned long flags;
 547
 548         if (host->use_dma)
 549                 irq_mask &= ~(BRR_EN | BWR_EN);
 550
 551         /* Disable timeout for erases */
 552         if (cmd->opcode == MMC_ERASE)
 553                 irq_mask &= ~DTO_EN;
 554
 555         spin_lock_irqsave(&host->irq_lock, flags);
 556         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 557         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 558
 559         /* latch pending CIRQ, but don't signal MMC core */
 560         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 561                 irq_mask |= CIRQ_EN;
 562         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 563         spin_unlock_irqrestore(&host->irq_lock, flags);
 564 }
 565
 566 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 567 {
 568         u32 irq_mask = 0;
 569         unsigned long flags;
 570
 571         spin_lock_irqsave(&host->irq_lock, flags);
 572         /* no transfer running but need to keep cirq if enabled */
 573         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 574                 irq_mask |= CIRQ_EN;
 575         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 576         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 577         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 578         spin_unlock_irqrestore(&host->irq_lock, flags);
 579 }
 580
 581 /* Calculate divisor for the given clock frequency */
 582 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 583 {
 584         u16 dsor = 0;
 585
 586         if (ios->clock) {
 587                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 588                 if (dsor > CLKD_MAX)
 589                         dsor = CLKD_MAX;
 590         }
 591
 592         return dsor;
 593 }
 594
 595 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 596 {
 597         struct mmc_ios *ios = &host->mmc->ios;
 598         unsigned long regval;
 599         unsigned long timeout;
 600         unsigned long clkdiv;
 601
 602         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 603
 604         omap_hsmmc_stop_clock(host);
 605
 606         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 607         regval = regval & ~(CLKD_MASK | DTO_MASK);
 608         clkdiv = calc_divisor(host, ios);
 609         regval = regval | (clkdiv << 6) | (DTO << 16);
 610         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 611         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 612                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 613
 614         /* Wait till the ICS bit is set */
 615         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 616         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 617                 && time_before(jiffies, timeout))
 618                 cpu_relax();
 619
 620         /*
 621          * Enable High-Speed Support
 622          * Pre-Requisites
 623          *      - Controller should support High-Speed-Enable Bit
 624          *      - Controller should not be using DDR Mode
 625          *      - Controller should advertise that it supports High Speed
 626          *        in capabilities register
 627          *      - MMC/SD clock coming out of controller > 25MHz
 628          */
 629         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
 630             (ios->timing != MMC_TIMING_MMC_DDR52) &&
 631             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 632                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 633                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 634                         regval |= HSPE;
 635                 else
 636                         regval &= ~HSPE;
 637
 638                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 639         }
 640
 641         omap_hsmmc_start_clock(host);
 642 }
 643
 644 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 645 {
 646         struct mmc_ios *ios = &host->mmc->ios;
 647         u32 con;
 648
 649         con = OMAP_HSMMC_READ(host->base, CON);
 650         if (ios->timing == MMC_TIMING_MMC_DDR52)
 651                 con |= DDR;     /* configure in DDR mode */
 652         else
 653                 con &= ~DDR;
 654         switch (ios->bus_width) {
 655         case MMC_BUS_WIDTH_8:
 656                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 657                 break;
 658         case MMC_BUS_WIDTH_4:
 659                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 660                 OMAP_HSMMC_WRITE(host->base, HCTL,
 661                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 662                 break;
 663         case MMC_BUS_WIDTH_1:
 664                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 665                 OMAP_HSMMC_WRITE(host->base, HCTL,
 666                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 667                 break;
 668         }
 669 }
 670
 671 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 672 {
 673         struct mmc_ios *ios = &host->mmc->ios;
 674         u32 con;
 675
 676         con = OMAP_HSMMC_READ(host->base, CON);
 677         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 678                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 679         else
 680                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 681 }
 682
 683 #ifdef CONFIG_PM
 684
 685 /*
 686  * Restore the MMC host context, if it was lost as result of a
 687  * power state change.
 688  */
 689 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 690 {
 691         struct mmc_ios *ios = &host->mmc->ios;
 692         u32 hctl, capa;
 693         unsigned long timeout;
 694
 695         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 696             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 697             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 698             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 699                 return 0;
 700
 701         host->context_loss++;
 702
 703         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 704                 if (host->power_mode != MMC_POWER_OFF &&
 705                     (1 << ios->vdd) <= MMC_VDD_23_24)
 706                         hctl = SDVS18;
 707                 else
 708                         hctl = SDVS30;
 709                 capa = VS30 | VS18;
 710         } else {
 711                 hctl = SDVS18;
 712                 capa = VS18;
 713         }
 714
 715         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
 716                 hctl |= IWE;
 717
 718         OMAP_HSMMC_WRITE(host->base, HCTL,
 719                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 720
 721         OMAP_HSMMC_WRITE(host->base, CAPA,
 722                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 723
 724         OMAP_HSMMC_WRITE(host->base, HCTL,
 725                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 726
 727         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 728         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 729                 && time_before(jiffies, timeout))
 730                 ;
 731
 732         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 733         OMAP_HSMMC_WRITE(host->base, IE, 0);
 734         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 735
 736         /* Do not initialize card-specific things if the power is off */
 737         if (host->power_mode == MMC_POWER_OFF)
 738                 goto out;
 739
 740         omap_hsmmc_set_bus_width(host);
 741
 742         omap_hsmmc_set_clock(host);
 743
 744         omap_hsmmc_set_bus_mode(host);
 745
 746 out:
 747         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 748                 host->context_loss);
 749         return 0;
 750 }
 751
 752 /*
 753  * Save the MMC host context (store the number of power state changes so far).
 754  */
 755 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 756 {
 757         host->con =  OMAP_HSMMC_READ(host->base, CON);
 758         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 759         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 760         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 761 }
 762
 763 #else
 764
 765 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 766 {
 767         return 0;
 768 }
 769
 770 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 771 {
 772 }
 773
 774 #endif
 775
 776 /*
 777  * Send init stream sequence to card
 778  * before sending IDLE command
 779  */
 780 static void send_init_stream(struct omap_hsmmc_host *host)
 781 {
 782         int reg = 0;
 783         unsigned long timeout;
 784
 785         if (host->protect_card)
 786                 return;
 787
 788         disable_irq(host->irq);
 789
 790         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 791         OMAP_HSMMC_WRITE(host->base, CON,
 792                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 793         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 794
 795         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 796         while ((reg != CC_EN) && time_before(jiffies, timeout))
 797                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 798
 799         OMAP_HSMMC_WRITE(host->base, CON,
 800                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 801
 802         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 803         OMAP_HSMMC_READ(host->base, STAT);
 804
 805         enable_irq(host->irq);
 806 }
 807
 808 static inline
 809 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 810 {
 811         int r = 1;
 812
 813         if (host->get_cover_state)
 814                 r = host->get_cover_state(host->dev);
 815         return r;
 816 }
 817
 818 static ssize_t
 819 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 820                            char *buf)
 821 {
 822         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 823         struct omap_hsmmc_host *host = mmc_priv(mmc);
 824
 825         return sprintf(buf, "%s\n",
 826                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 827 }
 828
 829 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 830
 831 static ssize_t
 832 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 833                         char *buf)
 834 {
 835         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 836         struct omap_hsmmc_host *host = mmc_priv(mmc);
 837
 838         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
 839 }
 840
 841 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 842
 843 /*
 844  * Configure the response type and send the cmd.
 845  */
 846 static void
 847 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 848         struct mmc_data *data)
 849 {
 850         int cmdreg = 0, resptype = 0, cmdtype = 0;
 851
 852         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 853                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 854         host->cmd = cmd;
 855
 856         omap_hsmmc_enable_irq(host, cmd);
 857
 858         host->response_busy = 0;
 859         if (cmd->flags & MMC_RSP_PRESENT) {
 860                 if (cmd->flags & MMC_RSP_136)
 861                         resptype = 1;
 862                 else if (cmd->flags & MMC_RSP_BUSY) {
 863                         resptype = 3;
 864                         host->response_busy = 1;
 865                 } else
 866                         resptype = 2;
 867         }
 868
 869         /*
 870          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 871          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 872          * a val of 0x3, rest 0x0.
 873          */
 874         if (cmd == host->mrq->stop)
 875                 cmdtype = 0x3;
 876
 877         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 878
 879         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 880             host->mrq->sbc) {
 881                 cmdreg |= ACEN_ACMD23;
 882                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
 883         }
 884         if (data) {
 885                 cmdreg |= DP_SELECT | MSBS | BCE;
 886                 if (data->flags & MMC_DATA_READ)
 887                         cmdreg |= DDIR;
 888                 else
 889                         cmdreg &= ~(DDIR);
 890         }
 891
 892         if (host->use_dma)
 893                 cmdreg |= DMAE;
 894
 895         host->req_in_progress = 1;
 896
 897         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 898         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 899 }
 900
 901 static int
 902 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 903 {
 904         if (data->flags & MMC_DATA_WRITE)
 905                 return DMA_TO_DEVICE;
 906         else
 907                 return DMA_FROM_DEVICE;
 908 }
 909
 910 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 911         struct mmc_data *data)
 912 {
 913         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 914 }
 915
 916 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 917 {
 918         int dma_ch;
 919         unsigned long flags;
 920
 921         spin_lock_irqsave(&host->irq_lock, flags);
 922         host->req_in_progress = 0;
 923         dma_ch = host->dma_ch;
 924         spin_unlock_irqrestore(&host->irq_lock, flags);
 925
 926         omap_hsmmc_disable_irq(host);
 927         /* Do not complete the request if DMA is still in progress */
 928         if (mrq->data && host->use_dma && dma_ch != -1)
 929                 return;
 930         host->mrq = NULL;
 931         mmc_request_done(host->mmc, mrq);
 932 }
 933
 934 /*
 935  * Notify the transfer complete to MMC core
 936  */
 937 static void
 938 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 939 {
 940         if (!data) {
 941                 struct mmc_request *mrq = host->mrq;
 942
 943                 /* TC before CC from CMD6 - don't know why, but it happens */
 944                 if (host->cmd && host->cmd->opcode == 6 &&
 945                     host->response_busy) {
 946                         host->response_busy = 0;
 947                         return;
 948                 }
 949
 950                 omap_hsmmc_request_done(host, mrq);
 951                 return;
 952         }
 953
 954         host->data = NULL;
 955
 956         if (!data->error)
 957                 data->bytes_xfered += data->blocks * (data->blksz);
 958         else
 959                 data->bytes_xfered = 0;
 960
 961         if (data->stop && (data->error || !host->mrq->sbc))
 962                 omap_hsmmc_start_command(host, data->stop, NULL);
 963         else
 964                 omap_hsmmc_request_done(host, data->mrq);
 965 }
 966
 967 /*
 968  * Notify the core about command completion
 969  */
 970 static void
 971 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 972 {
 973         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
 974             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
 975                 host->cmd = NULL;
 976                 omap_hsmmc_start_dma_transfer(host);
 977                 omap_hsmmc_start_command(host, host->mrq->cmd,
 978                                                 host->mrq->data);
 979                 return;
 980         }
 981
 982         host->cmd = NULL;
 983
 984         if (cmd->flags & MMC_RSP_PRESENT) {
 985                 if (cmd->flags & MMC_RSP_136) {
 986                         /* response type 2 */
 987                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 988                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 989                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 990                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 991                 } else {
 992                         /* response types 1, 1b, 3, 4, 5, 6 */
 993                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 994                 }
 995         }
 996         if ((host->data == NULL && !host->response_busy) || cmd->error)
 997                 omap_hsmmc_request_done(host, host->mrq);
 998 }
 999
1000 /*
1001  * DMA clean up for command errors
1002  */
1003 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1004 {
1005         int dma_ch;
1006         unsigned long flags;
1007
1008         host->data->error = errno;
1009
1010         spin_lock_irqsave(&host->irq_lock, flags);
1011         dma_ch = host->dma_ch;
1012         host->dma_ch = -1;
1013         spin_unlock_irqrestore(&host->irq_lock, flags);
1014
1015         if (host->use_dma && dma_ch != -1) {
1016                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1017
1018                 dmaengine_terminate_all(chan);
1019                 dma_unmap_sg(chan->device->dev,
1020                         host->data->sg, host->data->sg_len,
1021                         omap_hsmmc_get_dma_dir(host, host->data));
1022
1023                 host->data->host_cookie = 0;
1024         }
1025         host->data = NULL;
1026 }
1027
1028 /*
1029  * Readable error output
1030  */
1031 #ifdef CONFIG_MMC_DEBUG
1032 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1033 {
1034         /* --- means reserved bit without definition at documentation */
1035         static const char *omap_hsmmc_status_bits[] = {
1036                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1037                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1038                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1039                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1040         };
1041         char res[256];
1042         char *buf = res;
1043         int len, i;
1044
1045         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1046         buf += len;
1047
1048         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1049                 if (status & (1 << i)) {
1050                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1051                         buf += len;
1052                 }
1053
1054         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1055 }
1056 #else
1057 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1058                                              u32 status)
1059 {
1060 }
1061 #endif  /* CONFIG_MMC_DEBUG */
1062
1063 /*
1064  * MMC controller internal state machines reset
1065  *
1066  * Used to reset command or data internal state machines, using respectively
1067  *  SRC or SRD bit of SYSCTL register
1068  * Can be called from interrupt context
1069  */
1070 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1071                                                    unsigned long bit)
1072 {
1073         unsigned long i = 0;
1074         unsigned long limit = MMC_TIMEOUT_US;
1075
1076         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1077                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1078
1079         /*
1080          * OMAP4 ES2 and greater has an updated reset logic.
1081          * Monitor a 0->1 transition first
1082          */
1083         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1084                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1085                                         && (i++ < limit))
1086                         udelay(1);
1087         }
1088         i = 0;
1089
1090         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1091                 (i++ < limit))
1092                 udelay(1);
1093
1094         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1095                 dev_err(mmc_dev(host->mmc),
1096                         "Timeout waiting on controller reset in %s\n",
1097                         __func__);
1098 }
1099
1100 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1101                                         int err, int end_cmd)
1102 {
1103         if (end_cmd) {
1104                 omap_hsmmc_reset_controller_fsm(host, SRC);
1105                 if (host->cmd)
1106                         host->cmd->error = err;
1107         }
1108
1109         if (host->data) {
1110                 omap_hsmmc_reset_controller_fsm(host, SRD);
1111                 omap_hsmmc_dma_cleanup(host, err);
1112         } else if (host->mrq && host->mrq->cmd)
1113                 host->mrq->cmd->error = err;
1114 }
1115
1116 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1117 {
1118         struct mmc_data *data;
1119         int end_cmd = 0, end_trans = 0;
1120         int error = 0;
1121
1122         data = host->data;
1123         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1124
1125         if (status & ERR_EN) {
1126                 omap_hsmmc_dbg_report_irq(host, status);
1127
1128                 if (status & (CTO_EN | CCRC_EN))
1129                         end_cmd = 1;
1130                 if (status & (CTO_EN | DTO_EN))
1131                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1132                 else if (status & (CCRC_EN | DCRC_EN))
1133                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1134
1135                 if (status & ACE_EN) {
1136                         u32 ac12;
1137                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1138                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1139                                 end_cmd = 1;
1140                                 if (ac12 & ACTO)
1141                                         error =  -ETIMEDOUT;
1142                                 else if (ac12 & (ACCE | ACEB | ACIE))
1143                                         error = -EILSEQ;
1144                                 host->mrq->sbc->error = error;
1145                                 hsmmc_command_incomplete(host, error, end_cmd);
1146                         }
1147                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1148                 }
1149                 if (host->data || host->response_busy) {
1150                         end_trans = !end_cmd;
1151                         host->response_busy = 0;
1152                 }
1153         }
1154
1155         OMAP_HSMMC_WRITE(host->base, STAT, status);
1156         if (end_cmd || ((status & CC_EN) && host->cmd))
1157                 omap_hsmmc_cmd_done(host, host->cmd);
1158         if ((end_trans || (status & TC_EN)) && host->mrq)
1159                 omap_hsmmc_xfer_done(host, data);
1160 }
1161
1162 /*
1163  * MMC controller IRQ handler
1164  */
1165 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1166 {
1167         struct omap_hsmmc_host *host = dev_id;
1168         int status;
1169
1170         status = OMAP_HSMMC_READ(host->base, STAT);
1171         while (status & (INT_EN_MASK | CIRQ_EN)) {
1172                 if (host->req_in_progress)
1173                         omap_hsmmc_do_irq(host, status);
1174
1175                 if (status & CIRQ_EN)
1176                         mmc_signal_sdio_irq(host->mmc);
1177
1178                 /* Flush posted write */
1179                 status = OMAP_HSMMC_READ(host->base, STAT);
1180         }
1181
1182         return IRQ_HANDLED;
1183 }
1184
1185 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1186 {
1187         struct omap_hsmmc_host *host = dev_id;
1188
1189         /* cirq is level triggered, disable to avoid infinite loop */
1190         spin_lock(&host->irq_lock);
1191         if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1192                 disable_irq_nosync(host->wake_irq);
1193                 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1194         }
1195         spin_unlock(&host->irq_lock);
1196         pm_request_resume(host->dev); /* no use counter */
1197
1198         return IRQ_HANDLED;
1199 }
1200
1201 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1202 {
1203         unsigned long i;
1204
1205         OMAP_HSMMC_WRITE(host->base, HCTL,
1206                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1207         for (i = 0; i < loops_per_jiffy; i++) {
1208                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1209                         break;
1210                 cpu_relax();
1211         }
1212 }
1213
1214 /*
1215  * Switch MMC interface voltage ... only relevant for MMC1.
1216  *
1217  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1218  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1219  * Some chips, like eMMC ones, use internal transceivers.
1220  */
1221 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1222 {
1223         u32 reg_val = 0;
1224         int ret;
1225
1226         /* Disable the clocks */
1227         pm_runtime_put_sync(host->dev);
1228         if (host->dbclk)
1229                 clk_disable_unprepare(host->dbclk);
1230
1231         /* Turn the power off */
1232         ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1233
1234         /* Turn the power ON with given VDD 1.8 or 3.0v */
1235         if (!ret)
1236                 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1237         pm_runtime_get_sync(host->dev);
1238         if (host->dbclk)
1239                 clk_prepare_enable(host->dbclk);
1240
1241         if (ret != 0)
1242                 goto err;
1243
1244         OMAP_HSMMC_WRITE(host->base, HCTL,
1245                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1246         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1247
1248         /*
1249          * If a MMC dual voltage card is detected, the set_ios fn calls
1250          * this fn with VDD bit set for 1.8V. Upon card removal from the
1251          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1252          *
1253          * Cope with a bit of slop in the range ... per data sheets:
1254          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1255          *    but recommended values are 1.71V to 1.89V
1256          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1257          *    but recommended values are 2.7V to 3.3V
1258          *
1259          * Board setup code shouldn't permit anything very out-of-range.
1260          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1261          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1262          */
1263         if ((1 << vdd) <= MMC_VDD_23_24)
1264                 reg_val |= SDVS18;
1265         else
1266                 reg_val |= SDVS30;
1267
1268         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1269         set_sd_bus_power(host);
1270
1271         return 0;
1272 err:
1273         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1274         return ret;
1275 }
1276
1277 /* Protect the card while the cover is open */
1278 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1279 {
1280         if (!host->get_cover_state)
1281                 return;
1282
1283         host->reqs_blocked = 0;
1284         if (host->get_cover_state(host->dev)) {
1285                 if (host->protect_card) {
1286                         dev_info(host->dev, "%s: cover is closed, "
1287                                          "card is now accessible\n",
1288                                          mmc_hostname(host->mmc));
1289                         host->protect_card = 0;
1290                 }
1291         } else {
1292                 if (!host->protect_card) {
1293                         dev_info(host->dev, "%s: cover is open, "
1294                                          "card is now inaccessible\n",
1295                                          mmc_hostname(host->mmc));
1296                         host->protect_card = 1;
1297                 }
1298         }
1299 }
1300
1301 /*
1302  * irq handler to notify the core about card insertion/removal
1303  */
1304 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1305 {
1306         struct omap_hsmmc_host *host = dev_id;
1307         int carddetect;
1308
1309         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1310
1311         if (host->card_detect)
1312                 carddetect = host->card_detect(host->dev);
1313         else {
1314                 omap_hsmmc_protect_card(host);
1315                 carddetect = -ENOSYS;
1316         }
1317
1318         if (carddetect)
1319                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1320         else
1321                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1322         return IRQ_HANDLED;
1323 }
1324
1325 static void omap_hsmmc_dma_callback(void *param)
1326 {
1327         struct omap_hsmmc_host *host = param;
1328         struct dma_chan *chan;
1329         struct mmc_data *data;
1330         int req_in_progress;
1331
1332         spin_lock_irq(&host->irq_lock);
1333         if (host->dma_ch < 0) {
1334                 spin_unlock_irq(&host->irq_lock);
1335                 return;
1336         }
1337
1338         data = host->mrq->data;
1339         chan = omap_hsmmc_get_dma_chan(host, data);
1340         if (!data->host_cookie)
1341                 dma_unmap_sg(chan->device->dev,
1342                              data->sg, data->sg_len,
1343                              omap_hsmmc_get_dma_dir(host, data));
1344
1345         req_in_progress = host->req_in_progress;
1346         host->dma_ch = -1;
1347         spin_unlock_irq(&host->irq_lock);
1348
1349         /* If DMA has finished after TC, complete the request */
1350         if (!req_in_progress) {
1351                 struct mmc_request *mrq = host->mrq;
1352
1353                 host->mrq = NULL;
1354                 mmc_request_done(host->mmc, mrq);
1355         }
1356 }
1357
1358 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1359                                        struct mmc_data *data,
1360                                        struct omap_hsmmc_next *next,
1361                                        struct dma_chan *chan)
1362 {
1363         int dma_len;
1364
1365         if (!next && data->host_cookie &&
1366             data->host_cookie != host->next_data.cookie) {
1367                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1368                        " host->next_data.cookie %d\n",
1369                        __func__, data->host_cookie, host->next_data.cookie);
1370                 data->host_cookie = 0;
1371         }
1372
1373         /* Check if next job is already prepared */
1374         if (next || data->host_cookie != host->next_data.cookie) {
1375                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1376                                      omap_hsmmc_get_dma_dir(host, data));
1377
1378         } else {
1379                 dma_len = host->next_data.dma_len;
1380                 host->next_data.dma_len = 0;
1381         }
1382
1383
1384         if (dma_len == 0)
1385                 return -EINVAL;
1386
1387         if (next) {
1388                 next->dma_len = dma_len;
1389                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1390         } else
1391                 host->dma_len = dma_len;
1392
1393         return 0;
1394 }
1395
1396 /*
1397  * Routine to configure and start DMA for the MMC card
1398  */
1399 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1400                                         struct mmc_request *req)
1401 {
1402         struct dma_slave_config cfg;
1403         struct dma_async_tx_descriptor *tx;
1404         int ret = 0, i;
1405         struct mmc_data *data = req->data;
1406         struct dma_chan *chan;
1407
1408         /* Sanity check: all the SG entries must be aligned by block size. */
1409         for (i = 0; i < data->sg_len; i++) {
1410                 struct scatterlist *sgl;
1411
1412                 sgl = data->sg + i;
1413                 if (sgl->length % data->blksz)
1414                         return -EINVAL;
1415         }
1416         if ((data->blksz % 4) != 0)
1417                 /* REVISIT: The MMC buffer increments only when MSB is written.
1418                  * Return error for blksz which is non multiple of four.
1419                  */
1420                 return -EINVAL;
1421
1422         BUG_ON(host->dma_ch != -1);
1423
1424         chan = omap_hsmmc_get_dma_chan(host, data);
1425
1426         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1427         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1428         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1429         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1430         cfg.src_maxburst = data->blksz / 4;
1431         cfg.dst_maxburst = data->blksz / 4;
1432
1433         ret = dmaengine_slave_config(chan, &cfg);
1434         if (ret)
1435                 return ret;
1436
1437         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1438         if (ret)
1439                 return ret;
1440
1441         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1442                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1443                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1444         if (!tx) {
1445                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1446                 /* FIXME: cleanup */
1447                 return -1;
1448         }
1449
1450         tx->callback = omap_hsmmc_dma_callback;
1451         tx->callback_param = host;
1452
1453         /* Does not fail */
1454         dmaengine_submit(tx);
1455
1456         host->dma_ch = 1;
1457
1458         return 0;
1459 }
1460
1461 static void set_data_timeout(struct omap_hsmmc_host *host,
1462                              unsigned int timeout_ns,
1463                              unsigned int timeout_clks)
1464 {
1465         unsigned int timeout, cycle_ns;
1466         uint32_t reg, clkd, dto = 0;
1467
1468         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1469         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1470         if (clkd == 0)
1471                 clkd = 1;
1472
1473         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1474         timeout = timeout_ns / cycle_ns;
1475         timeout += timeout_clks;
1476         if (timeout) {
1477                 while ((timeout & 0x80000000) == 0) {
1478                         dto += 1;
1479                         timeout <<= 1;
1480                 }
1481                 dto = 31 - dto;
1482                 timeout <<= 1;
1483                 if (timeout && dto)
1484                         dto += 1;
1485                 if (dto >= 13)
1486                         dto -= 13;
1487                 else
1488                         dto = 0;
1489                 if (dto > 14)
1490                         dto = 14;
1491         }
1492
1493         reg &= ~DTO_MASK;
1494         reg |= dto << DTO_SHIFT;
1495         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1496 }
1497
1498 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1499 {
1500         struct mmc_request *req = host->mrq;
1501         struct dma_chan *chan;
1502
1503         if (!req->data)
1504                 return;
1505         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1506                                 | (req->data->blocks << 16));
1507         set_data_timeout(host, req->data->timeout_ns,
1508                                 req->data->timeout_clks);
1509         chan = omap_hsmmc_get_dma_chan(host, req->data);
1510         dma_async_issue_pending(chan);
1511 }
1512
1513 /*
1514  * Configure block length for MMC/SD cards and initiate the transfer.
1515  */
1516 static int
1517 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1518 {
1519         int ret;
1520         host->data = req->data;
1521
1522         if (req->data == NULL) {
1523                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1524                 /*
1525                  * Set an arbitrary 100ms data timeout for commands with
1526                  * busy signal.
1527                  */
1528                 if (req->cmd->flags & MMC_RSP_BUSY)
1529                         set_data_timeout(host, 100000000U, 0);
1530                 return 0;
1531         }
1532
1533         if (host->use_dma) {
1534                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1535                 if (ret != 0) {
1536                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1537                         return ret;
1538                 }
1539         }
1540         return 0;
1541 }
1542
1543 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1544                                 int err)
1545 {
1546         struct omap_hsmmc_host *host = mmc_priv(mmc);
1547         struct mmc_data *data = mrq->data;
1548
1549         if (host->use_dma && data->host_cookie) {
1550                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1551
1552                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1553                              omap_hsmmc_get_dma_dir(host, data));
1554                 data->host_cookie = 0;
1555         }
1556 }
1557
1558 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1559                                bool is_first_req)
1560 {
1561         struct omap_hsmmc_host *host = mmc_priv(mmc);
1562
1563         if (mrq->data->host_cookie) {
1564                 mrq->data->host_cookie = 0;
1565                 return ;
1566         }
1567
1568         if (host->use_dma) {
1569                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1570
1571                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1572                                                 &host->next_data, c))
1573                         mrq->data->host_cookie = 0;
1574         }
1575 }
1576
1577 /*
1578  * Request function. for read/write operation
1579  */
1580 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1581 {
1582         struct omap_hsmmc_host *host = mmc_priv(mmc);
1583         int err;
1584
1585         BUG_ON(host->req_in_progress);
1586         BUG_ON(host->dma_ch != -1);
1587         if (host->protect_card) {
1588                 if (host->reqs_blocked < 3) {
1589                         /*
1590                          * Ensure the controller is left in a consistent
1591                          * state by resetting the command and data state
1592                          * machines.
1593                          */
1594                         omap_hsmmc_reset_controller_fsm(host, SRD);
1595                         omap_hsmmc_reset_controller_fsm(host, SRC);
1596                         host->reqs_blocked += 1;
1597                 }
1598                 req->cmd->error = -EBADF;
1599                 if (req->data)
1600                         req->data->error = -EBADF;
1601                 req->cmd->retries = 0;
1602                 mmc_request_done(mmc, req);
1603                 return;
1604         } else if (host->reqs_blocked)
1605                 host->reqs_blocked = 0;
1606         WARN_ON(host->mrq != NULL);
1607         host->mrq = req;
1608         host->clk_rate = clk_get_rate(host->fclk);
1609         err = omap_hsmmc_prepare_data(host, req);
1610         if (err) {
1611                 req->cmd->error = err;
1612                 if (req->data)
1613                         req->data->error = err;
1614                 host->mrq = NULL;
1615                 mmc_request_done(mmc, req);
1616                 return;
1617         }
1618         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1619                 omap_hsmmc_start_command(host, req->sbc, NULL);
1620                 return;
1621         }
1622
1623         omap_hsmmc_start_dma_transfer(host);
1624         omap_hsmmc_start_command(host, req->cmd, req->data);
1625 }
1626
1627 /* Routine to configure clock values. Exposed API to core */
1628 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1629 {
1630         struct omap_hsmmc_host *host = mmc_priv(mmc);
1631         int do_send_init_stream = 0;
1632
1633         pm_runtime_get_sync(host->dev);
1634
1635         if (ios->power_mode != host->power_mode) {
1636                 switch (ios->power_mode) {
1637                 case MMC_POWER_OFF:
1638                         mmc_pdata(host)->set_power(host->dev, 0, 0);
1639                         break;
1640                 case MMC_POWER_UP:
1641                         mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1642                         break;
1643                 case MMC_POWER_ON:
1644                         do_send_init_stream = 1;
1645                         break;
1646                 }
1647                 host->power_mode = ios->power_mode;
1648         }
1649
1650         /* FIXME: set registers based only on changes to ios */
1651
1652         omap_hsmmc_set_bus_width(host);
1653
1654         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1655                 /* Only MMC1 can interface at 3V without some flavor
1656                  * of external transceiver; but they all handle 1.8V.
1657                  */
1658                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1659                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1660                                 /*
1661                                  * The mmc_select_voltage fn of the core does
1662                                  * not seem to set the power_mode to
1663                                  * MMC_POWER_UP upon recalculating the voltage.
1664                                  * vdd 1.8v.
1665                                  */
1666                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1667                                 dev_dbg(mmc_dev(host->mmc),
1668                                                 "Switch operation failed\n");
1669                 }
1670         }
1671
1672         omap_hsmmc_set_clock(host);
1673
1674         if (do_send_init_stream)
1675                 send_init_stream(host);
1676
1677         omap_hsmmc_set_bus_mode(host);
1678
1679         pm_runtime_put_autosuspend(host->dev);
1680 }
1681
1682 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1683 {
1684         struct omap_hsmmc_host *host = mmc_priv(mmc);
1685
1686         if (!host->card_detect)
1687                 return -ENOSYS;
1688         return host->card_detect(host->dev);
1689 }
1690
1691 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1692 {
1693         struct omap_hsmmc_host *host = mmc_priv(mmc);
1694
1695         if (!host->get_ro)
1696                 return -ENOSYS;
1697         return host->get_ro(host->dev);
1698 }
1699
1700 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1701 {
1702         struct omap_hsmmc_host *host = mmc_priv(mmc);
1703
1704         if (mmc_pdata(host)->init_card)
1705                 mmc_pdata(host)->init_card(card);
1706 }
1707
1708 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1709 {
1710         struct omap_hsmmc_host *host = mmc_priv(mmc);
1711         u32 irq_mask, con;
1712         unsigned long flags;
1713
1714         spin_lock_irqsave(&host->irq_lock, flags);
1715
1716         con = OMAP_HSMMC_READ(host->base, CON);
1717         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1718         if (enable) {
1719                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1720                 irq_mask |= CIRQ_EN;
1721                 con |= CTPL | CLKEXTFREE;
1722         } else {
1723                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1724                 irq_mask &= ~CIRQ_EN;
1725                 con &= ~(CTPL | CLKEXTFREE);
1726         }
1727         OMAP_HSMMC_WRITE(host->base, CON, con);
1728         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1729
1730         /*
1731          * if enable, piggy back detection on current request
1732          * but always disable immediately
1733          */
1734         if (!host->req_in_progress || !enable)
1735                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1736
1737         /* flush posted write */
1738         OMAP_HSMMC_READ(host->base, IE);
1739
1740         spin_unlock_irqrestore(&host->irq_lock, flags);
1741 }
1742
1743 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1744 {
1745         struct mmc_host *mmc = host->mmc;
1746         int ret;
1747
1748         /*
1749          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1750          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1751          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1752          * with functional clock disabled.
1753          */
1754         if (!host->dev->of_node || !host->wake_irq)
1755                 return -ENODEV;
1756
1757         /* Prevent auto-enabling of IRQ */
1758         irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1759         ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1760                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1761                                mmc_hostname(mmc), host);
1762         if (ret) {
1763                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1764                 goto err;
1765         }
1766
1767         /*
1768          * Some omaps don't have wake-up path from deeper idle states
1769          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1770          */
1771         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1772                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1773                 if (!p) {
1774                         ret = -ENODEV;
1775                         goto err_free_irq;
1776                 }
1777                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1778                         dev_info(host->dev, "missing default pinctrl state\n");
1779                         devm_pinctrl_put(p);
1780                         ret = -EINVAL;
1781                         goto err_free_irq;
1782                 }
1783
1784                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1785                         dev_info(host->dev, "missing idle pinctrl state\n");
1786                         devm_pinctrl_put(p);
1787                         ret = -EINVAL;
1788                         goto err_free_irq;
1789                 }
1790                 devm_pinctrl_put(p);
1791         }
1792
1793         OMAP_HSMMC_WRITE(host->base, HCTL,
1794                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1795         return 0;
1796
1797 err_free_irq:
1798         devm_free_irq(host->dev, host->wake_irq, host);
1799 err:
1800         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1801         host->wake_irq = 0;
1802         return ret;
1803 }
1804
1805 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1806 {
1807         u32 hctl, capa, value;
1808
1809         /* Only MMC1 supports 3.0V */
1810         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1811                 hctl = SDVS30;
1812                 capa = VS30 | VS18;
1813         } else {
1814                 hctl = SDVS18;
1815                 capa = VS18;
1816         }
1817
1818         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1819         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1820
1821         value = OMAP_HSMMC_READ(host->base, CAPA);
1822         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1823
1824         /* Set SD bus power bit */
1825         set_sd_bus_power(host);
1826 }
1827
1828 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1829 {
1830         struct omap_hsmmc_host *host = mmc_priv(mmc);
1831
1832         pm_runtime_get_sync(host->dev);
1833
1834         return 0;
1835 }
1836
1837 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1838 {
1839         struct omap_hsmmc_host *host = mmc_priv(mmc);
1840
1841         pm_runtime_mark_last_busy(host->dev);
1842         pm_runtime_put_autosuspend(host->dev);
1843
1844         return 0;
1845 }
1846
1847 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1848                                      unsigned int direction, int blk_size)
1849 {
1850         /* This controller can't do multiblock reads due to hw bugs */
1851         if (direction == MMC_DATA_READ)
1852                 return 1;
1853
1854         return blk_size;
1855 }
1856
1857 static struct mmc_host_ops omap_hsmmc_ops = {
1858         .enable = omap_hsmmc_enable_fclk,
1859         .disable = omap_hsmmc_disable_fclk,
1860         .post_req = omap_hsmmc_post_req,
1861         .pre_req = omap_hsmmc_pre_req,
1862         .request = omap_hsmmc_request,
1863         .set_ios = omap_hsmmc_set_ios,
1864         .get_cd = omap_hsmmc_get_cd,
1865         .get_ro = omap_hsmmc_get_ro,
1866         .init_card = omap_hsmmc_init_card,
1867         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1868 };
1869
1870 #ifdef CONFIG_DEBUG_FS
1871
1872 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1873 {
1874         struct mmc_host *mmc = s->private;
1875         struct omap_hsmmc_host *host = mmc_priv(mmc);
1876
1877         seq_printf(s, "mmc%d:\n", mmc->index);
1878         seq_printf(s, "sdio irq mode\t%s\n",
1879                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1880
1881         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1882                 seq_printf(s, "sdio irq \t%s\n",
1883                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1884                            : "disabled");
1885         }
1886         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1887
1888         pm_runtime_get_sync(host->dev);
1889         seq_puts(s, "\nregs:\n");
1890         seq_printf(s, "CON:\t\t0x%08x\n",
1891                         OMAP_HSMMC_READ(host->base, CON));
1892         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1893                    OMAP_HSMMC_READ(host->base, PSTATE));
1894         seq_printf(s, "HCTL:\t\t0x%08x\n",
1895                         OMAP_HSMMC_READ(host->base, HCTL));
1896         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1897                         OMAP_HSMMC_READ(host->base, SYSCTL));
1898         seq_printf(s, "IE:\t\t0x%08x\n",
1899                         OMAP_HSMMC_READ(host->base, IE));
1900         seq_printf(s, "ISE:\t\t0x%08x\n",
1901                         OMAP_HSMMC_READ(host->base, ISE));
1902         seq_printf(s, "CAPA:\t\t0x%08x\n",
1903                         OMAP_HSMMC_READ(host->base, CAPA));
1904
1905         pm_runtime_mark_last_busy(host->dev);
1906         pm_runtime_put_autosuspend(host->dev);
1907
1908         return 0;
1909 }
1910
1911 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1912 {
1913         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1914 }
1915
1916 static const struct file_operations mmc_regs_fops = {
1917         .open           = omap_hsmmc_regs_open,
1918         .read           = seq_read,
1919         .llseek         = seq_lseek,
1920         .release        = single_release,
1921 };
1922
1923 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1924 {
1925         if (mmc->debugfs_root)
1926                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1927                         mmc, &mmc_regs_fops);
1928 }
1929
1930 #else
1931
1932 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1933 {
1934 }
1935
1936 #endif
1937
1938 #ifdef CONFIG_OF
1939 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1940         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1941         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1942 };
1943
1944 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1945         .reg_offset = 0x100,
1946 };
1947 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1948         .reg_offset = 0x100,
1949         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1950 };
1951
1952 static const struct of_device_id omap_mmc_of_match[] = {
1953         {
1954                 .compatible = "ti,omap2-hsmmc",
1955         },
1956         {
1957                 .compatible = "ti,omap3-pre-es3-hsmmc",
1958                 .data = &omap3_pre_es3_mmc_of_data,
1959         },
1960         {
1961                 .compatible = "ti,omap3-hsmmc",
1962         },
1963         {
1964                 .compatible = "ti,omap4-hsmmc",
1965                 .data = &omap4_mmc_of_data,
1966         },
1967         {
1968                 .compatible = "ti,am33xx-hsmmc",
1969                 .data = &am33xx_mmc_of_data,
1970         },
1971         {},
1972 };
1973 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1974
1975 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1976 {
1977         struct omap_hsmmc_platform_data *pdata;
1978         struct device_node *np = dev->of_node;
1979         u32 bus_width, max_freq;
1980         int cd_gpio, wp_gpio;
1981
1982         cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1983         wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1984         if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1985                 return ERR_PTR(-EPROBE_DEFER);
1986
1987         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1988         if (!pdata)
1989                 return ERR_PTR(-ENOMEM); /* out of memory */
1990
1991         if (of_find_property(np, "ti,dual-volt", NULL))
1992                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1993
1994         pdata->switch_pin = cd_gpio;
1995         pdata->gpio_wp = wp_gpio;
1996
1997         if (of_find_property(np, "ti,non-removable", NULL)) {
1998                 pdata->nonremovable = true;
1999                 pdata->no_regulator_off_init = true;
2000         }
2001         of_property_read_u32(np, "bus-width", &bus_width);
2002         if (bus_width == 4)
2003                 pdata->caps |= MMC_CAP_4_BIT_DATA;
2004         else if (bus_width == 8)
2005                 pdata->caps |= MMC_CAP_8_BIT_DATA;
2006
2007         if (of_find_property(np, "ti,needs-special-reset", NULL))
2008                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
2009
2010         if (!of_property_read_u32(np, "max-frequency", &max_freq))
2011                 pdata->max_freq = max_freq;
2012
2013         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
2014                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
2015
2016         if (of_find_property(np, "keep-power-in-suspend", NULL))
2017                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2018
2019         if (of_find_property(np, "enable-sdio-wakeup", NULL))
2020                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2021
2022         return pdata;
2023 }
2024 #else
2025 static inline struct omap_hsmmc_platform_data
2026                         *of_get_hsmmc_pdata(struct device *dev)
2027 {
2028         return ERR_PTR(-EINVAL);
2029 }
2030 #endif
2031
2032 static int omap_hsmmc_probe(struct platform_device *pdev)
2033 {
2034         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
2035         struct mmc_host *mmc;
2036         struct omap_hsmmc_host *host = NULL;
2037         struct resource *res;
2038         int ret, irq;
2039         const struct of_device_id *match;
2040         dma_cap_mask_t mask;
2041         unsigned tx_req, rx_req;
2042         const struct omap_mmc_of_data *data;
2043         void __iomem *base;
2044
2045         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2046         if (match) {
2047                 pdata = of_get_hsmmc_pdata(&pdev->dev);
2048
2049                 if (IS_ERR(pdata))
2050                         return PTR_ERR(pdata);
2051
2052                 if (match->data) {
2053                         data = match->data;
2054                         pdata->reg_offset = data->reg_offset;
2055                         pdata->controller_flags |= data->controller_flags;
2056                 }
2057         }
2058
2059         if (pdata == NULL) {
2060                 dev_err(&pdev->dev, "Platform Data is missing\n");
2061                 return -ENXIO;
2062         }
2063
2064         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2065         irq = platform_get_irq(pdev, 0);
2066         if (res == NULL || irq < 0)
2067                 return -ENXIO;
2068
2069         base = devm_ioremap_resource(&pdev->dev, res);
2070         if (IS_ERR(base))
2071                 return PTR_ERR(base);
2072
2073         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2074         if (!mmc) {
2075                 ret = -ENOMEM;
2076                 goto err;
2077         }
2078
2079         host            = mmc_priv(mmc);
2080         host->mmc       = mmc;
2081         host->pdata     = pdata;
2082         host->dev       = &pdev->dev;
2083         host->use_dma   = 1;
2084         host->dma_ch    = -1;
2085         host->irq       = irq;
2086         host->mapbase   = res->start + pdata->reg_offset;
2087         host->base      = base + pdata->reg_offset;
2088         host->power_mode = MMC_POWER_OFF;
2089         host->next_data.cookie = 1;
2090         host->pbias_enabled = 0;
2091
2092         ret = omap_hsmmc_gpio_init(host, pdata);
2093         if (ret)
2094                 goto err_gpio;
2095
2096         platform_set_drvdata(pdev, host);
2097
2098         if (pdev->dev.of_node)
2099                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2100
2101         mmc->ops        = &omap_hsmmc_ops;
2102
2103         mmc->f_min = OMAP_MMC_MIN_CLOCK;
2104
2105         if (pdata->max_freq > 0)
2106                 mmc->f_max = pdata->max_freq;
2107         else
2108                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2109
2110         spin_lock_init(&host->irq_lock);
2111
2112         host->fclk = devm_clk_get(&pdev->dev, "fck");
2113         if (IS_ERR(host->fclk)) {
2114                 ret = PTR_ERR(host->fclk);
2115                 host->fclk = NULL;
2116                 goto err1;
2117         }
2118
2119         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2120                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2121                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2122         }
2123
2124         pm_runtime_enable(host->dev);
2125         pm_runtime_get_sync(host->dev);
2126         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2127         pm_runtime_use_autosuspend(host->dev);
2128
2129         omap_hsmmc_context_save(host);
2130
2131         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2132         /*
2133          * MMC can still work without debounce clock.
2134          */
2135         if (IS_ERR(host->dbclk)) {
2136                 host->dbclk = NULL;
2137         } else if (clk_prepare_enable(host->dbclk) != 0) {
2138                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2139                 host->dbclk = NULL;
2140         }
2141
2142         /* Since we do only SG emulation, we can have as many segs
2143          * as we want. */
2144         mmc->max_segs = 1024;
2145
2146         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2147         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2148         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2149         mmc->max_seg_size = mmc->max_req_size;
2150
2151         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2152                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2153
2154         mmc->caps |= mmc_pdata(host)->caps;
2155         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2156                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2157
2158         if (mmc_pdata(host)->nonremovable)
2159                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2160
2161         mmc->pm_caps = mmc_pdata(host)->pm_caps;
2162
2163         omap_hsmmc_conf_bus_power(host);
2164
2165         if (!pdev->dev.of_node) {
2166                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2167                 if (!res) {
2168                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2169                         ret = -ENXIO;
2170                         goto err_irq;
2171                 }
2172                 tx_req = res->start;
2173
2174                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2175                 if (!res) {
2176                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2177                         ret = -ENXIO;
2178                         goto err_irq;
2179                 }
2180                 rx_req = res->start;
2181         }
2182
2183         dma_cap_zero(mask);
2184         dma_cap_set(DMA_SLAVE, mask);
2185
2186         host->rx_chan =
2187                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2188                                                  &rx_req, &pdev->dev, "rx");
2189
2190         if (!host->rx_chan) {
2191                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2192                 ret = -ENXIO;
2193                 goto err_irq;
2194         }
2195
2196         host->tx_chan =
2197                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2198                                                  &tx_req, &pdev->dev, "tx");
2199
2200         if (!host->tx_chan) {
2201                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2202                 ret = -ENXIO;
2203                 goto err_irq;
2204         }
2205
2206         /* Request IRQ for MMC operations */
2207         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2208                         mmc_hostname(mmc), host);
2209         if (ret) {
2210                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2211                 goto err_irq;
2212         }
2213
2214         if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2215                 ret = omap_hsmmc_reg_get(host);
2216                 if (ret)
2217                         goto err_irq;
2218                 host->use_reg = 1;
2219         }
2220
2221         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2222
2223         /* Request IRQ for card detect */
2224         if (host->card_detect_irq) {
2225                 ret = devm_request_threaded_irq(&pdev->dev,
2226                                                 host->card_detect_irq,
2227                                                 NULL, omap_hsmmc_detect,
2228                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2229                                            mmc_hostname(mmc), host);
2230                 if (ret) {
2231                         dev_err(mmc_dev(host->mmc),
2232                                 "Unable to grab MMC CD IRQ\n");
2233                         goto err_irq_cd;
2234                 }
2235                 host->suspend = omap_hsmmc_suspend_cdirq;
2236                 host->resume = omap_hsmmc_resume_cdirq;
2237         }
2238
2239         omap_hsmmc_disable_irq(host);
2240
2241         /*
2242          * For now, only support SDIO interrupt if we have a separate
2243          * wake-up interrupt configured from device tree. This is because
2244          * the wake-up interrupt is needed for idle state and some
2245          * platforms need special quirks. And we don't want to add new
2246          * legacy mux platform init code callbacks any longer as we
2247          * are moving to DT based booting anyways.
2248          */
2249         ret = omap_hsmmc_configure_wake_irq(host);
2250         if (!ret)
2251                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2252
2253         omap_hsmmc_protect_card(host);
2254
2255         mmc_add_host(mmc);
2256
2257         if (mmc_pdata(host)->name != NULL) {
2258                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2259                 if (ret < 0)
2260                         goto err_slot_name;
2261         }
2262         if (host->card_detect_irq && host->get_cover_state) {
2263                 ret = device_create_file(&mmc->class_dev,
2264                                         &dev_attr_cover_switch);
2265                 if (ret < 0)
2266                         goto err_slot_name;
2267         }
2268
2269         omap_hsmmc_debugfs(mmc);
2270         pm_runtime_mark_last_busy(host->dev);
2271         pm_runtime_put_autosuspend(host->dev);
2272
2273         return 0;
2274
2275 err_slot_name:
2276         mmc_remove_host(mmc);
2277 err_irq_cd:
2278         if (host->use_reg)
2279                 omap_hsmmc_reg_put(host);
2280 err_irq:
2281         if (host->tx_chan)
2282                 dma_release_channel(host->tx_chan);
2283         if (host->rx_chan)
2284                 dma_release_channel(host->rx_chan);
2285         pm_runtime_put_sync(host->dev);
2286         pm_runtime_disable(host->dev);
2287         if (host->dbclk)
2288                 clk_disable_unprepare(host->dbclk);
2289 err1:
2290         omap_hsmmc_gpio_free(host, pdata);
2291 err_gpio:
2292         mmc_free_host(mmc);
2293 err:
2294         return ret;
2295 }
2296
2297 static int omap_hsmmc_remove(struct platform_device *pdev)
2298 {
2299         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2300
2301         pm_runtime_get_sync(host->dev);
2302         mmc_remove_host(host->mmc);
2303         if (host->use_reg)
2304                 omap_hsmmc_reg_put(host);
2305
2306         if (host->tx_chan)
2307                 dma_release_channel(host->tx_chan);
2308         if (host->rx_chan)
2309                 dma_release_channel(host->rx_chan);
2310
2311         pm_runtime_put_sync(host->dev);
2312         pm_runtime_disable(host->dev);
2313         if (host->dbclk)
2314                 clk_disable_unprepare(host->dbclk);
2315
2316         omap_hsmmc_gpio_free(host, host->pdata);
2317         mmc_free_host(host->mmc);
2318
2319         return 0;
2320 }
2321
2322 #ifdef CONFIG_PM
2323 static int omap_hsmmc_prepare(struct device *dev)
2324 {
2325         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2326
2327         if (host->suspend)
2328                 return host->suspend(dev);
2329
2330         return 0;
2331 }
2332
2333 static void omap_hsmmc_complete(struct device *dev)
2334 {
2335         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2336
2337         if (host->resume)
2338                 host->resume(dev);
2339
2340 }
2341
2342 static int omap_hsmmc_suspend(struct device *dev)
2343 {
2344         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2345
2346         if (!host)
2347                 return 0;
2348
2349         pm_runtime_get_sync(host->dev);
2350
2351         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2352                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2353                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2354                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2355                 OMAP_HSMMC_WRITE(host->base, HCTL,
2356                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2357         }
2358
2359         /* do not wake up due to sdio irq */
2360         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2361             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2362                 disable_irq(host->wake_irq);
2363
2364         if (host->dbclk)
2365                 clk_disable_unprepare(host->dbclk);
2366
2367         pm_runtime_put_sync(host->dev);
2368         return 0;
2369 }
2370
2371 /* Routine to resume the MMC device */
2372 static int omap_hsmmc_resume(struct device *dev)
2373 {
2374         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2375
2376         if (!host)
2377                 return 0;
2378
2379         pm_runtime_get_sync(host->dev);
2380
2381         if (host->dbclk)
2382                 clk_prepare_enable(host->dbclk);
2383
2384         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2385                 omap_hsmmc_conf_bus_power(host);
2386
2387         omap_hsmmc_protect_card(host);
2388
2389         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2390             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2391                 enable_irq(host->wake_irq);
2392
2393         pm_runtime_mark_last_busy(host->dev);
2394         pm_runtime_put_autosuspend(host->dev);
2395         return 0;
2396 }
2397
2398 #else
2399 #define omap_hsmmc_prepare      NULL
2400 #define omap_hsmmc_complete     NULL
2401 #define omap_hsmmc_suspend      NULL
2402 #define omap_hsmmc_resume       NULL
2403 #endif
2404
2405 static int omap_hsmmc_runtime_suspend(struct device *dev)
2406 {
2407         struct omap_hsmmc_host *host;
2408         unsigned long flags;
2409         int ret = 0;
2410
2411         host = platform_get_drvdata(to_platform_device(dev));
2412         omap_hsmmc_context_save(host);
2413         dev_dbg(dev, "disabled\n");
2414
2415         spin_lock_irqsave(&host->irq_lock, flags);
2416         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2417             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2418                 /* disable sdio irq handling to prevent race */
2419                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2420                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2421
2422                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2423                         /*
2424                          * dat1 line low, pending sdio irq
2425                          * race condition: possible irq handler running on
2426                          * multi-core, abort
2427                          */
2428                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2429                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2430                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2431                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2432                         pm_runtime_mark_last_busy(dev);
2433                         ret = -EBUSY;
2434                         goto abort;
2435                 }
2436
2437                 pinctrl_pm_select_idle_state(dev);
2438
2439                 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2440                 enable_irq(host->wake_irq);
2441                 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2442         } else {
2443                 pinctrl_pm_select_idle_state(dev);
2444         }
2445
2446 abort:
2447         spin_unlock_irqrestore(&host->irq_lock, flags);
2448         return ret;
2449 }
2450
2451 static int omap_hsmmc_runtime_resume(struct device *dev)
2452 {
2453         struct omap_hsmmc_host *host;
2454         unsigned long flags;
2455
2456         host = platform_get_drvdata(to_platform_device(dev));
2457         omap_hsmmc_context_restore(host);
2458         dev_dbg(dev, "enabled\n");
2459
2460         spin_lock_irqsave(&host->irq_lock, flags);
2461         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2462             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2463                 /* sdio irq flag can't change while in runtime suspend */
2464                 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2465                         disable_irq_nosync(host->wake_irq);
2466                         host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2467                 }
2468
2469                 pinctrl_pm_select_default_state(host->dev);
2470
2471                 /* irq lost, if pinmux incorrect */
2472                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2473                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2474                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2475         } else {
2476                 pinctrl_pm_select_default_state(host->dev);
2477         }
2478         spin_unlock_irqrestore(&host->irq_lock, flags);
2479         return 0;
2480 }
2481
2482 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2483         .suspend        = omap_hsmmc_suspend,
2484         .resume         = omap_hsmmc_resume,
2485         .prepare        = omap_hsmmc_prepare,
2486         .complete       = omap_hsmmc_complete,
2487         .runtime_suspend = omap_hsmmc_runtime_suspend,
2488         .runtime_resume = omap_hsmmc_runtime_resume,
2489 };
2490
2491 static struct platform_driver omap_hsmmc_driver = {
2492         .probe          = omap_hsmmc_probe,
2493         .remove         = omap_hsmmc_remove,
2494         .driver         = {
2495                 .name = DRIVER_NAME,
2496                 .pm = &omap_hsmmc_dev_pm_ops,
2497                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2498         },
2499 };
2500
2501 module_platform_driver(omap_hsmmc_driver);
2502 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2503 MODULE_LICENSE("GPL");
2504 MODULE_ALIAS("platform:" DRIVER_NAME);
2505 MODULE_AUTHOR("Texas Instruments Inc");