drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/of.h>
  30 #include <linux/of_gpio.h>
  31 #include <linux/of_device.h>
  32 #include <linux/mmc/host.h>
  33 #include <linux/mmc/core.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/io.h>
  36 #include <linux/semaphore.h>
  37 #include <linux/gpio.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/pm_runtime.h>
  40 #include <plat/dma.h>
  41 #include <mach/hardware.h>
  42 #include <plat/board.h>
  43 #include <plat/mmc.h>
  44 #include <plat/cpu.h>
  45
  46 /* OMAP HSMMC Host Controller Registers */
  47 #define OMAP_HSMMC_SYSCONFIG    0x0010
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_BLK          0x0104
  51 #define OMAP_HSMMC_ARG          0x0108
  52 #define OMAP_HSMMC_CMD          0x010C
  53 #define OMAP_HSMMC_RSP10        0x0110
  54 #define OMAP_HSMMC_RSP32        0x0114
  55 #define OMAP_HSMMC_RSP54        0x0118
  56 #define OMAP_HSMMC_RSP76        0x011C
  57 #define OMAP_HSMMC_DATA         0x0120
  58 #define OMAP_HSMMC_HCTL         0x0128
  59 #define OMAP_HSMMC_SYSCTL       0x012C
  60 #define OMAP_HSMMC_STAT         0x0130
  61 #define OMAP_HSMMC_IE           0x0134
  62 #define OMAP_HSMMC_ISE          0x0138
  63 #define OMAP_HSMMC_CAPA         0x0140
  64
  65 #define VS18                    (1 << 26)
  66 #define VS30                    (1 << 25)
  67 #define SDVS18                  (0x5 << 9)
  68 #define SDVS30                  (0x6 << 9)
  69 #define SDVS33                  (0x7 << 9)
  70 #define SDVS_MASK               0x00000E00
  71 #define SDVSCLR                 0xFFFFF1FF
  72 #define SDVSDET                 0x00000400
  73 #define AUTOIDLE                0x1
  74 #define SDBP                    (1 << 8)
  75 #define DTO                     0xe
  76 #define ICE                     0x1
  77 #define ICS                     0x2
  78 #define CEN                     (1 << 2)
  79 #define CLKD_MASK               0x0000FFC0
  80 #define CLKD_SHIFT              6
  81 #define DTO_MASK                0x000F0000
  82 #define DTO_SHIFT               16
  83 #define INT_EN_MASK             0x307F0033
  84 #define BWR_ENABLE              (1 << 4)
  85 #define BRR_ENABLE              (1 << 5)
  86 #define DTO_ENABLE              (1 << 20)
  87 #define INIT_STREAM             (1 << 1)
  88 #define ACEN_ACMD12             (1 << 2)
  89 #define DP_SELECT               (1 << 21)
  90 #define DDIR                    (1 << 4)
  91 #define DMA_EN                  0x1
  92 #define MSBS                    (1 << 5)
  93 #define BCE                     (1 << 1)
  94 #define FOUR_BIT                (1 << 1)
  95 #define DDR                     (1 << 19)
  96 #define DW8                     (1 << 5)
  97 #define CC                      0x1
  98 #define TC                      0x02
  99 #define OD                      0x1
 100 #define ERR                     (1 << 15)
 101 #define CMD_TIMEOUT             (1 << 16)
 102 #define DATA_TIMEOUT            (1 << 20)
 103 #define CMD_CRC                 (1 << 17)
 104 #define DATA_CRC                (1 << 21)
 105 #define CARD_ERR                (1 << 28)
 106 #define STAT_CLEAR              0xFFFFFFFF
 107 #define INIT_STREAM_CMD         0x00000000
 108 #define DUAL_VOLT_OCR_BIT       7
 109 #define SRC                     (1 << 25)
 110 #define SRD                     (1 << 26)
 111 #define SOFTRESET               (1 << 1)
 112 #define RESETDONE               (1 << 0)
 113
 114 #define MMC_AUTOSUSPEND_DELAY   100
 115 #define MMC_TIMEOUT_MS          20
 116 #define OMAP_MMC_MIN_CLOCK      400000
 117 #define OMAP_MMC_MAX_CLOCK      52000000
 118 #define DRIVER_NAME             "omap_hsmmc"
 119
 120 #define AUTO_CMD12              (1 << 0)        /* Auto CMD12 support */
 121 /*
 122  * One controller can have multiple slots, like on some omap boards using
 123  * omap.c controller driver. Luckily this is not currently done on any known
 124  * omap_hsmmc.c device.
 125  */
 126 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 127
 128 /*
 129  * MMC Host controller read/write API's
 130  */
 131 #define OMAP_HSMMC_READ(base, reg)      \
 132         __raw_readl((base) + OMAP_HSMMC_##reg)
 133
 134 #define OMAP_HSMMC_WRITE(base, reg, val) \
 135         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 136
 137 struct omap_hsmmc_next {
 138         unsigned int    dma_len;
 139         s32             cookie;
 140 };
 141
 142 struct omap_hsmmc_host {
 143         struct  device          *dev;
 144         struct  mmc_host        *mmc;
 145         struct  mmc_request     *mrq;
 146         struct  mmc_command     *cmd;
 147         struct  mmc_data        *data;
 148         struct  clk             *fclk;
 149         struct  clk             *dbclk;
 150         /*
 151          * vcc == configured supply
 152          * vcc_aux == optional
 153          *   -  MMC1, supply for DAT4..DAT7
 154          *   -  MMC2/MMC2, external level shifter voltage supply, for
 155          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 156          */
 157         struct  regulator       *vcc;
 158         struct  regulator       *vcc_aux;
 159         void    __iomem         *base;
 160         resource_size_t         mapbase;
 161         spinlock_t              irq_lock; /* Prevent races with irq handler */
 162         unsigned int            dma_len;
 163         unsigned int            dma_sg_idx;
 164         unsigned char           bus_mode;
 165         unsigned char           power_mode;
 166         u32                     *buffer;
 167         u32                     bytesleft;
 168         int                     suspended;
 169         int                     irq;
 170         int                     use_dma, dma_ch;
 171         int                     dma_line_tx, dma_line_rx;
 172         int                     slot_id;
 173         int                     response_busy;
 174         int                     context_loss;
 175         int                     vdd;
 176         int                     protect_card;
 177         int                     reqs_blocked;
 178         int                     use_reg;
 179         int                     req_in_progress;
 180         unsigned int            flags;
 181         struct omap_hsmmc_next  next_data;
 182
 183         struct  omap_mmc_platform_data  *pdata;
 184 };
 185
 186 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 187 {
 188         struct omap_mmc_platform_data *mmc = dev->platform_data;
 189
 190         /* NOTE: assumes card detect signal is active-low */
 191         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 192 }
 193
 194 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 195 {
 196         struct omap_mmc_platform_data *mmc = dev->platform_data;
 197
 198         /* NOTE: assumes write protect signal is active-high */
 199         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 200 }
 201
 202 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 203 {
 204         struct omap_mmc_platform_data *mmc = dev->platform_data;
 205
 206         /* NOTE: assumes card detect signal is active-low */
 207         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 208 }
 209
 210 #ifdef CONFIG_PM
 211
 212 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 213 {
 214         struct omap_mmc_platform_data *mmc = dev->platform_data;
 215
 216         disable_irq(mmc->slots[0].card_detect_irq);
 217         return 0;
 218 }
 219
 220 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 221 {
 222         struct omap_mmc_platform_data *mmc = dev->platform_data;
 223
 224         enable_irq(mmc->slots[0].card_detect_irq);
 225         return 0;
 226 }
 227
 228 #else
 229
 230 #define omap_hsmmc_suspend_cdirq        NULL
 231 #define omap_hsmmc_resume_cdirq         NULL
 232
 233 #endif
 234
 235 #ifdef CONFIG_REGULATOR
 236
 237 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 238                                    int vdd)
 239 {
 240         struct omap_hsmmc_host *host =
 241                 platform_get_drvdata(to_platform_device(dev));
 242         int ret = 0;
 243
 244         /*
 245          * If we don't see a Vcc regulator, assume it's a fixed
 246          * voltage always-on regulator.
 247          */
 248         if (!host->vcc)
 249                 return 0;
 250         /*
 251          * With DT, never turn OFF the regulator. This is because
 252          * the pbias cell programming support is still missing when
 253          * booting with Device tree
 254          */
 255         if (dev->of_node && !vdd)
 256                 return 0;
 257
 258         if (mmc_slot(host).before_set_reg)
 259                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 260
 261         /*
 262          * Assume Vcc regulator is used only to power the card ... OMAP
 263          * VDDS is used to power the pins, optionally with a transceiver to
 264          * support cards using voltages other than VDDS (1.8V nominal).  When a
 265          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 266          *
 267          * In some cases this regulator won't support enable/disable;
 268          * e.g. it's a fixed rail for a WLAN chip.
 269          *
 270          * In other cases vcc_aux switches interface power.  Example, for
 271          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 272          * chips/cards need an interface voltage rail too.
 273          */
 274         if (power_on) {
 275                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 276                 /* Enable interface voltage rail, if needed */
 277                 if (ret == 0 && host->vcc_aux) {
 278                         ret = regulator_enable(host->vcc_aux);
 279                         if (ret < 0)
 280                                 ret = mmc_regulator_set_ocr(host->mmc,
 281                                                         host->vcc, 0);
 282                 }
 283         } else {
 284                 /* Shut down the rail */
 285                 if (host->vcc_aux)
 286                         ret = regulator_disable(host->vcc_aux);
 287                 if (!ret) {
 288                         /* Then proceed to shut down the local regulator */
 289                         ret = mmc_regulator_set_ocr(host->mmc,
 290                                                 host->vcc, 0);
 291                 }
 292         }
 293
 294         if (mmc_slot(host).after_set_reg)
 295                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 296
 297         return ret;
 298 }
 299
 300 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 301 {
 302         struct regulator *reg;
 303         int ocr_value = 0;
 304
 305         mmc_slot(host).set_power = omap_hsmmc_set_power;
 306
 307         reg = regulator_get(host->dev, "vmmc");
 308         if (IS_ERR(reg)) {
 309                 dev_dbg(host->dev, "vmmc regulator missing\n");
 310         } else {
 311                 host->vcc = reg;
 312                 ocr_value = mmc_regulator_get_ocrmask(reg);
 313                 if (!mmc_slot(host).ocr_mask) {
 314                         mmc_slot(host).ocr_mask = ocr_value;
 315                 } else {
 316                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 317                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 318                                         mmc_slot(host).ocr_mask);
 319                                 mmc_slot(host).ocr_mask = 0;
 320                                 return -EINVAL;
 321                         }
 322                 }
 323
 324                 /* Allow an aux regulator */
 325                 reg = regulator_get(host->dev, "vmmc_aux");
 326                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 327
 328                 /* For eMMC do not power off when not in sleep state */
 329                 if (mmc_slot(host).no_regulator_off_init)
 330                         return 0;
 331                 /*
 332                 * UGLY HACK:  workaround regulator framework bugs.
 333                 * When the bootloader leaves a supply active, it's
 334                 * initialized with zero usecount ... and we can't
 335                 * disable it without first enabling it.  Until the
 336                 * framework is fixed, we need a workaround like this
 337                 * (which is safe for MMC, but not in general).
 338                 */
 339                 if (regulator_is_enabled(host->vcc) > 0 ||
 340                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 341                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 342
 343                         mmc_slot(host).set_power(host->dev, host->slot_id,
 344                                                  1, vdd);
 345                         mmc_slot(host).set_power(host->dev, host->slot_id,
 346                                                  0, 0);
 347                 }
 348         }
 349
 350         return 0;
 351 }
 352
 353 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 354 {
 355         regulator_put(host->vcc);
 356         regulator_put(host->vcc_aux);
 357         mmc_slot(host).set_power = NULL;
 358 }
 359
 360 static inline int omap_hsmmc_have_reg(void)
 361 {
 362         return 1;
 363 }
 364
 365 #else
 366
 367 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 368 {
 369         return -EINVAL;
 370 }
 371
 372 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 373 {
 374 }
 375
 376 static inline int omap_hsmmc_have_reg(void)
 377 {
 378         return 0;
 379 }
 380
 381 #endif
 382
 383 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 384 {
 385         int ret;
 386
 387         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 388                 if (pdata->slots[0].cover)
 389                         pdata->slots[0].get_cover_state =
 390                                         omap_hsmmc_get_cover_state;
 391                 else
 392                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 393                 pdata->slots[0].card_detect_irq =
 394                                 gpio_to_irq(pdata->slots[0].switch_pin);
 395                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 396                 if (ret)
 397                         return ret;
 398                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 399                 if (ret)
 400                         goto err_free_sp;
 401         } else
 402                 pdata->slots[0].switch_pin = -EINVAL;
 403
 404         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 405                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 406                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 407                 if (ret)
 408                         goto err_free_cd;
 409                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 410                 if (ret)
 411                         goto err_free_wp;
 412         } else
 413                 pdata->slots[0].gpio_wp = -EINVAL;
 414
 415         return 0;
 416
 417 err_free_wp:
 418         gpio_free(pdata->slots[0].gpio_wp);
 419 err_free_cd:
 420         if (gpio_is_valid(pdata->slots[0].switch_pin))
 421 err_free_sp:
 422                 gpio_free(pdata->slots[0].switch_pin);
 423         return ret;
 424 }
 425
 426 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 427 {
 428         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 429                 gpio_free(pdata->slots[0].gpio_wp);
 430         if (gpio_is_valid(pdata->slots[0].switch_pin))
 431                 gpio_free(pdata->slots[0].switch_pin);
 432 }
 433
 434 /*
 435  * Start clock to the card
 436  */
 437 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 438 {
 439         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 440                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 441 }
 442
 443 /*
 444  * Stop clock to the card
 445  */
 446 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 447 {
 448         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 449                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 450         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 451                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 452 }
 453
 454 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 455                                   struct mmc_command *cmd)
 456 {
 457         unsigned int irq_mask;
 458
 459         if (host->use_dma)
 460                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 461         else
 462                 irq_mask = INT_EN_MASK;
 463
 464         /* Disable timeout for erases */
 465         if (cmd->opcode == MMC_ERASE)
 466                 irq_mask &= ~DTO_ENABLE;
 467
 468         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 469         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 470         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 471 }
 472
 473 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 474 {
 475         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 476         OMAP_HSMMC_WRITE(host->base, IE, 0);
 477         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 478 }
 479
 480 /* Calculate divisor for the given clock frequency */
 481 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 482 {
 483         u16 dsor = 0;
 484
 485         if (ios->clock) {
 486                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 487                 if (dsor > 250)
 488                         dsor = 250;
 489         }
 490
 491         return dsor;
 492 }
 493
 494 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 495 {
 496         struct mmc_ios *ios = &host->mmc->ios;
 497         unsigned long regval;
 498         unsigned long timeout;
 499
 500         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 501
 502         omap_hsmmc_stop_clock(host);
 503
 504         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 505         regval = regval & ~(CLKD_MASK | DTO_MASK);
 506         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 507         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 508         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 509                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 510
 511         /* Wait till the ICS bit is set */
 512         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 513         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 514                 && time_before(jiffies, timeout))
 515                 cpu_relax();
 516
 517         omap_hsmmc_start_clock(host);
 518 }
 519
 520 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 521 {
 522         struct mmc_ios *ios = &host->mmc->ios;
 523         u32 con;
 524
 525         con = OMAP_HSMMC_READ(host->base, CON);
 526         if (ios->timing == MMC_TIMING_UHS_DDR50)
 527                 con |= DDR;     /* configure in DDR mode */
 528         else
 529                 con &= ~DDR;
 530         switch (ios->bus_width) {
 531         case MMC_BUS_WIDTH_8:
 532                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 533                 break;
 534         case MMC_BUS_WIDTH_4:
 535                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 536                 OMAP_HSMMC_WRITE(host->base, HCTL,
 537                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 538                 break;
 539         case MMC_BUS_WIDTH_1:
 540                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 541                 OMAP_HSMMC_WRITE(host->base, HCTL,
 542                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 543                 break;
 544         }
 545 }
 546
 547 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 548 {
 549         struct mmc_ios *ios = &host->mmc->ios;
 550         u32 con;
 551
 552         con = OMAP_HSMMC_READ(host->base, CON);
 553         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 554                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 555         else
 556                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 557 }
 558
 559 #ifdef CONFIG_PM
 560
 561 /*
 562  * Restore the MMC host context, if it was lost as result of a
 563  * power state change.
 564  */
 565 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 566 {
 567         struct mmc_ios *ios = &host->mmc->ios;
 568         struct omap_mmc_platform_data *pdata = host->pdata;
 569         int context_loss = 0;
 570         u32 hctl, capa;
 571         unsigned long timeout;
 572
 573         if (pdata->get_context_loss_count) {
 574                 context_loss = pdata->get_context_loss_count(host->dev);
 575                 if (context_loss < 0)
 576                         return 1;
 577         }
 578
 579         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 580                 context_loss == host->context_loss ? "not " : "");
 581         if (host->context_loss == context_loss)
 582                 return 1;
 583
 584         /* Wait for hardware reset */
 585         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 586         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 587                 && time_before(jiffies, timeout))
 588                 ;
 589
 590         /* Do software reset */
 591         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 592         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 593         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 594                 && time_before(jiffies, timeout))
 595                 ;
 596
 597         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 598                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 599
 600         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 601                 if (host->power_mode != MMC_POWER_OFF &&
 602                     (1 << ios->vdd) <= MMC_VDD_23_24)
 603                         hctl = SDVS18;
 604                 else
 605                         hctl = SDVS30;
 606                 capa = VS30 | VS18;
 607         } else {
 608                 hctl = SDVS18;
 609                 capa = VS18;
 610         }
 611
 612         OMAP_HSMMC_WRITE(host->base, HCTL,
 613                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 614
 615         OMAP_HSMMC_WRITE(host->base, CAPA,
 616                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 617
 618         OMAP_HSMMC_WRITE(host->base, HCTL,
 619                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 620
 621         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 622         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 623                 && time_before(jiffies, timeout))
 624                 ;
 625
 626         omap_hsmmc_disable_irq(host);
 627
 628         /* Do not initialize card-specific things if the power is off */
 629         if (host->power_mode == MMC_POWER_OFF)
 630                 goto out;
 631
 632         omap_hsmmc_set_bus_width(host);
 633
 634         omap_hsmmc_set_clock(host);
 635
 636         omap_hsmmc_set_bus_mode(host);
 637
 638 out:
 639         host->context_loss = context_loss;
 640
 641         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 642         return 0;
 643 }
 644
 645 /*
 646  * Save the MMC host context (store the number of power state changes so far).
 647  */
 648 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 649 {
 650         struct omap_mmc_platform_data *pdata = host->pdata;
 651         int context_loss;
 652
 653         if (pdata->get_context_loss_count) {
 654                 context_loss = pdata->get_context_loss_count(host->dev);
 655                 if (context_loss < 0)
 656                         return;
 657                 host->context_loss = context_loss;
 658         }
 659 }
 660
 661 #else
 662
 663 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 664 {
 665         return 0;
 666 }
 667
 668 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 669 {
 670 }
 671
 672 #endif
 673
 674 /*
 675  * Send init stream sequence to card
 676  * before sending IDLE command
 677  */
 678 static void send_init_stream(struct omap_hsmmc_host *host)
 679 {
 680         int reg = 0;
 681         unsigned long timeout;
 682
 683         if (host->protect_card)
 684                 return;
 685
 686         disable_irq(host->irq);
 687
 688         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 689         OMAP_HSMMC_WRITE(host->base, CON,
 690                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 691         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 692
 693         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 694         while ((reg != CC) && time_before(jiffies, timeout))
 695                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 696
 697         OMAP_HSMMC_WRITE(host->base, CON,
 698                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 699
 700         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 701         OMAP_HSMMC_READ(host->base, STAT);
 702
 703         enable_irq(host->irq);
 704 }
 705
 706 static inline
 707 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 708 {
 709         int r = 1;
 710
 711         if (mmc_slot(host).get_cover_state)
 712                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 713         return r;
 714 }
 715
 716 static ssize_t
 717 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 718                            char *buf)
 719 {
 720         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 721         struct omap_hsmmc_host *host = mmc_priv(mmc);
 722
 723         return sprintf(buf, "%s\n",
 724                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 725 }
 726
 727 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 728
 729 static ssize_t
 730 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 731                         char *buf)
 732 {
 733         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 734         struct omap_hsmmc_host *host = mmc_priv(mmc);
 735
 736         return sprintf(buf, "%s\n", mmc_slot(host).name);
 737 }
 738
 739 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 740
 741 /*
 742  * Configure the response type and send the cmd.
 743  */
 744 static void
 745 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 746         struct mmc_data *data)
 747 {
 748         int cmdreg = 0, resptype = 0, cmdtype = 0;
 749
 750         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 751                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 752         host->cmd = cmd;
 753
 754         omap_hsmmc_enable_irq(host, cmd);
 755
 756         host->response_busy = 0;
 757         if (cmd->flags & MMC_RSP_PRESENT) {
 758                 if (cmd->flags & MMC_RSP_136)
 759                         resptype = 1;
 760                 else if (cmd->flags & MMC_RSP_BUSY) {
 761                         resptype = 3;
 762                         host->response_busy = 1;
 763                 } else
 764                         resptype = 2;
 765         }
 766
 767         /*
 768          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 769          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 770          * a val of 0x3, rest 0x0.
 771          */
 772         if (cmd == host->mrq->stop)
 773                 cmdtype = 0x3;
 774
 775         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 776         if ((host->flags & AUTO_CMD12) && mmc_op_multi(cmd->opcode))
 777                 cmdreg |= ACEN_ACMD12;
 778
 779         if (data) {
 780                 cmdreg |= DP_SELECT | MSBS | BCE;
 781                 if (data->flags & MMC_DATA_READ)
 782                         cmdreg |= DDIR;
 783                 else
 784                         cmdreg &= ~(DDIR);
 785         }
 786
 787         if (host->use_dma)
 788                 cmdreg |= DMA_EN;
 789
 790         host->req_in_progress = 1;
 791
 792         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 793         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 794 }
 795
 796 static int
 797 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 798 {
 799         if (data->flags & MMC_DATA_WRITE)
 800                 return DMA_TO_DEVICE;
 801         else
 802                 return DMA_FROM_DEVICE;
 803 }
 804
 805 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 806 {
 807         int dma_ch;
 808         unsigned long flags;
 809
 810         spin_lock_irqsave(&host->irq_lock, flags);
 811         host->req_in_progress = 0;
 812         dma_ch = host->dma_ch;
 813         spin_unlock_irqrestore(&host->irq_lock, flags);
 814
 815         omap_hsmmc_disable_irq(host);
 816         /* Do not complete the request if DMA is still in progress */
 817         if (mrq->data && host->use_dma && dma_ch != -1)
 818                 return;
 819         host->mrq = NULL;
 820         mmc_request_done(host->mmc, mrq);
 821 }
 822
 823 /*
 824  * Notify the transfer complete to MMC core
 825  */
 826 static void
 827 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 828 {
 829         if (!data) {
 830                 struct mmc_request *mrq = host->mrq;
 831
 832                 /* TC before CC from CMD6 - don't know why, but it happens */
 833                 if (host->cmd && host->cmd->opcode == 6 &&
 834                     host->response_busy) {
 835                         host->response_busy = 0;
 836                         return;
 837                 }
 838
 839                 omap_hsmmc_request_done(host, mrq);
 840                 return;
 841         }
 842
 843         host->data = NULL;
 844
 845         if (!data->error)
 846                 data->bytes_xfered += data->blocks * (data->blksz);
 847         else
 848                 data->bytes_xfered = 0;
 849
 850         if (data->stop && ((!(host->flags & AUTO_CMD12)) || data->error)) {
 851                 omap_hsmmc_start_command(host, data->stop, NULL);
 852         } else {
 853                 if (data->stop)
 854                         data->stop->resp[0] = OMAP_HSMMC_READ(host->base,
 855                                                         RSP76);
 856                 omap_hsmmc_request_done(host, data->mrq);
 857         }
 858 }
 859
 860 /*
 861  * Notify the core about command completion
 862  */
 863 static void
 864 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 865 {
 866         host->cmd = NULL;
 867
 868         if (cmd->flags & MMC_RSP_PRESENT) {
 869                 if (cmd->flags & MMC_RSP_136) {
 870                         /* response type 2 */
 871                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 872                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 873                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 874                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 875                 } else {
 876                         /* response types 1, 1b, 3, 4, 5, 6 */
 877                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 878                 }
 879         }
 880         if ((host->data == NULL && !host->response_busy) || cmd->error)
 881                 omap_hsmmc_request_done(host, cmd->mrq);
 882 }
 883
 884 /*
 885  * DMA clean up for command errors
 886  */
 887 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 888 {
 889         int dma_ch;
 890         unsigned long flags;
 891
 892         host->data->error = errno;
 893
 894         spin_lock_irqsave(&host->irq_lock, flags);
 895         dma_ch = host->dma_ch;
 896         host->dma_ch = -1;
 897         spin_unlock_irqrestore(&host->irq_lock, flags);
 898
 899         if (host->use_dma && dma_ch != -1) {
 900                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 901                         host->data->sg_len,
 902                         omap_hsmmc_get_dma_dir(host, host->data));
 903                 omap_free_dma(dma_ch);
 904                 host->data->host_cookie = 0;
 905         }
 906         host->data = NULL;
 907 }
 908
 909 /*
 910  * Readable error output
 911  */
 912 #ifdef CONFIG_MMC_DEBUG
 913 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 914 {
 915         /* --- means reserved bit without definition at documentation */
 916         static const char *omap_hsmmc_status_bits[] = {
 917                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 918                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 919                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 920                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 921         };
 922         char res[256];
 923         char *buf = res;
 924         int len, i;
 925
 926         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 927         buf += len;
 928
 929         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 930                 if (status & (1 << i)) {
 931                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 932                         buf += len;
 933                 }
 934
 935         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 936 }
 937 #else
 938 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 939                                              u32 status)
 940 {
 941 }
 942 #endif  /* CONFIG_MMC_DEBUG */
 943
 944 /*
 945  * MMC controller internal state machines reset
 946  *
 947  * Used to reset command or data internal state machines, using respectively
 948  *  SRC or SRD bit of SYSCTL register
 949  * Can be called from interrupt context
 950  */
 951 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 952                                                    unsigned long bit)
 953 {
 954         unsigned long i = 0;
 955         unsigned long limit = (loops_per_jiffy *
 956                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 957
 958         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 959                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 960
 961         /*
 962          * OMAP4 ES2 and greater has an updated reset logic.
 963          * Monitor a 0->1 transition first
 964          */
 965         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 966                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 967                                         && (i++ < limit))
 968                         cpu_relax();
 969         }
 970         i = 0;
 971
 972         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 973                 (i++ < limit))
 974                 cpu_relax();
 975
 976         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 977                 dev_err(mmc_dev(host->mmc),
 978                         "Timeout waiting on controller reset in %s\n",
 979                         __func__);
 980 }
 981
 982 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 983 {
 984         struct mmc_data *data;
 985         int end_cmd = 0, end_trans = 0;
 986
 987         if (!host->req_in_progress) {
 988                 do {
 989                         OMAP_HSMMC_WRITE(host->base, STAT, status);
 990                         /* Flush posted write */
 991                         status = OMAP_HSMMC_READ(host->base, STAT);
 992                 } while (status & INT_EN_MASK);
 993                 return;
 994         }
 995
 996         data = host->data;
 997         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 998
 999         if (status & ERR) {
1000                 omap_hsmmc_dbg_report_irq(host, status);
1001                 if ((status & CMD_TIMEOUT) ||
1002                         (status & CMD_CRC)) {
1003                         if (host->cmd) {
1004                                 if (status & CMD_TIMEOUT) {
1005                                         omap_hsmmc_reset_controller_fsm(host,
1006                                                                         SRC);
1007                                         host->cmd->error = -ETIMEDOUT;
1008                                 } else {
1009                                         host->cmd->error = -EILSEQ;
1010                                 }
1011                                 end_cmd = 1;
1012                         }
1013                         if (host->data || host->response_busy) {
1014                                 if (host->data)
1015                                         omap_hsmmc_dma_cleanup(host,
1016                                                                 -ETIMEDOUT);
1017                                 host->response_busy = 0;
1018                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1019                         }
1020                 }
1021                 if ((status & DATA_TIMEOUT) ||
1022                         (status & DATA_CRC)) {
1023                         if (host->data || host->response_busy) {
1024                                 int err = (status & DATA_TIMEOUT) ?
1025                                                 -ETIMEDOUT : -EILSEQ;
1026
1027                                 if (host->data)
1028                                         omap_hsmmc_dma_cleanup(host, err);
1029                                 else
1030                                         host->mrq->cmd->error = err;
1031                                 host->response_busy = 0;
1032                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1033                                 end_trans = 1;
1034                         }
1035                 }
1036                 if (status & CARD_ERR) {
1037                         dev_dbg(mmc_dev(host->mmc),
1038                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1039                         if (host->cmd)
1040                                 end_cmd = 1;
1041                         if (host->data)
1042                                 end_trans = 1;
1043                 }
1044         }
1045
1046         OMAP_HSMMC_WRITE(host->base, STAT, status);
1047
1048         if (end_cmd || ((status & CC) && host->cmd))
1049                 omap_hsmmc_cmd_done(host, host->cmd);
1050         if ((end_trans || (status & TC)) && host->mrq)
1051                 omap_hsmmc_xfer_done(host, data);
1052 }
1053
1054 /*
1055  * MMC controller IRQ handler
1056  */
1057 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1058 {
1059         struct omap_hsmmc_host *host = dev_id;
1060         int status;
1061
1062         status = OMAP_HSMMC_READ(host->base, STAT);
1063         do {
1064                 omap_hsmmc_do_irq(host, status);
1065                 /* Flush posted write */
1066                 status = OMAP_HSMMC_READ(host->base, STAT);
1067         } while (status & INT_EN_MASK);
1068
1069         return IRQ_HANDLED;
1070 }
1071
1072 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1073 {
1074         unsigned long i;
1075
1076         OMAP_HSMMC_WRITE(host->base, HCTL,
1077                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1078         for (i = 0; i < loops_per_jiffy; i++) {
1079                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1080                         break;
1081                 cpu_relax();
1082         }
1083 }
1084
1085 /*
1086  * Switch MMC interface voltage ... only relevant for MMC1.
1087  *
1088  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1089  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1090  * Some chips, like eMMC ones, use internal transceivers.
1091  */
1092 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1093 {
1094         u32 reg_val = 0;
1095         int ret;
1096
1097         /* Disable the clocks */
1098         pm_runtime_put_sync(host->dev);
1099         if (host->dbclk)
1100                 clk_disable(host->dbclk);
1101
1102         /* Turn the power off */
1103         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1104
1105         /* Turn the power ON with given VDD 1.8 or 3.0v */
1106         if (!ret)
1107                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1108                                                vdd);
1109         pm_runtime_get_sync(host->dev);
1110         if (host->dbclk)
1111                 clk_enable(host->dbclk);
1112
1113         if (ret != 0)
1114                 goto err;
1115
1116         OMAP_HSMMC_WRITE(host->base, HCTL,
1117                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1118         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1119
1120         /*
1121          * If a MMC dual voltage card is detected, the set_ios fn calls
1122          * this fn with VDD bit set for 1.8V. Upon card removal from the
1123          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1124          *
1125          * Cope with a bit of slop in the range ... per data sheets:
1126          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1127          *    but recommended values are 1.71V to 1.89V
1128          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1129          *    but recommended values are 2.7V to 3.3V
1130          *
1131          * Board setup code shouldn't permit anything very out-of-range.
1132          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1133          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1134          */
1135         if ((1 << vdd) <= MMC_VDD_23_24)
1136                 reg_val |= SDVS18;
1137         else
1138                 reg_val |= SDVS30;
1139
1140         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1141         set_sd_bus_power(host);
1142
1143         return 0;
1144 err:
1145         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1146         return ret;
1147 }
1148
1149 /* Protect the card while the cover is open */
1150 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1151 {
1152         if (!mmc_slot(host).get_cover_state)
1153                 return;
1154
1155         host->reqs_blocked = 0;
1156         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1157                 if (host->protect_card) {
1158                         dev_info(host->dev, "%s: cover is closed, "
1159                                          "card is now accessible\n",
1160                                          mmc_hostname(host->mmc));
1161                         host->protect_card = 0;
1162                 }
1163         } else {
1164                 if (!host->protect_card) {
1165                         dev_info(host->dev, "%s: cover is open, "
1166                                          "card is now inaccessible\n",
1167                                          mmc_hostname(host->mmc));
1168                         host->protect_card = 1;
1169                 }
1170         }
1171 }
1172
1173 /*
1174  * irq handler to notify the core about card insertion/removal
1175  */
1176 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1177 {
1178         struct omap_hsmmc_host *host = dev_id;
1179         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1180         int carddetect;
1181
1182         if (host->suspended)
1183                 return IRQ_HANDLED;
1184
1185         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1186
1187         if (slot->card_detect)
1188                 carddetect = slot->card_detect(host->dev, host->slot_id);
1189         else {
1190                 omap_hsmmc_protect_card(host);
1191                 carddetect = -ENOSYS;
1192         }
1193
1194         if (carddetect)
1195                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1196         else
1197                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1198         return IRQ_HANDLED;
1199 }
1200
1201 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1202                                      struct mmc_data *data)
1203 {
1204         int sync_dev;
1205
1206         if (data->flags & MMC_DATA_WRITE)
1207                 sync_dev = host->dma_line_tx;
1208         else
1209                 sync_dev = host->dma_line_rx;
1210         return sync_dev;
1211 }
1212
1213 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1214                                        struct mmc_data *data,
1215                                        struct scatterlist *sgl)
1216 {
1217         int blksz, nblk, dma_ch;
1218
1219         dma_ch = host->dma_ch;
1220         if (data->flags & MMC_DATA_WRITE) {
1221                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1222                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1223                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1224                         sg_dma_address(sgl), 0, 0);
1225         } else {
1226                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1227                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1228                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1229                         sg_dma_address(sgl), 0, 0);
1230         }
1231
1232         blksz = host->data->blksz;
1233         nblk = sg_dma_len(sgl) / blksz;
1234
1235         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1236                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1237                         omap_hsmmc_get_dma_sync_dev(host, data),
1238                         !(data->flags & MMC_DATA_WRITE));
1239
1240         omap_start_dma(dma_ch);
1241 }
1242
1243 /*
1244  * DMA call back function
1245  */
1246 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1247 {
1248         struct omap_hsmmc_host *host = cb_data;
1249         struct mmc_data *data;
1250         int dma_ch, req_in_progress;
1251         unsigned long flags;
1252
1253         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1254                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1255                         ch_status);
1256                 return;
1257         }
1258
1259         spin_lock_irqsave(&host->irq_lock, flags);
1260         if (host->dma_ch < 0) {
1261                 spin_unlock_irqrestore(&host->irq_lock, flags);
1262                 return;
1263         }
1264
1265         data = host->mrq->data;
1266         host->dma_sg_idx++;
1267         if (host->dma_sg_idx < host->dma_len) {
1268                 /* Fire up the next transfer. */
1269                 omap_hsmmc_config_dma_params(host, data,
1270                                            data->sg + host->dma_sg_idx);
1271                 spin_unlock_irqrestore(&host->irq_lock, flags);
1272                 return;
1273         }
1274
1275         if (!data->host_cookie)
1276                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1277                              omap_hsmmc_get_dma_dir(host, data));
1278
1279         req_in_progress = host->req_in_progress;
1280         dma_ch = host->dma_ch;
1281         host->dma_ch = -1;
1282         spin_unlock_irqrestore(&host->irq_lock, flags);
1283
1284         omap_free_dma(dma_ch);
1285
1286         /* If DMA has finished after TC, complete the request */
1287         if (!req_in_progress) {
1288                 struct mmc_request *mrq = host->mrq;
1289
1290                 host->mrq = NULL;
1291                 mmc_request_done(host->mmc, mrq);
1292         }
1293 }
1294
1295 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1296                                        struct mmc_data *data,
1297                                        struct omap_hsmmc_next *next)
1298 {
1299         int dma_len;
1300
1301         if (!next && data->host_cookie &&
1302             data->host_cookie != host->next_data.cookie) {
1303                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1304                        " host->next_data.cookie %d\n",
1305                        __func__, data->host_cookie, host->next_data.cookie);
1306                 data->host_cookie = 0;
1307         }
1308
1309         /* Check if next job is already prepared */
1310         if (next ||
1311             (!next && data->host_cookie != host->next_data.cookie)) {
1312                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1313                                      data->sg_len,
1314                                      omap_hsmmc_get_dma_dir(host, data));
1315
1316         } else {
1317                 dma_len = host->next_data.dma_len;
1318                 host->next_data.dma_len = 0;
1319         }
1320
1321
1322         if (dma_len == 0)
1323                 return -EINVAL;
1324
1325         if (next) {
1326                 next->dma_len = dma_len;
1327                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1328         } else
1329                 host->dma_len = dma_len;
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * Routine to configure and start DMA for the MMC card
1336  */
1337 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1338                                         struct mmc_request *req)
1339 {
1340         int dma_ch = 0, ret = 0, i;
1341         struct mmc_data *data = req->data;
1342
1343         /* Sanity check: all the SG entries must be aligned by block size. */
1344         for (i = 0; i < data->sg_len; i++) {
1345                 struct scatterlist *sgl;
1346
1347                 sgl = data->sg + i;
1348                 if (sgl->length % data->blksz)
1349                         return -EINVAL;
1350         }
1351         if ((data->blksz % 4) != 0)
1352                 /* REVISIT: The MMC buffer increments only when MSB is written.
1353                  * Return error for blksz which is non multiple of four.
1354                  */
1355                 return -EINVAL;
1356
1357         BUG_ON(host->dma_ch != -1);
1358
1359         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1360                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1361         if (ret != 0) {
1362                 dev_err(mmc_dev(host->mmc),
1363                         "%s: omap_request_dma() failed with %d\n",
1364                         mmc_hostname(host->mmc), ret);
1365                 return ret;
1366         }
1367         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1368         if (ret)
1369                 return ret;
1370
1371         host->dma_ch = dma_ch;
1372         host->dma_sg_idx = 0;
1373
1374         omap_hsmmc_config_dma_params(host, data, data->sg);
1375
1376         return 0;
1377 }
1378
1379 static void set_data_timeout(struct omap_hsmmc_host *host,
1380                              unsigned int timeout_ns,
1381                              unsigned int timeout_clks)
1382 {
1383         unsigned int timeout, cycle_ns;
1384         uint32_t reg, clkd, dto = 0;
1385
1386         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1387         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1388         if (clkd == 0)
1389                 clkd = 1;
1390
1391         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1392         timeout = timeout_ns / cycle_ns;
1393         timeout += timeout_clks;
1394         if (timeout) {
1395                 while ((timeout & 0x80000000) == 0) {
1396                         dto += 1;
1397                         timeout <<= 1;
1398                 }
1399                 dto = 31 - dto;
1400                 timeout <<= 1;
1401                 if (timeout && dto)
1402                         dto += 1;
1403                 if (dto >= 13)
1404                         dto -= 13;
1405                 else
1406                         dto = 0;
1407                 if (dto > 14)
1408                         dto = 14;
1409         }
1410
1411         reg &= ~DTO_MASK;
1412         reg |= dto << DTO_SHIFT;
1413         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1414 }
1415
1416 /*
1417  * Configure block length for MMC/SD cards and initiate the transfer.
1418  */
1419 static int
1420 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1421 {
1422         int ret;
1423         host->data = req->data;
1424
1425         if (req->data == NULL) {
1426                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1427                 /*
1428                  * Set an arbitrary 100ms data timeout for commands with
1429                  * busy signal.
1430                  */
1431                 if (req->cmd->flags & MMC_RSP_BUSY)
1432                         set_data_timeout(host, 100000000U, 0);
1433                 return 0;
1434         }
1435
1436         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1437                                         | (req->data->blocks << 16));
1438         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1439
1440         if (host->use_dma) {
1441                 ret = omap_hsmmc_start_dma_transfer(host, req);
1442                 if (ret != 0) {
1443                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1444                         return ret;
1445                 }
1446         }
1447         return 0;
1448 }
1449
1450 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1451                                 int err)
1452 {
1453         struct omap_hsmmc_host *host = mmc_priv(mmc);
1454         struct mmc_data *data = mrq->data;
1455
1456         if (host->use_dma) {
1457                 if (data->host_cookie)
1458                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1459                                      data->sg_len,
1460                                      omap_hsmmc_get_dma_dir(host, data));
1461                 data->host_cookie = 0;
1462         }
1463 }
1464
1465 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1466                                bool is_first_req)
1467 {
1468         struct omap_hsmmc_host *host = mmc_priv(mmc);
1469
1470         if (mrq->data->host_cookie) {
1471                 mrq->data->host_cookie = 0;
1472                 return ;
1473         }
1474
1475         if (host->use_dma)
1476                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1477                                                 &host->next_data))
1478                         mrq->data->host_cookie = 0;
1479 }
1480
1481 /*
1482  * Request function. for read/write operation
1483  */
1484 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1485 {
1486         struct omap_hsmmc_host *host = mmc_priv(mmc);
1487         int err;
1488
1489         BUG_ON(host->req_in_progress);
1490         BUG_ON(host->dma_ch != -1);
1491         if (host->protect_card) {
1492                 if (host->reqs_blocked < 3) {
1493                         /*
1494                          * Ensure the controller is left in a consistent
1495                          * state by resetting the command and data state
1496                          * machines.
1497                          */
1498                         omap_hsmmc_reset_controller_fsm(host, SRD);
1499                         omap_hsmmc_reset_controller_fsm(host, SRC);
1500                         host->reqs_blocked += 1;
1501                 }
1502                 req->cmd->error = -EBADF;
1503                 if (req->data)
1504                         req->data->error = -EBADF;
1505                 req->cmd->retries = 0;
1506                 mmc_request_done(mmc, req);
1507                 return;
1508         } else if (host->reqs_blocked)
1509                 host->reqs_blocked = 0;
1510         WARN_ON(host->mrq != NULL);
1511         host->mrq = req;
1512         err = omap_hsmmc_prepare_data(host, req);
1513         if (err) {
1514                 req->cmd->error = err;
1515                 if (req->data)
1516                         req->data->error = err;
1517                 host->mrq = NULL;
1518                 mmc_request_done(mmc, req);
1519                 return;
1520         }
1521
1522         omap_hsmmc_start_command(host, req->cmd, req->data);
1523 }
1524
1525 /* Routine to configure clock values. Exposed API to core */
1526 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1527 {
1528         struct omap_hsmmc_host *host = mmc_priv(mmc);
1529         int do_send_init_stream = 0;
1530
1531         pm_runtime_get_sync(host->dev);
1532
1533         if (ios->power_mode != host->power_mode) {
1534                 switch (ios->power_mode) {
1535                 case MMC_POWER_OFF:
1536                         mmc_slot(host).set_power(host->dev, host->slot_id,
1537                                                  0, 0);
1538                         host->vdd = 0;
1539                         break;
1540                 case MMC_POWER_UP:
1541                         mmc_slot(host).set_power(host->dev, host->slot_id,
1542                                                  1, ios->vdd);
1543                         host->vdd = ios->vdd;
1544                         break;
1545                 case MMC_POWER_ON:
1546                         do_send_init_stream = 1;
1547                         break;
1548                 }
1549                 host->power_mode = ios->power_mode;
1550         }
1551
1552         /* FIXME: set registers based only on changes to ios */
1553
1554         omap_hsmmc_set_bus_width(host);
1555
1556         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1557                 /* Only MMC1 can interface at 3V without some flavor
1558                  * of external transceiver; but they all handle 1.8V.
1559                  */
1560                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1561                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1562                         /*
1563                          * With pbias cell programming missing, this
1564                          * can't be allowed when booting with device
1565                          * tree.
1566                          */
1567                         !host->dev->of_node) {
1568                                 /*
1569                                  * The mmc_select_voltage fn of the core does
1570                                  * not seem to set the power_mode to
1571                                  * MMC_POWER_UP upon recalculating the voltage.
1572                                  * vdd 1.8v.
1573                                  */
1574                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1575                                 dev_dbg(mmc_dev(host->mmc),
1576                                                 "Switch operation failed\n");
1577                 }
1578         }
1579
1580         omap_hsmmc_set_clock(host);
1581
1582         if (do_send_init_stream)
1583                 send_init_stream(host);
1584
1585         omap_hsmmc_set_bus_mode(host);
1586
1587         pm_runtime_put_autosuspend(host->dev);
1588 }
1589
1590 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1591 {
1592         struct omap_hsmmc_host *host = mmc_priv(mmc);
1593
1594         if (!mmc_slot(host).card_detect)
1595                 return -ENOSYS;
1596         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1597 }
1598
1599 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1600 {
1601         struct omap_hsmmc_host *host = mmc_priv(mmc);
1602
1603         if (!mmc_slot(host).get_ro)
1604                 return -ENOSYS;
1605         return mmc_slot(host).get_ro(host->dev, 0);
1606 }
1607
1608 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1609 {
1610         struct omap_hsmmc_host *host = mmc_priv(mmc);
1611
1612         if (mmc_slot(host).init_card)
1613                 mmc_slot(host).init_card(card);
1614 }
1615
1616 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1617 {
1618         u32 hctl, capa, value;
1619
1620         /* Only MMC1 supports 3.0V */
1621         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1622                 hctl = SDVS30;
1623                 capa = VS30 | VS18;
1624         } else {
1625                 hctl = SDVS18;
1626                 capa = VS18;
1627         }
1628
1629         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1630         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1631
1632         value = OMAP_HSMMC_READ(host->base, CAPA);
1633         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1634
1635         /* Set the controller to AUTO IDLE mode */
1636         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1637         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1638
1639         /* Set SD bus power bit */
1640         set_sd_bus_power(host);
1641 }
1642
1643 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1644 {
1645         struct omap_hsmmc_host *host = mmc_priv(mmc);
1646
1647         pm_runtime_get_sync(host->dev);
1648
1649         return 0;
1650 }
1651
1652 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1653 {
1654         struct omap_hsmmc_host *host = mmc_priv(mmc);
1655
1656         pm_runtime_mark_last_busy(host->dev);
1657         pm_runtime_put_autosuspend(host->dev);
1658
1659         return 0;
1660 }
1661
1662 static const struct mmc_host_ops omap_hsmmc_ops = {
1663         .enable = omap_hsmmc_enable_fclk,
1664         .disable = omap_hsmmc_disable_fclk,
1665         .post_req = omap_hsmmc_post_req,
1666         .pre_req = omap_hsmmc_pre_req,
1667         .request = omap_hsmmc_request,
1668         .set_ios = omap_hsmmc_set_ios,
1669         .get_cd = omap_hsmmc_get_cd,
1670         .get_ro = omap_hsmmc_get_ro,
1671         .init_card = omap_hsmmc_init_card,
1672         /* NYET -- enable_sdio_irq */
1673 };
1674
1675 #ifdef CONFIG_DEBUG_FS
1676
1677 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1678 {
1679         struct mmc_host *mmc = s->private;
1680         struct omap_hsmmc_host *host = mmc_priv(mmc);
1681         int context_loss = 0;
1682
1683         if (host->pdata->get_context_loss_count)
1684                 context_loss = host->pdata->get_context_loss_count(host->dev);
1685
1686         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1687                         mmc->index, host->context_loss, context_loss);
1688
1689         if (host->suspended) {
1690                 seq_printf(s, "host suspended, can't read registers\n");
1691                 return 0;
1692         }
1693
1694         pm_runtime_get_sync(host->dev);
1695
1696         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1697                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1698         seq_printf(s, "CON:\t\t0x%08x\n",
1699                         OMAP_HSMMC_READ(host->base, CON));
1700         seq_printf(s, "HCTL:\t\t0x%08x\n",
1701                         OMAP_HSMMC_READ(host->base, HCTL));
1702         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1703                         OMAP_HSMMC_READ(host->base, SYSCTL));
1704         seq_printf(s, "IE:\t\t0x%08x\n",
1705                         OMAP_HSMMC_READ(host->base, IE));
1706         seq_printf(s, "ISE:\t\t0x%08x\n",
1707                         OMAP_HSMMC_READ(host->base, ISE));
1708         seq_printf(s, "CAPA:\t\t0x%08x\n",
1709                         OMAP_HSMMC_READ(host->base, CAPA));
1710
1711         pm_runtime_mark_last_busy(host->dev);
1712         pm_runtime_put_autosuspend(host->dev);
1713
1714         return 0;
1715 }
1716
1717 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1718 {
1719         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1720 }
1721
1722 static const struct file_operations mmc_regs_fops = {
1723         .open           = omap_hsmmc_regs_open,
1724         .read           = seq_read,
1725         .llseek         = seq_lseek,
1726         .release        = single_release,
1727 };
1728
1729 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1730 {
1731         if (mmc->debugfs_root)
1732                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1733                         mmc, &mmc_regs_fops);
1734 }
1735
1736 #else
1737
1738 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1739 {
1740 }
1741
1742 #endif
1743
1744 #ifdef CONFIG_OF
1745 static u16 omap4_reg_offset = 0x100;
1746
1747 static const struct of_device_id omap_mmc_of_match[] = {
1748         {
1749                 .compatible = "ti,omap2-hsmmc",
1750         },
1751         {
1752                 .compatible = "ti,omap3-hsmmc",
1753         },
1754         {
1755                 .compatible = "ti,omap4-hsmmc",
1756                 .data = &omap4_reg_offset,
1757         },
1758         {},
1759 };
1760 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1761
1762 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1763 {
1764         struct omap_mmc_platform_data *pdata;
1765         struct device_node *np = dev->of_node;
1766         u32 bus_width;
1767
1768         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1769         if (!pdata)
1770                 return NULL; /* out of memory */
1771
1772         if (of_find_property(np, "ti,dual-volt", NULL))
1773                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1774
1775         /* This driver only supports 1 slot */
1776         pdata->nr_slots = 1;
1777         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1778         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1779
1780         if (of_find_property(np, "ti,non-removable", NULL)) {
1781                 pdata->slots[0].nonremovable = true;
1782                 pdata->slots[0].no_regulator_off_init = true;
1783         }
1784         of_property_read_u32(np, "bus-width", &bus_width);
1785         if (bus_width == 4)
1786                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1787         else if (bus_width == 8)
1788                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1789
1790         if (of_find_property(np, "ti,needs-special-reset", NULL))
1791                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1792
1793         return pdata;
1794 }
1795 #else
1796 static inline struct omap_mmc_platform_data
1797                         *of_get_hsmmc_pdata(struct device *dev)
1798 {
1799         return NULL;
1800 }
1801 #endif
1802
1803 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1804 {
1805         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1806         struct mmc_host *mmc;
1807         struct omap_hsmmc_host *host = NULL;
1808         struct resource *res;
1809         int ret, irq;
1810         const struct of_device_id *match;
1811
1812         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1813         if (match) {
1814                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1815                 if (match->data) {
1816                         u16 *offsetp = match->data;
1817                         pdata->reg_offset = *offsetp;
1818                 }
1819         }
1820
1821         if (pdata == NULL) {
1822                 dev_err(&pdev->dev, "Platform Data is missing\n");
1823                 return -ENXIO;
1824         }
1825
1826         if (pdata->nr_slots == 0) {
1827                 dev_err(&pdev->dev, "No Slots\n");
1828                 return -ENXIO;
1829         }
1830
1831         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1832         irq = platform_get_irq(pdev, 0);
1833         if (res == NULL || irq < 0)
1834                 return -ENXIO;
1835
1836         res = request_mem_region(res->start, resource_size(res), pdev->name);
1837         if (res == NULL)
1838                 return -EBUSY;
1839
1840         ret = omap_hsmmc_gpio_init(pdata);
1841         if (ret)
1842                 goto err;
1843
1844         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1845         if (!mmc) {
1846                 ret = -ENOMEM;
1847                 goto err_alloc;
1848         }
1849
1850         host            = mmc_priv(mmc);
1851         host->mmc       = mmc;
1852         host->pdata     = pdata;
1853         host->dev       = &pdev->dev;
1854         host->use_dma   = 1;
1855         host->dev->dma_mask = &pdata->dma_mask;
1856         host->dma_ch    = -1;
1857         host->irq       = irq;
1858         host->slot_id   = 0;
1859         host->mapbase   = res->start + pdata->reg_offset;
1860         host->base      = ioremap(host->mapbase, SZ_4K);
1861         host->power_mode = MMC_POWER_OFF;
1862         host->flags     = AUTO_CMD12;
1863         host->next_data.cookie = 1;
1864
1865         platform_set_drvdata(pdev, host);
1866
1867         mmc->ops        = &omap_hsmmc_ops;
1868
1869         /*
1870          * If regulator_disable can only put vcc_aux to sleep then there is
1871          * no off state.
1872          */
1873         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1874                 mmc_slot(host).no_off = 1;
1875
1876         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1877
1878         if (pdata->max_freq > 0)
1879                 mmc->f_max = pdata->max_freq;
1880         else
1881                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1882
1883         spin_lock_init(&host->irq_lock);
1884
1885         host->fclk = clk_get(&pdev->dev, "fck");
1886         if (IS_ERR(host->fclk)) {
1887                 ret = PTR_ERR(host->fclk);
1888                 host->fclk = NULL;
1889                 goto err1;
1890         }
1891
1892         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1893                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1894                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1895         }
1896
1897         pm_runtime_enable(host->dev);
1898         pm_runtime_get_sync(host->dev);
1899         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1900         pm_runtime_use_autosuspend(host->dev);
1901
1902         omap_hsmmc_context_save(host);
1903
1904         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1905         /*
1906          * MMC can still work without debounce clock.
1907          */
1908         if (IS_ERR(host->dbclk)) {
1909                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1910                 host->dbclk = NULL;
1911         } else if (clk_enable(host->dbclk) != 0) {
1912                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1913                 clk_put(host->dbclk);
1914                 host->dbclk = NULL;
1915         }
1916
1917         /* Since we do only SG emulation, we can have as many segs
1918          * as we want. */
1919         mmc->max_segs = 1024;
1920
1921         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1922         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1923         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1924         mmc->max_seg_size = mmc->max_req_size;
1925
1926         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1927                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1928
1929         mmc->caps |= mmc_slot(host).caps;
1930         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1931                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1932
1933         if (mmc_slot(host).nonremovable)
1934                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1935
1936         mmc->pm_caps = mmc_slot(host).pm_caps;
1937
1938         omap_hsmmc_conf_bus_power(host);
1939
1940         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1941         if (!res) {
1942                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1943                 goto err_irq;
1944         }
1945         host->dma_line_tx = res->start;
1946
1947         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1948         if (!res) {
1949                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1950                 goto err_irq;
1951         }
1952         host->dma_line_rx = res->start;
1953
1954         /* Request IRQ for MMC operations */
1955         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1956                         mmc_hostname(mmc), host);
1957         if (ret) {
1958                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1959                 goto err_irq;
1960         }
1961
1962         if (pdata->init != NULL) {
1963                 if (pdata->init(&pdev->dev) != 0) {
1964                         dev_dbg(mmc_dev(host->mmc),
1965                                 "Unable to configure MMC IRQs\n");
1966                         goto err_irq_cd_init;
1967                 }
1968         }
1969
1970         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1971                 ret = omap_hsmmc_reg_get(host);
1972                 if (ret)
1973                         goto err_reg;
1974                 host->use_reg = 1;
1975         }
1976
1977         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1978
1979         /* Request IRQ for card detect */
1980         if ((mmc_slot(host).card_detect_irq)) {
1981                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1982                                            NULL,
1983                                            omap_hsmmc_detect,
1984                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1985                                            mmc_hostname(mmc), host);
1986                 if (ret) {
1987                         dev_dbg(mmc_dev(host->mmc),
1988                                 "Unable to grab MMC CD IRQ\n");
1989                         goto err_irq_cd;
1990                 }
1991                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1992                 pdata->resume = omap_hsmmc_resume_cdirq;
1993         }
1994
1995         omap_hsmmc_disable_irq(host);
1996
1997         omap_hsmmc_protect_card(host);
1998
1999         mmc_add_host(mmc);
2000
2001         if (mmc_slot(host).name != NULL) {
2002                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2003                 if (ret < 0)
2004                         goto err_slot_name;
2005         }
2006         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2007                 ret = device_create_file(&mmc->class_dev,
2008                                         &dev_attr_cover_switch);
2009                 if (ret < 0)
2010                         goto err_slot_name;
2011         }
2012
2013         omap_hsmmc_debugfs(mmc);
2014         pm_runtime_mark_last_busy(host->dev);
2015         pm_runtime_put_autosuspend(host->dev);
2016
2017         return 0;
2018
2019 err_slot_name:
2020         mmc_remove_host(mmc);
2021         free_irq(mmc_slot(host).card_detect_irq, host);
2022 err_irq_cd:
2023         if (host->use_reg)
2024                 omap_hsmmc_reg_put(host);
2025 err_reg:
2026         if (host->pdata->cleanup)
2027                 host->pdata->cleanup(&pdev->dev);
2028 err_irq_cd_init:
2029         free_irq(host->irq, host);
2030 err_irq:
2031         pm_runtime_put_sync(host->dev);
2032         pm_runtime_disable(host->dev);
2033         clk_put(host->fclk);
2034         if (host->dbclk) {
2035                 clk_disable(host->dbclk);
2036                 clk_put(host->dbclk);
2037         }
2038 err1:
2039         iounmap(host->base);
2040         platform_set_drvdata(pdev, NULL);
2041         mmc_free_host(mmc);
2042 err_alloc:
2043         omap_hsmmc_gpio_free(pdata);
2044 err:
2045         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2046         if (res)
2047                 release_mem_region(res->start, resource_size(res));
2048         return ret;
2049 }
2050
2051 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2052 {
2053         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2054         struct resource *res;
2055
2056         pm_runtime_get_sync(host->dev);
2057         mmc_remove_host(host->mmc);
2058         if (host->use_reg)
2059                 omap_hsmmc_reg_put(host);
2060         if (host->pdata->cleanup)
2061                 host->pdata->cleanup(&pdev->dev);
2062         free_irq(host->irq, host);
2063         if (mmc_slot(host).card_detect_irq)
2064                 free_irq(mmc_slot(host).card_detect_irq, host);
2065
2066         pm_runtime_put_sync(host->dev);
2067         pm_runtime_disable(host->dev);
2068         clk_put(host->fclk);
2069         if (host->dbclk) {
2070                 clk_disable(host->dbclk);
2071                 clk_put(host->dbclk);
2072         }
2073
2074         mmc_free_host(host->mmc);
2075         iounmap(host->base);
2076         omap_hsmmc_gpio_free(pdev->dev.platform_data);
2077
2078         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2079         if (res)
2080                 release_mem_region(res->start, resource_size(res));
2081         platform_set_drvdata(pdev, NULL);
2082
2083         return 0;
2084 }
2085
2086 #ifdef CONFIG_PM
2087 static int omap_hsmmc_suspend(struct device *dev)
2088 {
2089         int ret = 0;
2090         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2091
2092         if (!host)
2093                 return 0;
2094
2095         if (host && host->suspended)
2096                 return 0;
2097
2098         pm_runtime_get_sync(host->dev);
2099         host->suspended = 1;
2100         if (host->pdata->suspend) {
2101                 ret = host->pdata->suspend(dev, host->slot_id);
2102                 if (ret) {
2103                         dev_dbg(dev, "Unable to handle MMC board"
2104                                         " level suspend\n");
2105                         host->suspended = 0;
2106                         return ret;
2107                 }
2108         }
2109         ret = mmc_suspend_host(host->mmc);
2110
2111         if (ret) {
2112                 host->suspended = 0;
2113                 if (host->pdata->resume) {
2114                         ret = host->pdata->resume(dev, host->slot_id);
2115                         if (ret)
2116                                 dev_dbg(dev, "Unmask interrupt failed\n");
2117                 }
2118                 goto err;
2119         }
2120
2121         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2122                 omap_hsmmc_disable_irq(host);
2123                 OMAP_HSMMC_WRITE(host->base, HCTL,
2124                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2125         }
2126
2127         if (host->dbclk)
2128                 clk_disable(host->dbclk);
2129 err:
2130         pm_runtime_put_sync(host->dev);
2131         return ret;
2132 }
2133
2134 /* Routine to resume the MMC device */
2135 static int omap_hsmmc_resume(struct device *dev)
2136 {
2137         int ret = 0;
2138         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2139
2140         if (!host)
2141                 return 0;
2142
2143         if (host && !host->suspended)
2144                 return 0;
2145
2146         pm_runtime_get_sync(host->dev);
2147
2148         if (host->dbclk)
2149                 clk_enable(host->dbclk);
2150
2151         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2152                 omap_hsmmc_conf_bus_power(host);
2153
2154         if (host->pdata->resume) {
2155                 ret = host->pdata->resume(dev, host->slot_id);
2156                 if (ret)
2157                         dev_dbg(dev, "Unmask interrupt failed\n");
2158         }
2159
2160         omap_hsmmc_protect_card(host);
2161
2162         /* Notify the core to resume the host */
2163         ret = mmc_resume_host(host->mmc);
2164         if (ret == 0)
2165                 host->suspended = 0;
2166
2167         pm_runtime_mark_last_busy(host->dev);
2168         pm_runtime_put_autosuspend(host->dev);
2169
2170         return ret;
2171
2172 }
2173
2174 #else
2175 #define omap_hsmmc_suspend      NULL
2176 #define omap_hsmmc_resume               NULL
2177 #endif
2178
2179 static int omap_hsmmc_runtime_suspend(struct device *dev)
2180 {
2181         struct omap_hsmmc_host *host;
2182
2183         host = platform_get_drvdata(to_platform_device(dev));
2184         omap_hsmmc_context_save(host);
2185         dev_dbg(dev, "disabled\n");
2186
2187         return 0;
2188 }
2189
2190 static int omap_hsmmc_runtime_resume(struct device *dev)
2191 {
2192         struct omap_hsmmc_host *host;
2193
2194         host = platform_get_drvdata(to_platform_device(dev));
2195         omap_hsmmc_context_restore(host);
2196         dev_dbg(dev, "enabled\n");
2197
2198         return 0;
2199 }
2200
2201 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2202         .suspend        = omap_hsmmc_suspend,
2203         .resume         = omap_hsmmc_resume,
2204         .runtime_suspend = omap_hsmmc_runtime_suspend,
2205         .runtime_resume = omap_hsmmc_runtime_resume,
2206 };
2207
2208 static struct platform_driver omap_hsmmc_driver = {
2209         .probe          = omap_hsmmc_probe,
2210         .remove         = __devexit_p(omap_hsmmc_remove),
2211         .driver         = {
2212                 .name = DRIVER_NAME,
2213                 .owner = THIS_MODULE,
2214                 .pm = &omap_hsmmc_dev_pm_ops,
2215                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2216         },
2217 };
2218
2219 module_platform_driver(omap_hsmmc_driver);
2220 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2221 MODULE_LICENSE("GPL");
2222 MODULE_ALIAS("platform:" DRIVER_NAME);
2223 MODULE_AUTHOR("Texas Instruments Inc");