drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/sizes.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/timer.h>
  30 #include <linux/clk.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/omap-dmaengine.h>
  36 #include <linux/mmc/host.h>
  37 #include <linux/mmc/core.h>
  38 #include <linux/mmc/mmc.h>
  39 #include <linux/io.h>
  40 #include <linux/irq.h>
  41 #include <linux/gpio.h>
  42 #include <linux/regulator/consumer.h>
  43 #include <linux/pinctrl/consumer.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/platform_data/hsmmc-omap.h>
  46
  47 /* OMAP HSMMC Host Controller Registers */
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_SDMASA       0x0100
  51 #define OMAP_HSMMC_BLK          0x0104
  52 #define OMAP_HSMMC_ARG          0x0108
  53 #define OMAP_HSMMC_CMD          0x010C
  54 #define OMAP_HSMMC_RSP10        0x0110
  55 #define OMAP_HSMMC_RSP32        0x0114
  56 #define OMAP_HSMMC_RSP54        0x0118
  57 #define OMAP_HSMMC_RSP76        0x011C
  58 #define OMAP_HSMMC_DATA         0x0120
  59 #define OMAP_HSMMC_PSTATE       0x0124
  60 #define OMAP_HSMMC_HCTL         0x0128
  61 #define OMAP_HSMMC_SYSCTL       0x012C
  62 #define OMAP_HSMMC_STAT         0x0130
  63 #define OMAP_HSMMC_IE           0x0134
  64 #define OMAP_HSMMC_ISE          0x0138
  65 #define OMAP_HSMMC_AC12         0x013C
  66 #define OMAP_HSMMC_CAPA         0x0140
  67
  68 #define VS18                    (1 << 26)
  69 #define VS30                    (1 << 25)
  70 #define HSS                     (1 << 21)
  71 #define SDVS18                  (0x5 << 9)
  72 #define SDVS30                  (0x6 << 9)
  73 #define SDVS33                  (0x7 << 9)
  74 #define SDVS_MASK               0x00000E00
  75 #define SDVSCLR                 0xFFFFF1FF
  76 #define SDVSDET                 0x00000400
  77 #define AUTOIDLE                0x1
  78 #define SDBP                    (1 << 8)
  79 #define DTO                     0xe
  80 #define ICE                     0x1
  81 #define ICS                     0x2
  82 #define CEN                     (1 << 2)
  83 #define CLKD_MAX                0x3FF           /* max clock divisor: 1023 */
  84 #define CLKD_MASK               0x0000FFC0
  85 #define CLKD_SHIFT              6
  86 #define DTO_MASK                0x000F0000
  87 #define DTO_SHIFT               16
  88 #define INIT_STREAM             (1 << 1)
  89 #define ACEN_ACMD23             (2 << 2)
  90 #define DP_SELECT               (1 << 21)
  91 #define DDIR                    (1 << 4)
  92 #define DMAE                    0x1
  93 #define MSBS                    (1 << 5)
  94 #define BCE                     (1 << 1)
  95 #define FOUR_BIT                (1 << 1)
  96 #define HSPE                    (1 << 2)
  97 #define IWE                     (1 << 24)
  98 #define DDR                     (1 << 19)
  99 #define CLKEXTFREE              (1 << 16)
 100 #define CTPL                    (1 << 11)
 101 #define DW8                     (1 << 5)
 102 #define OD                      0x1
 103 #define STAT_CLEAR              0xFFFFFFFF
 104 #define INIT_STREAM_CMD         0x00000000
 105 #define DUAL_VOLT_OCR_BIT       7
 106 #define SRC                     (1 << 25)
 107 #define SRD                     (1 << 26)
 108 #define SOFTRESET               (1 << 1)
 109
 110 /* PSTATE */
 111 #define DLEV_DAT(x)             (1 << (20 + (x)))
 112
 113 /* Interrupt masks for IE and ISE register */
 114 #define CC_EN                   (1 << 0)
 115 #define TC_EN                   (1 << 1)
 116 #define BWR_EN                  (1 << 4)
 117 #define BRR_EN                  (1 << 5)
 118 #define CIRQ_EN                 (1 << 8)
 119 #define ERR_EN                  (1 << 15)
 120 #define CTO_EN                  (1 << 16)
 121 #define CCRC_EN                 (1 << 17)
 122 #define CEB_EN                  (1 << 18)
 123 #define CIE_EN                  (1 << 19)
 124 #define DTO_EN                  (1 << 20)
 125 #define DCRC_EN                 (1 << 21)
 126 #define DEB_EN                  (1 << 22)
 127 #define ACE_EN                  (1 << 24)
 128 #define CERR_EN                 (1 << 28)
 129 #define BADA_EN                 (1 << 29)
 130
 131 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
 132                 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
 133                 BRR_EN | BWR_EN | TC_EN | CC_EN)
 134
 135 #define CNI     (1 << 7)
 136 #define ACIE    (1 << 4)
 137 #define ACEB    (1 << 3)
 138 #define ACCE    (1 << 2)
 139 #define ACTO    (1 << 1)
 140 #define ACNE    (1 << 0)
 141
 142 #define MMC_AUTOSUSPEND_DELAY   100
 143 #define MMC_TIMEOUT_MS          20              /* 20 mSec */
 144 #define MMC_TIMEOUT_US          20000           /* 20000 micro Sec */
 145 #define OMAP_MMC_MIN_CLOCK      400000
 146 #define OMAP_MMC_MAX_CLOCK      52000000
 147 #define DRIVER_NAME             "omap_hsmmc"
 148
 149 #define VDD_1V8                 1800000         /* 180000 uV */
 150 #define VDD_3V0                 3000000         /* 300000 uV */
 151 #define VDD_165_195             (ffs(MMC_VDD_165_195) - 1)
 152
 153 /*
 154  * One controller can have multiple slots, like on some omap boards using
 155  * omap.c controller driver. Luckily this is not currently done on any known
 156  * omap_hsmmc.c device.
 157  */
 158 #define mmc_pdata(host)         host->pdata
 159
 160 /*
 161  * MMC Host controller read/write API's
 162  */
 163 #define OMAP_HSMMC_READ(base, reg)      \
 164         __raw_readl((base) + OMAP_HSMMC_##reg)
 165
 166 #define OMAP_HSMMC_WRITE(base, reg, val) \
 167         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 168
 169 struct omap_hsmmc_next {
 170         unsigned int    dma_len;
 171         s32             cookie;
 172 };
 173
 174 struct omap_hsmmc_host {
 175         struct  device          *dev;
 176         struct  mmc_host        *mmc;
 177         struct  mmc_request     *mrq;
 178         struct  mmc_command     *cmd;
 179         struct  mmc_data        *data;
 180         struct  clk             *fclk;
 181         struct  clk             *dbclk;
 182         /*
 183          * vcc == configured supply
 184          * vcc_aux == optional
 185          *   -  MMC1, supply for DAT4..DAT7
 186          *   -  MMC2/MMC2, external level shifter voltage supply, for
 187          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 188          */
 189         struct  regulator       *vcc;
 190         struct  regulator       *vcc_aux;
 191         struct  regulator       *pbias;
 192         bool                    pbias_enabled;
 193         void    __iomem         *base;
 194         resource_size_t         mapbase;
 195         spinlock_t              irq_lock; /* Prevent races with irq handler */
 196         unsigned int            dma_len;
 197         unsigned int            dma_sg_idx;
 198         unsigned char           bus_mode;
 199         unsigned char           power_mode;
 200         int                     suspended;
 201         u32                     con;
 202         u32                     hctl;
 203         u32                     sysctl;
 204         u32                     capa;
 205         int                     irq;
 206         int                     wake_irq;
 207         int                     use_dma, dma_ch;
 208         struct dma_chan         *tx_chan;
 209         struct dma_chan         *rx_chan;
 210         int                     response_busy;
 211         int                     context_loss;
 212         int                     protect_card;
 213         int                     reqs_blocked;
 214         int                     use_reg;
 215         int                     req_in_progress;
 216         unsigned long           clk_rate;
 217         unsigned int            flags;
 218 #define AUTO_CMD23              (1 << 0)        /* Auto CMD23 support */
 219 #define HSMMC_SDIO_IRQ_ENABLED  (1 << 1)        /* SDIO irq enabled */
 220 #define HSMMC_WAKE_IRQ_ENABLED  (1 << 2)
 221         struct omap_hsmmc_next  next_data;
 222         struct  omap_hsmmc_platform_data        *pdata;
 223
 224         /* To handle board related suspend/resume functionality for MMC */
 225         int (*suspend)(struct device *dev);
 226         int (*resume)(struct device *dev);
 227
 228         /* return MMC cover switch state, can be NULL if not supported.
 229          *
 230          * possible return values:
 231          *   0 - closed
 232          *   1 - open
 233          */
 234         int (*get_cover_state)(struct device *dev);
 235
 236         /* Card detection IRQs */
 237         int card_detect_irq;
 238
 239         int (*card_detect)(struct device *dev);
 240         int (*get_ro)(struct device *dev);
 241
 242 };
 243
 244 struct omap_mmc_of_data {
 245         u32 reg_offset;
 246         u8 controller_flags;
 247 };
 248
 249 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
 250
 251 static int omap_hsmmc_card_detect(struct device *dev)
 252 {
 253         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 254         struct omap_hsmmc_platform_data *mmc = host->pdata;
 255
 256         /* NOTE: assumes card detect signal is active-low */
 257         return !gpio_get_value_cansleep(mmc->switch_pin);
 258 }
 259
 260 static int omap_hsmmc_get_wp(struct device *dev)
 261 {
 262         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 263         struct omap_hsmmc_platform_data *mmc = host->pdata;
 264
 265         /* NOTE: assumes write protect signal is active-high */
 266         return gpio_get_value_cansleep(mmc->gpio_wp);
 267 }
 268
 269 static int omap_hsmmc_get_cover_state(struct device *dev)
 270 {
 271         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 272         struct omap_hsmmc_platform_data *mmc = host->pdata;
 273
 274         /* NOTE: assumes card detect signal is active-low */
 275         return !gpio_get_value_cansleep(mmc->switch_pin);
 276 }
 277
 278 #ifdef CONFIG_PM
 279
 280 static int omap_hsmmc_suspend_cdirq(struct device *dev)
 281 {
 282         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 283
 284         disable_irq(host->card_detect_irq);
 285         return 0;
 286 }
 287
 288 static int omap_hsmmc_resume_cdirq(struct device *dev)
 289 {
 290         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
 291
 292         enable_irq(host->card_detect_irq);
 293         return 0;
 294 }
 295
 296 #else
 297
 298 #define omap_hsmmc_suspend_cdirq        NULL
 299 #define omap_hsmmc_resume_cdirq         NULL
 300
 301 #endif
 302
 303 #ifdef CONFIG_REGULATOR
 304
 305 static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
 306 {
 307         struct omap_hsmmc_host *host =
 308                 platform_get_drvdata(to_platform_device(dev));
 309         int ret = 0;
 310
 311         /*
 312          * If we don't see a Vcc regulator, assume it's a fixed
 313          * voltage always-on regulator.
 314          */
 315         if (!host->vcc)
 316                 return 0;
 317
 318         if (mmc_pdata(host)->before_set_reg)
 319                 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
 320
 321         if (host->pbias) {
 322                 if (host->pbias_enabled == 1) {
 323                         ret = regulator_disable(host->pbias);
 324                         if (!ret)
 325                                 host->pbias_enabled = 0;
 326                 }
 327                 regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0);
 328         }
 329
 330         /*
 331          * Assume Vcc regulator is used only to power the card ... OMAP
 332          * VDDS is used to power the pins, optionally with a transceiver to
 333          * support cards using voltages other than VDDS (1.8V nominal).  When a
 334          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 335          *
 336          * In some cases this regulator won't support enable/disable;
 337          * e.g. it's a fixed rail for a WLAN chip.
 338          *
 339          * In other cases vcc_aux switches interface power.  Example, for
 340          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 341          * chips/cards need an interface voltage rail too.
 342          */
 343         if (power_on) {
 344                 if (host->vcc)
 345                         ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 346                 /* Enable interface voltage rail, if needed */
 347                 if (ret == 0 && host->vcc_aux) {
 348                         ret = regulator_enable(host->vcc_aux);
 349                         if (ret < 0 && host->vcc)
 350                                 ret = mmc_regulator_set_ocr(host->mmc,
 351                                                         host->vcc, 0);
 352                 }
 353         } else {
 354                 /* Shut down the rail */
 355                 if (host->vcc_aux)
 356                         ret = regulator_disable(host->vcc_aux);
 357                 if (host->vcc) {
 358                         /* Then proceed to shut down the local regulator */
 359                         ret = mmc_regulator_set_ocr(host->mmc,
 360                                                 host->vcc, 0);
 361                 }
 362         }
 363
 364         if (host->pbias) {
 365                 if (vdd <= VDD_165_195)
 366                         ret = regulator_set_voltage(host->pbias, VDD_1V8,
 367                                                                 VDD_1V8);
 368                 else
 369                         ret = regulator_set_voltage(host->pbias, VDD_3V0,
 370                                                                 VDD_3V0);
 371                 if (ret < 0)
 372                         goto error_set_power;
 373
 374                 if (host->pbias_enabled == 0) {
 375                         ret = regulator_enable(host->pbias);
 376                         if (!ret)
 377                                 host->pbias_enabled = 1;
 378                 }
 379         }
 380
 381         if (mmc_pdata(host)->after_set_reg)
 382                 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
 383
 384 error_set_power:
 385         return ret;
 386 }
 387
 388 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 389 {
 390         struct regulator *reg;
 391         int ocr_value = 0;
 392
 393         reg = devm_regulator_get(host->dev, "vmmc");
 394         if (IS_ERR(reg)) {
 395                 dev_err(host->dev, "unable to get vmmc regulator %ld\n",
 396                         PTR_ERR(reg));
 397                 return PTR_ERR(reg);
 398         } else {
 399                 host->vcc = reg;
 400                 ocr_value = mmc_regulator_get_ocrmask(reg);
 401                 if (!mmc_pdata(host)->ocr_mask) {
 402                         mmc_pdata(host)->ocr_mask = ocr_value;
 403                 } else {
 404                         if (!(mmc_pdata(host)->ocr_mask & ocr_value)) {
 405                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 406                                         mmc_pdata(host)->ocr_mask);
 407                                 mmc_pdata(host)->ocr_mask = 0;
 408                                 return -EINVAL;
 409                         }
 410                 }
 411         }
 412         mmc_pdata(host)->set_power = omap_hsmmc_set_power;
 413
 414         /* Allow an aux regulator */
 415         reg = devm_regulator_get_optional(host->dev, "vmmc_aux");
 416         host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 417
 418         reg = devm_regulator_get_optional(host->dev, "pbias");
 419         host->pbias = IS_ERR(reg) ? NULL : reg;
 420
 421         /* For eMMC do not power off when not in sleep state */
 422         if (mmc_pdata(host)->no_regulator_off_init)
 423                 return 0;
 424         /*
 425          * To disable boot_on regulator, enable regulator
 426          * to increase usecount and then disable it.
 427          */
 428         if ((host->vcc && regulator_is_enabled(host->vcc) > 0) ||
 429             (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 430                 int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1;
 431
 432                 mmc_pdata(host)->set_power(host->dev, 1, vdd);
 433                 mmc_pdata(host)->set_power(host->dev, 0, 0);
 434         }
 435
 436         return 0;
 437 }
 438
 439 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 440 {
 441         mmc_pdata(host)->set_power = NULL;
 442 }
 443
 444 static inline int omap_hsmmc_have_reg(void)
 445 {
 446         return 1;
 447 }
 448
 449 #else
 450
 451 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 452 {
 453         return -EINVAL;
 454 }
 455
 456 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 457 {
 458 }
 459
 460 static inline int omap_hsmmc_have_reg(void)
 461 {
 462         return 0;
 463 }
 464
 465 #endif
 466
 467 static int omap_hsmmc_gpio_init(struct omap_hsmmc_host *host,
 468                                 struct omap_hsmmc_platform_data *pdata)
 469 {
 470         int ret;
 471
 472         if (gpio_is_valid(pdata->switch_pin)) {
 473                 if (pdata->cover)
 474                         host->get_cover_state =
 475                                 omap_hsmmc_get_cover_state;
 476                 else
 477                         host->card_detect = omap_hsmmc_card_detect;
 478                 host->card_detect_irq =
 479                                 gpio_to_irq(pdata->switch_pin);
 480                 ret = gpio_request(pdata->switch_pin, "mmc_cd");
 481                 if (ret)
 482                         return ret;
 483                 ret = gpio_direction_input(pdata->switch_pin);
 484                 if (ret)
 485                         goto err_free_sp;
 486         } else {
 487                 pdata->switch_pin = -EINVAL;
 488         }
 489
 490         if (gpio_is_valid(pdata->gpio_wp)) {
 491                 host->get_ro = omap_hsmmc_get_wp;
 492                 ret = gpio_request(pdata->gpio_wp, "mmc_wp");
 493                 if (ret)
 494                         goto err_free_cd;
 495                 ret = gpio_direction_input(pdata->gpio_wp);
 496                 if (ret)
 497                         goto err_free_wp;
 498         } else {
 499                 pdata->gpio_wp = -EINVAL;
 500         }
 501
 502         return 0;
 503
 504 err_free_wp:
 505         gpio_free(pdata->gpio_wp);
 506 err_free_cd:
 507         if (gpio_is_valid(pdata->switch_pin))
 508 err_free_sp:
 509                 gpio_free(pdata->switch_pin);
 510         return ret;
 511 }
 512
 513 static void omap_hsmmc_gpio_free(struct omap_hsmmc_host *host,
 514                                  struct omap_hsmmc_platform_data *pdata)
 515 {
 516         if (gpio_is_valid(pdata->gpio_wp))
 517                 gpio_free(pdata->gpio_wp);
 518         if (gpio_is_valid(pdata->switch_pin))
 519                 gpio_free(pdata->switch_pin);
 520 }
 521
 522 /*
 523  * Start clock to the card
 524  */
 525 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 526 {
 527         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 528                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 529 }
 530
 531 /*
 532  * Stop clock to the card
 533  */
 534 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 535 {
 536         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 537                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 538         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 539                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
 540 }
 541
 542 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 543                                   struct mmc_command *cmd)
 544 {
 545         u32 irq_mask = INT_EN_MASK;
 546         unsigned long flags;
 547
 548         if (host->use_dma)
 549                 irq_mask &= ~(BRR_EN | BWR_EN);
 550
 551         /* Disable timeout for erases */
 552         if (cmd->opcode == MMC_ERASE)
 553                 irq_mask &= ~DTO_EN;
 554
 555         spin_lock_irqsave(&host->irq_lock, flags);
 556         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 557         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 558
 559         /* latch pending CIRQ, but don't signal MMC core */
 560         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 561                 irq_mask |= CIRQ_EN;
 562         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 563         spin_unlock_irqrestore(&host->irq_lock, flags);
 564 }
 565
 566 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 567 {
 568         u32 irq_mask = 0;
 569         unsigned long flags;
 570
 571         spin_lock_irqsave(&host->irq_lock, flags);
 572         /* no transfer running but need to keep cirq if enabled */
 573         if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
 574                 irq_mask |= CIRQ_EN;
 575         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 576         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 577         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 578         spin_unlock_irqrestore(&host->irq_lock, flags);
 579 }
 580
 581 /* Calculate divisor for the given clock frequency */
 582 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 583 {
 584         u16 dsor = 0;
 585
 586         if (ios->clock) {
 587                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 588                 if (dsor > CLKD_MAX)
 589                         dsor = CLKD_MAX;
 590         }
 591
 592         return dsor;
 593 }
 594
 595 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 596 {
 597         struct mmc_ios *ios = &host->mmc->ios;
 598         unsigned long regval;
 599         unsigned long timeout;
 600         unsigned long clkdiv;
 601
 602         dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 603
 604         omap_hsmmc_stop_clock(host);
 605
 606         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 607         regval = regval & ~(CLKD_MASK | DTO_MASK);
 608         clkdiv = calc_divisor(host, ios);
 609         regval = regval | (clkdiv << 6) | (DTO << 16);
 610         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 611         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 612                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 613
 614         /* Wait till the ICS bit is set */
 615         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 616         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 617                 && time_before(jiffies, timeout))
 618                 cpu_relax();
 619
 620         /*
 621          * Enable High-Speed Support
 622          * Pre-Requisites
 623          *      - Controller should support High-Speed-Enable Bit
 624          *      - Controller should not be using DDR Mode
 625          *      - Controller should advertise that it supports High Speed
 626          *        in capabilities register
 627          *      - MMC/SD clock coming out of controller > 25MHz
 628          */
 629         if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
 630             (ios->timing != MMC_TIMING_MMC_DDR52) &&
 631             (ios->timing != MMC_TIMING_UHS_DDR50) &&
 632             ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
 633                 regval = OMAP_HSMMC_READ(host->base, HCTL);
 634                 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
 635                         regval |= HSPE;
 636                 else
 637                         regval &= ~HSPE;
 638
 639                 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
 640         }
 641
 642         omap_hsmmc_start_clock(host);
 643 }
 644
 645 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 646 {
 647         struct mmc_ios *ios = &host->mmc->ios;
 648         u32 con;
 649
 650         con = OMAP_HSMMC_READ(host->base, CON);
 651         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
 652             ios->timing == MMC_TIMING_UHS_DDR50)
 653                 con |= DDR;     /* configure in DDR mode */
 654         else
 655                 con &= ~DDR;
 656         switch (ios->bus_width) {
 657         case MMC_BUS_WIDTH_8:
 658                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 659                 break;
 660         case MMC_BUS_WIDTH_4:
 661                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 662                 OMAP_HSMMC_WRITE(host->base, HCTL,
 663                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 664                 break;
 665         case MMC_BUS_WIDTH_1:
 666                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 667                 OMAP_HSMMC_WRITE(host->base, HCTL,
 668                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 669                 break;
 670         }
 671 }
 672
 673 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 674 {
 675         struct mmc_ios *ios = &host->mmc->ios;
 676         u32 con;
 677
 678         con = OMAP_HSMMC_READ(host->base, CON);
 679         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 680                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 681         else
 682                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 683 }
 684
 685 #ifdef CONFIG_PM
 686
 687 /*
 688  * Restore the MMC host context, if it was lost as result of a
 689  * power state change.
 690  */
 691 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 692 {
 693         struct mmc_ios *ios = &host->mmc->ios;
 694         u32 hctl, capa;
 695         unsigned long timeout;
 696
 697         if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
 698             host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
 699             host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
 700             host->capa == OMAP_HSMMC_READ(host->base, CAPA))
 701                 return 0;
 702
 703         host->context_loss++;
 704
 705         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 706                 if (host->power_mode != MMC_POWER_OFF &&
 707                     (1 << ios->vdd) <= MMC_VDD_23_24)
 708                         hctl = SDVS18;
 709                 else
 710                         hctl = SDVS30;
 711                 capa = VS30 | VS18;
 712         } else {
 713                 hctl = SDVS18;
 714                 capa = VS18;
 715         }
 716
 717         if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
 718                 hctl |= IWE;
 719
 720         OMAP_HSMMC_WRITE(host->base, HCTL,
 721                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 722
 723         OMAP_HSMMC_WRITE(host->base, CAPA,
 724                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 725
 726         OMAP_HSMMC_WRITE(host->base, HCTL,
 727                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 728
 729         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 730         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 731                 && time_before(jiffies, timeout))
 732                 ;
 733
 734         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 735         OMAP_HSMMC_WRITE(host->base, IE, 0);
 736         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 737
 738         /* Do not initialize card-specific things if the power is off */
 739         if (host->power_mode == MMC_POWER_OFF)
 740                 goto out;
 741
 742         omap_hsmmc_set_bus_width(host);
 743
 744         omap_hsmmc_set_clock(host);
 745
 746         omap_hsmmc_set_bus_mode(host);
 747
 748 out:
 749         dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
 750                 host->context_loss);
 751         return 0;
 752 }
 753
 754 /*
 755  * Save the MMC host context (store the number of power state changes so far).
 756  */
 757 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 758 {
 759         host->con =  OMAP_HSMMC_READ(host->base, CON);
 760         host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
 761         host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
 762         host->capa = OMAP_HSMMC_READ(host->base, CAPA);
 763 }
 764
 765 #else
 766
 767 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 768 {
 769         return 0;
 770 }
 771
 772 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 773 {
 774 }
 775
 776 #endif
 777
 778 /*
 779  * Send init stream sequence to card
 780  * before sending IDLE command
 781  */
 782 static void send_init_stream(struct omap_hsmmc_host *host)
 783 {
 784         int reg = 0;
 785         unsigned long timeout;
 786
 787         if (host->protect_card)
 788                 return;
 789
 790         disable_irq(host->irq);
 791
 792         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 793         OMAP_HSMMC_WRITE(host->base, CON,
 794                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 795         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 796
 797         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 798         while ((reg != CC_EN) && time_before(jiffies, timeout))
 799                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
 800
 801         OMAP_HSMMC_WRITE(host->base, CON,
 802                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 803
 804         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 805         OMAP_HSMMC_READ(host->base, STAT);
 806
 807         enable_irq(host->irq);
 808 }
 809
 810 static inline
 811 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 812 {
 813         int r = 1;
 814
 815         if (host->get_cover_state)
 816                 r = host->get_cover_state(host->dev);
 817         return r;
 818 }
 819
 820 static ssize_t
 821 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 822                            char *buf)
 823 {
 824         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 825         struct omap_hsmmc_host *host = mmc_priv(mmc);
 826
 827         return sprintf(buf, "%s\n",
 828                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 829 }
 830
 831 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 832
 833 static ssize_t
 834 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 835                         char *buf)
 836 {
 837         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 838         struct omap_hsmmc_host *host = mmc_priv(mmc);
 839
 840         return sprintf(buf, "%s\n", mmc_pdata(host)->name);
 841 }
 842
 843 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 844
 845 /*
 846  * Configure the response type and send the cmd.
 847  */
 848 static void
 849 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 850         struct mmc_data *data)
 851 {
 852         int cmdreg = 0, resptype = 0, cmdtype = 0;
 853
 854         dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 855                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 856         host->cmd = cmd;
 857
 858         omap_hsmmc_enable_irq(host, cmd);
 859
 860         host->response_busy = 0;
 861         if (cmd->flags & MMC_RSP_PRESENT) {
 862                 if (cmd->flags & MMC_RSP_136)
 863                         resptype = 1;
 864                 else if (cmd->flags & MMC_RSP_BUSY) {
 865                         resptype = 3;
 866                         host->response_busy = 1;
 867                 } else
 868                         resptype = 2;
 869         }
 870
 871         /*
 872          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 873          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 874          * a val of 0x3, rest 0x0.
 875          */
 876         if (cmd == host->mrq->stop)
 877                 cmdtype = 0x3;
 878
 879         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 880
 881         if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
 882             host->mrq->sbc) {
 883                 cmdreg |= ACEN_ACMD23;
 884                 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
 885         }
 886         if (data) {
 887                 cmdreg |= DP_SELECT | MSBS | BCE;
 888                 if (data->flags & MMC_DATA_READ)
 889                         cmdreg |= DDIR;
 890                 else
 891                         cmdreg &= ~(DDIR);
 892         }
 893
 894         if (host->use_dma)
 895                 cmdreg |= DMAE;
 896
 897         host->req_in_progress = 1;
 898
 899         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 900         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 901 }
 902
 903 static int
 904 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 905 {
 906         if (data->flags & MMC_DATA_WRITE)
 907                 return DMA_TO_DEVICE;
 908         else
 909                 return DMA_FROM_DEVICE;
 910 }
 911
 912 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 913         struct mmc_data *data)
 914 {
 915         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 916 }
 917
 918 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 919 {
 920         int dma_ch;
 921         unsigned long flags;
 922
 923         spin_lock_irqsave(&host->irq_lock, flags);
 924         host->req_in_progress = 0;
 925         dma_ch = host->dma_ch;
 926         spin_unlock_irqrestore(&host->irq_lock, flags);
 927
 928         omap_hsmmc_disable_irq(host);
 929         /* Do not complete the request if DMA is still in progress */
 930         if (mrq->data && host->use_dma && dma_ch != -1)
 931                 return;
 932         host->mrq = NULL;
 933         mmc_request_done(host->mmc, mrq);
 934 }
 935
 936 /*
 937  * Notify the transfer complete to MMC core
 938  */
 939 static void
 940 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 941 {
 942         if (!data) {
 943                 struct mmc_request *mrq = host->mrq;
 944
 945                 /* TC before CC from CMD6 - don't know why, but it happens */
 946                 if (host->cmd && host->cmd->opcode == 6 &&
 947                     host->response_busy) {
 948                         host->response_busy = 0;
 949                         return;
 950                 }
 951
 952                 omap_hsmmc_request_done(host, mrq);
 953                 return;
 954         }
 955
 956         host->data = NULL;
 957
 958         if (!data->error)
 959                 data->bytes_xfered += data->blocks * (data->blksz);
 960         else
 961                 data->bytes_xfered = 0;
 962
 963         if (data->stop && (data->error || !host->mrq->sbc))
 964                 omap_hsmmc_start_command(host, data->stop, NULL);
 965         else
 966                 omap_hsmmc_request_done(host, data->mrq);
 967 }
 968
 969 /*
 970  * Notify the core about command completion
 971  */
 972 static void
 973 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 974 {
 975         if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
 976             !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
 977                 host->cmd = NULL;
 978                 omap_hsmmc_start_dma_transfer(host);
 979                 omap_hsmmc_start_command(host, host->mrq->cmd,
 980                                                 host->mrq->data);
 981                 return;
 982         }
 983
 984         host->cmd = NULL;
 985
 986         if (cmd->flags & MMC_RSP_PRESENT) {
 987                 if (cmd->flags & MMC_RSP_136) {
 988                         /* response type 2 */
 989                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 990                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 991                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 992                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 993                 } else {
 994                         /* response types 1, 1b, 3, 4, 5, 6 */
 995                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 996                 }
 997         }
 998         if ((host->data == NULL && !host->response_busy) || cmd->error)
 999                 omap_hsmmc_request_done(host, host->mrq);
1000 }
1001
1002 /*
1003  * DMA clean up for command errors
1004  */
1005 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1006 {
1007         int dma_ch;
1008         unsigned long flags;
1009
1010         host->data->error = errno;
1011
1012         spin_lock_irqsave(&host->irq_lock, flags);
1013         dma_ch = host->dma_ch;
1014         host->dma_ch = -1;
1015         spin_unlock_irqrestore(&host->irq_lock, flags);
1016
1017         if (host->use_dma && dma_ch != -1) {
1018                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1019
1020                 dmaengine_terminate_all(chan);
1021                 dma_unmap_sg(chan->device->dev,
1022                         host->data->sg, host->data->sg_len,
1023                         omap_hsmmc_get_dma_dir(host, host->data));
1024
1025                 host->data->host_cookie = 0;
1026         }
1027         host->data = NULL;
1028 }
1029
1030 /*
1031  * Readable error output
1032  */
1033 #ifdef CONFIG_MMC_DEBUG
1034 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1035 {
1036         /* --- means reserved bit without definition at documentation */
1037         static const char *omap_hsmmc_status_bits[] = {
1038                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1039                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1040                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1041                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1042         };
1043         char res[256];
1044         char *buf = res;
1045         int len, i;
1046
1047         len = sprintf(buf, "MMC IRQ 0x%x :", status);
1048         buf += len;
1049
1050         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1051                 if (status & (1 << i)) {
1052                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1053                         buf += len;
1054                 }
1055
1056         dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1057 }
1058 #else
1059 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1060                                              u32 status)
1061 {
1062 }
1063 #endif  /* CONFIG_MMC_DEBUG */
1064
1065 /*
1066  * MMC controller internal state machines reset
1067  *
1068  * Used to reset command or data internal state machines, using respectively
1069  *  SRC or SRD bit of SYSCTL register
1070  * Can be called from interrupt context
1071  */
1072 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1073                                                    unsigned long bit)
1074 {
1075         unsigned long i = 0;
1076         unsigned long limit = MMC_TIMEOUT_US;
1077
1078         OMAP_HSMMC_WRITE(host->base, SYSCTL,
1079                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1080
1081         /*
1082          * OMAP4 ES2 and greater has an updated reset logic.
1083          * Monitor a 0->1 transition first
1084          */
1085         if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1086                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1087                                         && (i++ < limit))
1088                         udelay(1);
1089         }
1090         i = 0;
1091
1092         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1093                 (i++ < limit))
1094                 udelay(1);
1095
1096         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1097                 dev_err(mmc_dev(host->mmc),
1098                         "Timeout waiting on controller reset in %s\n",
1099                         __func__);
1100 }
1101
1102 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1103                                         int err, int end_cmd)
1104 {
1105         if (end_cmd) {
1106                 omap_hsmmc_reset_controller_fsm(host, SRC);
1107                 if (host->cmd)
1108                         host->cmd->error = err;
1109         }
1110
1111         if (host->data) {
1112                 omap_hsmmc_reset_controller_fsm(host, SRD);
1113                 omap_hsmmc_dma_cleanup(host, err);
1114         } else if (host->mrq && host->mrq->cmd)
1115                 host->mrq->cmd->error = err;
1116 }
1117
1118 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1119 {
1120         struct mmc_data *data;
1121         int end_cmd = 0, end_trans = 0;
1122         int error = 0;
1123
1124         data = host->data;
1125         dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1126
1127         if (status & ERR_EN) {
1128                 omap_hsmmc_dbg_report_irq(host, status);
1129
1130                 if (status & (CTO_EN | CCRC_EN))
1131                         end_cmd = 1;
1132                 if (status & (CTO_EN | DTO_EN))
1133                         hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1134                 else if (status & (CCRC_EN | DCRC_EN))
1135                         hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1136
1137                 if (status & ACE_EN) {
1138                         u32 ac12;
1139                         ac12 = OMAP_HSMMC_READ(host->base, AC12);
1140                         if (!(ac12 & ACNE) && host->mrq->sbc) {
1141                                 end_cmd = 1;
1142                                 if (ac12 & ACTO)
1143                                         error =  -ETIMEDOUT;
1144                                 else if (ac12 & (ACCE | ACEB | ACIE))
1145                                         error = -EILSEQ;
1146                                 host->mrq->sbc->error = error;
1147                                 hsmmc_command_incomplete(host, error, end_cmd);
1148                         }
1149                         dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1150                 }
1151                 if (host->data || host->response_busy) {
1152                         end_trans = !end_cmd;
1153                         host->response_busy = 0;
1154                 }
1155         }
1156
1157         OMAP_HSMMC_WRITE(host->base, STAT, status);
1158         if (end_cmd || ((status & CC_EN) && host->cmd))
1159                 omap_hsmmc_cmd_done(host, host->cmd);
1160         if ((end_trans || (status & TC_EN)) && host->mrq)
1161                 omap_hsmmc_xfer_done(host, data);
1162 }
1163
1164 /*
1165  * MMC controller IRQ handler
1166  */
1167 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1168 {
1169         struct omap_hsmmc_host *host = dev_id;
1170         int status;
1171
1172         status = OMAP_HSMMC_READ(host->base, STAT);
1173         while (status & (INT_EN_MASK | CIRQ_EN)) {
1174                 if (host->req_in_progress)
1175                         omap_hsmmc_do_irq(host, status);
1176
1177                 if (status & CIRQ_EN)
1178                         mmc_signal_sdio_irq(host->mmc);
1179
1180                 /* Flush posted write */
1181                 status = OMAP_HSMMC_READ(host->base, STAT);
1182         }
1183
1184         return IRQ_HANDLED;
1185 }
1186
1187 static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id)
1188 {
1189         struct omap_hsmmc_host *host = dev_id;
1190
1191         /* cirq is level triggered, disable to avoid infinite loop */
1192         spin_lock(&host->irq_lock);
1193         if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
1194                 disable_irq_nosync(host->wake_irq);
1195                 host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
1196         }
1197         spin_unlock(&host->irq_lock);
1198         pm_request_resume(host->dev); /* no use counter */
1199
1200         return IRQ_HANDLED;
1201 }
1202
1203 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1204 {
1205         unsigned long i;
1206
1207         OMAP_HSMMC_WRITE(host->base, HCTL,
1208                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1209         for (i = 0; i < loops_per_jiffy; i++) {
1210                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1211                         break;
1212                 cpu_relax();
1213         }
1214 }
1215
1216 /*
1217  * Switch MMC interface voltage ... only relevant for MMC1.
1218  *
1219  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1220  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1221  * Some chips, like eMMC ones, use internal transceivers.
1222  */
1223 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1224 {
1225         u32 reg_val = 0;
1226         int ret;
1227
1228         /* Disable the clocks */
1229         pm_runtime_put_sync(host->dev);
1230         if (host->dbclk)
1231                 clk_disable_unprepare(host->dbclk);
1232
1233         /* Turn the power off */
1234         ret = mmc_pdata(host)->set_power(host->dev, 0, 0);
1235
1236         /* Turn the power ON with given VDD 1.8 or 3.0v */
1237         if (!ret)
1238                 ret = mmc_pdata(host)->set_power(host->dev, 1, vdd);
1239         pm_runtime_get_sync(host->dev);
1240         if (host->dbclk)
1241                 clk_prepare_enable(host->dbclk);
1242
1243         if (ret != 0)
1244                 goto err;
1245
1246         OMAP_HSMMC_WRITE(host->base, HCTL,
1247                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1248         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1249
1250         /*
1251          * If a MMC dual voltage card is detected, the set_ios fn calls
1252          * this fn with VDD bit set for 1.8V. Upon card removal from the
1253          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1254          *
1255          * Cope with a bit of slop in the range ... per data sheets:
1256          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1257          *    but recommended values are 1.71V to 1.89V
1258          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1259          *    but recommended values are 2.7V to 3.3V
1260          *
1261          * Board setup code shouldn't permit anything very out-of-range.
1262          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1263          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1264          */
1265         if ((1 << vdd) <= MMC_VDD_23_24)
1266                 reg_val |= SDVS18;
1267         else
1268                 reg_val |= SDVS30;
1269
1270         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1271         set_sd_bus_power(host);
1272
1273         return 0;
1274 err:
1275         dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1276         return ret;
1277 }
1278
1279 /* Protect the card while the cover is open */
1280 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1281 {
1282         if (!host->get_cover_state)
1283                 return;
1284
1285         host->reqs_blocked = 0;
1286         if (host->get_cover_state(host->dev)) {
1287                 if (host->protect_card) {
1288                         dev_info(host->dev, "%s: cover is closed, "
1289                                          "card is now accessible\n",
1290                                          mmc_hostname(host->mmc));
1291                         host->protect_card = 0;
1292                 }
1293         } else {
1294                 if (!host->protect_card) {
1295                         dev_info(host->dev, "%s: cover is open, "
1296                                          "card is now inaccessible\n",
1297                                          mmc_hostname(host->mmc));
1298                         host->protect_card = 1;
1299                 }
1300         }
1301 }
1302
1303 /*
1304  * irq handler to notify the core about card insertion/removal
1305  */
1306 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1307 {
1308         struct omap_hsmmc_host *host = dev_id;
1309         int carddetect;
1310
1311         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1312
1313         if (host->card_detect)
1314                 carddetect = host->card_detect(host->dev);
1315         else {
1316                 omap_hsmmc_protect_card(host);
1317                 carddetect = -ENOSYS;
1318         }
1319
1320         if (carddetect)
1321                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1322         else
1323                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1324         return IRQ_HANDLED;
1325 }
1326
1327 static void omap_hsmmc_dma_callback(void *param)
1328 {
1329         struct omap_hsmmc_host *host = param;
1330         struct dma_chan *chan;
1331         struct mmc_data *data;
1332         int req_in_progress;
1333
1334         spin_lock_irq(&host->irq_lock);
1335         if (host->dma_ch < 0) {
1336                 spin_unlock_irq(&host->irq_lock);
1337                 return;
1338         }
1339
1340         data = host->mrq->data;
1341         chan = omap_hsmmc_get_dma_chan(host, data);
1342         if (!data->host_cookie)
1343                 dma_unmap_sg(chan->device->dev,
1344                              data->sg, data->sg_len,
1345                              omap_hsmmc_get_dma_dir(host, data));
1346
1347         req_in_progress = host->req_in_progress;
1348         host->dma_ch = -1;
1349         spin_unlock_irq(&host->irq_lock);
1350
1351         /* If DMA has finished after TC, complete the request */
1352         if (!req_in_progress) {
1353                 struct mmc_request *mrq = host->mrq;
1354
1355                 host->mrq = NULL;
1356                 mmc_request_done(host->mmc, mrq);
1357         }
1358 }
1359
1360 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1361                                        struct mmc_data *data,
1362                                        struct omap_hsmmc_next *next,
1363                                        struct dma_chan *chan)
1364 {
1365         int dma_len;
1366
1367         if (!next && data->host_cookie &&
1368             data->host_cookie != host->next_data.cookie) {
1369                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1370                        " host->next_data.cookie %d\n",
1371                        __func__, data->host_cookie, host->next_data.cookie);
1372                 data->host_cookie = 0;
1373         }
1374
1375         /* Check if next job is already prepared */
1376         if (next || data->host_cookie != host->next_data.cookie) {
1377                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1378                                      omap_hsmmc_get_dma_dir(host, data));
1379
1380         } else {
1381                 dma_len = host->next_data.dma_len;
1382                 host->next_data.dma_len = 0;
1383         }
1384
1385
1386         if (dma_len == 0)
1387                 return -EINVAL;
1388
1389         if (next) {
1390                 next->dma_len = dma_len;
1391                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1392         } else
1393                 host->dma_len = dma_len;
1394
1395         return 0;
1396 }
1397
1398 /*
1399  * Routine to configure and start DMA for the MMC card
1400  */
1401 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1402                                         struct mmc_request *req)
1403 {
1404         struct dma_slave_config cfg;
1405         struct dma_async_tx_descriptor *tx;
1406         int ret = 0, i;
1407         struct mmc_data *data = req->data;
1408         struct dma_chan *chan;
1409
1410         /* Sanity check: all the SG entries must be aligned by block size. */
1411         for (i = 0; i < data->sg_len; i++) {
1412                 struct scatterlist *sgl;
1413
1414                 sgl = data->sg + i;
1415                 if (sgl->length % data->blksz)
1416                         return -EINVAL;
1417         }
1418         if ((data->blksz % 4) != 0)
1419                 /* REVISIT: The MMC buffer increments only when MSB is written.
1420                  * Return error for blksz which is non multiple of four.
1421                  */
1422                 return -EINVAL;
1423
1424         BUG_ON(host->dma_ch != -1);
1425
1426         chan = omap_hsmmc_get_dma_chan(host, data);
1427
1428         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1429         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1430         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1431         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1432         cfg.src_maxburst = data->blksz / 4;
1433         cfg.dst_maxburst = data->blksz / 4;
1434
1435         ret = dmaengine_slave_config(chan, &cfg);
1436         if (ret)
1437                 return ret;
1438
1439         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1440         if (ret)
1441                 return ret;
1442
1443         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1444                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1445                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1446         if (!tx) {
1447                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1448                 /* FIXME: cleanup */
1449                 return -1;
1450         }
1451
1452         tx->callback = omap_hsmmc_dma_callback;
1453         tx->callback_param = host;
1454
1455         /* Does not fail */
1456         dmaengine_submit(tx);
1457
1458         host->dma_ch = 1;
1459
1460         return 0;
1461 }
1462
1463 static void set_data_timeout(struct omap_hsmmc_host *host,
1464                              unsigned int timeout_ns,
1465                              unsigned int timeout_clks)
1466 {
1467         unsigned int timeout, cycle_ns;
1468         uint32_t reg, clkd, dto = 0;
1469
1470         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1471         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1472         if (clkd == 0)
1473                 clkd = 1;
1474
1475         cycle_ns = 1000000000 / (host->clk_rate / clkd);
1476         timeout = timeout_ns / cycle_ns;
1477         timeout += timeout_clks;
1478         if (timeout) {
1479                 while ((timeout & 0x80000000) == 0) {
1480                         dto += 1;
1481                         timeout <<= 1;
1482                 }
1483                 dto = 31 - dto;
1484                 timeout <<= 1;
1485                 if (timeout && dto)
1486                         dto += 1;
1487                 if (dto >= 13)
1488                         dto -= 13;
1489                 else
1490                         dto = 0;
1491                 if (dto > 14)
1492                         dto = 14;
1493         }
1494
1495         reg &= ~DTO_MASK;
1496         reg |= dto << DTO_SHIFT;
1497         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1498 }
1499
1500 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1501 {
1502         struct mmc_request *req = host->mrq;
1503         struct dma_chan *chan;
1504
1505         if (!req->data)
1506                 return;
1507         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1508                                 | (req->data->blocks << 16));
1509         set_data_timeout(host, req->data->timeout_ns,
1510                                 req->data->timeout_clks);
1511         chan = omap_hsmmc_get_dma_chan(host, req->data);
1512         dma_async_issue_pending(chan);
1513 }
1514
1515 /*
1516  * Configure block length for MMC/SD cards and initiate the transfer.
1517  */
1518 static int
1519 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1520 {
1521         int ret;
1522         host->data = req->data;
1523
1524         if (req->data == NULL) {
1525                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1526                 /*
1527                  * Set an arbitrary 100ms data timeout for commands with
1528                  * busy signal.
1529                  */
1530                 if (req->cmd->flags & MMC_RSP_BUSY)
1531                         set_data_timeout(host, 100000000U, 0);
1532                 return 0;
1533         }
1534
1535         if (host->use_dma) {
1536                 ret = omap_hsmmc_setup_dma_transfer(host, req);
1537                 if (ret != 0) {
1538                         dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1539                         return ret;
1540                 }
1541         }
1542         return 0;
1543 }
1544
1545 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1546                                 int err)
1547 {
1548         struct omap_hsmmc_host *host = mmc_priv(mmc);
1549         struct mmc_data *data = mrq->data;
1550
1551         if (host->use_dma && data->host_cookie) {
1552                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1553
1554                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1555                              omap_hsmmc_get_dma_dir(host, data));
1556                 data->host_cookie = 0;
1557         }
1558 }
1559
1560 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1561                                bool is_first_req)
1562 {
1563         struct omap_hsmmc_host *host = mmc_priv(mmc);
1564
1565         if (mrq->data->host_cookie) {
1566                 mrq->data->host_cookie = 0;
1567                 return ;
1568         }
1569
1570         if (host->use_dma) {
1571                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1572
1573                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1574                                                 &host->next_data, c))
1575                         mrq->data->host_cookie = 0;
1576         }
1577 }
1578
1579 /*
1580  * Request function. for read/write operation
1581  */
1582 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1583 {
1584         struct omap_hsmmc_host *host = mmc_priv(mmc);
1585         int err;
1586
1587         BUG_ON(host->req_in_progress);
1588         BUG_ON(host->dma_ch != -1);
1589         if (host->protect_card) {
1590                 if (host->reqs_blocked < 3) {
1591                         /*
1592                          * Ensure the controller is left in a consistent
1593                          * state by resetting the command and data state
1594                          * machines.
1595                          */
1596                         omap_hsmmc_reset_controller_fsm(host, SRD);
1597                         omap_hsmmc_reset_controller_fsm(host, SRC);
1598                         host->reqs_blocked += 1;
1599                 }
1600                 req->cmd->error = -EBADF;
1601                 if (req->data)
1602                         req->data->error = -EBADF;
1603                 req->cmd->retries = 0;
1604                 mmc_request_done(mmc, req);
1605                 return;
1606         } else if (host->reqs_blocked)
1607                 host->reqs_blocked = 0;
1608         WARN_ON(host->mrq != NULL);
1609         host->mrq = req;
1610         host->clk_rate = clk_get_rate(host->fclk);
1611         err = omap_hsmmc_prepare_data(host, req);
1612         if (err) {
1613                 req->cmd->error = err;
1614                 if (req->data)
1615                         req->data->error = err;
1616                 host->mrq = NULL;
1617                 mmc_request_done(mmc, req);
1618                 return;
1619         }
1620         if (req->sbc && !(host->flags & AUTO_CMD23)) {
1621                 omap_hsmmc_start_command(host, req->sbc, NULL);
1622                 return;
1623         }
1624
1625         omap_hsmmc_start_dma_transfer(host);
1626         omap_hsmmc_start_command(host, req->cmd, req->data);
1627 }
1628
1629 /* Routine to configure clock values. Exposed API to core */
1630 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1631 {
1632         struct omap_hsmmc_host *host = mmc_priv(mmc);
1633         int do_send_init_stream = 0;
1634
1635         pm_runtime_get_sync(host->dev);
1636
1637         if (ios->power_mode != host->power_mode) {
1638                 switch (ios->power_mode) {
1639                 case MMC_POWER_OFF:
1640                         mmc_pdata(host)->set_power(host->dev, 0, 0);
1641                         break;
1642                 case MMC_POWER_UP:
1643                         mmc_pdata(host)->set_power(host->dev, 1, ios->vdd);
1644                         break;
1645                 case MMC_POWER_ON:
1646                         do_send_init_stream = 1;
1647                         break;
1648                 }
1649                 host->power_mode = ios->power_mode;
1650         }
1651
1652         /* FIXME: set registers based only on changes to ios */
1653
1654         omap_hsmmc_set_bus_width(host);
1655
1656         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1657                 /* Only MMC1 can interface at 3V without some flavor
1658                  * of external transceiver; but they all handle 1.8V.
1659                  */
1660                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1661                         (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1662                                 /*
1663                                  * The mmc_select_voltage fn of the core does
1664                                  * not seem to set the power_mode to
1665                                  * MMC_POWER_UP upon recalculating the voltage.
1666                                  * vdd 1.8v.
1667                                  */
1668                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1669                                 dev_dbg(mmc_dev(host->mmc),
1670                                                 "Switch operation failed\n");
1671                 }
1672         }
1673
1674         omap_hsmmc_set_clock(host);
1675
1676         if (do_send_init_stream)
1677                 send_init_stream(host);
1678
1679         omap_hsmmc_set_bus_mode(host);
1680
1681         pm_runtime_put_autosuspend(host->dev);
1682 }
1683
1684 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1685 {
1686         struct omap_hsmmc_host *host = mmc_priv(mmc);
1687
1688         if (!host->card_detect)
1689                 return -ENOSYS;
1690         return host->card_detect(host->dev);
1691 }
1692
1693 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1694 {
1695         struct omap_hsmmc_host *host = mmc_priv(mmc);
1696
1697         if (!host->get_ro)
1698                 return -ENOSYS;
1699         return host->get_ro(host->dev);
1700 }
1701
1702 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1703 {
1704         struct omap_hsmmc_host *host = mmc_priv(mmc);
1705
1706         if (mmc_pdata(host)->init_card)
1707                 mmc_pdata(host)->init_card(card);
1708 }
1709
1710 static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1711 {
1712         struct omap_hsmmc_host *host = mmc_priv(mmc);
1713         u32 irq_mask, con;
1714         unsigned long flags;
1715
1716         spin_lock_irqsave(&host->irq_lock, flags);
1717
1718         con = OMAP_HSMMC_READ(host->base, CON);
1719         irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1720         if (enable) {
1721                 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1722                 irq_mask |= CIRQ_EN;
1723                 con |= CTPL | CLKEXTFREE;
1724         } else {
1725                 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1726                 irq_mask &= ~CIRQ_EN;
1727                 con &= ~(CTPL | CLKEXTFREE);
1728         }
1729         OMAP_HSMMC_WRITE(host->base, CON, con);
1730         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1731
1732         /*
1733          * if enable, piggy back detection on current request
1734          * but always disable immediately
1735          */
1736         if (!host->req_in_progress || !enable)
1737                 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1738
1739         /* flush posted write */
1740         OMAP_HSMMC_READ(host->base, IE);
1741
1742         spin_unlock_irqrestore(&host->irq_lock, flags);
1743 }
1744
1745 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1746 {
1747         struct mmc_host *mmc = host->mmc;
1748         int ret;
1749
1750         /*
1751          * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1752          * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1753          * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1754          * with functional clock disabled.
1755          */
1756         if (!host->dev->of_node || !host->wake_irq)
1757                 return -ENODEV;
1758
1759         /* Prevent auto-enabling of IRQ */
1760         irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN);
1761         ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq,
1762                                IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1763                                mmc_hostname(mmc), host);
1764         if (ret) {
1765                 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1766                 goto err;
1767         }
1768
1769         /*
1770          * Some omaps don't have wake-up path from deeper idle states
1771          * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1772          */
1773         if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1774                 struct pinctrl *p = devm_pinctrl_get(host->dev);
1775                 if (!p) {
1776                         ret = -ENODEV;
1777                         goto err_free_irq;
1778                 }
1779                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1780                         dev_info(host->dev, "missing default pinctrl state\n");
1781                         devm_pinctrl_put(p);
1782                         ret = -EINVAL;
1783                         goto err_free_irq;
1784                 }
1785
1786                 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1787                         dev_info(host->dev, "missing idle pinctrl state\n");
1788                         devm_pinctrl_put(p);
1789                         ret = -EINVAL;
1790                         goto err_free_irq;
1791                 }
1792                 devm_pinctrl_put(p);
1793         }
1794
1795         OMAP_HSMMC_WRITE(host->base, HCTL,
1796                          OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1797         return 0;
1798
1799 err_free_irq:
1800         devm_free_irq(host->dev, host->wake_irq, host);
1801 err:
1802         dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1803         host->wake_irq = 0;
1804         return ret;
1805 }
1806
1807 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1808 {
1809         u32 hctl, capa, value;
1810
1811         /* Only MMC1 supports 3.0V */
1812         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1813                 hctl = SDVS30;
1814                 capa = VS30 | VS18;
1815         } else {
1816                 hctl = SDVS18;
1817                 capa = VS18;
1818         }
1819
1820         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1821         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1822
1823         value = OMAP_HSMMC_READ(host->base, CAPA);
1824         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1825
1826         /* Set SD bus power bit */
1827         set_sd_bus_power(host);
1828 }
1829
1830 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1831 {
1832         struct omap_hsmmc_host *host = mmc_priv(mmc);
1833
1834         pm_runtime_get_sync(host->dev);
1835
1836         return 0;
1837 }
1838
1839 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1840 {
1841         struct omap_hsmmc_host *host = mmc_priv(mmc);
1842
1843         pm_runtime_mark_last_busy(host->dev);
1844         pm_runtime_put_autosuspend(host->dev);
1845
1846         return 0;
1847 }
1848
1849 static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1850                                      unsigned int direction, int blk_size)
1851 {
1852         /* This controller can't do multiblock reads due to hw bugs */
1853         if (direction == MMC_DATA_READ)
1854                 return 1;
1855
1856         return blk_size;
1857 }
1858
1859 static struct mmc_host_ops omap_hsmmc_ops = {
1860         .enable = omap_hsmmc_enable_fclk,
1861         .disable = omap_hsmmc_disable_fclk,
1862         .post_req = omap_hsmmc_post_req,
1863         .pre_req = omap_hsmmc_pre_req,
1864         .request = omap_hsmmc_request,
1865         .set_ios = omap_hsmmc_set_ios,
1866         .get_cd = omap_hsmmc_get_cd,
1867         .get_ro = omap_hsmmc_get_ro,
1868         .init_card = omap_hsmmc_init_card,
1869         .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1870 };
1871
1872 #ifdef CONFIG_DEBUG_FS
1873
1874 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1875 {
1876         struct mmc_host *mmc = s->private;
1877         struct omap_hsmmc_host *host = mmc_priv(mmc);
1878
1879         seq_printf(s, "mmc%d:\n", mmc->index);
1880         seq_printf(s, "sdio irq mode\t%s\n",
1881                    (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1882
1883         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1884                 seq_printf(s, "sdio irq \t%s\n",
1885                            (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1886                            : "disabled");
1887         }
1888         seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1889
1890         pm_runtime_get_sync(host->dev);
1891         seq_puts(s, "\nregs:\n");
1892         seq_printf(s, "CON:\t\t0x%08x\n",
1893                         OMAP_HSMMC_READ(host->base, CON));
1894         seq_printf(s, "PSTATE:\t\t0x%08x\n",
1895                    OMAP_HSMMC_READ(host->base, PSTATE));
1896         seq_printf(s, "HCTL:\t\t0x%08x\n",
1897                         OMAP_HSMMC_READ(host->base, HCTL));
1898         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1899                         OMAP_HSMMC_READ(host->base, SYSCTL));
1900         seq_printf(s, "IE:\t\t0x%08x\n",
1901                         OMAP_HSMMC_READ(host->base, IE));
1902         seq_printf(s, "ISE:\t\t0x%08x\n",
1903                         OMAP_HSMMC_READ(host->base, ISE));
1904         seq_printf(s, "CAPA:\t\t0x%08x\n",
1905                         OMAP_HSMMC_READ(host->base, CAPA));
1906
1907         pm_runtime_mark_last_busy(host->dev);
1908         pm_runtime_put_autosuspend(host->dev);
1909
1910         return 0;
1911 }
1912
1913 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1914 {
1915         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1916 }
1917
1918 static const struct file_operations mmc_regs_fops = {
1919         .open           = omap_hsmmc_regs_open,
1920         .read           = seq_read,
1921         .llseek         = seq_lseek,
1922         .release        = single_release,
1923 };
1924
1925 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1926 {
1927         if (mmc->debugfs_root)
1928                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1929                         mmc, &mmc_regs_fops);
1930 }
1931
1932 #else
1933
1934 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1935 {
1936 }
1937
1938 #endif
1939
1940 #ifdef CONFIG_OF
1941 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1942         /* See 35xx errata 2.1.1.128 in SPRZ278F */
1943         .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1944 };
1945
1946 static const struct omap_mmc_of_data omap4_mmc_of_data = {
1947         .reg_offset = 0x100,
1948 };
1949 static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1950         .reg_offset = 0x100,
1951         .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1952 };
1953
1954 static const struct of_device_id omap_mmc_of_match[] = {
1955         {
1956                 .compatible = "ti,omap2-hsmmc",
1957         },
1958         {
1959                 .compatible = "ti,omap3-pre-es3-hsmmc",
1960                 .data = &omap3_pre_es3_mmc_of_data,
1961         },
1962         {
1963                 .compatible = "ti,omap3-hsmmc",
1964         },
1965         {
1966                 .compatible = "ti,omap4-hsmmc",
1967                 .data = &omap4_mmc_of_data,
1968         },
1969         {
1970                 .compatible = "ti,am33xx-hsmmc",
1971                 .data = &am33xx_mmc_of_data,
1972         },
1973         {},
1974 };
1975 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1976
1977 static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1978 {
1979         struct omap_hsmmc_platform_data *pdata;
1980         struct device_node *np = dev->of_node;
1981         u32 bus_width, max_freq;
1982         int cd_gpio, wp_gpio;
1983
1984         cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
1985         wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1986         if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
1987                 return ERR_PTR(-EPROBE_DEFER);
1988
1989         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1990         if (!pdata)
1991                 return ERR_PTR(-ENOMEM); /* out of memory */
1992
1993         if (of_find_property(np, "ti,dual-volt", NULL))
1994                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1995
1996         pdata->switch_pin = cd_gpio;
1997         pdata->gpio_wp = wp_gpio;
1998
1999         if (of_find_property(np, "ti,non-removable", NULL)) {
2000                 pdata->nonremovable = true;
2001                 pdata->no_regulator_off_init = true;
2002         }
2003         of_property_read_u32(np, "bus-width", &bus_width);
2004         if (bus_width == 4)
2005                 pdata->caps |= MMC_CAP_4_BIT_DATA;
2006         else if (bus_width == 8)
2007                 pdata->caps |= MMC_CAP_8_BIT_DATA;
2008
2009         if (of_find_property(np, "ti,needs-special-reset", NULL))
2010                 pdata->features |= HSMMC_HAS_UPDATED_RESET;
2011
2012         if (!of_property_read_u32(np, "max-frequency", &max_freq))
2013                 pdata->max_freq = max_freq;
2014
2015         if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
2016                 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
2017
2018         if (of_find_property(np, "keep-power-in-suspend", NULL))
2019                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2020
2021         if (of_find_property(np, "enable-sdio-wakeup", NULL))
2022                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2023
2024         return pdata;
2025 }
2026 #else
2027 static inline struct omap_hsmmc_platform_data
2028                         *of_get_hsmmc_pdata(struct device *dev)
2029 {
2030         return ERR_PTR(-EINVAL);
2031 }
2032 #endif
2033
2034 static int omap_hsmmc_probe(struct platform_device *pdev)
2035 {
2036         struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
2037         struct mmc_host *mmc;
2038         struct omap_hsmmc_host *host = NULL;
2039         struct resource *res;
2040         int ret, irq;
2041         const struct of_device_id *match;
2042         dma_cap_mask_t mask;
2043         unsigned tx_req, rx_req;
2044         const struct omap_mmc_of_data *data;
2045         void __iomem *base;
2046
2047         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2048         if (match) {
2049                 pdata = of_get_hsmmc_pdata(&pdev->dev);
2050
2051                 if (IS_ERR(pdata))
2052                         return PTR_ERR(pdata);
2053
2054                 if (match->data) {
2055                         data = match->data;
2056                         pdata->reg_offset = data->reg_offset;
2057                         pdata->controller_flags |= data->controller_flags;
2058                 }
2059         }
2060
2061         if (pdata == NULL) {
2062                 dev_err(&pdev->dev, "Platform Data is missing\n");
2063                 return -ENXIO;
2064         }
2065
2066         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2067         irq = platform_get_irq(pdev, 0);
2068         if (res == NULL || irq < 0)
2069                 return -ENXIO;
2070
2071         base = devm_ioremap_resource(&pdev->dev, res);
2072         if (IS_ERR(base))
2073                 return PTR_ERR(base);
2074
2075         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2076         if (!mmc) {
2077                 ret = -ENOMEM;
2078                 goto err;
2079         }
2080
2081         host            = mmc_priv(mmc);
2082         host->mmc       = mmc;
2083         host->pdata     = pdata;
2084         host->dev       = &pdev->dev;
2085         host->use_dma   = 1;
2086         host->dma_ch    = -1;
2087         host->irq       = irq;
2088         host->mapbase   = res->start + pdata->reg_offset;
2089         host->base      = base + pdata->reg_offset;
2090         host->power_mode = MMC_POWER_OFF;
2091         host->next_data.cookie = 1;
2092         host->pbias_enabled = 0;
2093
2094         ret = omap_hsmmc_gpio_init(host, pdata);
2095         if (ret)
2096                 goto err_gpio;
2097
2098         platform_set_drvdata(pdev, host);
2099
2100         if (pdev->dev.of_node)
2101                 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2102
2103         mmc->ops        = &omap_hsmmc_ops;
2104
2105         mmc->f_min = OMAP_MMC_MIN_CLOCK;
2106
2107         if (pdata->max_freq > 0)
2108                 mmc->f_max = pdata->max_freq;
2109         else
2110                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2111
2112         spin_lock_init(&host->irq_lock);
2113
2114         host->fclk = devm_clk_get(&pdev->dev, "fck");
2115         if (IS_ERR(host->fclk)) {
2116                 ret = PTR_ERR(host->fclk);
2117                 host->fclk = NULL;
2118                 goto err1;
2119         }
2120
2121         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2122                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2123                 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
2124         }
2125
2126         pm_runtime_enable(host->dev);
2127         pm_runtime_get_sync(host->dev);
2128         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2129         pm_runtime_use_autosuspend(host->dev);
2130
2131         omap_hsmmc_context_save(host);
2132
2133         host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2134         /*
2135          * MMC can still work without debounce clock.
2136          */
2137         if (IS_ERR(host->dbclk)) {
2138                 host->dbclk = NULL;
2139         } else if (clk_prepare_enable(host->dbclk) != 0) {
2140                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2141                 host->dbclk = NULL;
2142         }
2143
2144         /* Since we do only SG emulation, we can have as many segs
2145          * as we want. */
2146         mmc->max_segs = 1024;
2147
2148         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2149         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2150         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2151         mmc->max_seg_size = mmc->max_req_size;
2152
2153         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2154                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2155
2156         mmc->caps |= mmc_pdata(host)->caps;
2157         if (mmc->caps & MMC_CAP_8_BIT_DATA)
2158                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2159
2160         if (mmc_pdata(host)->nonremovable)
2161                 mmc->caps |= MMC_CAP_NONREMOVABLE;
2162
2163         mmc->pm_caps = mmc_pdata(host)->pm_caps;
2164
2165         omap_hsmmc_conf_bus_power(host);
2166
2167         if (!pdev->dev.of_node) {
2168                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2169                 if (!res) {
2170                         dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2171                         ret = -ENXIO;
2172                         goto err_irq;
2173                 }
2174                 tx_req = res->start;
2175
2176                 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2177                 if (!res) {
2178                         dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2179                         ret = -ENXIO;
2180                         goto err_irq;
2181                 }
2182                 rx_req = res->start;
2183         }
2184
2185         dma_cap_zero(mask);
2186         dma_cap_set(DMA_SLAVE, mask);
2187
2188         host->rx_chan =
2189                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2190                                                  &rx_req, &pdev->dev, "rx");
2191
2192         if (!host->rx_chan) {
2193                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
2194                 ret = -ENXIO;
2195                 goto err_irq;
2196         }
2197
2198         host->tx_chan =
2199                 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2200                                                  &tx_req, &pdev->dev, "tx");
2201
2202         if (!host->tx_chan) {
2203                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
2204                 ret = -ENXIO;
2205                 goto err_irq;
2206         }
2207
2208         /* Request IRQ for MMC operations */
2209         ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2210                         mmc_hostname(mmc), host);
2211         if (ret) {
2212                 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2213                 goto err_irq;
2214         }
2215
2216         if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) {
2217                 ret = omap_hsmmc_reg_get(host);
2218                 if (ret)
2219                         goto err_irq;
2220                 host->use_reg = 1;
2221         }
2222
2223         mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2224
2225         /* Request IRQ for card detect */
2226         if (host->card_detect_irq) {
2227                 ret = devm_request_threaded_irq(&pdev->dev,
2228                                                 host->card_detect_irq,
2229                                                 NULL, omap_hsmmc_detect,
2230                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2231                                            mmc_hostname(mmc), host);
2232                 if (ret) {
2233                         dev_err(mmc_dev(host->mmc),
2234                                 "Unable to grab MMC CD IRQ\n");
2235                         goto err_irq_cd;
2236                 }
2237                 host->suspend = omap_hsmmc_suspend_cdirq;
2238                 host->resume = omap_hsmmc_resume_cdirq;
2239         }
2240
2241         omap_hsmmc_disable_irq(host);
2242
2243         /*
2244          * For now, only support SDIO interrupt if we have a separate
2245          * wake-up interrupt configured from device tree. This is because
2246          * the wake-up interrupt is needed for idle state and some
2247          * platforms need special quirks. And we don't want to add new
2248          * legacy mux platform init code callbacks any longer as we
2249          * are moving to DT based booting anyways.
2250          */
2251         ret = omap_hsmmc_configure_wake_irq(host);
2252         if (!ret)
2253                 mmc->caps |= MMC_CAP_SDIO_IRQ;
2254
2255         omap_hsmmc_protect_card(host);
2256
2257         mmc_add_host(mmc);
2258
2259         if (mmc_pdata(host)->name != NULL) {
2260                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2261                 if (ret < 0)
2262                         goto err_slot_name;
2263         }
2264         if (host->card_detect_irq && host->get_cover_state) {
2265                 ret = device_create_file(&mmc->class_dev,
2266                                         &dev_attr_cover_switch);
2267                 if (ret < 0)
2268                         goto err_slot_name;
2269         }
2270
2271         omap_hsmmc_debugfs(mmc);
2272         pm_runtime_mark_last_busy(host->dev);
2273         pm_runtime_put_autosuspend(host->dev);
2274
2275         return 0;
2276
2277 err_slot_name:
2278         mmc_remove_host(mmc);
2279 err_irq_cd:
2280         if (host->use_reg)
2281                 omap_hsmmc_reg_put(host);
2282 err_irq:
2283         if (host->tx_chan)
2284                 dma_release_channel(host->tx_chan);
2285         if (host->rx_chan)
2286                 dma_release_channel(host->rx_chan);
2287         pm_runtime_put_sync(host->dev);
2288         pm_runtime_disable(host->dev);
2289         if (host->dbclk)
2290                 clk_disable_unprepare(host->dbclk);
2291 err1:
2292         omap_hsmmc_gpio_free(host, pdata);
2293 err_gpio:
2294         mmc_free_host(mmc);
2295 err:
2296         return ret;
2297 }
2298
2299 static int omap_hsmmc_remove(struct platform_device *pdev)
2300 {
2301         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2302
2303         pm_runtime_get_sync(host->dev);
2304         mmc_remove_host(host->mmc);
2305         if (host->use_reg)
2306                 omap_hsmmc_reg_put(host);
2307
2308         if (host->tx_chan)
2309                 dma_release_channel(host->tx_chan);
2310         if (host->rx_chan)
2311                 dma_release_channel(host->rx_chan);
2312
2313         pm_runtime_put_sync(host->dev);
2314         pm_runtime_disable(host->dev);
2315         if (host->dbclk)
2316                 clk_disable_unprepare(host->dbclk);
2317
2318         omap_hsmmc_gpio_free(host, host->pdata);
2319         mmc_free_host(host->mmc);
2320
2321         return 0;
2322 }
2323
2324 #ifdef CONFIG_PM
2325 static int omap_hsmmc_prepare(struct device *dev)
2326 {
2327         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2328
2329         if (host->suspend)
2330                 return host->suspend(dev);
2331
2332         return 0;
2333 }
2334
2335 static void omap_hsmmc_complete(struct device *dev)
2336 {
2337         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2338
2339         if (host->resume)
2340                 host->resume(dev);
2341
2342 }
2343
2344 static int omap_hsmmc_suspend(struct device *dev)
2345 {
2346         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2347
2348         if (!host)
2349                 return 0;
2350
2351         pm_runtime_get_sync(host->dev);
2352
2353         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2354                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2355                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2356                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2357                 OMAP_HSMMC_WRITE(host->base, HCTL,
2358                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2359         }
2360
2361         /* do not wake up due to sdio irq */
2362         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2363             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2364                 disable_irq(host->wake_irq);
2365
2366         if (host->dbclk)
2367                 clk_disable_unprepare(host->dbclk);
2368
2369         pm_runtime_put_sync(host->dev);
2370         return 0;
2371 }
2372
2373 /* Routine to resume the MMC device */
2374 static int omap_hsmmc_resume(struct device *dev)
2375 {
2376         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2377
2378         if (!host)
2379                 return 0;
2380
2381         pm_runtime_get_sync(host->dev);
2382
2383         if (host->dbclk)
2384                 clk_prepare_enable(host->dbclk);
2385
2386         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2387                 omap_hsmmc_conf_bus_power(host);
2388
2389         omap_hsmmc_protect_card(host);
2390
2391         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2392             !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ))
2393                 enable_irq(host->wake_irq);
2394
2395         pm_runtime_mark_last_busy(host->dev);
2396         pm_runtime_put_autosuspend(host->dev);
2397         return 0;
2398 }
2399
2400 #else
2401 #define omap_hsmmc_prepare      NULL
2402 #define omap_hsmmc_complete     NULL
2403 #define omap_hsmmc_suspend      NULL
2404 #define omap_hsmmc_resume       NULL
2405 #endif
2406
2407 static int omap_hsmmc_runtime_suspend(struct device *dev)
2408 {
2409         struct omap_hsmmc_host *host;
2410         unsigned long flags;
2411         int ret = 0;
2412
2413         host = platform_get_drvdata(to_platform_device(dev));
2414         omap_hsmmc_context_save(host);
2415         dev_dbg(dev, "disabled\n");
2416
2417         spin_lock_irqsave(&host->irq_lock, flags);
2418         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2419             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2420                 /* disable sdio irq handling to prevent race */
2421                 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2422                 OMAP_HSMMC_WRITE(host->base, IE, 0);
2423
2424                 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2425                         /*
2426                          * dat1 line low, pending sdio irq
2427                          * race condition: possible irq handler running on
2428                          * multi-core, abort
2429                          */
2430                         dev_dbg(dev, "pending sdio irq, abort suspend\n");
2431                         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2432                         OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2433                         OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2434                         pm_runtime_mark_last_busy(dev);
2435                         ret = -EBUSY;
2436                         goto abort;
2437                 }
2438
2439                 pinctrl_pm_select_idle_state(dev);
2440
2441                 WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED);
2442                 enable_irq(host->wake_irq);
2443                 host->flags |= HSMMC_WAKE_IRQ_ENABLED;
2444         } else {
2445                 pinctrl_pm_select_idle_state(dev);
2446         }
2447
2448 abort:
2449         spin_unlock_irqrestore(&host->irq_lock, flags);
2450         return ret;
2451 }
2452
2453 static int omap_hsmmc_runtime_resume(struct device *dev)
2454 {
2455         struct omap_hsmmc_host *host;
2456         unsigned long flags;
2457
2458         host = platform_get_drvdata(to_platform_device(dev));
2459         omap_hsmmc_context_restore(host);
2460         dev_dbg(dev, "enabled\n");
2461
2462         spin_lock_irqsave(&host->irq_lock, flags);
2463         if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2464             (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2465                 /* sdio irq flag can't change while in runtime suspend */
2466                 if (host->flags & HSMMC_WAKE_IRQ_ENABLED) {
2467                         disable_irq_nosync(host->wake_irq);
2468                         host->flags &= ~HSMMC_WAKE_IRQ_ENABLED;
2469                 }
2470
2471                 pinctrl_pm_select_default_state(host->dev);
2472
2473                 /* irq lost, if pinmux incorrect */
2474                 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2475                 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2476                 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2477         } else {
2478                 pinctrl_pm_select_default_state(host->dev);
2479         }
2480         spin_unlock_irqrestore(&host->irq_lock, flags);
2481         return 0;
2482 }
2483
2484 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2485         .suspend        = omap_hsmmc_suspend,
2486         .resume         = omap_hsmmc_resume,
2487         .prepare        = omap_hsmmc_prepare,
2488         .complete       = omap_hsmmc_complete,
2489         .runtime_suspend = omap_hsmmc_runtime_suspend,
2490         .runtime_resume = omap_hsmmc_runtime_resume,
2491 };
2492
2493 static struct platform_driver omap_hsmmc_driver = {
2494         .probe          = omap_hsmmc_probe,
2495         .remove         = omap_hsmmc_remove,
2496         .driver         = {
2497                 .name = DRIVER_NAME,
2498                 .pm = &omap_hsmmc_dev_pm_ops,
2499                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2500         },
2501 };
2502
2503 module_platform_driver(omap_hsmmc_driver);
2504 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2505 MODULE_LICENSE("GPL");
2506 MODULE_ALIAS("platform:" DRIVER_NAME);
2507 MODULE_AUTHOR("Texas Instruments Inc");