drivers/mmc/host/s3cmci.c

   1 /*
   2  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   3  *
   4  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
   5  *
   6  * Current driver maintained by Ben Dooks and Simtec Electronics
   7  *  Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/clk.h>
  18 #include <linux/mmc/host.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/cpufreq.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/gpio.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/gpio-cfg.h>
  28 #include <mach/dma.h>
  29 #include <mach/gpio-samsung.h>
  30
  31 #include <linux/platform_data/dma-s3c24xx.h>
  32 #include <linux/platform_data/mmc-s3cmci.h>
  33
  34 #include "s3cmci.h"
  35
  36 #define DRIVER_NAME "s3c-mci"
  37
  38 #define S3C2410_SDICON                  (0x00)
  39 #define S3C2410_SDIPRE                  (0x04)
  40 #define S3C2410_SDICMDARG               (0x08)
  41 #define S3C2410_SDICMDCON               (0x0C)
  42 #define S3C2410_SDICMDSTAT              (0x10)
  43 #define S3C2410_SDIRSP0                 (0x14)
  44 #define S3C2410_SDIRSP1                 (0x18)
  45 #define S3C2410_SDIRSP2                 (0x1C)
  46 #define S3C2410_SDIRSP3                 (0x20)
  47 #define S3C2410_SDITIMER                (0x24)
  48 #define S3C2410_SDIBSIZE                (0x28)
  49 #define S3C2410_SDIDCON                 (0x2C)
  50 #define S3C2410_SDIDCNT                 (0x30)
  51 #define S3C2410_SDIDSTA                 (0x34)
  52 #define S3C2410_SDIFSTA                 (0x38)
  53
  54 #define S3C2410_SDIDATA                 (0x3C)
  55 #define S3C2410_SDIIMSK                 (0x40)
  56
  57 #define S3C2440_SDIDATA                 (0x40)
  58 #define S3C2440_SDIIMSK                 (0x3C)
  59
  60 #define S3C2440_SDICON_SDRESET          (1 << 8)
  61 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  62 #define S3C2410_SDICON_FIFORESET        (1 << 1)
  63 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  64
  65 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  66 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  67 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  68 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  69 #define S3C2410_SDICMDCON_INDEX         (0x3f)
  70
  71 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  72 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  73 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  74 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  75
  76 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  77 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  78 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  79 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  80 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  81 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
  82 #define S3C2410_SDIDCON_STOP            (1 << 14)
  83 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
  84
  85 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  86 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  87
  88 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  89
  90 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  91 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  92 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  93 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  94 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  95 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
  96 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
  97 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
  98
  99 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
 100 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
 101 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
 102 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
 103 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
 104
 105 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 106 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 107 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 108 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 109 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 110 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 111 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 112 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 113 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 114 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 115 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 116 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 117 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 118
 119 enum dbg_channels {
 120         dbg_err   = (1 << 0),
 121         dbg_debug = (1 << 1),
 122         dbg_info  = (1 << 2),
 123         dbg_irq   = (1 << 3),
 124         dbg_sg    = (1 << 4),
 125         dbg_dma   = (1 << 5),
 126         dbg_pio   = (1 << 6),
 127         dbg_fail  = (1 << 7),
 128         dbg_conf  = (1 << 8),
 129 };
 130
 131 static const int dbgmap_err   = dbg_fail;
 132 static const int dbgmap_info  = dbg_info | dbg_conf;
 133 static const int dbgmap_debug = dbg_err | dbg_debug;
 134
 135 #define dbg(host, channels, args...)              \
 136         do {                                      \
 137         if (dbgmap_err & channels)                \
 138                 dev_err(&host->pdev->dev, args);  \
 139         else if (dbgmap_info & channels)          \
 140                 dev_info(&host->pdev->dev, args); \
 141         else if (dbgmap_debug & channels)         \
 142                 dev_dbg(&host->pdev->dev, args);  \
 143         } while (0)
 144
 145 static void finalize_request(struct s3cmci_host *host);
 146 static void s3cmci_send_request(struct mmc_host *mmc);
 147 static void s3cmci_reset(struct s3cmci_host *host);
 148
 149 #ifdef CONFIG_MMC_DEBUG
 150
 151 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 152 {
 153         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
 154         u32 datcon, datcnt, datsta, fsta, imask;
 155
 156         con     = readl(host->base + S3C2410_SDICON);
 157         pre     = readl(host->base + S3C2410_SDIPRE);
 158         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 159         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 160         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 161         r0      = readl(host->base + S3C2410_SDIRSP0);
 162         r1      = readl(host->base + S3C2410_SDIRSP1);
 163         r2      = readl(host->base + S3C2410_SDIRSP2);
 164         r3      = readl(host->base + S3C2410_SDIRSP3);
 165         timer   = readl(host->base + S3C2410_SDITIMER);
 166         bsize   = readl(host->base + S3C2410_SDIBSIZE);
 167         datcon  = readl(host->base + S3C2410_SDIDCON);
 168         datcnt  = readl(host->base + S3C2410_SDIDCNT);
 169         datsta  = readl(host->base + S3C2410_SDIDSTA);
 170         fsta    = readl(host->base + S3C2410_SDIFSTA);
 171         imask   = readl(host->base + host->sdiimsk);
 172
 173         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 174                                 prefix, con, pre, timer);
 175
 176         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 177                                 prefix, cmdcon, cmdarg, cmdsta);
 178
 179         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 180                                " DSTA:[%08x] DCNT:[%08x]\n",
 181                                 prefix, datcon, fsta, datsta, datcnt);
 182
 183         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 184                                "   R2:[%08x]   R3:[%08x]\n",
 185                                 prefix, r0, r1, r2, r3);
 186 }
 187
 188 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 189                            int stop)
 190 {
 191         snprintf(host->dbgmsg_cmd, 300,
 192                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 193                  host->ccnt, (stop ? " (STOP)" : ""),
 194                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 195
 196         if (cmd->data) {
 197                 snprintf(host->dbgmsg_dat, 300,
 198                          "#%u bsize:%u blocks:%u bytes:%u",
 199                          host->dcnt, cmd->data->blksz,
 200                          cmd->data->blocks,
 201                          cmd->data->blocks * cmd->data->blksz);
 202         } else {
 203                 host->dbgmsg_dat[0] = '\0';
 204         }
 205 }
 206
 207 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 208                         int fail)
 209 {
 210         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 211
 212         if (!cmd)
 213                 return;
 214
 215         if (cmd->error == 0) {
 216                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 217                         host->dbgmsg_cmd, cmd->resp[0]);
 218         } else {
 219                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 220                         cmd->error, host->dbgmsg_cmd, host->status);
 221         }
 222
 223         if (!cmd->data)
 224                 return;
 225
 226         if (cmd->data->error == 0) {
 227                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 228         } else {
 229                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 230                         cmd->data->error, host->dbgmsg_dat,
 231                         readl(host->base + S3C2410_SDIDCNT));
 232         }
 233 }
 234 #else
 235 static void dbg_dumpcmd(struct s3cmci_host *host,
 236                         struct mmc_command *cmd, int fail) { }
 237
 238 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 239                            int stop) { }
 240
 241 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 242
 243 #endif /* CONFIG_MMC_DEBUG */
 244
 245 /**
 246  * s3cmci_host_usedma - return whether the host is using dma or pio
 247  * @host: The host state
 248  *
 249  * Return true if the host is using DMA to transfer data, else false
 250  * to use PIO mode. Will return static data depending on the driver
 251  * configuration.
 252  */
 253 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 254 {
 255 #ifdef CONFIG_MMC_S3C_PIO
 256         return false;
 257 #else /* CONFIG_MMC_S3C_DMA */
 258         return true;
 259 #endif
 260 }
 261
 262 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 263 {
 264         u32 newmask;
 265
 266         newmask = readl(host->base + host->sdiimsk);
 267         newmask |= imask;
 268
 269         writel(newmask, host->base + host->sdiimsk);
 270
 271         return newmask;
 272 }
 273
 274 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 275 {
 276         u32 newmask;
 277
 278         newmask = readl(host->base + host->sdiimsk);
 279         newmask &= ~imask;
 280
 281         writel(newmask, host->base + host->sdiimsk);
 282
 283         return newmask;
 284 }
 285
 286 static inline void clear_imask(struct s3cmci_host *host)
 287 {
 288         u32 mask = readl(host->base + host->sdiimsk);
 289
 290         /* preserve the SDIO IRQ mask state */
 291         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 292         writel(mask, host->base + host->sdiimsk);
 293 }
 294
 295 /**
 296  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 297  * @host: The host to check.
 298  *
 299  * Test to see if the SDIO interrupt is being signalled in case the
 300  * controller has failed to re-detect a card interrupt. Read GPE8 and
 301  * see if it is low and if so, signal a SDIO interrupt.
 302  *
 303  * This is currently called if a request is finished (we assume that the
 304  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 305  * already being indicated.
 306 */
 307 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 308 {
 309         if (host->sdio_irqen) {
 310                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 311                         pr_debug("%s: signalling irq\n", __func__);
 312                         mmc_signal_sdio_irq(host->mmc);
 313                 }
 314         }
 315 }
 316
 317 static inline int get_data_buffer(struct s3cmci_host *host,
 318                                   u32 *bytes, u32 **pointer)
 319 {
 320         struct scatterlist *sg;
 321
 322         if (host->pio_active == XFER_NONE)
 323                 return -EINVAL;
 324
 325         if ((!host->mrq) || (!host->mrq->data))
 326                 return -EINVAL;
 327
 328         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 329                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 330                       host->pio_sgptr, host->mrq->data->sg_len);
 331                 return -EBUSY;
 332         }
 333         sg = &host->mrq->data->sg[host->pio_sgptr];
 334
 335         *bytes = sg->length;
 336         *pointer = sg_virt(sg);
 337
 338         host->pio_sgptr++;
 339
 340         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 341             host->pio_sgptr, host->mrq->data->sg_len);
 342
 343         return 0;
 344 }
 345
 346 static inline u32 fifo_count(struct s3cmci_host *host)
 347 {
 348         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 349
 350         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 351         return fifostat;
 352 }
 353
 354 static inline u32 fifo_free(struct s3cmci_host *host)
 355 {
 356         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 357
 358         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 359         return 63 - fifostat;
 360 }
 361
 362 /**
 363  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 364  * @host: The device state.
 365  * @more: True if more IRQs are expected from transfer.
 366  *
 367  * Enable the main IRQ if needed after it has been disabled.
 368  *
 369  * The IRQ can be one of the following states:
 370  *      - disabled during IDLE
 371  *      - disabled whilst processing data
 372  *      - enabled during transfer
 373  *      - enabled whilst awaiting SDIO interrupt detection
 374  */
 375 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 376 {
 377         unsigned long flags;
 378         bool enable = false;
 379
 380         local_irq_save(flags);
 381
 382         host->irq_enabled = more;
 383         host->irq_disabled = false;
 384
 385         enable = more | host->sdio_irqen;
 386
 387         if (host->irq_state != enable) {
 388                 host->irq_state = enable;
 389
 390                 if (enable)
 391                         enable_irq(host->irq);
 392                 else
 393                         disable_irq(host->irq);
 394         }
 395
 396         local_irq_restore(flags);
 397 }
 398
 399 /**
 400  *
 401  */
 402 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 403 {
 404         unsigned long flags;
 405
 406         local_irq_save(flags);
 407
 408         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 409
 410         host->irq_disabled = transfer;
 411
 412         if (transfer && host->irq_state) {
 413                 host->irq_state = false;
 414                 disable_irq(host->irq);
 415         }
 416
 417         local_irq_restore(flags);
 418 }
 419
 420 static void do_pio_read(struct s3cmci_host *host)
 421 {
 422         int res;
 423         u32 fifo;
 424         u32 *ptr;
 425         u32 fifo_words;
 426         void __iomem *from_ptr;
 427
 428         /* write real prescaler to host, it might be set slow to fix */
 429         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 430
 431         from_ptr = host->base + host->sdidata;
 432
 433         while ((fifo = fifo_count(host))) {
 434                 if (!host->pio_bytes) {
 435                         res = get_data_buffer(host, &host->pio_bytes,
 436                                               &host->pio_ptr);
 437                         if (res) {
 438                                 host->pio_active = XFER_NONE;
 439                                 host->complete_what = COMPLETION_FINALIZE;
 440
 441                                 dbg(host, dbg_pio, "pio_read(): "
 442                                     "complete (no more data).\n");
 443                                 return;
 444                         }
 445
 446                         dbg(host, dbg_pio,
 447                             "pio_read(): new target: [%i]@[%p]\n",
 448                             host->pio_bytes, host->pio_ptr);
 449                 }
 450
 451                 dbg(host, dbg_pio,
 452                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 453                     fifo, host->pio_bytes,
 454                     readl(host->base + S3C2410_SDIDCNT));
 455
 456                 /* If we have reached the end of the block, we can
 457                  * read a word and get 1 to 3 bytes.  If we in the
 458                  * middle of the block, we have to read full words,
 459                  * otherwise we will write garbage, so round down to
 460                  * an even multiple of 4. */
 461                 if (fifo >= host->pio_bytes)
 462                         fifo = host->pio_bytes;
 463                 else
 464                         fifo -= fifo & 3;
 465
 466                 host->pio_bytes -= fifo;
 467                 host->pio_count += fifo;
 468
 469                 fifo_words = fifo >> 2;
 470                 ptr = host->pio_ptr;
 471                 while (fifo_words--)
 472                         *ptr++ = readl(from_ptr);
 473                 host->pio_ptr = ptr;
 474
 475                 if (fifo & 3) {
 476                         u32 n = fifo & 3;
 477                         u32 data = readl(from_ptr);
 478                         u8 *p = (u8 *)host->pio_ptr;
 479
 480                         while (n--) {
 481                                 *p++ = data;
 482                                 data >>= 8;
 483                         }
 484                 }
 485         }
 486
 487         if (!host->pio_bytes) {
 488                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 489                 if (res) {
 490                         dbg(host, dbg_pio,
 491                             "pio_read(): complete (no more buffers).\n");
 492                         host->pio_active = XFER_NONE;
 493                         host->complete_what = COMPLETION_FINALIZE;
 494
 495                         return;
 496                 }
 497         }
 498
 499         enable_imask(host,
 500                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 501 }
 502
 503 static void do_pio_write(struct s3cmci_host *host)
 504 {
 505         void __iomem *to_ptr;
 506         int res;
 507         u32 fifo;
 508         u32 *ptr;
 509
 510         to_ptr = host->base + host->sdidata;
 511
 512         while ((fifo = fifo_free(host)) > 3) {
 513                 if (!host->pio_bytes) {
 514                         res = get_data_buffer(host, &host->pio_bytes,
 515                                                         &host->pio_ptr);
 516                         if (res) {
 517                                 dbg(host, dbg_pio,
 518                                     "pio_write(): complete (no more data).\n");
 519                                 host->pio_active = XFER_NONE;
 520
 521                                 return;
 522                         }
 523
 524                         dbg(host, dbg_pio,
 525                             "pio_write(): new source: [%i]@[%p]\n",
 526                             host->pio_bytes, host->pio_ptr);
 527
 528                 }
 529
 530                 /* If we have reached the end of the block, we have to
 531                  * write exactly the remaining number of bytes.  If we
 532                  * in the middle of the block, we have to write full
 533                  * words, so round down to an even multiple of 4. */
 534                 if (fifo >= host->pio_bytes)
 535                         fifo = host->pio_bytes;
 536                 else
 537                         fifo -= fifo & 3;
 538
 539                 host->pio_bytes -= fifo;
 540                 host->pio_count += fifo;
 541
 542                 fifo = (fifo + 3) >> 2;
 543                 ptr = host->pio_ptr;
 544                 while (fifo--)
 545                         writel(*ptr++, to_ptr);
 546                 host->pio_ptr = ptr;
 547         }
 548
 549         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 550 }
 551
 552 static void pio_tasklet(unsigned long data)
 553 {
 554         struct s3cmci_host *host = (struct s3cmci_host *) data;
 555
 556         s3cmci_disable_irq(host, true);
 557
 558         if (host->pio_active == XFER_WRITE)
 559                 do_pio_write(host);
 560
 561         if (host->pio_active == XFER_READ)
 562                 do_pio_read(host);
 563
 564         if (host->complete_what == COMPLETION_FINALIZE) {
 565                 clear_imask(host);
 566                 if (host->pio_active != XFER_NONE) {
 567                         dbg(host, dbg_err, "unfinished %s "
 568                             "- pio_count:[%u] pio_bytes:[%u]\n",
 569                             (host->pio_active == XFER_READ) ? "read" : "write",
 570                             host->pio_count, host->pio_bytes);
 571
 572                         if (host->mrq->data)
 573                                 host->mrq->data->error = -EINVAL;
 574                 }
 575
 576                 s3cmci_enable_irq(host, false);
 577                 finalize_request(host);
 578         } else
 579                 s3cmci_enable_irq(host, true);
 580 }
 581
 582 /*
 583  * ISR for SDI Interface IRQ
 584  * Communication between driver and ISR works as follows:
 585  *   host->mrq                  points to current request
 586  *   host->complete_what        Indicates when the request is considered done
 587  *     COMPLETION_CMDSENT         when the command was sent
 588  *     COMPLETION_RSPFIN          when a response was received
 589  *     COMPLETION_XFERFINISH      when the data transfer is finished
 590  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 591  *   host->complete_request     is the completion-object the driver waits for
 592  *
 593  * 1) Driver sets up host->mrq and host->complete_what
 594  * 2) Driver prepares the transfer
 595  * 3) Driver enables interrupts
 596  * 4) Driver starts transfer
 597  * 5) Driver waits for host->complete_rquest
 598  * 6) ISR checks for request status (errors and success)
 599  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 600  * 7) ISR completes host->complete_request
 601  * 8) ISR disables interrupts
 602  * 9) Driver wakes up and takes care of the request
 603  *
 604  * Note: "->error"-fields are expected to be set to 0 before the request
 605  *       was issued by mmc.c - therefore they are only set, when an error
 606  *       contition comes up
 607  */
 608
 609 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 610 {
 611         struct s3cmci_host *host = dev_id;
 612         struct mmc_command *cmd;
 613         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 614         u32 mci_cclear = 0, mci_dclear;
 615         unsigned long iflags;
 616
 617         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 618         mci_imsk = readl(host->base + host->sdiimsk);
 619
 620         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 621                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 622                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 623                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 624
 625                         mmc_signal_sdio_irq(host->mmc);
 626                         return IRQ_HANDLED;
 627                 }
 628         }
 629
 630         spin_lock_irqsave(&host->complete_lock, iflags);
 631
 632         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 633         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 634         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 635         mci_dclear = 0;
 636
 637         if ((host->complete_what == COMPLETION_NONE) ||
 638             (host->complete_what == COMPLETION_FINALIZE)) {
 639                 host->status = "nothing to complete";
 640                 clear_imask(host);
 641                 goto irq_out;
 642         }
 643
 644         if (!host->mrq) {
 645                 host->status = "no active mrq";
 646                 clear_imask(host);
 647                 goto irq_out;
 648         }
 649
 650         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 651
 652         if (!cmd) {
 653                 host->status = "no active cmd";
 654                 clear_imask(host);
 655                 goto irq_out;
 656         }
 657
 658         if (!s3cmci_host_usedma(host)) {
 659                 if ((host->pio_active == XFER_WRITE) &&
 660                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 661
 662                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 663                         tasklet_schedule(&host->pio_tasklet);
 664                         host->status = "pio tx";
 665                 }
 666
 667                 if ((host->pio_active == XFER_READ) &&
 668                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 669
 670                         disable_imask(host,
 671                                       S3C2410_SDIIMSK_RXFIFOHALF |
 672                                       S3C2410_SDIIMSK_RXFIFOLAST);
 673
 674                         tasklet_schedule(&host->pio_tasklet);
 675                         host->status = "pio rx";
 676                 }
 677         }
 678
 679         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 680                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 681                 cmd->error = -ETIMEDOUT;
 682                 host->status = "error: command timeout";
 683                 goto fail_transfer;
 684         }
 685
 686         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 687                 if (host->complete_what == COMPLETION_CMDSENT) {
 688                         host->status = "ok: command sent";
 689                         goto close_transfer;
 690                 }
 691
 692                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 693         }
 694
 695         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 696                 if (cmd->flags & MMC_RSP_CRC) {
 697                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 698                                 dbg(host, dbg_irq,
 699                                     "fixup: ignore CRC fail with long rsp\n");
 700                         } else {
 701                                 /* note, we used to fail the transfer
 702                                  * here, but it seems that this is just
 703                                  * the hardware getting it wrong.
 704                                  *
 705                                  * cmd->error = -EILSEQ;
 706                                  * host->status = "error: bad command crc";
 707                                  * goto fail_transfer;
 708                                 */
 709                         }
 710                 }
 711
 712                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 713         }
 714
 715         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 716                 if (host->complete_what == COMPLETION_RSPFIN) {
 717                         host->status = "ok: command response received";
 718                         goto close_transfer;
 719                 }
 720
 721                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 722                         host->complete_what = COMPLETION_XFERFINISH;
 723
 724                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 725         }
 726
 727         /* errors handled after this point are only relevant
 728            when a data transfer is in progress */
 729
 730         if (!cmd->data)
 731                 goto clear_status_bits;
 732
 733         /* Check for FIFO failure */
 734         if (host->is2440) {
 735                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 736                         dbg(host, dbg_err, "FIFO failure\n");
 737                         host->mrq->data->error = -EILSEQ;
 738                         host->status = "error: 2440 fifo failure";
 739                         goto fail_transfer;
 740                 }
 741         } else {
 742                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 743                         dbg(host, dbg_err, "FIFO failure\n");
 744                         cmd->data->error = -EILSEQ;
 745                         host->status = "error:  fifo failure";
 746                         goto fail_transfer;
 747                 }
 748         }
 749
 750         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 751                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 752                 cmd->data->error = -EILSEQ;
 753                 host->status = "error: bad data crc (outgoing)";
 754                 goto fail_transfer;
 755         }
 756
 757         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 758                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 759                 cmd->data->error = -EILSEQ;
 760                 host->status = "error: bad data crc (incoming)";
 761                 goto fail_transfer;
 762         }
 763
 764         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 765                 dbg(host, dbg_err, "data timeout\n");
 766                 cmd->data->error = -ETIMEDOUT;
 767                 host->status = "error: data timeout";
 768                 goto fail_transfer;
 769         }
 770
 771         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 772                 if (host->complete_what == COMPLETION_XFERFINISH) {
 773                         host->status = "ok: data transfer completed";
 774                         goto close_transfer;
 775                 }
 776
 777                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 778                         host->complete_what = COMPLETION_RSPFIN;
 779
 780                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 781         }
 782
 783 clear_status_bits:
 784         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 785         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 786
 787         goto irq_out;
 788
 789 fail_transfer:
 790         host->pio_active = XFER_NONE;
 791
 792 close_transfer:
 793         host->complete_what = COMPLETION_FINALIZE;
 794
 795         clear_imask(host);
 796         tasklet_schedule(&host->pio_tasklet);
 797
 798         goto irq_out;
 799
 800 irq_out:
 801         dbg(host, dbg_irq,
 802             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 803             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 804
 805         spin_unlock_irqrestore(&host->complete_lock, iflags);
 806         return IRQ_HANDLED;
 807
 808 }
 809
 810 /*
 811  * ISR for the CardDetect Pin
 812 */
 813
 814 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
 815 {
 816         struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
 817
 818         dbg(host, dbg_irq, "card detect\n");
 819
 820         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 821
 822         return IRQ_HANDLED;
 823 }
 824
 825 static void s3cmci_dma_done_callback(void *arg)
 826 {
 827         struct s3cmci_host *host = arg;
 828         unsigned long iflags;
 829
 830         BUG_ON(!host->mrq);
 831         BUG_ON(!host->mrq->data);
 832
 833         spin_lock_irqsave(&host->complete_lock, iflags);
 834
 835         dbg(host, dbg_dma, "DMA FINISHED\n");
 836
 837         host->dma_complete = 1;
 838         host->complete_what = COMPLETION_FINALIZE;
 839
 840         tasklet_schedule(&host->pio_tasklet);
 841         spin_unlock_irqrestore(&host->complete_lock, iflags);
 842
 843 }
 844
 845 static void finalize_request(struct s3cmci_host *host)
 846 {
 847         struct mmc_request *mrq = host->mrq;
 848         struct mmc_command *cmd;
 849         int debug_as_failure = 0;
 850
 851         if (host->complete_what != COMPLETION_FINALIZE)
 852                 return;
 853
 854         if (!mrq)
 855                 return;
 856         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 857
 858         if (cmd->data && (cmd->error == 0) &&
 859             (cmd->data->error == 0)) {
 860                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 861                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 862                             host->dma_complete);
 863                         return;
 864                 }
 865         }
 866
 867         /* Read response from controller. */
 868         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 869         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 870         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 871         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 872
 873         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 874
 875         if (cmd->error)
 876                 debug_as_failure = 1;
 877
 878         if (cmd->data && cmd->data->error)
 879                 debug_as_failure = 1;
 880
 881         dbg_dumpcmd(host, cmd, debug_as_failure);
 882
 883         /* Cleanup controller */
 884         writel(0, host->base + S3C2410_SDICMDARG);
 885         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 886         writel(0, host->base + S3C2410_SDICMDCON);
 887         clear_imask(host);
 888
 889         if (cmd->data && cmd->error)
 890                 cmd->data->error = cmd->error;
 891
 892         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 893                 host->cmd_is_stop = 1;
 894                 s3cmci_send_request(host->mmc);
 895                 return;
 896         }
 897
 898         /* If we have no data transfer we are finished here */
 899         if (!mrq->data)
 900                 goto request_done;
 901
 902         /* Calculate the amout of bytes transfer if there was no error */
 903         if (mrq->data->error == 0) {
 904                 mrq->data->bytes_xfered =
 905                         (mrq->data->blocks * mrq->data->blksz);
 906         } else {
 907                 mrq->data->bytes_xfered = 0;
 908         }
 909
 910         /* If we had an error while transferring data we flush the
 911          * DMA channel and the fifo to clear out any garbage. */
 912         if (mrq->data->error != 0) {
 913                 if (s3cmci_host_usedma(host))
 914                         dmaengine_terminate_all(host->dma);
 915
 916                 if (host->is2440) {
 917                         /* Clear failure register and reset fifo. */
 918                         writel(S3C2440_SDIFSTA_FIFORESET |
 919                                S3C2440_SDIFSTA_FIFOFAIL,
 920                                host->base + S3C2410_SDIFSTA);
 921                 } else {
 922                         u32 mci_con;
 923
 924                         /* reset fifo */
 925                         mci_con = readl(host->base + S3C2410_SDICON);
 926                         mci_con |= S3C2410_SDICON_FIFORESET;
 927
 928                         writel(mci_con, host->base + S3C2410_SDICON);
 929                 }
 930         }
 931
 932 request_done:
 933         host->complete_what = COMPLETION_NONE;
 934         host->mrq = NULL;
 935
 936         s3cmci_check_sdio_irq(host);
 937         mmc_request_done(host->mmc, mrq);
 938 }
 939
 940 static void s3cmci_send_command(struct s3cmci_host *host,
 941                                         struct mmc_command *cmd)
 942 {
 943         u32 ccon, imsk;
 944
 945         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 946                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 947                 S3C2410_SDIIMSK_RESPONSECRC;
 948
 949         enable_imask(host, imsk);
 950
 951         if (cmd->data)
 952                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 953         else if (cmd->flags & MMC_RSP_PRESENT)
 954                 host->complete_what = COMPLETION_RSPFIN;
 955         else
 956                 host->complete_what = COMPLETION_CMDSENT;
 957
 958         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 959
 960         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 961         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 962
 963         if (cmd->flags & MMC_RSP_PRESENT)
 964                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 965
 966         if (cmd->flags & MMC_RSP_136)
 967                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 968
 969         writel(ccon, host->base + S3C2410_SDICMDCON);
 970 }
 971
 972 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 973 {
 974         u32 dcon, imsk, stoptries = 3;
 975
 976         /* write DCON register */
 977
 978         if (!data) {
 979                 writel(0, host->base + S3C2410_SDIDCON);
 980                 return 0;
 981         }
 982
 983         if ((data->blksz & 3) != 0) {
 984                 /* We cannot deal with unaligned blocks with more than
 985                  * one block being transferred. */
 986
 987                 if (data->blocks > 1) {
 988                         pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
 989                                 __func__, data->blksz);
 990                         return -EINVAL;
 991                 }
 992         }
 993
 994         while (readl(host->base + S3C2410_SDIDSTA) &
 995                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 996
 997                 dbg(host, dbg_err,
 998                     "mci_setup_data() transfer stillin progress.\n");
 999
1000                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
1001                 s3cmci_reset(host);
1002
1003                 if ((stoptries--) == 0) {
1004                         dbg_dumpregs(host, "DRF");
1005                         return -EINVAL;
1006                 }
1007         }
1008
1009         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
1010
1011         if (s3cmci_host_usedma(host))
1012                 dcon |= S3C2410_SDIDCON_DMAEN;
1013
1014         if (host->bus_width == MMC_BUS_WIDTH_4)
1015                 dcon |= S3C2410_SDIDCON_WIDEBUS;
1016
1017         dcon |= S3C2410_SDIDCON_BLOCKMODE;
1018
1019         if (data->flags & MMC_DATA_WRITE) {
1020                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
1021                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1022         }
1023
1024         if (data->flags & MMC_DATA_READ) {
1025                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1026                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1027         }
1028
1029         if (host->is2440) {
1030                 dcon |= S3C2440_SDIDCON_DS_WORD;
1031                 dcon |= S3C2440_SDIDCON_DATSTART;
1032         }
1033
1034         writel(dcon, host->base + S3C2410_SDIDCON);
1035
1036         /* write BSIZE register */
1037
1038         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1039
1040         /* add to IMASK register */
1041         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1042                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1043
1044         enable_imask(host, imsk);
1045
1046         /* write TIMER register */
1047
1048         if (host->is2440) {
1049                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1050         } else {
1051                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1052
1053                 /* FIX: set slow clock to prevent timeouts on read */
1054                 if (data->flags & MMC_DATA_READ)
1055                         writel(0xFF, host->base + S3C2410_SDIPRE);
1056         }
1057
1058         return 0;
1059 }
1060
1061 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1062
1063 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1064 {
1065         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1066
1067         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1068
1069         host->pio_sgptr = 0;
1070         host->pio_bytes = 0;
1071         host->pio_count = 0;
1072         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1073
1074         if (rw) {
1075                 do_pio_write(host);
1076                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1077         } else {
1078                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1079                              | S3C2410_SDIIMSK_RXFIFOLAST);
1080         }
1081
1082         return 0;
1083 }
1084
1085 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1086 {
1087         int rw = data->flags & MMC_DATA_WRITE;
1088         struct dma_async_tx_descriptor *desc;
1089         struct dma_slave_config conf = {
1090                 .src_addr = host->mem->start + host->sdidata,
1091                 .dst_addr = host->mem->start + host->sdidata,
1092                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1093                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1094         };
1095
1096         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1097
1098         /* Restore prescaler value */
1099         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1100
1101         if (!rw)
1102                 conf.direction = DMA_DEV_TO_MEM;
1103         else
1104                 conf.direction = DMA_MEM_TO_DEV;
1105
1106         dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1107                              rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1108
1109         dmaengine_slave_config(host->dma, &conf);
1110         desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1111                 conf.direction,
1112                 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1113         if (!desc)
1114                 goto unmap_exit;
1115         desc->callback = s3cmci_dma_done_callback;
1116         desc->callback_param = host;
1117         dmaengine_submit(desc);
1118         dma_async_issue_pending(host->dma);
1119
1120         return 0;
1121
1122 unmap_exit:
1123         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1124                              rw ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1125         return -ENOMEM;
1126 }
1127
1128 static void s3cmci_send_request(struct mmc_host *mmc)
1129 {
1130         struct s3cmci_host *host = mmc_priv(mmc);
1131         struct mmc_request *mrq = host->mrq;
1132         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1133
1134         host->ccnt++;
1135         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1136
1137         /* Clear command, data and fifo status registers
1138            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1139         */
1140         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1141         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1142         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1143
1144         if (cmd->data) {
1145                 int res = s3cmci_setup_data(host, cmd->data);
1146
1147                 host->dcnt++;
1148
1149                 if (res) {
1150                         dbg(host, dbg_err, "setup data error %d\n", res);
1151                         cmd->error = res;
1152                         cmd->data->error = res;
1153
1154                         mmc_request_done(mmc, mrq);
1155                         return;
1156                 }
1157
1158                 if (s3cmci_host_usedma(host))
1159                         res = s3cmci_prepare_dma(host, cmd->data);
1160                 else
1161                         res = s3cmci_prepare_pio(host, cmd->data);
1162
1163                 if (res) {
1164                         dbg(host, dbg_err, "data prepare error %d\n", res);
1165                         cmd->error = res;
1166                         cmd->data->error = res;
1167
1168                         mmc_request_done(mmc, mrq);
1169                         return;
1170                 }
1171         }
1172
1173         /* Send command */
1174         s3cmci_send_command(host, cmd);
1175
1176         /* Enable Interrupt */
1177         s3cmci_enable_irq(host, true);
1178 }
1179
1180 static int s3cmci_card_present(struct mmc_host *mmc)
1181 {
1182         struct s3cmci_host *host = mmc_priv(mmc);
1183         struct s3c24xx_mci_pdata *pdata = host->pdata;
1184         int ret;
1185
1186         if (pdata->no_detect)
1187                 return -ENOSYS;
1188
1189         ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1190         return ret ^ pdata->detect_invert;
1191 }
1192
1193 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1194 {
1195         struct s3cmci_host *host = mmc_priv(mmc);
1196
1197         host->status = "mmc request";
1198         host->cmd_is_stop = 0;
1199         host->mrq = mrq;
1200
1201         if (s3cmci_card_present(mmc) == 0) {
1202                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1203                 host->mrq->cmd->error = -ENOMEDIUM;
1204                 mmc_request_done(mmc, mrq);
1205         } else
1206                 s3cmci_send_request(mmc);
1207 }
1208
1209 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1210 {
1211         u32 mci_psc;
1212
1213         /* Set clock */
1214         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1215                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1216
1217                 if (host->real_rate <= ios->clock)
1218                         break;
1219         }
1220
1221         if (mci_psc > 255)
1222                 mci_psc = 255;
1223
1224         host->prescaler = mci_psc;
1225         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1226
1227         /* If requested clock is 0, real_rate will be 0, too */
1228         if (ios->clock == 0)
1229                 host->real_rate = 0;
1230 }
1231
1232 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1233 {
1234         struct s3cmci_host *host = mmc_priv(mmc);
1235         u32 mci_con;
1236
1237         /* Set the power state */
1238
1239         mci_con = readl(host->base + S3C2410_SDICON);
1240
1241         switch (ios->power_mode) {
1242         case MMC_POWER_ON:
1243         case MMC_POWER_UP:
1244                 /* Configure GPE5...GPE10 pins in SD mode */
1245                 s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1246                                       S3C_GPIO_PULL_NONE);
1247
1248                 if (host->pdata->set_power)
1249                         host->pdata->set_power(ios->power_mode, ios->vdd);
1250
1251                 if (!host->is2440)
1252                         mci_con |= S3C2410_SDICON_FIFORESET;
1253
1254                 break;
1255
1256         case MMC_POWER_OFF:
1257         default:
1258                 gpio_direction_output(S3C2410_GPE(5), 0);
1259
1260                 if (host->is2440)
1261                         mci_con |= S3C2440_SDICON_SDRESET;
1262
1263                 if (host->pdata->set_power)
1264                         host->pdata->set_power(ios->power_mode, ios->vdd);
1265
1266                 break;
1267         }
1268
1269         s3cmci_set_clk(host, ios);
1270
1271         /* Set CLOCK_ENABLE */
1272         if (ios->clock)
1273                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1274         else
1275                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1276
1277         writel(mci_con, host->base + S3C2410_SDICON);
1278
1279         if ((ios->power_mode == MMC_POWER_ON) ||
1280             (ios->power_mode == MMC_POWER_UP)) {
1281                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1282                         host->real_rate/1000, ios->clock/1000);
1283         } else {
1284                 dbg(host, dbg_conf, "powered down.\n");
1285         }
1286
1287         host->bus_width = ios->bus_width;
1288 }
1289
1290 static void s3cmci_reset(struct s3cmci_host *host)
1291 {
1292         u32 con = readl(host->base + S3C2410_SDICON);
1293
1294         con |= S3C2440_SDICON_SDRESET;
1295         writel(con, host->base + S3C2410_SDICON);
1296 }
1297
1298 static int s3cmci_get_ro(struct mmc_host *mmc)
1299 {
1300         struct s3cmci_host *host = mmc_priv(mmc);
1301         struct s3c24xx_mci_pdata *pdata = host->pdata;
1302         int ret;
1303
1304         if (pdata->no_wprotect)
1305                 return 0;
1306
1307         ret = gpio_get_value(pdata->gpio_wprotect) ? 1 : 0;
1308         ret ^= pdata->wprotect_invert;
1309
1310         return ret;
1311 }
1312
1313 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1314 {
1315         struct s3cmci_host *host = mmc_priv(mmc);
1316         unsigned long flags;
1317         u32 con;
1318
1319         local_irq_save(flags);
1320
1321         con = readl(host->base + S3C2410_SDICON);
1322         host->sdio_irqen = enable;
1323
1324         if (enable == host->sdio_irqen)
1325                 goto same_state;
1326
1327         if (enable) {
1328                 con |= S3C2410_SDICON_SDIOIRQ;
1329                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1330
1331                 if (!host->irq_state && !host->irq_disabled) {
1332                         host->irq_state = true;
1333                         enable_irq(host->irq);
1334                 }
1335         } else {
1336                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1337                 con &= ~S3C2410_SDICON_SDIOIRQ;
1338
1339                 if (!host->irq_enabled && host->irq_state) {
1340                         disable_irq_nosync(host->irq);
1341                         host->irq_state = false;
1342                 }
1343         }
1344
1345         writel(con, host->base + S3C2410_SDICON);
1346
1347  same_state:
1348         local_irq_restore(flags);
1349
1350         s3cmci_check_sdio_irq(host);
1351 }
1352
1353 static struct mmc_host_ops s3cmci_ops = {
1354         .request        = s3cmci_request,
1355         .set_ios        = s3cmci_set_ios,
1356         .get_ro         = s3cmci_get_ro,
1357         .get_cd         = s3cmci_card_present,
1358         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1359 };
1360
1361 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1362         /* This is currently here to avoid a number of if (host->pdata)
1363          * checks. Any zero fields to ensure reasonable defaults are picked. */
1364          .no_wprotect = 1,
1365          .no_detect = 1,
1366 };
1367
1368 #ifdef CONFIG_CPU_FREQ
1369
1370 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1371                                      unsigned long val, void *data)
1372 {
1373         struct s3cmci_host *host;
1374         struct mmc_host *mmc;
1375         unsigned long newclk;
1376         unsigned long flags;
1377
1378         host = container_of(nb, struct s3cmci_host, freq_transition);
1379         newclk = clk_get_rate(host->clk);
1380         mmc = host->mmc;
1381
1382         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1383             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1384                 spin_lock_irqsave(&mmc->lock, flags);
1385
1386                 host->clk_rate = newclk;
1387
1388                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1389                     mmc->ios.clock != 0)
1390                         s3cmci_set_clk(host, &mmc->ios);
1391
1392                 spin_unlock_irqrestore(&mmc->lock, flags);
1393         }
1394
1395         return 0;
1396 }
1397
1398 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1399 {
1400         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1401
1402         return cpufreq_register_notifier(&host->freq_transition,
1403                                          CPUFREQ_TRANSITION_NOTIFIER);
1404 }
1405
1406 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1407 {
1408         cpufreq_unregister_notifier(&host->freq_transition,
1409                                     CPUFREQ_TRANSITION_NOTIFIER);
1410 }
1411
1412 #else
1413 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1414 {
1415         return 0;
1416 }
1417
1418 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1419 {
1420 }
1421 #endif
1422
1423
1424 #ifdef CONFIG_DEBUG_FS
1425
1426 static int s3cmci_state_show(struct seq_file *seq, void *v)
1427 {
1428         struct s3cmci_host *host = seq->private;
1429
1430         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1431         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1432         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1433         seq_printf(seq, "is2440 = %d\n", host->is2440);
1434         seq_printf(seq, "IRQ = %d\n", host->irq);
1435         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1436         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1437         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1438         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1439         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1440         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1441         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1442
1443         return 0;
1444 }
1445
1446 static int s3cmci_state_open(struct inode *inode, struct file *file)
1447 {
1448         return single_open(file, s3cmci_state_show, inode->i_private);
1449 }
1450
1451 static const struct file_operations s3cmci_fops_state = {
1452         .owner          = THIS_MODULE,
1453         .open           = s3cmci_state_open,
1454         .read           = seq_read,
1455         .llseek         = seq_lseek,
1456         .release        = single_release,
1457 };
1458
1459 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1460
1461 struct s3cmci_reg {
1462         unsigned short  addr;
1463         unsigned char   *name;
1464 } debug_regs[] = {
1465         DBG_REG(CON),
1466         DBG_REG(PRE),
1467         DBG_REG(CMDARG),
1468         DBG_REG(CMDCON),
1469         DBG_REG(CMDSTAT),
1470         DBG_REG(RSP0),
1471         DBG_REG(RSP1),
1472         DBG_REG(RSP2),
1473         DBG_REG(RSP3),
1474         DBG_REG(TIMER),
1475         DBG_REG(BSIZE),
1476         DBG_REG(DCON),
1477         DBG_REG(DCNT),
1478         DBG_REG(DSTA),
1479         DBG_REG(FSTA),
1480         {}
1481 };
1482
1483 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1484 {
1485         struct s3cmci_host *host = seq->private;
1486         struct s3cmci_reg *rptr = debug_regs;
1487
1488         for (; rptr->name; rptr++)
1489                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1490                            readl(host->base + rptr->addr));
1491
1492         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1493
1494         return 0;
1495 }
1496
1497 static int s3cmci_regs_open(struct inode *inode, struct file *file)
1498 {
1499         return single_open(file, s3cmci_regs_show, inode->i_private);
1500 }
1501
1502 static const struct file_operations s3cmci_fops_regs = {
1503         .owner          = THIS_MODULE,
1504         .open           = s3cmci_regs_open,
1505         .read           = seq_read,
1506         .llseek         = seq_lseek,
1507         .release        = single_release,
1508 };
1509
1510 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1511 {
1512         struct device *dev = &host->pdev->dev;
1513
1514         host->debug_root = debugfs_create_dir(dev_name(dev), NULL);
1515         if (IS_ERR(host->debug_root)) {
1516                 dev_err(dev, "failed to create debugfs root\n");
1517                 return;
1518         }
1519
1520         host->debug_state = debugfs_create_file("state", 0444,
1521                                                 host->debug_root, host,
1522                                                 &s3cmci_fops_state);
1523
1524         if (IS_ERR(host->debug_state))
1525                 dev_err(dev, "failed to create debug state file\n");
1526
1527         host->debug_regs = debugfs_create_file("regs", 0444,
1528                                                host->debug_root, host,
1529                                                &s3cmci_fops_regs);
1530
1531         if (IS_ERR(host->debug_regs))
1532                 dev_err(dev, "failed to create debug regs file\n");
1533 }
1534
1535 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1536 {
1537         debugfs_remove(host->debug_regs);
1538         debugfs_remove(host->debug_state);
1539         debugfs_remove(host->debug_root);
1540 }
1541
1542 #else
1543 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1544 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1545
1546 #endif /* CONFIG_DEBUG_FS */
1547
1548 static int s3cmci_probe(struct platform_device *pdev)
1549 {
1550         struct s3cmci_host *host;
1551         struct mmc_host *mmc;
1552         int ret;
1553         int is2440;
1554         int i;
1555
1556         is2440 = platform_get_device_id(pdev)->driver_data;
1557
1558         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1559         if (!mmc) {
1560                 ret = -ENOMEM;
1561                 goto probe_out;
1562         }
1563
1564         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1565                 ret = gpio_request(i, dev_name(&pdev->dev));
1566                 if (ret) {
1567                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1568
1569                         for (i--; i >= S3C2410_GPE(5); i--)
1570                                 gpio_free(i);
1571
1572                         goto probe_free_host;
1573                 }
1574         }
1575
1576         host = mmc_priv(mmc);
1577         host->mmc       = mmc;
1578         host->pdev      = pdev;
1579         host->is2440    = is2440;
1580
1581         host->pdata = pdev->dev.platform_data;
1582         if (!host->pdata) {
1583                 pdev->dev.platform_data = &s3cmci_def_pdata;
1584                 host->pdata = &s3cmci_def_pdata;
1585         }
1586
1587         spin_lock_init(&host->complete_lock);
1588         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1589
1590         if (is2440) {
1591                 host->sdiimsk   = S3C2440_SDIIMSK;
1592                 host->sdidata   = S3C2440_SDIDATA;
1593                 host->clk_div   = 1;
1594         } else {
1595                 host->sdiimsk   = S3C2410_SDIIMSK;
1596                 host->sdidata   = S3C2410_SDIDATA;
1597                 host->clk_div   = 2;
1598         }
1599
1600         host->complete_what     = COMPLETION_NONE;
1601         host->pio_active        = XFER_NONE;
1602
1603         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1604         if (!host->mem) {
1605                 dev_err(&pdev->dev,
1606                         "failed to get io memory region resource.\n");
1607
1608                 ret = -ENOENT;
1609                 goto probe_free_gpio;
1610         }
1611
1612         host->mem = request_mem_region(host->mem->start,
1613                                        resource_size(host->mem), pdev->name);
1614
1615         if (!host->mem) {
1616                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1617                 ret = -ENOENT;
1618                 goto probe_free_gpio;
1619         }
1620
1621         host->base = ioremap(host->mem->start, resource_size(host->mem));
1622         if (!host->base) {
1623                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1624                 ret = -EINVAL;
1625                 goto probe_free_mem_region;
1626         }
1627
1628         host->irq = platform_get_irq(pdev, 0);
1629         if (host->irq == 0) {
1630                 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1631                 ret = -EINVAL;
1632                 goto probe_iounmap;
1633         }
1634
1635         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1636                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1637                 ret = -ENOENT;
1638                 goto probe_iounmap;
1639         }
1640
1641         /* We get spurious interrupts even when we have set the IMSK
1642          * register to ignore everything, so use disable_irq() to make
1643          * ensure we don't lock the system with un-serviceable requests. */
1644
1645         disable_irq(host->irq);
1646         host->irq_state = false;
1647
1648         if (!host->pdata->no_detect) {
1649                 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1650                 if (ret) {
1651                         dev_err(&pdev->dev, "failed to get detect gpio\n");
1652                         goto probe_free_irq;
1653                 }
1654
1655                 host->irq_cd = gpio_to_irq(host->pdata->gpio_detect);
1656
1657                 if (host->irq_cd >= 0) {
1658                         if (request_irq(host->irq_cd, s3cmci_irq_cd,
1659                                         IRQF_TRIGGER_RISING |
1660                                         IRQF_TRIGGER_FALLING,
1661                                         DRIVER_NAME, host)) {
1662                                 dev_err(&pdev->dev,
1663                                         "can't get card detect irq.\n");
1664                                 ret = -ENOENT;
1665                                 goto probe_free_gpio_cd;
1666                         }
1667                 } else {
1668                         dev_warn(&pdev->dev,
1669                                  "host detect has no irq available\n");
1670                         gpio_direction_input(host->pdata->gpio_detect);
1671                 }
1672         } else
1673                 host->irq_cd = -1;
1674
1675         if (!host->pdata->no_wprotect) {
1676                 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1677                 if (ret) {
1678                         dev_err(&pdev->dev, "failed to get writeprotect\n");
1679                         goto probe_free_irq_cd;
1680                 }
1681
1682                 gpio_direction_input(host->pdata->gpio_wprotect);
1683         }
1684
1685         /* depending on the dma state, get a dma channel to use. */
1686
1687         if (s3cmci_host_usedma(host)) {
1688                 dma_cap_mask_t mask;
1689
1690                 dma_cap_zero(mask);
1691                 dma_cap_set(DMA_SLAVE, mask);
1692
1693                 host->dma = dma_request_slave_channel_compat(mask,
1694                         s3c24xx_dma_filter, (void *)DMACH_SDI, &pdev->dev, "rx-tx");
1695                 if (!host->dma) {
1696                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1697                         ret = -EBUSY;
1698                         goto probe_free_gpio_wp;
1699                 }
1700         }
1701
1702         host->clk = clk_get(&pdev->dev, "sdi");
1703         if (IS_ERR(host->clk)) {
1704                 dev_err(&pdev->dev, "failed to find clock source.\n");
1705                 ret = PTR_ERR(host->clk);
1706                 host->clk = NULL;
1707                 goto probe_free_dma;
1708         }
1709
1710         ret = clk_prepare_enable(host->clk);
1711         if (ret) {
1712                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1713                 goto clk_free;
1714         }
1715
1716         host->clk_rate = clk_get_rate(host->clk);
1717
1718         mmc->ops        = &s3cmci_ops;
1719         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1720 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1721         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1722 #else
1723         mmc->caps       = MMC_CAP_4_BIT_DATA;
1724 #endif
1725         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1726         mmc->f_max      = host->clk_rate / host->clk_div;
1727
1728         if (host->pdata->ocr_avail)
1729                 mmc->ocr_avail = host->pdata->ocr_avail;
1730
1731         mmc->max_blk_count      = 4095;
1732         mmc->max_blk_size       = 4095;
1733         mmc->max_req_size       = 4095 * 512;
1734         mmc->max_seg_size       = mmc->max_req_size;
1735
1736         mmc->max_segs           = 128;
1737
1738         dbg(host, dbg_debug,
1739             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1740             (host->is2440?"2440":""),
1741             host->base, host->irq, host->irq_cd, host->dma);
1742
1743         ret = s3cmci_cpufreq_register(host);
1744         if (ret) {
1745                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1746                 goto free_dmabuf;
1747         }
1748
1749         ret = mmc_add_host(mmc);
1750         if (ret) {
1751                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1752                 goto free_cpufreq;
1753         }
1754
1755         s3cmci_debugfs_attach(host);
1756
1757         platform_set_drvdata(pdev, mmc);
1758         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1759                  s3cmci_host_usedma(host) ? "dma" : "pio",
1760                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1761
1762         return 0;
1763
1764  free_cpufreq:
1765         s3cmci_cpufreq_deregister(host);
1766
1767  free_dmabuf:
1768         clk_disable_unprepare(host->clk);
1769
1770  clk_free:
1771         clk_put(host->clk);
1772
1773  probe_free_dma:
1774         if (s3cmci_host_usedma(host))
1775                 dma_release_channel(host->dma);
1776
1777  probe_free_gpio_wp:
1778         if (!host->pdata->no_wprotect)
1779                 gpio_free(host->pdata->gpio_wprotect);
1780
1781  probe_free_gpio_cd:
1782         if (!host->pdata->no_detect)
1783                 gpio_free(host->pdata->gpio_detect);
1784
1785  probe_free_irq_cd:
1786         if (host->irq_cd >= 0)
1787                 free_irq(host->irq_cd, host);
1788
1789  probe_free_irq:
1790         free_irq(host->irq, host);
1791
1792  probe_iounmap:
1793         iounmap(host->base);
1794
1795  probe_free_mem_region:
1796         release_mem_region(host->mem->start, resource_size(host->mem));
1797
1798  probe_free_gpio:
1799         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1800                 gpio_free(i);
1801
1802  probe_free_host:
1803         mmc_free_host(mmc);
1804
1805  probe_out:
1806         return ret;
1807 }
1808
1809 static void s3cmci_shutdown(struct platform_device *pdev)
1810 {
1811         struct mmc_host *mmc = platform_get_drvdata(pdev);
1812         struct s3cmci_host *host = mmc_priv(mmc);
1813
1814         if (host->irq_cd >= 0)
1815                 free_irq(host->irq_cd, host);
1816
1817         s3cmci_debugfs_remove(host);
1818         s3cmci_cpufreq_deregister(host);
1819         mmc_remove_host(mmc);
1820         clk_disable_unprepare(host->clk);
1821 }
1822
1823 static int s3cmci_remove(struct platform_device *pdev)
1824 {
1825         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1826         struct s3cmci_host      *host = mmc_priv(mmc);
1827         struct s3c24xx_mci_pdata *pd = host->pdata;
1828         int i;
1829
1830         s3cmci_shutdown(pdev);
1831
1832         clk_put(host->clk);
1833
1834         tasklet_disable(&host->pio_tasklet);
1835
1836         if (s3cmci_host_usedma(host))
1837                 dma_release_channel(host->dma);
1838
1839         free_irq(host->irq, host);
1840
1841         if (!pd->no_wprotect)
1842                 gpio_free(pd->gpio_wprotect);
1843
1844         if (!pd->no_detect)
1845                 gpio_free(pd->gpio_detect);
1846
1847         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1848                 gpio_free(i);
1849
1850
1851         iounmap(host->base);
1852         release_mem_region(host->mem->start, resource_size(host->mem));
1853
1854         mmc_free_host(mmc);
1855         return 0;
1856 }
1857
1858 static const struct platform_device_id s3cmci_driver_ids[] = {
1859         {
1860                 .name   = "s3c2410-sdi",
1861                 .driver_data    = 0,
1862         }, {
1863                 .name   = "s3c2412-sdi",
1864                 .driver_data    = 1,
1865         }, {
1866                 .name   = "s3c2440-sdi",
1867                 .driver_data    = 1,
1868         },
1869         { }
1870 };
1871
1872 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1873
1874 static struct platform_driver s3cmci_driver = {
1875         .driver = {
1876                 .name   = "s3c-sdi",
1877         },
1878         .id_table       = s3cmci_driver_ids,
1879         .probe          = s3cmci_probe,
1880         .remove         = s3cmci_remove,
1881         .shutdown       = s3cmci_shutdown,
1882 };
1883
1884 module_platform_driver(s3cmci_driver);
1885
1886 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1887 MODULE_LICENSE("GPL v2");
1888 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");