2 * Freescale eSDHC i.MX controller driver for the platform bus.
4 * derived from the OF-version.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include "sdhci-pltfm.h"
31 #include "sdhci-esdhc.h"
33 #define SDHCI_CTRL_D3CD 0x08
34 /* VENDOR SPEC register */
35 #define SDHCI_VENDOR_SPEC 0xC0
36 #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002
37 #define SDHCI_WTMK_LVL 0x44
38 #define SDHCI_MIX_CTRL 0x48
41 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
42 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
43 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
44 * Define this macro DMA error INT for fsl eSDHC
46 #define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000
49 * The CMDTYPE of the CMD register (offset 0xE) should be set to
50 * "11" when the STOP CMD12 is issued on imx53 to abort one
51 * open ended multi-blk IO. Otherwise the TC INT wouldn't
53 * In exact block transfer, the controller doesn't complete the
54 * operations automatically as required at the end of the
55 * transfer and remains on hold if the abort command is not sent.
56 * As a result, the TC flag is not asserted and SW received timeout
57 * exeception. Bit1 of Vendor Spec registor is used to fix it.
59 #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
69 struct pltfm_imx_data {
72 enum imx_esdhc_type devtype;
73 struct pinctrl *pinctrl;
74 struct esdhc_platform_data boarddata;
80 static struct platform_device_id imx_esdhc_devtype[] = {
82 .name = "sdhci-esdhc-imx25",
83 .driver_data = IMX25_ESDHC,
85 .name = "sdhci-esdhc-imx35",
86 .driver_data = IMX35_ESDHC,
88 .name = "sdhci-esdhc-imx51",
89 .driver_data = IMX51_ESDHC,
91 .name = "sdhci-esdhc-imx53",
92 .driver_data = IMX53_ESDHC,
94 .name = "sdhci-usdhc-imx6q",
95 .driver_data = IMX6Q_USDHC,
100 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
102 static const struct of_device_id imx_esdhc_dt_ids[] = {
103 { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
104 { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
105 { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
106 { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
107 { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
110 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
112 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
114 return data->devtype == IMX25_ESDHC;
117 static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
119 return data->devtype == IMX35_ESDHC;
122 static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
124 return data->devtype == IMX51_ESDHC;
127 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
129 return data->devtype == IMX53_ESDHC;
132 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
134 return data->devtype == IMX6Q_USDHC;
137 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
139 void __iomem *base = host->ioaddr + (reg & ~0x3);
140 u32 shift = (reg & 0x3) * 8;
142 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
145 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
147 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
148 struct pltfm_imx_data *imx_data = pltfm_host->priv;
149 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
151 u32 val = readl(host->ioaddr + reg);
153 if (unlikely(reg == SDHCI_CAPABILITIES)) {
154 /* In FSL esdhc IC module, only bit20 is used to indicate the
155 * ADMA2 capability of esdhc, but this bit is messed up on
156 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
157 * don't actually support ADMA2). So set the BROKEN_ADMA
158 * uirk on MX25/35 platforms.
161 if (val & SDHCI_CAN_DO_ADMA1) {
162 val &= ~SDHCI_CAN_DO_ADMA1;
163 val |= SDHCI_CAN_DO_ADMA2;
167 if (unlikely(reg == SDHCI_INT_STATUS)) {
168 if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
169 val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
170 val |= SDHCI_INT_ADMA_ERROR;
177 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
179 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
180 struct pltfm_imx_data *imx_data = pltfm_host->priv;
181 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
184 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
185 if (val & SDHCI_INT_CARD_INT) {
187 * Clear and then set D3CD bit to avoid missing the
188 * card interrupt. This is a eSDHC controller problem
189 * so we need to apply the following workaround: clear
190 * and set D3CD bit will make eSDHC re-sample the card
191 * interrupt. In case a card interrupt was lost,
192 * re-sample it by the following steps.
194 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
195 data &= ~SDHCI_CTRL_D3CD;
196 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
197 data |= SDHCI_CTRL_D3CD;
198 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
202 if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
203 && (reg == SDHCI_INT_STATUS)
204 && (val & SDHCI_INT_DATA_END))) {
206 v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
207 v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
208 writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
211 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
212 if (val & SDHCI_INT_ADMA_ERROR) {
213 val &= ~SDHCI_INT_ADMA_ERROR;
214 val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
218 writel(val, host->ioaddr + reg);
221 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
223 if (unlikely(reg == SDHCI_HOST_VERSION)) {
224 u16 val = readw(host->ioaddr + (reg ^ 2));
226 * uSDHC supports SDHCI v3.0, but it's encoded as value
227 * 0x3 in host controller version register, which violates
228 * SDHCI_SPEC_300 definition. Work it around here.
230 if ((val & SDHCI_SPEC_VER_MASK) == 3)
234 return readw(host->ioaddr + reg);
237 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
239 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
240 struct pltfm_imx_data *imx_data = pltfm_host->priv;
243 case SDHCI_TRANSFER_MODE:
245 * Postpone this write, we must do it together with a
246 * command write that is down below.
248 if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
249 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
250 && (host->cmd->data->blocks > 1)
251 && (host->cmd->data->flags & MMC_DATA_READ)) {
253 v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
254 v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
255 writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
257 imx_data->scratchpad = val;
260 if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
261 host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
262 (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
263 val |= SDHCI_CMD_ABORTCMD;
265 if (is_imx6q_usdhc(imx_data)) {
266 u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL);
267 m = imx_data->scratchpad | (m & 0xffff0000);
268 writel(m, host->ioaddr + SDHCI_MIX_CTRL);
270 host->ioaddr + SDHCI_TRANSFER_MODE);
272 writel(val << 16 | imx_data->scratchpad,
273 host->ioaddr + SDHCI_TRANSFER_MODE);
276 case SDHCI_BLOCK_SIZE:
277 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
280 esdhc_clrset_le(host, 0xffff, val, reg);
283 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
285 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
286 struct pltfm_imx_data *imx_data = pltfm_host->priv;
290 case SDHCI_POWER_CONTROL:
292 * FSL put some DMA bits here
293 * If your board has a regulator, code should be here
296 case SDHCI_HOST_CONTROL:
297 /* FSL messed up here, so we can just keep those three */
298 new_val = val & (SDHCI_CTRL_LED | \
299 SDHCI_CTRL_4BITBUS | \
301 /* ensure the endianness */
302 new_val |= ESDHC_HOST_CONTROL_LE;
303 /* bits 8&9 are reserved on mx25 */
304 if (!is_imx25_esdhc(imx_data)) {
305 /* DMA mode bits are shifted */
306 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
309 esdhc_clrset_le(host, 0xffff, new_val, reg);
312 esdhc_clrset_le(host, 0xff, val, reg);
315 * The esdhc has a design violation to SDHC spec which tells
316 * that software reset should not affect card detection circuit.
317 * But esdhc clears its SYSCTL register bits [0..2] during the
318 * software reset. This will stop those clocks that card detection
319 * circuit relies on. To work around it, we turn the clocks on back
320 * to keep card detection circuit functional.
322 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1))
323 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
326 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
328 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
330 return clk_get_rate(pltfm_host->clk);
333 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
335 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
337 return clk_get_rate(pltfm_host->clk) / 256 / 16;
340 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
342 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
343 struct pltfm_imx_data *imx_data = pltfm_host->priv;
344 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
346 switch (boarddata->wp_type) {
348 return mmc_gpio_get_ro(host->mmc);
349 case ESDHC_WP_CONTROLLER:
350 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
351 SDHCI_WRITE_PROTECT);
359 static struct sdhci_ops sdhci_esdhc_ops = {
360 .read_l = esdhc_readl_le,
361 .read_w = esdhc_readw_le,
362 .write_l = esdhc_writel_le,
363 .write_w = esdhc_writew_le,
364 .write_b = esdhc_writeb_le,
365 .set_clock = esdhc_set_clock,
366 .get_max_clock = esdhc_pltfm_get_max_clock,
367 .get_min_clock = esdhc_pltfm_get_min_clock,
368 .get_ro = esdhc_pltfm_get_ro,
371 static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
372 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
373 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
374 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
375 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
376 .ops = &sdhci_esdhc_ops,
381 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
382 struct esdhc_platform_data *boarddata)
384 struct device_node *np = pdev->dev.of_node;
389 if (of_get_property(np, "non-removable", NULL))
390 boarddata->cd_type = ESDHC_CD_PERMANENT;
392 if (of_get_property(np, "fsl,cd-controller", NULL))
393 boarddata->cd_type = ESDHC_CD_CONTROLLER;
395 if (of_get_property(np, "fsl,wp-controller", NULL))
396 boarddata->wp_type = ESDHC_WP_CONTROLLER;
398 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
399 if (gpio_is_valid(boarddata->cd_gpio))
400 boarddata->cd_type = ESDHC_CD_GPIO;
402 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
403 if (gpio_is_valid(boarddata->wp_gpio))
404 boarddata->wp_type = ESDHC_WP_GPIO;
410 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
411 struct esdhc_platform_data *boarddata)
417 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
419 const struct of_device_id *of_id =
420 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
421 struct sdhci_pltfm_host *pltfm_host;
422 struct sdhci_host *host;
423 struct esdhc_platform_data *boarddata;
425 struct pltfm_imx_data *imx_data;
427 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
429 return PTR_ERR(host);
431 pltfm_host = sdhci_priv(host);
433 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
440 pdev->id_entry = of_id->data;
441 imx_data->devtype = pdev->id_entry->driver_data;
442 pltfm_host->priv = imx_data;
444 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
445 if (IS_ERR(imx_data->clk_ipg)) {
446 err = PTR_ERR(imx_data->clk_ipg);
450 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
451 if (IS_ERR(imx_data->clk_ahb)) {
452 err = PTR_ERR(imx_data->clk_ahb);
456 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
457 if (IS_ERR(imx_data->clk_per)) {
458 err = PTR_ERR(imx_data->clk_per);
462 pltfm_host->clk = imx_data->clk_per;
464 clk_prepare_enable(imx_data->clk_per);
465 clk_prepare_enable(imx_data->clk_ipg);
466 clk_prepare_enable(imx_data->clk_ahb);
468 imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
469 if (IS_ERR(imx_data->pinctrl)) {
470 err = PTR_ERR(imx_data->pinctrl);
474 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
476 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
477 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
478 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
479 | SDHCI_QUIRK_BROKEN_ADMA;
481 if (is_imx53_esdhc(imx_data))
482 imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
485 * The imx6q ROM code will change the default watermark level setting
486 * to something insane. Change it back here.
488 if (is_imx6q_usdhc(imx_data))
489 writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL);
491 boarddata = &imx_data->boarddata;
492 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
493 if (!host->mmc->parent->platform_data) {
494 dev_err(mmc_dev(host->mmc), "no board data!\n");
498 imx_data->boarddata = *((struct esdhc_platform_data *)
499 host->mmc->parent->platform_data);
503 if (boarddata->wp_type == ESDHC_WP_GPIO) {
504 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
506 dev_err(mmc_dev(host->mmc),
507 "failed to request write-protect gpio!\n");
510 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
514 switch (boarddata->cd_type) {
516 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
518 dev_err(mmc_dev(host->mmc),
519 "failed to request card-detect gpio!\n");
524 case ESDHC_CD_CONTROLLER:
525 /* we have a working card_detect back */
526 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
529 case ESDHC_CD_PERMANENT:
530 host->mmc->caps = MMC_CAP_NONREMOVABLE;
537 err = sdhci_add_host(host);
544 clk_disable_unprepare(imx_data->clk_per);
545 clk_disable_unprepare(imx_data->clk_ipg);
546 clk_disable_unprepare(imx_data->clk_ahb);
548 sdhci_pltfm_free(pdev);
552 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
554 struct sdhci_host *host = platform_get_drvdata(pdev);
555 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
556 struct pltfm_imx_data *imx_data = pltfm_host->priv;
557 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
559 sdhci_remove_host(host, dead);
561 clk_disable_unprepare(imx_data->clk_per);
562 clk_disable_unprepare(imx_data->clk_ipg);
563 clk_disable_unprepare(imx_data->clk_ahb);
565 sdhci_pltfm_free(pdev);
570 static struct platform_driver sdhci_esdhc_imx_driver = {
572 .name = "sdhci-esdhc-imx",
573 .owner = THIS_MODULE,
574 .of_match_table = imx_esdhc_dt_ids,
575 .pm = SDHCI_PLTFM_PMOPS,
577 .id_table = imx_esdhc_devtype,
578 .probe = sdhci_esdhc_imx_probe,
579 .remove = sdhci_esdhc_imx_remove,
582 module_platform_driver(sdhci_esdhc_imx_driver);
584 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
585 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
586 MODULE_LICENSE("GPL v2");