drivers/mmc/host/sdhci-pxav3.c

   1 /*
   2  * Copyright (C) 2010 Marvell International Ltd.
   3  *              Zhangfei Gao <zhangfei.gao@marvell.com>
   4  *              Kevin Wang <dwang4@marvell.com>
   5  *              Mingwei Wang <mwwang@marvell.com>
   6  *              Philip Rakity <prakity@marvell.com>
   7  *              Mark Brown <markb@marvell.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/gpio.h>
  25 #include <linux/mmc/card.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/slot-gpio.h>
  28 #include <linux/platform_data/pxa_sdhci.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_gpio.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/mbus.h>
  38
  39 #include "sdhci.h"
  40 #include "sdhci-pltfm.h"
  41
  42 #define PXAV3_RPM_DELAY_MS     50
  43
  44 #define SD_CLOCK_BURST_SIZE_SETUP               0x10A
  45 #define SDCLK_SEL       0x100
  46 #define SDCLK_DELAY_SHIFT       9
  47 #define SDCLK_DELAY_MASK        0x1f
  48
  49 #define SD_CFG_FIFO_PARAM       0x100
  50 #define SDCFG_GEN_PAD_CLK_ON    (1<<6)
  51 #define SDCFG_GEN_PAD_CLK_CNT_MASK      0xFF
  52 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT     24
  53
  54 #define SD_SPI_MODE          0x108
  55 #define SD_CE_ATA_1          0x10C
  56
  57 #define SD_CE_ATA_2          0x10E
  58 #define SDCE_MISC_INT           (1<<2)
  59 #define SDCE_MISC_INT_EN        (1<<1)
  60
  61 /*
  62  * These registers are relative to the second register region, for the
  63  * MBus bridge.
  64  */
  65 #define SDHCI_WINDOW_CTRL(i)    (0x80 + ((i) << 3))
  66 #define SDHCI_WINDOW_BASE(i)    (0x84 + ((i) << 3))
  67 #define SDHCI_MAX_WIN_NUM       8
  68
  69 static int mv_conf_mbus_windows(struct platform_device *pdev,
  70                                 const struct mbus_dram_target_info *dram)
  71 {
  72         int i;
  73         void __iomem *regs;
  74         struct resource *res;
  75
  76         if (!dram) {
  77                 dev_err(&pdev->dev, "no mbus dram info\n");
  78                 return -EINVAL;
  79         }
  80
  81         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  82         if (!res) {
  83                 dev_err(&pdev->dev, "cannot get mbus registers\n");
  84                 return -EINVAL;
  85         }
  86
  87         regs = ioremap(res->start, resource_size(res));
  88         if (!regs) {
  89                 dev_err(&pdev->dev, "cannot map mbus registers\n");
  90                 return -ENOMEM;
  91         }
  92
  93         for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
  94                 writel(0, regs + SDHCI_WINDOW_CTRL(i));
  95                 writel(0, regs + SDHCI_WINDOW_BASE(i));
  96         }
  97
  98         for (i = 0; i < dram->num_cs; i++) {
  99                 const struct mbus_dram_window *cs = dram->cs + i;
 100
 101                 /* Write size, attributes and target id to control register */
 102                 writel(((cs->size - 1) & 0xffff0000) |
 103                         (cs->mbus_attr << 8) |
 104                         (dram->mbus_dram_target_id << 4) | 1,
 105                         regs + SDHCI_WINDOW_CTRL(i));
 106                 /* Write base address to base register */
 107                 writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 108         }
 109
 110         iounmap(regs);
 111
 112         return 0;
 113 }
 114
 115 static void pxav3_reset(struct sdhci_host *host, u8 mask)
 116 {
 117         struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 118         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 119
 120         sdhci_reset(host, mask);
 121
 122         if (mask == SDHCI_RESET_ALL) {
 123                 /*
 124                  * tune timing of read data/command when crc error happen
 125                  * no performance impact
 126                  */
 127                 if (pdata && 0 != pdata->clk_delay_cycles) {
 128                         u16 tmp;
 129
 130                         tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 131                         tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
 132                                 << SDCLK_DELAY_SHIFT;
 133                         tmp |= SDCLK_SEL;
 134                         writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 135                 }
 136         }
 137 }
 138
 139 #define MAX_WAIT_COUNT 5
 140 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 141 {
 142         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 143         struct sdhci_pxa *pxa = pltfm_host->priv;
 144         u16 tmp;
 145         int count;
 146
 147         if (pxa->power_mode == MMC_POWER_UP
 148                         && power_mode == MMC_POWER_ON) {
 149
 150                 dev_dbg(mmc_dev(host->mmc),
 151                                 "%s: slot->power_mode = %d,"
 152                                 "ios->power_mode = %d\n",
 153                                 __func__,
 154                                 pxa->power_mode,
 155                                 power_mode);
 156
 157                 /* set we want notice of when 74 clocks are sent */
 158                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 159                 tmp |= SDCE_MISC_INT_EN;
 160                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 161
 162                 /* start sending the 74 clocks */
 163                 tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
 164                 tmp |= SDCFG_GEN_PAD_CLK_ON;
 165                 writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
 166
 167                 /* slowest speed is about 100KHz or 10usec per clock */
 168                 udelay(740);
 169                 count = 0;
 170
 171                 while (count++ < MAX_WAIT_COUNT) {
 172                         if ((readw(host->ioaddr + SD_CE_ATA_2)
 173                                                 & SDCE_MISC_INT) == 0)
 174                                 break;
 175                         udelay(10);
 176                 }
 177
 178                 if (count == MAX_WAIT_COUNT)
 179                         dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
 180
 181                 /* clear the interrupt bit if posted */
 182                 tmp = readw(host->ioaddr + SD_CE_ATA_2);
 183                 tmp |= SDCE_MISC_INT;
 184                 writew(tmp, host->ioaddr + SD_CE_ATA_2);
 185         }
 186         pxa->power_mode = power_mode;
 187 }
 188
 189 static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 190 {
 191         u16 ctrl_2;
 192
 193         /*
 194          * Set V18_EN -- UHS modes do not work without this.
 195          * does not change signaling voltage
 196          */
 197         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 198
 199         /* Select Bus Speed Mode for host */
 200         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
 201         switch (uhs) {
 202         case MMC_TIMING_UHS_SDR12:
 203                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
 204                 break;
 205         case MMC_TIMING_UHS_SDR25:
 206                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
 207                 break;
 208         case MMC_TIMING_UHS_SDR50:
 209                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
 210                 break;
 211         case MMC_TIMING_UHS_SDR104:
 212                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
 213                 break;
 214         case MMC_TIMING_UHS_DDR50:
 215                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
 216                 break;
 217         }
 218
 219         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 220         dev_dbg(mmc_dev(host->mmc),
 221                 "%s uhs = %d, ctrl_2 = %04X\n",
 222                 __func__, uhs, ctrl_2);
 223 }
 224
 225 static const struct sdhci_ops pxav3_sdhci_ops = {
 226         .set_clock = sdhci_set_clock,
 227         .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
 228         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 229         .set_bus_width = sdhci_set_bus_width,
 230         .reset = pxav3_reset,
 231         .set_uhs_signaling = pxav3_set_uhs_signaling,
 232 };
 233
 234 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
 235         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
 236                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 237                 | SDHCI_QUIRK_32BIT_ADMA_SIZE
 238                 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
 239         .ops = &pxav3_sdhci_ops,
 240 };
 241
 242 #ifdef CONFIG_OF
 243 static const struct of_device_id sdhci_pxav3_of_match[] = {
 244         {
 245                 .compatible = "mrvl,pxav3-mmc",
 246         },
 247         {
 248                 .compatible = "marvell,armada-380-sdhci",
 249         },
 250         {},
 251 };
 252 MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
 253
 254 static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 255 {
 256         struct sdhci_pxa_platdata *pdata;
 257         struct device_node *np = dev->of_node;
 258         u32 clk_delay_cycles;
 259
 260         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 261         if (!pdata)
 262                 return NULL;
 263
 264         of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
 265         if (clk_delay_cycles > 0)
 266                 pdata->clk_delay_cycles = clk_delay_cycles;
 267
 268         return pdata;
 269 }
 270 #else
 271 static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
 272 {
 273         return NULL;
 274 }
 275 #endif
 276
 277 static int sdhci_pxav3_probe(struct platform_device *pdev)
 278 {
 279         struct sdhci_pltfm_host *pltfm_host;
 280         struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
 281         struct device *dev = &pdev->dev;
 282         struct device_node *np = pdev->dev.of_node;
 283         struct sdhci_host *host = NULL;
 284         struct sdhci_pxa *pxa = NULL;
 285         const struct of_device_id *match;
 286
 287         int ret;
 288         struct clk *clk;
 289
 290         pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
 291         if (!pxa)
 292                 return -ENOMEM;
 293
 294         host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
 295         if (IS_ERR(host))
 296                 return PTR_ERR(host);
 297
 298         if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
 299                 ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
 300                 if (ret < 0)
 301                         goto err_mbus_win;
 302         }
 303
 304
 305         pltfm_host = sdhci_priv(host);
 306         pltfm_host->priv = pxa;
 307
 308         clk = devm_clk_get(dev, NULL);
 309         if (IS_ERR(clk)) {
 310                 dev_err(dev, "failed to get io clock\n");
 311                 ret = PTR_ERR(clk);
 312                 goto err_clk_get;
 313         }
 314         pltfm_host->clk = clk;
 315         clk_prepare_enable(clk);
 316
 317         /* enable 1/8V DDR capable */
 318         host->mmc->caps |= MMC_CAP_1_8V_DDR;
 319
 320         match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
 321         if (match) {
 322                 ret = mmc_of_parse(host->mmc);
 323                 if (ret)
 324                         goto err_of_parse;
 325                 sdhci_get_of_property(pdev);
 326                 pdata = pxav3_get_mmc_pdata(dev);
 327         } else if (pdata) {
 328                 /* on-chip device */
 329                 if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
 330                         host->mmc->caps |= MMC_CAP_NONREMOVABLE;
 331
 332                 /* If slot design supports 8 bit data, indicate this to MMC. */
 333                 if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
 334                         host->mmc->caps |= MMC_CAP_8_BIT_DATA;
 335
 336                 if (pdata->quirks)
 337                         host->quirks |= pdata->quirks;
 338                 if (pdata->quirks2)
 339                         host->quirks2 |= pdata->quirks2;
 340                 if (pdata->host_caps)
 341                         host->mmc->caps |= pdata->host_caps;
 342                 if (pdata->host_caps2)
 343                         host->mmc->caps2 |= pdata->host_caps2;
 344                 if (pdata->pm_caps)
 345                         host->mmc->pm_caps |= pdata->pm_caps;
 346
 347                 if (gpio_is_valid(pdata->ext_cd_gpio)) {
 348                         ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
 349                                                   0);
 350                         if (ret) {
 351                                 dev_err(mmc_dev(host->mmc),
 352                                         "failed to allocate card detect gpio\n");
 353                                 goto err_cd_req;
 354                         }
 355                 }
 356         }
 357
 358         pm_runtime_enable(&pdev->dev);
 359         pm_runtime_get_sync(&pdev->dev);
 360         pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
 361         pm_runtime_use_autosuspend(&pdev->dev);
 362         pm_suspend_ignore_children(&pdev->dev, 1);
 363
 364         ret = sdhci_add_host(host);
 365         if (ret) {
 366                 dev_err(&pdev->dev, "failed to add host\n");
 367                 goto err_add_host;
 368         }
 369
 370         platform_set_drvdata(pdev, host);
 371
 372         if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
 373                 device_init_wakeup(&pdev->dev, 1);
 374                 host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
 375         } else {
 376                 device_init_wakeup(&pdev->dev, 0);
 377         }
 378
 379         pm_runtime_put_autosuspend(&pdev->dev);
 380
 381         return 0;
 382
 383 err_add_host:
 384         pm_runtime_put_sync(&pdev->dev);
 385         pm_runtime_disable(&pdev->dev);
 386 err_of_parse:
 387 err_cd_req:
 388         clk_disable_unprepare(clk);
 389 err_clk_get:
 390 err_mbus_win:
 391         sdhci_pltfm_free(pdev);
 392         return ret;
 393 }
 394
 395 static int sdhci_pxav3_remove(struct platform_device *pdev)
 396 {
 397         struct sdhci_host *host = platform_get_drvdata(pdev);
 398         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 399
 400         pm_runtime_get_sync(&pdev->dev);
 401         sdhci_remove_host(host, 1);
 402         pm_runtime_disable(&pdev->dev);
 403
 404         clk_disable_unprepare(pltfm_host->clk);
 405
 406         sdhci_pltfm_free(pdev);
 407
 408         return 0;
 409 }
 410
 411 #ifdef CONFIG_PM_SLEEP
 412 static int sdhci_pxav3_suspend(struct device *dev)
 413 {
 414         int ret;
 415         struct sdhci_host *host = dev_get_drvdata(dev);
 416
 417         pm_runtime_get_sync(dev);
 418         ret = sdhci_suspend_host(host);
 419         pm_runtime_mark_last_busy(dev);
 420         pm_runtime_put_autosuspend(dev);
 421
 422         return ret;
 423 }
 424
 425 static int sdhci_pxav3_resume(struct device *dev)
 426 {
 427         int ret;
 428         struct sdhci_host *host = dev_get_drvdata(dev);
 429
 430         pm_runtime_get_sync(dev);
 431         ret = sdhci_resume_host(host);
 432         pm_runtime_mark_last_busy(dev);
 433         pm_runtime_put_autosuspend(dev);
 434
 435         return ret;
 436 }
 437 #endif
 438
 439 #ifdef CONFIG_PM_RUNTIME
 440 static int sdhci_pxav3_runtime_suspend(struct device *dev)
 441 {
 442         struct sdhci_host *host = dev_get_drvdata(dev);
 443         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 444         unsigned long flags;
 445
 446         if (pltfm_host->clk) {
 447                 spin_lock_irqsave(&host->lock, flags);
 448                 host->runtime_suspended = true;
 449                 spin_unlock_irqrestore(&host->lock, flags);
 450
 451                 clk_disable_unprepare(pltfm_host->clk);
 452         }
 453
 454         return 0;
 455 }
 456
 457 static int sdhci_pxav3_runtime_resume(struct device *dev)
 458 {
 459         struct sdhci_host *host = dev_get_drvdata(dev);
 460         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 461         unsigned long flags;
 462
 463         if (pltfm_host->clk) {
 464                 clk_prepare_enable(pltfm_host->clk);
 465
 466                 spin_lock_irqsave(&host->lock, flags);
 467                 host->runtime_suspended = false;
 468                 spin_unlock_irqrestore(&host->lock, flags);
 469         }
 470
 471         return 0;
 472 }
 473 #endif
 474
 475 #ifdef CONFIG_PM
 476 static const struct dev_pm_ops sdhci_pxav3_pmops = {
 477         SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
 478         SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
 479                 sdhci_pxav3_runtime_resume, NULL)
 480 };
 481
 482 #define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
 483
 484 #else
 485 #define SDHCI_PXAV3_PMOPS NULL
 486 #endif
 487
 488 static struct platform_driver sdhci_pxav3_driver = {
 489         .driver         = {
 490                 .name   = "sdhci-pxav3",
 491 #ifdef CONFIG_OF
 492                 .of_match_table = sdhci_pxav3_of_match,
 493 #endif
 494                 .pm     = SDHCI_PXAV3_PMOPS,
 495         },
 496         .probe          = sdhci_pxav3_probe,
 497         .remove         = sdhci_pxav3_remove,
 498 };
 499
 500 module_platform_driver(sdhci_pxav3_driver);
 501
 502 MODULE_DESCRIPTION("SDHCI driver for pxav3");
 503 MODULE_AUTHOR("Marvell International Ltd.");
 504 MODULE_LICENSE("GPL v2");
 505