drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 /*
  48  * The ADMA2 descriptor table size is calculated as the maximum number of
  49  * segments (128), times 2 to allow for an alignment descriptor for each
  50  * segment, plus 1 for a nop end descriptor, all multipled by the 32-bit
  51  * descriptor size (8).
  52  */
  53 #define ADMA_SIZE       ((128 * 2 + 1) * 8)
  54
  55 static unsigned int debug_quirks = 0;
  56 static unsigned int debug_quirks2;
  57
  58 static void sdhci_finish_data(struct sdhci_host *);
  59
  60 static void sdhci_finish_command(struct sdhci_host *);
  61 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  62 static void sdhci_tuning_timer(unsigned long data);
  63 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  64
  65 #ifdef CONFIG_PM_RUNTIME
  66 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  67 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  68 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  69 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  70 #else
  71 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  72 {
  73         return 0;
  74 }
  75 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  76 {
  77         return 0;
  78 }
  79 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  80 {
  81 }
  82 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  83 {
  84 }
  85 #endif
  86
  87 static void sdhci_dumpregs(struct sdhci_host *host)
  88 {
  89         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  90                 mmc_hostname(host->mmc));
  91
  92         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  93                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  94                 sdhci_readw(host, SDHCI_HOST_VERSION));
  95         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  96                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  97                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  98         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  99                 sdhci_readl(host, SDHCI_ARGUMENT),
 100                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
 101         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 102                 sdhci_readl(host, SDHCI_PRESENT_STATE),
 103                 sdhci_readb(host, SDHCI_HOST_CONTROL));
 104         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 105                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 106                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 107         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 108                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 109                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 110         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 111                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 112                 sdhci_readl(host, SDHCI_INT_STATUS));
 113         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 114                 sdhci_readl(host, SDHCI_INT_ENABLE),
 115                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 116         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 117                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 118                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 119         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 120                 sdhci_readl(host, SDHCI_CAPABILITIES),
 121                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 122         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 123                 sdhci_readw(host, SDHCI_COMMAND),
 124                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 125         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 126                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 127
 128         if (host->flags & SDHCI_USE_ADMA)
 129                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 130                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 131                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 132
 133         pr_debug(DRIVER_NAME ": ===========================================\n");
 134 }
 135
 136 /*****************************************************************************\
 137  *                                                                           *
 138  * Low level functions                                                       *
 139  *                                                                           *
 140 \*****************************************************************************/
 141
 142 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 143 {
 144         u32 present;
 145
 146         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 147             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 148                 return;
 149
 150         if (enable) {
 151                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 152                                       SDHCI_CARD_PRESENT;
 153
 154                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 155                                        SDHCI_INT_CARD_INSERT;
 156         } else {
 157                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 158         }
 159
 160         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 161         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 162 }
 163
 164 static void sdhci_enable_card_detection(struct sdhci_host *host)
 165 {
 166         sdhci_set_card_detection(host, true);
 167 }
 168
 169 static void sdhci_disable_card_detection(struct sdhci_host *host)
 170 {
 171         sdhci_set_card_detection(host, false);
 172 }
 173
 174 void sdhci_reset(struct sdhci_host *host, u8 mask)
 175 {
 176         unsigned long timeout;
 177
 178         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 179
 180         if (mask & SDHCI_RESET_ALL) {
 181                 host->clock = 0;
 182                 /* Reset-all turns off SD Bus Power */
 183                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 184                         sdhci_runtime_pm_bus_off(host);
 185         }
 186
 187         /* Wait max 100 ms */
 188         timeout = 100;
 189
 190         /* hw clears the bit when it's done */
 191         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 192                 if (timeout == 0) {
 193                         pr_err("%s: Reset 0x%x never completed.\n",
 194                                 mmc_hostname(host->mmc), (int)mask);
 195                         sdhci_dumpregs(host);
 196                         return;
 197                 }
 198                 timeout--;
 199                 mdelay(1);
 200         }
 201 }
 202 EXPORT_SYMBOL_GPL(sdhci_reset);
 203
 204 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 205 {
 206         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 207                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 208                         SDHCI_CARD_PRESENT))
 209                         return;
 210         }
 211
 212         host->ops->reset(host, mask);
 213
 214         if (mask & SDHCI_RESET_ALL) {
 215                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 216                         if (host->ops->enable_dma)
 217                                 host->ops->enable_dma(host);
 218                 }
 219
 220                 /* Resetting the controller clears many */
 221                 host->preset_enabled = false;
 222         }
 223 }
 224
 225 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 226
 227 static void sdhci_init(struct sdhci_host *host, int soft)
 228 {
 229         if (soft)
 230                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 231         else
 232                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 233
 234         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 235                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 236                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 237                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 238                     SDHCI_INT_RESPONSE;
 239
 240         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 241         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 242
 243         if (soft) {
 244                 /* force clock reconfiguration */
 245                 host->clock = 0;
 246                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 247         }
 248 }
 249
 250 static void sdhci_reinit(struct sdhci_host *host)
 251 {
 252         sdhci_init(host, 0);
 253         /*
 254          * Retuning stuffs are affected by different cards inserted and only
 255          * applicable to UHS-I cards. So reset these fields to their initial
 256          * value when card is removed.
 257          */
 258         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 259                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 260
 261                 del_timer_sync(&host->tuning_timer);
 262                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 263                 host->mmc->max_blk_count =
 264                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 265         }
 266         sdhci_enable_card_detection(host);
 267 }
 268
 269 static void sdhci_activate_led(struct sdhci_host *host)
 270 {
 271         u8 ctrl;
 272
 273         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 274         ctrl |= SDHCI_CTRL_LED;
 275         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 276 }
 277
 278 static void sdhci_deactivate_led(struct sdhci_host *host)
 279 {
 280         u8 ctrl;
 281
 282         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 283         ctrl &= ~SDHCI_CTRL_LED;
 284         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 285 }
 286
 287 #ifdef SDHCI_USE_LEDS_CLASS
 288 static void sdhci_led_control(struct led_classdev *led,
 289         enum led_brightness brightness)
 290 {
 291         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 292         unsigned long flags;
 293
 294         spin_lock_irqsave(&host->lock, flags);
 295
 296         if (host->runtime_suspended)
 297                 goto out;
 298
 299         if (brightness == LED_OFF)
 300                 sdhci_deactivate_led(host);
 301         else
 302                 sdhci_activate_led(host);
 303 out:
 304         spin_unlock_irqrestore(&host->lock, flags);
 305 }
 306 #endif
 307
 308 /*****************************************************************************\
 309  *                                                                           *
 310  * Core functions                                                            *
 311  *                                                                           *
 312 \*****************************************************************************/
 313
 314 static void sdhci_read_block_pio(struct sdhci_host *host)
 315 {
 316         unsigned long flags;
 317         size_t blksize, len, chunk;
 318         u32 uninitialized_var(scratch);
 319         u8 *buf;
 320
 321         DBG("PIO reading\n");
 322
 323         blksize = host->data->blksz;
 324         chunk = 0;
 325
 326         local_irq_save(flags);
 327
 328         while (blksize) {
 329                 if (!sg_miter_next(&host->sg_miter))
 330                         BUG();
 331
 332                 len = min(host->sg_miter.length, blksize);
 333
 334                 blksize -= len;
 335                 host->sg_miter.consumed = len;
 336
 337                 buf = host->sg_miter.addr;
 338
 339                 while (len) {
 340                         if (chunk == 0) {
 341                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 342                                 chunk = 4;
 343                         }
 344
 345                         *buf = scratch & 0xFF;
 346
 347                         buf++;
 348                         scratch >>= 8;
 349                         chunk--;
 350                         len--;
 351                 }
 352         }
 353
 354         sg_miter_stop(&host->sg_miter);
 355
 356         local_irq_restore(flags);
 357 }
 358
 359 static void sdhci_write_block_pio(struct sdhci_host *host)
 360 {
 361         unsigned long flags;
 362         size_t blksize, len, chunk;
 363         u32 scratch;
 364         u8 *buf;
 365
 366         DBG("PIO writing\n");
 367
 368         blksize = host->data->blksz;
 369         chunk = 0;
 370         scratch = 0;
 371
 372         local_irq_save(flags);
 373
 374         while (blksize) {
 375                 if (!sg_miter_next(&host->sg_miter))
 376                         BUG();
 377
 378                 len = min(host->sg_miter.length, blksize);
 379
 380                 blksize -= len;
 381                 host->sg_miter.consumed = len;
 382
 383                 buf = host->sg_miter.addr;
 384
 385                 while (len) {
 386                         scratch |= (u32)*buf << (chunk * 8);
 387
 388                         buf++;
 389                         chunk++;
 390                         len--;
 391
 392                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 393                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 394                                 chunk = 0;
 395                                 scratch = 0;
 396                         }
 397                 }
 398         }
 399
 400         sg_miter_stop(&host->sg_miter);
 401
 402         local_irq_restore(flags);
 403 }
 404
 405 static void sdhci_transfer_pio(struct sdhci_host *host)
 406 {
 407         u32 mask;
 408
 409         BUG_ON(!host->data);
 410
 411         if (host->blocks == 0)
 412                 return;
 413
 414         if (host->data->flags & MMC_DATA_READ)
 415                 mask = SDHCI_DATA_AVAILABLE;
 416         else
 417                 mask = SDHCI_SPACE_AVAILABLE;
 418
 419         /*
 420          * Some controllers (JMicron JMB38x) mess up the buffer bits
 421          * for transfers < 4 bytes. As long as it is just one block,
 422          * we can ignore the bits.
 423          */
 424         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 425                 (host->data->blocks == 1))
 426                 mask = ~0;
 427
 428         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 429                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 430                         udelay(100);
 431
 432                 if (host->data->flags & MMC_DATA_READ)
 433                         sdhci_read_block_pio(host);
 434                 else
 435                         sdhci_write_block_pio(host);
 436
 437                 host->blocks--;
 438                 if (host->blocks == 0)
 439                         break;
 440         }
 441
 442         DBG("PIO transfer complete.\n");
 443 }
 444
 445 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 446 {
 447         local_irq_save(*flags);
 448         return kmap_atomic(sg_page(sg)) + sg->offset;
 449 }
 450
 451 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 452 {
 453         kunmap_atomic(buffer);
 454         local_irq_restore(*flags);
 455 }
 456
 457 static void sdhci_adma_write_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 458 {
 459         __le32 *dataddr = (__le32 __force *)(desc + 4);
 460         __le16 *cmdlen = (__le16 __force *)desc;
 461
 462         /* SDHCI specification says ADMA descriptors should be 4 byte
 463          * aligned, so using 16 or 32bit operations should be safe. */
 464
 465         cmdlen[0] = cpu_to_le16(cmd);
 466         cmdlen[1] = cpu_to_le16(len);
 467
 468         dataddr[0] = cpu_to_le32(addr);
 469 }
 470
 471 static void sdhci_adma_mark_end(void *desc)
 472 {
 473         u8 *dma_desc = desc;
 474
 475         dma_desc[0] |= 0x2; /* end */
 476 }
 477
 478 static int sdhci_adma_table_pre(struct sdhci_host *host,
 479         struct mmc_data *data)
 480 {
 481         int direction;
 482
 483         u8 *desc;
 484         u8 *align;
 485         dma_addr_t addr;
 486         dma_addr_t align_addr;
 487         int len, offset;
 488
 489         struct scatterlist *sg;
 490         int i;
 491         char *buffer;
 492         unsigned long flags;
 493
 494         /*
 495          * The spec does not specify endianness of descriptor table.
 496          * We currently guess that it is LE.
 497          */
 498
 499         if (data->flags & MMC_DATA_READ)
 500                 direction = DMA_FROM_DEVICE;
 501         else
 502                 direction = DMA_TO_DEVICE;
 503
 504         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 505                 host->align_buffer, 128 * 4, direction);
 506         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 507                 goto fail;
 508         BUG_ON(host->align_addr & 0x3);
 509
 510         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 511                 data->sg, data->sg_len, direction);
 512         if (host->sg_count == 0)
 513                 goto unmap_align;
 514
 515         desc = host->adma_table;
 516         align = host->align_buffer;
 517
 518         align_addr = host->align_addr;
 519
 520         for_each_sg(data->sg, sg, host->sg_count, i) {
 521                 addr = sg_dma_address(sg);
 522                 len = sg_dma_len(sg);
 523
 524                 /*
 525                  * The SDHCI specification states that ADMA
 526                  * addresses must be 32-bit aligned. If they
 527                  * aren't, then we use a bounce buffer for
 528                  * the (up to three) bytes that screw up the
 529                  * alignment.
 530                  */
 531                 offset = (4 - (addr & 0x3)) & 0x3;
 532                 if (offset) {
 533                         if (data->flags & MMC_DATA_WRITE) {
 534                                 buffer = sdhci_kmap_atomic(sg, &flags);
 535                                 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
 536                                         (PAGE_SIZE - offset));
 537                                 memcpy(align, buffer, offset);
 538                                 sdhci_kunmap_atomic(buffer, &flags);
 539                         }
 540
 541                         /* tran, valid */
 542                         sdhci_adma_write_desc(desc, align_addr, offset, 0x21);
 543
 544                         BUG_ON(offset > 65536);
 545
 546                         align += 4;
 547                         align_addr += 4;
 548
 549                         desc += 8;
 550
 551                         addr += offset;
 552                         len -= offset;
 553                 }
 554
 555                 BUG_ON(len > 65536);
 556
 557                 /* tran, valid */
 558                 sdhci_adma_write_desc(desc, addr, len, 0x21);
 559                 desc += 8;
 560
 561                 /*
 562                  * If this triggers then we have a calculation bug
 563                  * somewhere. :/
 564                  */
 565                 WARN_ON((desc - host->adma_table) >= ADMA_SIZE);
 566         }
 567
 568         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 569                 /*
 570                 * Mark the last descriptor as the terminating descriptor
 571                 */
 572                 if (desc != host->adma_table) {
 573                         desc -= 8;
 574                         sdhci_adma_mark_end(desc);
 575                 }
 576         } else {
 577                 /*
 578                 * Add a terminating entry.
 579                 */
 580
 581                 /* nop, end, valid */
 582                 sdhci_adma_write_desc(desc, 0, 0, 0x3);
 583         }
 584
 585         /*
 586          * Resync align buffer as we might have changed it.
 587          */
 588         if (data->flags & MMC_DATA_WRITE) {
 589                 dma_sync_single_for_device(mmc_dev(host->mmc),
 590                         host->align_addr, 128 * 4, direction);
 591         }
 592
 593         return 0;
 594
 595 unmap_align:
 596         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 597                 128 * 4, direction);
 598 fail:
 599         return -EINVAL;
 600 }
 601
 602 static void sdhci_adma_table_post(struct sdhci_host *host,
 603         struct mmc_data *data)
 604 {
 605         int direction;
 606
 607         struct scatterlist *sg;
 608         int i, size;
 609         u8 *align;
 610         char *buffer;
 611         unsigned long flags;
 612         bool has_unaligned;
 613
 614         if (data->flags & MMC_DATA_READ)
 615                 direction = DMA_FROM_DEVICE;
 616         else
 617                 direction = DMA_TO_DEVICE;
 618
 619         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 620                 128 * 4, direction);
 621
 622         /* Do a quick scan of the SG list for any unaligned mappings */
 623         has_unaligned = false;
 624         for_each_sg(data->sg, sg, host->sg_count, i)
 625                 if (sg_dma_address(sg) & 3) {
 626                         has_unaligned = true;
 627                         break;
 628                 }
 629
 630         if (has_unaligned && data->flags & MMC_DATA_READ) {
 631                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 632                         data->sg_len, direction);
 633
 634                 align = host->align_buffer;
 635
 636                 for_each_sg(data->sg, sg, host->sg_count, i) {
 637                         if (sg_dma_address(sg) & 0x3) {
 638                                 size = 4 - (sg_dma_address(sg) & 0x3);
 639
 640                                 buffer = sdhci_kmap_atomic(sg, &flags);
 641                                 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
 642                                         (PAGE_SIZE - size));
 643                                 memcpy(buffer, align, size);
 644                                 sdhci_kunmap_atomic(buffer, &flags);
 645
 646                                 align += 4;
 647                         }
 648                 }
 649         }
 650
 651         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 652                 data->sg_len, direction);
 653 }
 654
 655 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 656 {
 657         u8 count;
 658         struct mmc_data *data = cmd->data;
 659         unsigned target_timeout, current_timeout;
 660
 661         /*
 662          * If the host controller provides us with an incorrect timeout
 663          * value, just skip the check and use 0xE.  The hardware may take
 664          * longer to time out, but that's much better than having a too-short
 665          * timeout value.
 666          */
 667         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 668                 return 0xE;
 669
 670         /* Unspecified timeout, assume max */
 671         if (!data && !cmd->busy_timeout)
 672                 return 0xE;
 673
 674         /* timeout in us */
 675         if (!data)
 676                 target_timeout = cmd->busy_timeout * 1000;
 677         else {
 678                 target_timeout = data->timeout_ns / 1000;
 679                 if (host->clock)
 680                         target_timeout += data->timeout_clks / host->clock;
 681         }
 682
 683         /*
 684          * Figure out needed cycles.
 685          * We do this in steps in order to fit inside a 32 bit int.
 686          * The first step is the minimum timeout, which will have a
 687          * minimum resolution of 6 bits:
 688          * (1) 2^13*1000 > 2^22,
 689          * (2) host->timeout_clk < 2^16
 690          *     =>
 691          *     (1) / (2) > 2^6
 692          */
 693         count = 0;
 694         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 695         while (current_timeout < target_timeout) {
 696                 count++;
 697                 current_timeout <<= 1;
 698                 if (count >= 0xF)
 699                         break;
 700         }
 701
 702         if (count >= 0xF) {
 703                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 704                     mmc_hostname(host->mmc), count, cmd->opcode);
 705                 count = 0xE;
 706         }
 707
 708         return count;
 709 }
 710
 711 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 712 {
 713         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 714         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 715
 716         if (host->flags & SDHCI_REQ_USE_DMA)
 717                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 718         else
 719                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 720
 721         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 722         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 723 }
 724
 725 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 726 {
 727         u8 count;
 728
 729         if (host->ops->set_timeout) {
 730                 host->ops->set_timeout(host, cmd);
 731         } else {
 732                 count = sdhci_calc_timeout(host, cmd);
 733                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 734         }
 735 }
 736
 737 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 738 {
 739         u8 ctrl;
 740         struct mmc_data *data = cmd->data;
 741         int ret;
 742
 743         WARN_ON(host->data);
 744
 745         if (data || (cmd->flags & MMC_RSP_BUSY))
 746                 sdhci_set_timeout(host, cmd);
 747
 748         if (!data)
 749                 return;
 750
 751         /* Sanity checks */
 752         BUG_ON(data->blksz * data->blocks > 524288);
 753         BUG_ON(data->blksz > host->mmc->max_blk_size);
 754         BUG_ON(data->blocks > 65535);
 755
 756         host->data = data;
 757         host->data_early = 0;
 758         host->data->bytes_xfered = 0;
 759
 760         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 761                 host->flags |= SDHCI_REQ_USE_DMA;
 762
 763         /*
 764          * FIXME: This doesn't account for merging when mapping the
 765          * scatterlist.
 766          */
 767         if (host->flags & SDHCI_REQ_USE_DMA) {
 768                 int broken, i;
 769                 struct scatterlist *sg;
 770
 771                 broken = 0;
 772                 if (host->flags & SDHCI_USE_ADMA) {
 773                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 774                                 broken = 1;
 775                 } else {
 776                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 777                                 broken = 1;
 778                 }
 779
 780                 if (unlikely(broken)) {
 781                         for_each_sg(data->sg, sg, data->sg_len, i) {
 782                                 if (sg->length & 0x3) {
 783                                         DBG("Reverting to PIO because of "
 784                                                 "transfer size (%d)\n",
 785                                                 sg->length);
 786                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 787                                         break;
 788                                 }
 789                         }
 790                 }
 791         }
 792
 793         /*
 794          * The assumption here being that alignment is the same after
 795          * translation to device address space.
 796          */
 797         if (host->flags & SDHCI_REQ_USE_DMA) {
 798                 int broken, i;
 799                 struct scatterlist *sg;
 800
 801                 broken = 0;
 802                 if (host->flags & SDHCI_USE_ADMA) {
 803                         /*
 804                          * As we use 3 byte chunks to work around
 805                          * alignment problems, we need to check this
 806                          * quirk.
 807                          */
 808                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 809                                 broken = 1;
 810                 } else {
 811                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 812                                 broken = 1;
 813                 }
 814
 815                 if (unlikely(broken)) {
 816                         for_each_sg(data->sg, sg, data->sg_len, i) {
 817                                 if (sg->offset & 0x3) {
 818                                         DBG("Reverting to PIO because of "
 819                                                 "bad alignment\n");
 820                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 821                                         break;
 822                                 }
 823                         }
 824                 }
 825         }
 826
 827         if (host->flags & SDHCI_REQ_USE_DMA) {
 828                 if (host->flags & SDHCI_USE_ADMA) {
 829                         ret = sdhci_adma_table_pre(host, data);
 830                         if (ret) {
 831                                 /*
 832                                  * This only happens when someone fed
 833                                  * us an invalid request.
 834                                  */
 835                                 WARN_ON(1);
 836                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 837                         } else {
 838                                 sdhci_writel(host, host->adma_addr,
 839                                         SDHCI_ADMA_ADDRESS);
 840                         }
 841                 } else {
 842                         int sg_cnt;
 843
 844                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 845                                         data->sg, data->sg_len,
 846                                         (data->flags & MMC_DATA_READ) ?
 847                                                 DMA_FROM_DEVICE :
 848                                                 DMA_TO_DEVICE);
 849                         if (sg_cnt == 0) {
 850                                 /*
 851                                  * This only happens when someone fed
 852                                  * us an invalid request.
 853                                  */
 854                                 WARN_ON(1);
 855                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 856                         } else {
 857                                 WARN_ON(sg_cnt != 1);
 858                                 sdhci_writel(host, sg_dma_address(data->sg),
 859                                         SDHCI_DMA_ADDRESS);
 860                         }
 861                 }
 862         }
 863
 864         /*
 865          * Always adjust the DMA selection as some controllers
 866          * (e.g. JMicron) can't do PIO properly when the selection
 867          * is ADMA.
 868          */
 869         if (host->version >= SDHCI_SPEC_200) {
 870                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 871                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 872                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 873                         (host->flags & SDHCI_USE_ADMA))
 874                         ctrl |= SDHCI_CTRL_ADMA32;
 875                 else
 876                         ctrl |= SDHCI_CTRL_SDMA;
 877                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 878         }
 879
 880         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 881                 int flags;
 882
 883                 flags = SG_MITER_ATOMIC;
 884                 if (host->data->flags & MMC_DATA_READ)
 885                         flags |= SG_MITER_TO_SG;
 886                 else
 887                         flags |= SG_MITER_FROM_SG;
 888                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 889                 host->blocks = data->blocks;
 890         }
 891
 892         sdhci_set_transfer_irqs(host);
 893
 894         /* Set the DMA boundary value and block size */
 895         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 896                 data->blksz), SDHCI_BLOCK_SIZE);
 897         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 898 }
 899
 900 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 901         struct mmc_command *cmd)
 902 {
 903         u16 mode;
 904         struct mmc_data *data = cmd->data;
 905
 906         if (data == NULL) {
 907                 /* clear Auto CMD settings for no data CMDs */
 908                 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 909                 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 910                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 911                 return;
 912         }
 913
 914         WARN_ON(!host->data);
 915
 916         mode = SDHCI_TRNS_BLK_CNT_EN;
 917         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 918                 mode |= SDHCI_TRNS_MULTI;
 919                 /*
 920                  * If we are sending CMD23, CMD12 never gets sent
 921                  * on successful completion (so no Auto-CMD12).
 922                  */
 923                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 924                         mode |= SDHCI_TRNS_AUTO_CMD12;
 925                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 926                         mode |= SDHCI_TRNS_AUTO_CMD23;
 927                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 928                 }
 929         }
 930
 931         if (data->flags & MMC_DATA_READ)
 932                 mode |= SDHCI_TRNS_READ;
 933         if (host->flags & SDHCI_REQ_USE_DMA)
 934                 mode |= SDHCI_TRNS_DMA;
 935
 936         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 937 }
 938
 939 static void sdhci_finish_data(struct sdhci_host *host)
 940 {
 941         struct mmc_data *data;
 942
 943         BUG_ON(!host->data);
 944
 945         data = host->data;
 946         host->data = NULL;
 947
 948         if (host->flags & SDHCI_REQ_USE_DMA) {
 949                 if (host->flags & SDHCI_USE_ADMA)
 950                         sdhci_adma_table_post(host, data);
 951                 else {
 952                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 953                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 954                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 955                 }
 956         }
 957
 958         /*
 959          * The specification states that the block count register must
 960          * be updated, but it does not specify at what point in the
 961          * data flow. That makes the register entirely useless to read
 962          * back so we have to assume that nothing made it to the card
 963          * in the event of an error.
 964          */
 965         if (data->error)
 966                 data->bytes_xfered = 0;
 967         else
 968                 data->bytes_xfered = data->blksz * data->blocks;
 969
 970         /*
 971          * Need to send CMD12 if -
 972          * a) open-ended multiblock transfer (no CMD23)
 973          * b) error in multiblock transfer
 974          */
 975         if (data->stop &&
 976             (data->error ||
 977              !host->mrq->sbc)) {
 978
 979                 /*
 980                  * The controller needs a reset of internal state machines
 981                  * upon error conditions.
 982                  */
 983                 if (data->error) {
 984                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 985                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 986                 }
 987
 988                 sdhci_send_command(host, data->stop);
 989         } else
 990                 tasklet_schedule(&host->finish_tasklet);
 991 }
 992
 993 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 994 {
 995         int flags;
 996         u32 mask;
 997         unsigned long timeout;
 998
 999         WARN_ON(host->cmd);
1000
1001         /* Wait max 10 ms */
1002         timeout = 10;
1003
1004         mask = SDHCI_CMD_INHIBIT;
1005         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1006                 mask |= SDHCI_DATA_INHIBIT;
1007
1008         /* We shouldn't wait for data inihibit for stop commands, even
1009            though they might use busy signaling */
1010         if (host->mrq->data && (cmd == host->mrq->data->stop))
1011                 mask &= ~SDHCI_DATA_INHIBIT;
1012
1013         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1014                 if (timeout == 0) {
1015                         pr_err("%s: Controller never released "
1016                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1017                         sdhci_dumpregs(host);
1018                         cmd->error = -EIO;
1019                         tasklet_schedule(&host->finish_tasklet);
1020                         return;
1021                 }
1022                 timeout--;
1023                 mdelay(1);
1024         }
1025
1026         timeout = jiffies;
1027         if (!cmd->data && cmd->busy_timeout > 9000)
1028                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1029         else
1030                 timeout += 10 * HZ;
1031         mod_timer(&host->timer, timeout);
1032
1033         host->cmd = cmd;
1034         host->busy_handle = 0;
1035
1036         sdhci_prepare_data(host, cmd);
1037
1038         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1039
1040         sdhci_set_transfer_mode(host, cmd);
1041
1042         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1043                 pr_err("%s: Unsupported response type!\n",
1044                         mmc_hostname(host->mmc));
1045                 cmd->error = -EINVAL;
1046                 tasklet_schedule(&host->finish_tasklet);
1047                 return;
1048         }
1049
1050         if (!(cmd->flags & MMC_RSP_PRESENT))
1051                 flags = SDHCI_CMD_RESP_NONE;
1052         else if (cmd->flags & MMC_RSP_136)
1053                 flags = SDHCI_CMD_RESP_LONG;
1054         else if (cmd->flags & MMC_RSP_BUSY)
1055                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1056         else
1057                 flags = SDHCI_CMD_RESP_SHORT;
1058
1059         if (cmd->flags & MMC_RSP_CRC)
1060                 flags |= SDHCI_CMD_CRC;
1061         if (cmd->flags & MMC_RSP_OPCODE)
1062                 flags |= SDHCI_CMD_INDEX;
1063
1064         /* CMD19 is special in that the Data Present Select should be set */
1065         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1066             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1067                 flags |= SDHCI_CMD_DATA;
1068
1069         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1070 }
1071 EXPORT_SYMBOL_GPL(sdhci_send_command);
1072
1073 static void sdhci_finish_command(struct sdhci_host *host)
1074 {
1075         int i;
1076
1077         BUG_ON(host->cmd == NULL);
1078
1079         if (host->cmd->flags & MMC_RSP_PRESENT) {
1080                 if (host->cmd->flags & MMC_RSP_136) {
1081                         /* CRC is stripped so we need to do some shifting. */
1082                         for (i = 0;i < 4;i++) {
1083                                 host->cmd->resp[i] = sdhci_readl(host,
1084                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1085                                 if (i != 3)
1086                                         host->cmd->resp[i] |=
1087                                                 sdhci_readb(host,
1088                                                 SDHCI_RESPONSE + (3-i)*4-1);
1089                         }
1090                 } else {
1091                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1092                 }
1093         }
1094
1095         host->cmd->error = 0;
1096
1097         /* Finished CMD23, now send actual command. */
1098         if (host->cmd == host->mrq->sbc) {
1099                 host->cmd = NULL;
1100                 sdhci_send_command(host, host->mrq->cmd);
1101         } else {
1102
1103                 /* Processed actual command. */
1104                 if (host->data && host->data_early)
1105                         sdhci_finish_data(host);
1106
1107                 if (!host->cmd->data)
1108                         tasklet_schedule(&host->finish_tasklet);
1109
1110                 host->cmd = NULL;
1111         }
1112 }
1113
1114 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1115 {
1116         u16 preset = 0;
1117
1118         switch (host->timing) {
1119         case MMC_TIMING_UHS_SDR12:
1120                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1121                 break;
1122         case MMC_TIMING_UHS_SDR25:
1123                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1124                 break;
1125         case MMC_TIMING_UHS_SDR50:
1126                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1127                 break;
1128         case MMC_TIMING_UHS_SDR104:
1129         case MMC_TIMING_MMC_HS200:
1130                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1131                 break;
1132         case MMC_TIMING_UHS_DDR50:
1133                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1134                 break;
1135         default:
1136                 pr_warn("%s: Invalid UHS-I mode selected\n",
1137                         mmc_hostname(host->mmc));
1138                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1139                 break;
1140         }
1141         return preset;
1142 }
1143
1144 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1145 {
1146         int div = 0; /* Initialized for compiler warning */
1147         int real_div = div, clk_mul = 1;
1148         u16 clk = 0;
1149         unsigned long timeout;
1150
1151         host->mmc->actual_clock = 0;
1152
1153         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1154
1155         if (clock == 0)
1156                 return;
1157
1158         if (host->version >= SDHCI_SPEC_300) {
1159                 if (host->preset_enabled) {
1160                         u16 pre_val;
1161
1162                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1163                         pre_val = sdhci_get_preset_value(host);
1164                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1165                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1166                         if (host->clk_mul &&
1167                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1168                                 clk = SDHCI_PROG_CLOCK_MODE;
1169                                 real_div = div + 1;
1170                                 clk_mul = host->clk_mul;
1171                         } else {
1172                                 real_div = max_t(int, 1, div << 1);
1173                         }
1174                         goto clock_set;
1175                 }
1176
1177                 /*
1178                  * Check if the Host Controller supports Programmable Clock
1179                  * Mode.
1180                  */
1181                 if (host->clk_mul) {
1182                         for (div = 1; div <= 1024; div++) {
1183                                 if ((host->max_clk * host->clk_mul / div)
1184                                         <= clock)
1185                                         break;
1186                         }
1187                         /*
1188                          * Set Programmable Clock Mode in the Clock
1189                          * Control register.
1190                          */
1191                         clk = SDHCI_PROG_CLOCK_MODE;
1192                         real_div = div;
1193                         clk_mul = host->clk_mul;
1194                         div--;
1195                 } else {
1196                         /* Version 3.00 divisors must be a multiple of 2. */
1197                         if (host->max_clk <= clock)
1198                                 div = 1;
1199                         else {
1200                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1201                                      div += 2) {
1202                                         if ((host->max_clk / div) <= clock)
1203                                                 break;
1204                                 }
1205                         }
1206                         real_div = div;
1207                         div >>= 1;
1208                 }
1209         } else {
1210                 /* Version 2.00 divisors must be a power of 2. */
1211                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1212                         if ((host->max_clk / div) <= clock)
1213                                 break;
1214                 }
1215                 real_div = div;
1216                 div >>= 1;
1217         }
1218
1219 clock_set:
1220         if (real_div)
1221                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1222         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1223         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1224                 << SDHCI_DIVIDER_HI_SHIFT;
1225         clk |= SDHCI_CLOCK_INT_EN;
1226         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1227
1228         /* Wait max 20 ms */
1229         timeout = 20;
1230         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1231                 & SDHCI_CLOCK_INT_STABLE)) {
1232                 if (timeout == 0) {
1233                         pr_err("%s: Internal clock never "
1234                                 "stabilised.\n", mmc_hostname(host->mmc));
1235                         sdhci_dumpregs(host);
1236                         return;
1237                 }
1238                 timeout--;
1239                 mdelay(1);
1240         }
1241
1242         clk |= SDHCI_CLOCK_CARD_EN;
1243         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1244 }
1245 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1246
1247 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1248                             unsigned short vdd)
1249 {
1250         struct mmc_host *mmc = host->mmc;
1251         u8 pwr = 0;
1252
1253         if (!IS_ERR(mmc->supply.vmmc)) {
1254                 spin_unlock_irq(&host->lock);
1255                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1256                 spin_lock_irq(&host->lock);
1257                 return;
1258         }
1259
1260         if (mode != MMC_POWER_OFF) {
1261                 switch (1 << vdd) {
1262                 case MMC_VDD_165_195:
1263                         pwr = SDHCI_POWER_180;
1264                         break;
1265                 case MMC_VDD_29_30:
1266                 case MMC_VDD_30_31:
1267                         pwr = SDHCI_POWER_300;
1268                         break;
1269                 case MMC_VDD_32_33:
1270                 case MMC_VDD_33_34:
1271                         pwr = SDHCI_POWER_330;
1272                         break;
1273                 default:
1274                         BUG();
1275                 }
1276         }
1277
1278         if (host->pwr == pwr)
1279                 return;
1280
1281         host->pwr = pwr;
1282
1283         if (pwr == 0) {
1284                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1285                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1286                         sdhci_runtime_pm_bus_off(host);
1287                 vdd = 0;
1288         } else {
1289                 /*
1290                  * Spec says that we should clear the power reg before setting
1291                  * a new value. Some controllers don't seem to like this though.
1292                  */
1293                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1294                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1295
1296                 /*
1297                  * At least the Marvell CaFe chip gets confused if we set the
1298                  * voltage and set turn on power at the same time, so set the
1299                  * voltage first.
1300                  */
1301                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1302                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1303
1304                 pwr |= SDHCI_POWER_ON;
1305
1306                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1307
1308                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1309                         sdhci_runtime_pm_bus_on(host);
1310
1311                 /*
1312                  * Some controllers need an extra 10ms delay of 10ms before
1313                  * they can apply clock after applying power
1314                  */
1315                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1316                         mdelay(10);
1317         }
1318 }
1319
1320 /*****************************************************************************\
1321  *                                                                           *
1322  * MMC callbacks                                                             *
1323  *                                                                           *
1324 \*****************************************************************************/
1325
1326 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1327 {
1328         struct sdhci_host *host;
1329         int present;
1330         unsigned long flags;
1331         u32 tuning_opcode;
1332
1333         host = mmc_priv(mmc);
1334
1335         sdhci_runtime_pm_get(host);
1336
1337         spin_lock_irqsave(&host->lock, flags);
1338
1339         WARN_ON(host->mrq != NULL);
1340
1341 #ifndef SDHCI_USE_LEDS_CLASS
1342         sdhci_activate_led(host);
1343 #endif
1344
1345         /*
1346          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1347          * requests if Auto-CMD12 is enabled.
1348          */
1349         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1350                 if (mrq->stop) {
1351                         mrq->data->stop = NULL;
1352                         mrq->stop = NULL;
1353                 }
1354         }
1355
1356         host->mrq = mrq;
1357
1358         /*
1359          * Firstly check card presence from cd-gpio.  The return could
1360          * be one of the following possibilities:
1361          *     negative: cd-gpio is not available
1362          *     zero: cd-gpio is used, and card is removed
1363          *     one: cd-gpio is used, and card is present
1364          */
1365         present = mmc_gpio_get_cd(host->mmc);
1366         if (present < 0) {
1367                 /* If polling, assume that the card is always present. */
1368                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1369                         present = 1;
1370                 else
1371                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1372                                         SDHCI_CARD_PRESENT;
1373         }
1374
1375         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1376                 host->mrq->cmd->error = -ENOMEDIUM;
1377                 tasklet_schedule(&host->finish_tasklet);
1378         } else {
1379                 u32 present_state;
1380
1381                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1382                 /*
1383                  * Check if the re-tuning timer has already expired and there
1384                  * is no on-going data transfer and DAT0 is not busy. If so,
1385                  * we need to execute tuning procedure before sending command.
1386                  */
1387                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1388                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1389                     (present_state & SDHCI_DATA_0_LVL_MASK)) {
1390                         if (mmc->card) {
1391                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1392                                 tuning_opcode =
1393                                         mmc->card->type == MMC_TYPE_MMC ?
1394                                         MMC_SEND_TUNING_BLOCK_HS200 :
1395                                         MMC_SEND_TUNING_BLOCK;
1396
1397                                 /* Here we need to set the host->mrq to NULL,
1398                                  * in case the pending finish_tasklet
1399                                  * finishes it incorrectly.
1400                                  */
1401                                 host->mrq = NULL;
1402
1403                                 spin_unlock_irqrestore(&host->lock, flags);
1404                                 sdhci_execute_tuning(mmc, tuning_opcode);
1405                                 spin_lock_irqsave(&host->lock, flags);
1406
1407                                 /* Restore original mmc_request structure */
1408                                 host->mrq = mrq;
1409                         }
1410                 }
1411
1412                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1413                         sdhci_send_command(host, mrq->sbc);
1414                 else
1415                         sdhci_send_command(host, mrq->cmd);
1416         }
1417
1418         mmiowb();
1419         spin_unlock_irqrestore(&host->lock, flags);
1420 }
1421
1422 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1423 {
1424         u8 ctrl;
1425
1426         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1427         if (width == MMC_BUS_WIDTH_8) {
1428                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1429                 if (host->version >= SDHCI_SPEC_300)
1430                         ctrl |= SDHCI_CTRL_8BITBUS;
1431         } else {
1432                 if (host->version >= SDHCI_SPEC_300)
1433                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1434                 if (width == MMC_BUS_WIDTH_4)
1435                         ctrl |= SDHCI_CTRL_4BITBUS;
1436                 else
1437                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1438         }
1439         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1440 }
1441 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1442
1443 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1444 {
1445         u16 ctrl_2;
1446
1447         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1448         /* Select Bus Speed Mode for host */
1449         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1450         if ((timing == MMC_TIMING_MMC_HS200) ||
1451             (timing == MMC_TIMING_UHS_SDR104))
1452                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1453         else if (timing == MMC_TIMING_UHS_SDR12)
1454                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1455         else if (timing == MMC_TIMING_UHS_SDR25)
1456                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1457         else if (timing == MMC_TIMING_UHS_SDR50)
1458                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1459         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1460                  (timing == MMC_TIMING_MMC_DDR52))
1461                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1462         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1463 }
1464 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1465
1466 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1467 {
1468         unsigned long flags;
1469         u8 ctrl;
1470         struct mmc_host *mmc = host->mmc;
1471
1472         spin_lock_irqsave(&host->lock, flags);
1473
1474         if (host->flags & SDHCI_DEVICE_DEAD) {
1475                 spin_unlock_irqrestore(&host->lock, flags);
1476                 if (!IS_ERR(mmc->supply.vmmc) &&
1477                     ios->power_mode == MMC_POWER_OFF)
1478                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1479                 return;
1480         }
1481
1482         /*
1483          * Reset the chip on each power off.
1484          * Should clear out any weird states.
1485          */
1486         if (ios->power_mode == MMC_POWER_OFF) {
1487                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1488                 sdhci_reinit(host);
1489         }
1490
1491         if (host->version >= SDHCI_SPEC_300 &&
1492                 (ios->power_mode == MMC_POWER_UP) &&
1493                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1494                 sdhci_enable_preset_value(host, false);
1495
1496         if (!ios->clock || ios->clock != host->clock) {
1497                 host->ops->set_clock(host, ios->clock);
1498                 host->clock = ios->clock;
1499
1500                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1501                     host->clock) {
1502                         host->timeout_clk = host->mmc->actual_clock ?
1503                                                 host->mmc->actual_clock / 1000 :
1504                                                 host->clock / 1000;
1505                         host->mmc->max_busy_timeout =
1506                                 host->ops->get_max_timeout_count ?
1507                                 host->ops->get_max_timeout_count(host) :
1508                                 1 << 27;
1509                         host->mmc->max_busy_timeout /= host->timeout_clk;
1510                 }
1511         }
1512
1513         sdhci_set_power(host, ios->power_mode, ios->vdd);
1514
1515         if (host->ops->platform_send_init_74_clocks)
1516                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1517
1518         host->ops->set_bus_width(host, ios->bus_width);
1519
1520         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1521
1522         if ((ios->timing == MMC_TIMING_SD_HS ||
1523              ios->timing == MMC_TIMING_MMC_HS)
1524             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1525                 ctrl |= SDHCI_CTRL_HISPD;
1526         else
1527                 ctrl &= ~SDHCI_CTRL_HISPD;
1528
1529         if (host->version >= SDHCI_SPEC_300) {
1530                 u16 clk, ctrl_2;
1531
1532                 /* In case of UHS-I modes, set High Speed Enable */
1533                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1534                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1535                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1536                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1537                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1538                     (ios->timing == MMC_TIMING_UHS_SDR25))
1539                         ctrl |= SDHCI_CTRL_HISPD;
1540
1541                 if (!host->preset_enabled) {
1542                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1543                         /*
1544                          * We only need to set Driver Strength if the
1545                          * preset value enable is not set.
1546                          */
1547                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1548                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1549                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1550                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1551                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1552                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1553
1554                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1555                 } else {
1556                         /*
1557                          * According to SDHC Spec v3.00, if the Preset Value
1558                          * Enable in the Host Control 2 register is set, we
1559                          * need to reset SD Clock Enable before changing High
1560                          * Speed Enable to avoid generating clock gliches.
1561                          */
1562
1563                         /* Reset SD Clock Enable */
1564                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1565                         clk &= ~SDHCI_CLOCK_CARD_EN;
1566                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1567
1568                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1569
1570                         /* Re-enable SD Clock */
1571                         host->ops->set_clock(host, host->clock);
1572                 }
1573
1574                 /* Reset SD Clock Enable */
1575                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1576                 clk &= ~SDHCI_CLOCK_CARD_EN;
1577                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1578
1579                 host->ops->set_uhs_signaling(host, ios->timing);
1580                 host->timing = ios->timing;
1581
1582                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1583                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1584                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1585                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1586                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1587                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1588                         u16 preset;
1589
1590                         sdhci_enable_preset_value(host, true);
1591                         preset = sdhci_get_preset_value(host);
1592                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1593                                 >> SDHCI_PRESET_DRV_SHIFT;
1594                 }
1595
1596                 /* Re-enable SD Clock */
1597                 host->ops->set_clock(host, host->clock);
1598         } else
1599                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1600
1601         /*
1602          * Some (ENE) controllers go apeshit on some ios operation,
1603          * signalling timeout and CRC errors even on CMD0. Resetting
1604          * it on each ios seems to solve the problem.
1605          */
1606         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1607                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1608
1609         mmiowb();
1610         spin_unlock_irqrestore(&host->lock, flags);
1611 }
1612
1613 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1614 {
1615         struct sdhci_host *host = mmc_priv(mmc);
1616
1617         sdhci_runtime_pm_get(host);
1618         sdhci_do_set_ios(host, ios);
1619         sdhci_runtime_pm_put(host);
1620 }
1621
1622 static int sdhci_do_get_cd(struct sdhci_host *host)
1623 {
1624         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1625
1626         if (host->flags & SDHCI_DEVICE_DEAD)
1627                 return 0;
1628
1629         /* If polling/nonremovable, assume that the card is always present. */
1630         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1631             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1632                 return 1;
1633
1634         /* Try slot gpio detect */
1635         if (!IS_ERR_VALUE(gpio_cd))
1636                 return !!gpio_cd;
1637
1638         /* Host native card detect */
1639         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1640 }
1641
1642 static int sdhci_get_cd(struct mmc_host *mmc)
1643 {
1644         struct sdhci_host *host = mmc_priv(mmc);
1645         int ret;
1646
1647         sdhci_runtime_pm_get(host);
1648         ret = sdhci_do_get_cd(host);
1649         sdhci_runtime_pm_put(host);
1650         return ret;
1651 }
1652
1653 static int sdhci_check_ro(struct sdhci_host *host)
1654 {
1655         unsigned long flags;
1656         int is_readonly;
1657
1658         spin_lock_irqsave(&host->lock, flags);
1659
1660         if (host->flags & SDHCI_DEVICE_DEAD)
1661                 is_readonly = 0;
1662         else if (host->ops->get_ro)
1663                 is_readonly = host->ops->get_ro(host);
1664         else
1665                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1666                                 & SDHCI_WRITE_PROTECT);
1667
1668         spin_unlock_irqrestore(&host->lock, flags);
1669
1670         /* This quirk needs to be replaced by a callback-function later */
1671         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1672                 !is_readonly : is_readonly;
1673 }
1674
1675 #define SAMPLE_COUNT    5
1676
1677 static int sdhci_do_get_ro(struct sdhci_host *host)
1678 {
1679         int i, ro_count;
1680
1681         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1682                 return sdhci_check_ro(host);
1683
1684         ro_count = 0;
1685         for (i = 0; i < SAMPLE_COUNT; i++) {
1686                 if (sdhci_check_ro(host)) {
1687                         if (++ro_count > SAMPLE_COUNT / 2)
1688                                 return 1;
1689                 }
1690                 msleep(30);
1691         }
1692         return 0;
1693 }
1694
1695 static void sdhci_hw_reset(struct mmc_host *mmc)
1696 {
1697         struct sdhci_host *host = mmc_priv(mmc);
1698
1699         if (host->ops && host->ops->hw_reset)
1700                 host->ops->hw_reset(host);
1701 }
1702
1703 static int sdhci_get_ro(struct mmc_host *mmc)
1704 {
1705         struct sdhci_host *host = mmc_priv(mmc);
1706         int ret;
1707
1708         sdhci_runtime_pm_get(host);
1709         ret = sdhci_do_get_ro(host);
1710         sdhci_runtime_pm_put(host);
1711         return ret;
1712 }
1713
1714 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1715 {
1716         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1717                 if (enable)
1718                         host->ier |= SDHCI_INT_CARD_INT;
1719                 else
1720                         host->ier &= ~SDHCI_INT_CARD_INT;
1721
1722                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1723                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1724                 mmiowb();
1725         }
1726 }
1727
1728 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1729 {
1730         struct sdhci_host *host = mmc_priv(mmc);
1731         unsigned long flags;
1732
1733         sdhci_runtime_pm_get(host);
1734
1735         spin_lock_irqsave(&host->lock, flags);
1736         if (enable)
1737                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1738         else
1739                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1740
1741         sdhci_enable_sdio_irq_nolock(host, enable);
1742         spin_unlock_irqrestore(&host->lock, flags);
1743
1744         sdhci_runtime_pm_put(host);
1745 }
1746
1747 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1748                                                 struct mmc_ios *ios)
1749 {
1750         struct mmc_host *mmc = host->mmc;
1751         u16 ctrl;
1752         int ret;
1753
1754         /*
1755          * Signal Voltage Switching is only applicable for Host Controllers
1756          * v3.00 and above.
1757          */
1758         if (host->version < SDHCI_SPEC_300)
1759                 return 0;
1760
1761         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1762
1763         switch (ios->signal_voltage) {
1764         case MMC_SIGNAL_VOLTAGE_330:
1765                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1766                 ctrl &= ~SDHCI_CTRL_VDD_180;
1767                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1768
1769                 if (!IS_ERR(mmc->supply.vqmmc)) {
1770                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1771                                                     3600000);
1772                         if (ret) {
1773                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1774                                         mmc_hostname(mmc));
1775                                 return -EIO;
1776                         }
1777                 }
1778                 /* Wait for 5ms */
1779                 usleep_range(5000, 5500);
1780
1781                 /* 3.3V regulator output should be stable within 5 ms */
1782                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1783                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1784                         return 0;
1785
1786                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1787                         mmc_hostname(mmc));
1788
1789                 return -EAGAIN;
1790         case MMC_SIGNAL_VOLTAGE_180:
1791                 if (!IS_ERR(mmc->supply.vqmmc)) {
1792                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1793                                         1700000, 1950000);
1794                         if (ret) {
1795                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1796                                         mmc_hostname(mmc));
1797                                 return -EIO;
1798                         }
1799                 }
1800
1801                 /*
1802                  * Enable 1.8V Signal Enable in the Host Control2
1803                  * register
1804                  */
1805                 ctrl |= SDHCI_CTRL_VDD_180;
1806                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1807
1808                 /* 1.8V regulator output should be stable within 5 ms */
1809                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1810                 if (ctrl & SDHCI_CTRL_VDD_180)
1811                         return 0;
1812
1813                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1814                         mmc_hostname(mmc));
1815
1816                 return -EAGAIN;
1817         case MMC_SIGNAL_VOLTAGE_120:
1818                 if (!IS_ERR(mmc->supply.vqmmc)) {
1819                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1820                                                     1300000);
1821                         if (ret) {
1822                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1823                                         mmc_hostname(mmc));
1824                                 return -EIO;
1825                         }
1826                 }
1827                 return 0;
1828         default:
1829                 /* No signal voltage switch required */
1830                 return 0;
1831         }
1832 }
1833
1834 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1835         struct mmc_ios *ios)
1836 {
1837         struct sdhci_host *host = mmc_priv(mmc);
1838         int err;
1839
1840         if (host->version < SDHCI_SPEC_300)
1841                 return 0;
1842         sdhci_runtime_pm_get(host);
1843         err = sdhci_do_start_signal_voltage_switch(host, ios);
1844         sdhci_runtime_pm_put(host);
1845         return err;
1846 }
1847
1848 static int sdhci_card_busy(struct mmc_host *mmc)
1849 {
1850         struct sdhci_host *host = mmc_priv(mmc);
1851         u32 present_state;
1852
1853         sdhci_runtime_pm_get(host);
1854         /* Check whether DAT[3:0] is 0000 */
1855         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1856         sdhci_runtime_pm_put(host);
1857
1858         return !(present_state & SDHCI_DATA_LVL_MASK);
1859 }
1860
1861 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1862 {
1863         struct sdhci_host *host = mmc_priv(mmc);
1864         u16 ctrl;
1865         int tuning_loop_counter = MAX_TUNING_LOOP;
1866         int err = 0;
1867         unsigned long flags;
1868
1869         sdhci_runtime_pm_get(host);
1870         spin_lock_irqsave(&host->lock, flags);
1871
1872         /*
1873          * The Host Controller needs tuning only in case of SDR104 mode
1874          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1875          * Capabilities register.
1876          * If the Host Controller supports the HS200 mode then the
1877          * tuning function has to be executed.
1878          */
1879         switch (host->timing) {
1880         case MMC_TIMING_MMC_HS200:
1881         case MMC_TIMING_UHS_SDR104:
1882                 break;
1883
1884         case MMC_TIMING_UHS_SDR50:
1885                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1886                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1887                         break;
1888                 /* FALLTHROUGH */
1889
1890         default:
1891                 spin_unlock_irqrestore(&host->lock, flags);
1892                 sdhci_runtime_pm_put(host);
1893                 return 0;
1894         }
1895
1896         if (host->ops->platform_execute_tuning) {
1897                 spin_unlock_irqrestore(&host->lock, flags);
1898                 err = host->ops->platform_execute_tuning(host, opcode);
1899                 sdhci_runtime_pm_put(host);
1900                 return err;
1901         }
1902
1903         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1904         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1905         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1906
1907         /*
1908          * As per the Host Controller spec v3.00, tuning command
1909          * generates Buffer Read Ready interrupt, so enable that.
1910          *
1911          * Note: The spec clearly says that when tuning sequence
1912          * is being performed, the controller does not generate
1913          * interrupts other than Buffer Read Ready interrupt. But
1914          * to make sure we don't hit a controller bug, we _only_
1915          * enable Buffer Read Ready interrupt here.
1916          */
1917         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1918         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1919
1920         /*
1921          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1922          * of loops reaches 40 times or a timeout of 150ms occurs.
1923          */
1924         do {
1925                 struct mmc_command cmd = {0};
1926                 struct mmc_request mrq = {NULL};
1927
1928                 cmd.opcode = opcode;
1929                 cmd.arg = 0;
1930                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1931                 cmd.retries = 0;
1932                 cmd.data = NULL;
1933                 cmd.error = 0;
1934
1935                 if (tuning_loop_counter-- == 0)
1936                         break;
1937
1938                 mrq.cmd = &cmd;
1939                 host->mrq = &mrq;
1940
1941                 /*
1942                  * In response to CMD19, the card sends 64 bytes of tuning
1943                  * block to the Host Controller. So we set the block size
1944                  * to 64 here.
1945                  */
1946                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1947                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1948                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1949                                              SDHCI_BLOCK_SIZE);
1950                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1951                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1952                                              SDHCI_BLOCK_SIZE);
1953                 } else {
1954                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1955                                      SDHCI_BLOCK_SIZE);
1956                 }
1957
1958                 /*
1959                  * The tuning block is sent by the card to the host controller.
1960                  * So we set the TRNS_READ bit in the Transfer Mode register.
1961                  * This also takes care of setting DMA Enable and Multi Block
1962                  * Select in the same register to 0.
1963                  */
1964                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1965
1966                 sdhci_send_command(host, &cmd);
1967
1968                 host->cmd = NULL;
1969                 host->mrq = NULL;
1970
1971                 spin_unlock_irqrestore(&host->lock, flags);
1972                 /* Wait for Buffer Read Ready interrupt */
1973                 wait_event_interruptible_timeout(host->buf_ready_int,
1974                                         (host->tuning_done == 1),
1975                                         msecs_to_jiffies(50));
1976                 spin_lock_irqsave(&host->lock, flags);
1977
1978                 if (!host->tuning_done) {
1979                         pr_info(DRIVER_NAME ": Timeout waiting for "
1980                                 "Buffer Read Ready interrupt during tuning "
1981                                 "procedure, falling back to fixed sampling "
1982                                 "clock\n");
1983                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1984                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1985                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1986                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1987
1988                         err = -EIO;
1989                         goto out;
1990                 }
1991
1992                 host->tuning_done = 0;
1993
1994                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1995
1996                 /* eMMC spec does not require a delay between tuning cycles */
1997                 if (opcode == MMC_SEND_TUNING_BLOCK)
1998                         mdelay(1);
1999         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2000
2001         /*
2002          * The Host Driver has exhausted the maximum number of loops allowed,
2003          * so use fixed sampling frequency.
2004          */
2005         if (tuning_loop_counter < 0) {
2006                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2007                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2008         }
2009         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2010                 pr_info(DRIVER_NAME ": Tuning procedure"
2011                         " failed, falling back to fixed sampling"
2012                         " clock\n");
2013                 err = -EIO;
2014         }
2015
2016 out:
2017         /*
2018          * If this is the very first time we are here, we start the retuning
2019          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2020          * flag won't be set, we check this condition before actually starting
2021          * the timer.
2022          */
2023         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2024             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2025                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2026                 mod_timer(&host->tuning_timer, jiffies +
2027                         host->tuning_count * HZ);
2028                 /* Tuning mode 1 limits the maximum data length to 4MB */
2029                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2030         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2031                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2032                 /* Reload the new initial value for timer */
2033                 mod_timer(&host->tuning_timer, jiffies +
2034                           host->tuning_count * HZ);
2035         }
2036
2037         /*
2038          * In case tuning fails, host controllers which support re-tuning can
2039          * try tuning again at a later time, when the re-tuning timer expires.
2040          * So for these controllers, we return 0. Since there might be other
2041          * controllers who do not have this capability, we return error for
2042          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2043          * a retuning timer to do the retuning for the card.
2044          */
2045         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2046                 err = 0;
2047
2048         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2049         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2050         spin_unlock_irqrestore(&host->lock, flags);
2051         sdhci_runtime_pm_put(host);
2052
2053         return err;
2054 }
2055
2056
2057 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2058 {
2059         /* Host Controller v3.00 defines preset value registers */
2060         if (host->version < SDHCI_SPEC_300)
2061                 return;
2062
2063         /*
2064          * We only enable or disable Preset Value if they are not already
2065          * enabled or disabled respectively. Otherwise, we bail out.
2066          */
2067         if (host->preset_enabled != enable) {
2068                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2069
2070                 if (enable)
2071                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2072                 else
2073                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2074
2075                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2076
2077                 if (enable)
2078                         host->flags |= SDHCI_PV_ENABLED;
2079                 else
2080                         host->flags &= ~SDHCI_PV_ENABLED;
2081
2082                 host->preset_enabled = enable;
2083         }
2084 }
2085
2086 static void sdhci_card_event(struct mmc_host *mmc)
2087 {
2088         struct sdhci_host *host = mmc_priv(mmc);
2089         unsigned long flags;
2090
2091         /* First check if client has provided their own card event */
2092         if (host->ops->card_event)
2093                 host->ops->card_event(host);
2094
2095         spin_lock_irqsave(&host->lock, flags);
2096
2097         /* Check host->mrq first in case we are runtime suspended */
2098         if (host->mrq && !sdhci_do_get_cd(host)) {
2099                 pr_err("%s: Card removed during transfer!\n",
2100                         mmc_hostname(host->mmc));
2101                 pr_err("%s: Resetting controller.\n",
2102                         mmc_hostname(host->mmc));
2103
2104                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2105                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2106
2107                 host->mrq->cmd->error = -ENOMEDIUM;
2108                 tasklet_schedule(&host->finish_tasklet);
2109         }
2110
2111         spin_unlock_irqrestore(&host->lock, flags);
2112 }
2113
2114 static const struct mmc_host_ops sdhci_ops = {
2115         .request        = sdhci_request,
2116         .set_ios        = sdhci_set_ios,
2117         .get_cd         = sdhci_get_cd,
2118         .get_ro         = sdhci_get_ro,
2119         .hw_reset       = sdhci_hw_reset,
2120         .enable_sdio_irq = sdhci_enable_sdio_irq,
2121         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2122         .execute_tuning                 = sdhci_execute_tuning,
2123         .card_event                     = sdhci_card_event,
2124         .card_busy      = sdhci_card_busy,
2125 };
2126
2127 /*****************************************************************************\
2128  *                                                                           *
2129  * Tasklets                                                                  *
2130  *                                                                           *
2131 \*****************************************************************************/
2132
2133 static void sdhci_tasklet_finish(unsigned long param)
2134 {
2135         struct sdhci_host *host;
2136         unsigned long flags;
2137         struct mmc_request *mrq;
2138
2139         host = (struct sdhci_host*)param;
2140
2141         spin_lock_irqsave(&host->lock, flags);
2142
2143         /*
2144          * If this tasklet gets rescheduled while running, it will
2145          * be run again afterwards but without any active request.
2146          */
2147         if (!host->mrq) {
2148                 spin_unlock_irqrestore(&host->lock, flags);
2149                 return;
2150         }
2151
2152         del_timer(&host->timer);
2153
2154         mrq = host->mrq;
2155
2156         /*
2157          * The controller needs a reset of internal state machines
2158          * upon error conditions.
2159          */
2160         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2161             ((mrq->cmd && mrq->cmd->error) ||
2162              (mrq->sbc && mrq->sbc->error) ||
2163              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2164                             (mrq->data->stop && mrq->data->stop->error))) ||
2165              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2166
2167                 /* Some controllers need this kick or reset won't work here */
2168                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2169                         /* This is to force an update */
2170                         host->ops->set_clock(host, host->clock);
2171
2172                 /* Spec says we should do both at the same time, but Ricoh
2173                    controllers do not like that. */
2174                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2175                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2176         }
2177
2178         host->mrq = NULL;
2179         host->cmd = NULL;
2180         host->data = NULL;
2181
2182 #ifndef SDHCI_USE_LEDS_CLASS
2183         sdhci_deactivate_led(host);
2184 #endif
2185
2186         mmiowb();
2187         spin_unlock_irqrestore(&host->lock, flags);
2188
2189         mmc_request_done(host->mmc, mrq);
2190         sdhci_runtime_pm_put(host);
2191 }
2192
2193 static void sdhci_timeout_timer(unsigned long data)
2194 {
2195         struct sdhci_host *host;
2196         unsigned long flags;
2197
2198         host = (struct sdhci_host*)data;
2199
2200         spin_lock_irqsave(&host->lock, flags);
2201
2202         if (host->mrq) {
2203                 pr_err("%s: Timeout waiting for hardware "
2204                         "interrupt.\n", mmc_hostname(host->mmc));
2205                 sdhci_dumpregs(host);
2206
2207                 if (host->data) {
2208                         host->data->error = -ETIMEDOUT;
2209                         sdhci_finish_data(host);
2210                 } else {
2211                         if (host->cmd)
2212                                 host->cmd->error = -ETIMEDOUT;
2213                         else
2214                                 host->mrq->cmd->error = -ETIMEDOUT;
2215
2216                         tasklet_schedule(&host->finish_tasklet);
2217                 }
2218         }
2219
2220         mmiowb();
2221         spin_unlock_irqrestore(&host->lock, flags);
2222 }
2223
2224 static void sdhci_tuning_timer(unsigned long data)
2225 {
2226         struct sdhci_host *host;
2227         unsigned long flags;
2228
2229         host = (struct sdhci_host *)data;
2230
2231         spin_lock_irqsave(&host->lock, flags);
2232
2233         host->flags |= SDHCI_NEEDS_RETUNING;
2234
2235         spin_unlock_irqrestore(&host->lock, flags);
2236 }
2237
2238 /*****************************************************************************\
2239  *                                                                           *
2240  * Interrupt handling                                                        *
2241  *                                                                           *
2242 \*****************************************************************************/
2243
2244 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2245 {
2246         BUG_ON(intmask == 0);
2247
2248         if (!host->cmd) {
2249                 pr_err("%s: Got command interrupt 0x%08x even "
2250                         "though no command operation was in progress.\n",
2251                         mmc_hostname(host->mmc), (unsigned)intmask);
2252                 sdhci_dumpregs(host);
2253                 return;
2254         }
2255
2256         if (intmask & SDHCI_INT_TIMEOUT)
2257                 host->cmd->error = -ETIMEDOUT;
2258         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2259                         SDHCI_INT_INDEX))
2260                 host->cmd->error = -EILSEQ;
2261
2262         if (host->cmd->error) {
2263                 tasklet_schedule(&host->finish_tasklet);
2264                 return;
2265         }
2266
2267         /*
2268          * The host can send and interrupt when the busy state has
2269          * ended, allowing us to wait without wasting CPU cycles.
2270          * Unfortunately this is overloaded on the "data complete"
2271          * interrupt, so we need to take some care when handling
2272          * it.
2273          *
2274          * Note: The 1.0 specification is a bit ambiguous about this
2275          *       feature so there might be some problems with older
2276          *       controllers.
2277          */
2278         if (host->cmd->flags & MMC_RSP_BUSY) {
2279                 if (host->cmd->data)
2280                         DBG("Cannot wait for busy signal when also "
2281                                 "doing a data transfer");
2282                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2283                                 && !host->busy_handle) {
2284                         /* Mark that command complete before busy is ended */
2285                         host->busy_handle = 1;
2286                         return;
2287                 }
2288
2289                 /* The controller does not support the end-of-busy IRQ,
2290                  * fall through and take the SDHCI_INT_RESPONSE */
2291         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2292                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2293                 *mask &= ~SDHCI_INT_DATA_END;
2294         }
2295
2296         if (intmask & SDHCI_INT_RESPONSE)
2297                 sdhci_finish_command(host);
2298 }
2299
2300 #ifdef CONFIG_MMC_DEBUG
2301 static void sdhci_adma_show_error(struct sdhci_host *host)
2302 {
2303         const char *name = mmc_hostname(host->mmc);
2304         u8 *desc = host->adma_table;
2305         __le32 *dma;
2306         __le16 *len;
2307         u8 attr;
2308
2309         sdhci_dumpregs(host);
2310
2311         while (true) {
2312                 dma = (__le32 *)(desc + 4);
2313                 len = (__le16 *)(desc + 2);
2314                 attr = *desc;
2315
2316                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2317                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2318
2319                 desc += 8;
2320
2321                 if (attr & 2)
2322                         break;
2323         }
2324 }
2325 #else
2326 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2327 #endif
2328
2329 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2330 {
2331         u32 command;
2332         BUG_ON(intmask == 0);
2333
2334         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2335         if (intmask & SDHCI_INT_DATA_AVAIL) {
2336                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2337                 if (command == MMC_SEND_TUNING_BLOCK ||
2338                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2339                         host->tuning_done = 1;
2340                         wake_up(&host->buf_ready_int);
2341                         return;
2342                 }
2343         }
2344
2345         if (!host->data) {
2346                 /*
2347                  * The "data complete" interrupt is also used to
2348                  * indicate that a busy state has ended. See comment
2349                  * above in sdhci_cmd_irq().
2350                  */
2351                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2352                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2353                                 host->cmd->error = -ETIMEDOUT;
2354                                 tasklet_schedule(&host->finish_tasklet);
2355                                 return;
2356                         }
2357                         if (intmask & SDHCI_INT_DATA_END) {
2358                                 /*
2359                                  * Some cards handle busy-end interrupt
2360                                  * before the command completed, so make
2361                                  * sure we do things in the proper order.
2362                                  */
2363                                 if (host->busy_handle)
2364                                         sdhci_finish_command(host);
2365                                 else
2366                                         host->busy_handle = 1;
2367                                 return;
2368                         }
2369                 }
2370
2371                 pr_err("%s: Got data interrupt 0x%08x even "
2372                         "though no data operation was in progress.\n",
2373                         mmc_hostname(host->mmc), (unsigned)intmask);
2374                 sdhci_dumpregs(host);
2375
2376                 return;
2377         }
2378
2379         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2380                 host->data->error = -ETIMEDOUT;
2381         else if (intmask & SDHCI_INT_DATA_END_BIT)
2382                 host->data->error = -EILSEQ;
2383         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2384                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2385                         != MMC_BUS_TEST_R)
2386                 host->data->error = -EILSEQ;
2387         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2388                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2389                 sdhci_adma_show_error(host);
2390                 host->data->error = -EIO;
2391                 if (host->ops->adma_workaround)
2392                         host->ops->adma_workaround(host, intmask);
2393         }
2394
2395         if (host->data->error)
2396                 sdhci_finish_data(host);
2397         else {
2398                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2399                         sdhci_transfer_pio(host);
2400
2401                 /*
2402                  * We currently don't do anything fancy with DMA
2403                  * boundaries, but as we can't disable the feature
2404                  * we need to at least restart the transfer.
2405                  *
2406                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2407                  * should return a valid address to continue from, but as
2408                  * some controllers are faulty, don't trust them.
2409                  */
2410                 if (intmask & SDHCI_INT_DMA_END) {
2411                         u32 dmastart, dmanow;
2412                         dmastart = sg_dma_address(host->data->sg);
2413                         dmanow = dmastart + host->data->bytes_xfered;
2414                         /*
2415                          * Force update to the next DMA block boundary.
2416                          */
2417                         dmanow = (dmanow &
2418                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2419                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2420                         host->data->bytes_xfered = dmanow - dmastart;
2421                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2422                                 " next 0x%08x\n",
2423                                 mmc_hostname(host->mmc), dmastart,
2424                                 host->data->bytes_xfered, dmanow);
2425                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2426                 }
2427
2428                 if (intmask & SDHCI_INT_DATA_END) {
2429                         if (host->cmd) {
2430                                 /*
2431                                  * Data managed to finish before the
2432                                  * command completed. Make sure we do
2433                                  * things in the proper order.
2434                                  */
2435                                 host->data_early = 1;
2436                         } else {
2437                                 sdhci_finish_data(host);
2438                         }
2439                 }
2440         }
2441 }
2442
2443 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2444 {
2445         irqreturn_t result = IRQ_NONE;
2446         struct sdhci_host *host = dev_id;
2447         u32 intmask, mask, unexpected = 0;
2448         int max_loops = 16;
2449
2450         spin_lock(&host->lock);
2451
2452         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2453                 spin_unlock(&host->lock);
2454                 return IRQ_NONE;
2455         }
2456
2457         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2458         if (!intmask || intmask == 0xffffffff) {
2459                 result = IRQ_NONE;
2460                 goto out;
2461         }
2462
2463         do {
2464                 /* Clear selected interrupts. */
2465                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2466                                   SDHCI_INT_BUS_POWER);
2467                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2468
2469                 DBG("*** %s got interrupt: 0x%08x\n",
2470                         mmc_hostname(host->mmc), intmask);
2471
2472                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2473                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2474                                       SDHCI_CARD_PRESENT;
2475
2476                         /*
2477                          * There is a observation on i.mx esdhc.  INSERT
2478                          * bit will be immediately set again when it gets
2479                          * cleared, if a card is inserted.  We have to mask
2480                          * the irq to prevent interrupt storm which will
2481                          * freeze the system.  And the REMOVE gets the
2482                          * same situation.
2483                          *
2484                          * More testing are needed here to ensure it works
2485                          * for other platforms though.
2486                          */
2487                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2488                                        SDHCI_INT_CARD_REMOVE);
2489                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2490                                                SDHCI_INT_CARD_INSERT;
2491                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2492                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2493
2494                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2495                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2496
2497                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2498                                                        SDHCI_INT_CARD_REMOVE);
2499                         result = IRQ_WAKE_THREAD;
2500                 }
2501
2502                 if (intmask & SDHCI_INT_CMD_MASK)
2503                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2504                                       &intmask);
2505
2506                 if (intmask & SDHCI_INT_DATA_MASK)
2507                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2508
2509                 if (intmask & SDHCI_INT_BUS_POWER)
2510                         pr_err("%s: Card is consuming too much power!\n",
2511                                 mmc_hostname(host->mmc));
2512
2513                 if (intmask & SDHCI_INT_CARD_INT) {
2514                         sdhci_enable_sdio_irq_nolock(host, false);
2515                         host->thread_isr |= SDHCI_INT_CARD_INT;
2516                         result = IRQ_WAKE_THREAD;
2517                 }
2518
2519                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2520                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2521                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2522                              SDHCI_INT_CARD_INT);
2523
2524                 if (intmask) {
2525                         unexpected |= intmask;
2526                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2527                 }
2528
2529                 if (result == IRQ_NONE)
2530                         result = IRQ_HANDLED;
2531
2532                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2533         } while (intmask && --max_loops);
2534 out:
2535         spin_unlock(&host->lock);
2536
2537         if (unexpected) {
2538                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2539                            mmc_hostname(host->mmc), unexpected);
2540                 sdhci_dumpregs(host);
2541         }
2542
2543         return result;
2544 }
2545
2546 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2547 {
2548         struct sdhci_host *host = dev_id;
2549         unsigned long flags;
2550         u32 isr;
2551
2552         spin_lock_irqsave(&host->lock, flags);
2553         isr = host->thread_isr;
2554         host->thread_isr = 0;
2555         spin_unlock_irqrestore(&host->lock, flags);
2556
2557         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2558                 sdhci_card_event(host->mmc);
2559                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2560         }
2561
2562         if (isr & SDHCI_INT_CARD_INT) {
2563                 sdio_run_irqs(host->mmc);
2564
2565                 spin_lock_irqsave(&host->lock, flags);
2566                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2567                         sdhci_enable_sdio_irq_nolock(host, true);
2568                 spin_unlock_irqrestore(&host->lock, flags);
2569         }
2570
2571         return isr ? IRQ_HANDLED : IRQ_NONE;
2572 }
2573
2574 /*****************************************************************************\
2575  *                                                                           *
2576  * Suspend/resume                                                            *
2577  *                                                                           *
2578 \*****************************************************************************/
2579
2580 #ifdef CONFIG_PM
2581 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2582 {
2583         u8 val;
2584         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2585                         | SDHCI_WAKE_ON_INT;
2586
2587         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2588         val |= mask ;
2589         /* Avoid fake wake up */
2590         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2591                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2592         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2593 }
2594 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2595
2596 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2597 {
2598         u8 val;
2599         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2600                         | SDHCI_WAKE_ON_INT;
2601
2602         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2603         val &= ~mask;
2604         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2605 }
2606
2607 int sdhci_suspend_host(struct sdhci_host *host)
2608 {
2609         sdhci_disable_card_detection(host);
2610
2611         /* Disable tuning since we are suspending */
2612         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2613                 del_timer_sync(&host->tuning_timer);
2614                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2615         }
2616
2617         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2618                 host->ier = 0;
2619                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2620                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2621                 free_irq(host->irq, host);
2622         } else {
2623                 sdhci_enable_irq_wakeups(host);
2624                 enable_irq_wake(host->irq);
2625         }
2626         return 0;
2627 }
2628
2629 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2630
2631 int sdhci_resume_host(struct sdhci_host *host)
2632 {
2633         int ret = 0;
2634
2635         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2636                 if (host->ops->enable_dma)
2637                         host->ops->enable_dma(host);
2638         }
2639
2640         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2641                 ret = request_threaded_irq(host->irq, sdhci_irq,
2642                                            sdhci_thread_irq, IRQF_SHARED,
2643                                            mmc_hostname(host->mmc), host);
2644                 if (ret)
2645                         return ret;
2646         } else {
2647                 sdhci_disable_irq_wakeups(host);
2648                 disable_irq_wake(host->irq);
2649         }
2650
2651         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2652             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2653                 /* Card keeps power but host controller does not */
2654                 sdhci_init(host, 0);
2655                 host->pwr = 0;
2656                 host->clock = 0;
2657                 sdhci_do_set_ios(host, &host->mmc->ios);
2658         } else {
2659                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2660                 mmiowb();
2661         }
2662
2663         sdhci_enable_card_detection(host);
2664
2665         /* Set the re-tuning expiration flag */
2666         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2667                 host->flags |= SDHCI_NEEDS_RETUNING;
2668
2669         return ret;
2670 }
2671
2672 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2673 #endif /* CONFIG_PM */
2674
2675 #ifdef CONFIG_PM_RUNTIME
2676
2677 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2678 {
2679         return pm_runtime_get_sync(host->mmc->parent);
2680 }
2681
2682 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2683 {
2684         pm_runtime_mark_last_busy(host->mmc->parent);
2685         return pm_runtime_put_autosuspend(host->mmc->parent);
2686 }
2687
2688 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2689 {
2690         if (host->runtime_suspended || host->bus_on)
2691                 return;
2692         host->bus_on = true;
2693         pm_runtime_get_noresume(host->mmc->parent);
2694 }
2695
2696 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2697 {
2698         if (host->runtime_suspended || !host->bus_on)
2699                 return;
2700         host->bus_on = false;
2701         pm_runtime_put_noidle(host->mmc->parent);
2702 }
2703
2704 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2705 {
2706         unsigned long flags;
2707
2708         /* Disable tuning since we are suspending */
2709         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2710                 del_timer_sync(&host->tuning_timer);
2711                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2712         }
2713
2714         spin_lock_irqsave(&host->lock, flags);
2715         host->ier &= SDHCI_INT_CARD_INT;
2716         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2717         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2718         spin_unlock_irqrestore(&host->lock, flags);
2719
2720         synchronize_hardirq(host->irq);
2721
2722         spin_lock_irqsave(&host->lock, flags);
2723         host->runtime_suspended = true;
2724         spin_unlock_irqrestore(&host->lock, flags);
2725
2726         return 0;
2727 }
2728 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2729
2730 int sdhci_runtime_resume_host(struct sdhci_host *host)
2731 {
2732         unsigned long flags;
2733         int host_flags = host->flags;
2734
2735         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2736                 if (host->ops->enable_dma)
2737                         host->ops->enable_dma(host);
2738         }
2739
2740         sdhci_init(host, 0);
2741
2742         /* Force clock and power re-program */
2743         host->pwr = 0;
2744         host->clock = 0;
2745         sdhci_do_set_ios(host, &host->mmc->ios);
2746
2747         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2748         if ((host_flags & SDHCI_PV_ENABLED) &&
2749                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2750                 spin_lock_irqsave(&host->lock, flags);
2751                 sdhci_enable_preset_value(host, true);
2752                 spin_unlock_irqrestore(&host->lock, flags);
2753         }
2754
2755         /* Set the re-tuning expiration flag */
2756         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2757                 host->flags |= SDHCI_NEEDS_RETUNING;
2758
2759         spin_lock_irqsave(&host->lock, flags);
2760
2761         host->runtime_suspended = false;
2762
2763         /* Enable SDIO IRQ */
2764         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2765                 sdhci_enable_sdio_irq_nolock(host, true);
2766
2767         /* Enable Card Detection */
2768         sdhci_enable_card_detection(host);
2769
2770         spin_unlock_irqrestore(&host->lock, flags);
2771
2772         return 0;
2773 }
2774 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2775
2776 #endif
2777
2778 /*****************************************************************************\
2779  *                                                                           *
2780  * Device allocation/registration                                            *
2781  *                                                                           *
2782 \*****************************************************************************/
2783
2784 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2785         size_t priv_size)
2786 {
2787         struct mmc_host *mmc;
2788         struct sdhci_host *host;
2789
2790         WARN_ON(dev == NULL);
2791
2792         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2793         if (!mmc)
2794                 return ERR_PTR(-ENOMEM);
2795
2796         host = mmc_priv(mmc);
2797         host->mmc = mmc;
2798
2799         return host;
2800 }
2801
2802 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2803
2804 int sdhci_add_host(struct sdhci_host *host)
2805 {
2806         struct mmc_host *mmc;
2807         u32 caps[2] = {0, 0};
2808         u32 max_current_caps;
2809         unsigned int ocr_avail;
2810         unsigned int override_timeout_clk;
2811         int ret;
2812
2813         WARN_ON(host == NULL);
2814         if (host == NULL)
2815                 return -EINVAL;
2816
2817         mmc = host->mmc;
2818
2819         if (debug_quirks)
2820                 host->quirks = debug_quirks;
2821         if (debug_quirks2)
2822                 host->quirks2 = debug_quirks2;
2823
2824         override_timeout_clk = host->timeout_clk;
2825
2826         sdhci_do_reset(host, SDHCI_RESET_ALL);
2827
2828         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2829         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2830                                 >> SDHCI_SPEC_VER_SHIFT;
2831         if (host->version > SDHCI_SPEC_300) {
2832                 pr_err("%s: Unknown controller version (%d). "
2833                         "You may experience problems.\n", mmc_hostname(mmc),
2834                         host->version);
2835         }
2836
2837         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2838                 sdhci_readl(host, SDHCI_CAPABILITIES);
2839
2840         if (host->version >= SDHCI_SPEC_300)
2841                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2842                         host->caps1 :
2843                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2844
2845         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2846                 host->flags |= SDHCI_USE_SDMA;
2847         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2848                 DBG("Controller doesn't have SDMA capability\n");
2849         else
2850                 host->flags |= SDHCI_USE_SDMA;
2851
2852         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2853                 (host->flags & SDHCI_USE_SDMA)) {
2854                 DBG("Disabling DMA as it is marked broken\n");
2855                 host->flags &= ~SDHCI_USE_SDMA;
2856         }
2857
2858         if ((host->version >= SDHCI_SPEC_200) &&
2859                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2860                 host->flags |= SDHCI_USE_ADMA;
2861
2862         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2863                 (host->flags & SDHCI_USE_ADMA)) {
2864                 DBG("Disabling ADMA as it is marked broken\n");
2865                 host->flags &= ~SDHCI_USE_ADMA;
2866         }
2867
2868         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2869                 if (host->ops->enable_dma) {
2870                         if (host->ops->enable_dma(host)) {
2871                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2872                                         mmc_hostname(mmc));
2873                                 host->flags &=
2874                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2875                         }
2876                 }
2877         }
2878
2879         if (host->flags & SDHCI_USE_ADMA) {
2880                 /*
2881                  * We need to allocate descriptors for all sg entries
2882                  * (128) and potentially one alignment transfer for
2883                  * each of those entries.
2884                  */
2885                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2886                                                       ADMA_SIZE,
2887                                                       &host->adma_addr,
2888                                                       GFP_KERNEL);
2889                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2890                 if (!host->adma_table || !host->align_buffer) {
2891                         dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2892                                           host->adma_table, host->adma_addr);
2893                         kfree(host->align_buffer);
2894                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2895                                 mmc_hostname(mmc));
2896                         host->flags &= ~SDHCI_USE_ADMA;
2897                         host->adma_table = NULL;
2898                         host->align_buffer = NULL;
2899                 } else if (host->adma_addr & 3) {
2900                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2901                                 mmc_hostname(mmc));
2902                         host->flags &= ~SDHCI_USE_ADMA;
2903                         dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
2904                                           host->adma_table, host->adma_addr);
2905                         kfree(host->align_buffer);
2906                         host->adma_table = NULL;
2907                         host->align_buffer = NULL;
2908                 }
2909         }
2910
2911         /*
2912          * If we use DMA, then it's up to the caller to set the DMA
2913          * mask, but PIO does not need the hw shim so we set a new
2914          * mask here in that case.
2915          */
2916         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2917                 host->dma_mask = DMA_BIT_MASK(64);
2918                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2919         }
2920
2921         if (host->version >= SDHCI_SPEC_300)
2922                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2923                         >> SDHCI_CLOCK_BASE_SHIFT;
2924         else
2925                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2926                         >> SDHCI_CLOCK_BASE_SHIFT;
2927
2928         host->max_clk *= 1000000;
2929         if (host->max_clk == 0 || host->quirks &
2930                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2931                 if (!host->ops->get_max_clock) {
2932                         pr_err("%s: Hardware doesn't specify base clock "
2933                                "frequency.\n", mmc_hostname(mmc));
2934                         return -ENODEV;
2935                 }
2936                 host->max_clk = host->ops->get_max_clock(host);
2937         }
2938
2939         /*
2940          * In case of Host Controller v3.00, find out whether clock
2941          * multiplier is supported.
2942          */
2943         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2944                         SDHCI_CLOCK_MUL_SHIFT;
2945
2946         /*
2947          * In case the value in Clock Multiplier is 0, then programmable
2948          * clock mode is not supported, otherwise the actual clock
2949          * multiplier is one more than the value of Clock Multiplier
2950          * in the Capabilities Register.
2951          */
2952         if (host->clk_mul)
2953                 host->clk_mul += 1;
2954
2955         /*
2956          * Set host parameters.
2957          */
2958         mmc->ops = &sdhci_ops;
2959         mmc->f_max = host->max_clk;
2960         if (host->ops->get_min_clock)
2961                 mmc->f_min = host->ops->get_min_clock(host);
2962         else if (host->version >= SDHCI_SPEC_300) {
2963                 if (host->clk_mul) {
2964                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2965                         mmc->f_max = host->max_clk * host->clk_mul;
2966                 } else
2967                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2968         } else
2969                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2970
2971         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2972                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
2973                                         SDHCI_TIMEOUT_CLK_SHIFT;
2974                 if (host->timeout_clk == 0) {
2975                         if (host->ops->get_timeout_clock) {
2976                                 host->timeout_clk =
2977                                         host->ops->get_timeout_clock(host);
2978                         } else {
2979                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
2980                                         mmc_hostname(mmc));
2981                                 return -ENODEV;
2982                         }
2983                 }
2984
2985                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2986                         host->timeout_clk *= 1000;
2987
2988                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
2989                         host->ops->get_max_timeout_count(host) : 1 << 27;
2990                 mmc->max_busy_timeout /= host->timeout_clk;
2991         }
2992
2993         if (override_timeout_clk)
2994                 host->timeout_clk = override_timeout_clk;
2995
2996         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2997         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2998
2999         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3000                 host->flags |= SDHCI_AUTO_CMD12;
3001
3002         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3003         if ((host->version >= SDHCI_SPEC_300) &&
3004             ((host->flags & SDHCI_USE_ADMA) ||
3005              !(host->flags & SDHCI_USE_SDMA))) {
3006                 host->flags |= SDHCI_AUTO_CMD23;
3007                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3008         } else {
3009                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3010         }
3011
3012         /*
3013          * A controller may support 8-bit width, but the board itself
3014          * might not have the pins brought out.  Boards that support
3015          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3016          * their platform code before calling sdhci_add_host(), and we
3017          * won't assume 8-bit width for hosts without that CAP.
3018          */
3019         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3020                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3021
3022         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3023                 mmc->caps &= ~MMC_CAP_CMD23;
3024
3025         if (caps[0] & SDHCI_CAN_DO_HISPD)
3026                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3027
3028         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3029             !(mmc->caps & MMC_CAP_NONREMOVABLE))
3030                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3031
3032         /* If there are external regulators, get them */
3033         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3034                 return -EPROBE_DEFER;
3035
3036         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3037         if (!IS_ERR(mmc->supply.vqmmc)) {
3038                 ret = regulator_enable(mmc->supply.vqmmc);
3039                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3040                                                     1950000))
3041                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3042                                         SDHCI_SUPPORT_SDR50 |
3043                                         SDHCI_SUPPORT_DDR50);
3044                 if (ret) {
3045                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3046                                 mmc_hostname(mmc), ret);
3047                         mmc->supply.vqmmc = NULL;
3048                 }
3049         }
3050
3051         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3052                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3053                        SDHCI_SUPPORT_DDR50);
3054
3055         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3056         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3057                        SDHCI_SUPPORT_DDR50))
3058                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3059
3060         /* SDR104 supports also implies SDR50 support */
3061         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3062                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3063                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3064                  * field can be promoted to support HS200.
3065                  */
3066                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
3067                         mmc->caps2 |= MMC_CAP2_HS200;
3068                         if (IS_ERR(mmc->supply.vqmmc) ||
3069                                         !regulator_is_supported_voltage
3070                                         (mmc->supply.vqmmc, 1100000, 1300000))
3071                                 mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
3072                 }
3073         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3074                 mmc->caps |= MMC_CAP_UHS_SDR50;
3075
3076         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3077                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3078                 mmc->caps |= MMC_CAP_UHS_DDR50;
3079
3080         /* Does the host need tuning for SDR50? */
3081         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3082                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3083
3084         /* Does the host need tuning for SDR104 / HS200? */
3085         if (mmc->caps2 & MMC_CAP2_HS200)
3086                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3087
3088         /* Driver Type(s) (A, C, D) supported by the host */
3089         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3090                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3091         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3092                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3093         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3094                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3095
3096         /* Initial value for re-tuning timer count */
3097         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3098                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3099
3100         /*
3101          * In case Re-tuning Timer is not disabled, the actual value of
3102          * re-tuning timer will be 2 ^ (n - 1).
3103          */
3104         if (host->tuning_count)
3105                 host->tuning_count = 1 << (host->tuning_count - 1);
3106
3107         /* Re-tuning mode supported by the Host Controller */
3108         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3109                              SDHCI_RETUNING_MODE_SHIFT;
3110
3111         ocr_avail = 0;
3112
3113         /*
3114          * According to SD Host Controller spec v3.00, if the Host System
3115          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3116          * the value is meaningful only if Voltage Support in the Capabilities
3117          * register is set. The actual current value is 4 times the register
3118          * value.
3119          */
3120         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3121         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3122                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3123                 if (curr > 0) {
3124
3125                         /* convert to SDHCI_MAX_CURRENT format */
3126                         curr = curr/1000;  /* convert to mA */
3127                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3128
3129                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3130                         max_current_caps =
3131                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3132                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3133                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3134                 }
3135         }
3136
3137         if (caps[0] & SDHCI_CAN_VDD_330) {
3138                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3139
3140                 mmc->max_current_330 = ((max_current_caps &
3141                                    SDHCI_MAX_CURRENT_330_MASK) >>
3142                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3143                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3144         }
3145         if (caps[0] & SDHCI_CAN_VDD_300) {
3146                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3147
3148                 mmc->max_current_300 = ((max_current_caps &
3149                                    SDHCI_MAX_CURRENT_300_MASK) >>
3150                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3151                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3152         }
3153         if (caps[0] & SDHCI_CAN_VDD_180) {
3154                 ocr_avail |= MMC_VDD_165_195;
3155
3156                 mmc->max_current_180 = ((max_current_caps &
3157                                    SDHCI_MAX_CURRENT_180_MASK) >>
3158                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3159                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3160         }
3161
3162         /* If OCR set by external regulators, use it instead */
3163         if (mmc->ocr_avail)
3164                 ocr_avail = mmc->ocr_avail;
3165
3166         if (host->ocr_mask)
3167                 ocr_avail &= host->ocr_mask;
3168
3169         mmc->ocr_avail = ocr_avail;
3170         mmc->ocr_avail_sdio = ocr_avail;
3171         if (host->ocr_avail_sdio)
3172                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3173         mmc->ocr_avail_sd = ocr_avail;
3174         if (host->ocr_avail_sd)
3175                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3176         else /* normal SD controllers don't support 1.8V */
3177                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3178         mmc->ocr_avail_mmc = ocr_avail;
3179         if (host->ocr_avail_mmc)
3180                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3181
3182         if (mmc->ocr_avail == 0) {
3183                 pr_err("%s: Hardware doesn't report any "
3184                         "support voltages.\n", mmc_hostname(mmc));
3185                 return -ENODEV;
3186         }
3187
3188         spin_lock_init(&host->lock);
3189
3190         /*
3191          * Maximum number of segments. Depends on if the hardware
3192          * can do scatter/gather or not.
3193          */
3194         if (host->flags & SDHCI_USE_ADMA)
3195                 mmc->max_segs = 128;
3196         else if (host->flags & SDHCI_USE_SDMA)
3197                 mmc->max_segs = 1;
3198         else /* PIO */
3199                 mmc->max_segs = 128;
3200
3201         /*
3202          * Maximum number of sectors in one transfer. Limited by DMA boundary
3203          * size (512KiB).
3204          */
3205         mmc->max_req_size = 524288;
3206
3207         /*
3208          * Maximum segment size. Could be one segment with the maximum number
3209          * of bytes. When doing hardware scatter/gather, each entry cannot
3210          * be larger than 64 KiB though.
3211          */
3212         if (host->flags & SDHCI_USE_ADMA) {
3213                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3214                         mmc->max_seg_size = 65535;
3215                 else
3216                         mmc->max_seg_size = 65536;
3217         } else {
3218                 mmc->max_seg_size = mmc->max_req_size;
3219         }
3220
3221         /*
3222          * Maximum block size. This varies from controller to controller and
3223          * is specified in the capabilities register.
3224          */
3225         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3226                 mmc->max_blk_size = 2;
3227         } else {
3228                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3229                                 SDHCI_MAX_BLOCK_SHIFT;
3230                 if (mmc->max_blk_size >= 3) {
3231                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3232                                 mmc_hostname(mmc));
3233                         mmc->max_blk_size = 0;
3234                 }
3235         }
3236
3237         mmc->max_blk_size = 512 << mmc->max_blk_size;
3238
3239         /*
3240          * Maximum block count.
3241          */
3242         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3243
3244         /*
3245          * Init tasklets.
3246          */
3247         tasklet_init(&host->finish_tasklet,
3248                 sdhci_tasklet_finish, (unsigned long)host);
3249
3250         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3251
3252         if (host->version >= SDHCI_SPEC_300) {
3253                 init_waitqueue_head(&host->buf_ready_int);
3254
3255                 /* Initialize re-tuning timer */
3256                 init_timer(&host->tuning_timer);
3257                 host->tuning_timer.data = (unsigned long)host;
3258                 host->tuning_timer.function = sdhci_tuning_timer;
3259         }
3260
3261         sdhci_init(host, 0);
3262
3263         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3264                                    IRQF_SHARED, mmc_hostname(mmc), host);
3265         if (ret) {
3266                 pr_err("%s: Failed to request IRQ %d: %d\n",
3267                        mmc_hostname(mmc), host->irq, ret);
3268                 goto untasklet;
3269         }
3270
3271 #ifdef CONFIG_MMC_DEBUG
3272         sdhci_dumpregs(host);
3273 #endif
3274
3275 #ifdef SDHCI_USE_LEDS_CLASS
3276         snprintf(host->led_name, sizeof(host->led_name),
3277                 "%s::", mmc_hostname(mmc));
3278         host->led.name = host->led_name;
3279         host->led.brightness = LED_OFF;
3280         host->led.default_trigger = mmc_hostname(mmc);
3281         host->led.brightness_set = sdhci_led_control;
3282
3283         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3284         if (ret) {
3285                 pr_err("%s: Failed to register LED device: %d\n",
3286                        mmc_hostname(mmc), ret);
3287                 goto reset;
3288         }
3289 #endif
3290
3291         mmiowb();
3292
3293         mmc_add_host(mmc);
3294
3295         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3296                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3297                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3298                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3299
3300         sdhci_enable_card_detection(host);
3301
3302         return 0;
3303
3304 #ifdef SDHCI_USE_LEDS_CLASS
3305 reset:
3306         sdhci_do_reset(host, SDHCI_RESET_ALL);
3307         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3308         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3309         free_irq(host->irq, host);
3310 #endif
3311 untasklet:
3312         tasklet_kill(&host->finish_tasklet);
3313
3314         return ret;
3315 }
3316
3317 EXPORT_SYMBOL_GPL(sdhci_add_host);
3318
3319 void sdhci_remove_host(struct sdhci_host *host, int dead)
3320 {
3321         struct mmc_host *mmc = host->mmc;
3322         unsigned long flags;
3323
3324         if (dead) {
3325                 spin_lock_irqsave(&host->lock, flags);
3326
3327                 host->flags |= SDHCI_DEVICE_DEAD;
3328
3329                 if (host->mrq) {
3330                         pr_err("%s: Controller removed during "
3331                                 " transfer!\n", mmc_hostname(mmc));
3332
3333                         host->mrq->cmd->error = -ENOMEDIUM;
3334                         tasklet_schedule(&host->finish_tasklet);
3335                 }
3336
3337                 spin_unlock_irqrestore(&host->lock, flags);
3338         }
3339
3340         sdhci_disable_card_detection(host);
3341
3342         mmc_remove_host(mmc);
3343
3344 #ifdef SDHCI_USE_LEDS_CLASS
3345         led_classdev_unregister(&host->led);
3346 #endif
3347
3348         if (!dead)
3349                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3350
3351         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3352         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3353         free_irq(host->irq, host);
3354
3355         del_timer_sync(&host->timer);
3356
3357         tasklet_kill(&host->finish_tasklet);
3358
3359         if (!IS_ERR(mmc->supply.vqmmc))
3360                 regulator_disable(mmc->supply.vqmmc);
3361
3362         if (host->adma_table)
3363                 dma_free_coherent(mmc_dev(mmc), ADMA_SIZE,
3364                                   host->adma_table, host->adma_addr);
3365         kfree(host->align_buffer);
3366
3367         host->adma_table = NULL;
3368         host->align_buffer = NULL;
3369 }
3370
3371 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3372
3373 void sdhci_free_host(struct sdhci_host *host)
3374 {
3375         mmc_free_host(host->mmc);
3376 }
3377
3378 EXPORT_SYMBOL_GPL(sdhci_free_host);
3379
3380 /*****************************************************************************\
3381  *                                                                           *
3382  * Driver init/exit                                                          *
3383  *                                                                           *
3384 \*****************************************************************************/
3385
3386 static int __init sdhci_drv_init(void)
3387 {
3388         pr_info(DRIVER_NAME
3389                 ": Secure Digital Host Controller Interface driver\n");
3390         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3391
3392         return 0;
3393 }
3394
3395 static void __exit sdhci_drv_exit(void)
3396 {
3397 }
3398
3399 module_init(sdhci_drv_init);
3400 module_exit(sdhci_drv_exit);
3401
3402 module_param(debug_quirks, uint, 0444);
3403 module_param(debug_quirks2, uint, 0444);
3404
3405 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3406 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3407 MODULE_LICENSE("GPL");
3408
3409 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3410 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");