drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/completion.h>
  35 #include <linux/of_device.h>
  36 #include <linux/of_mtd.h>
  37
  38 #include <asm/mach/flash.h>
  39 #include <linux/platform_data/mtd-mxc_nand.h>
  40
  41 #define DRIVER_NAME "mxc_nand"
  42
  43 /* Addresses for NFC registers */
  44 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  45 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  46 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  47 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  48 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  49 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  50 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  51 #define NFC_V1_V2_RSLTSPARE_AREA        (host->regs + 0x10)
  52 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  53 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  54 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  55 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  56 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  57 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  58 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  59 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  60 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  61 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  62 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  63 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  64 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  65 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  66
  67 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  68 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  69 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  70 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  71 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  72 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  73 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  74 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  75 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  76 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  77
  78 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  79
  80 /*
  81  * Operation modes for the NFC. Valid for v1, v2 and v3
  82  * type controllers.
  83  */
  84 #define NFC_CMD                         (1 << 0)
  85 #define NFC_ADDR                        (1 << 1)
  86 #define NFC_INPUT                       (1 << 2)
  87 #define NFC_OUTPUT                      (1 << 3)
  88 #define NFC_ID                          (1 << 4)
  89 #define NFC_STATUS                      (1 << 5)
  90
  91 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  92 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  93
  94 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  95 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
  96 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
  97
  98 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
  99
 100 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
 101
 102 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
 103 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
 104 #define NFC_V3_WRPROT_LOCK              (1 << 1)
 105 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
 106 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
 107
 108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
 109
 110 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
 111 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
 112 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
 113 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
 114 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
 115 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 116 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 118 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 119 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
 120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 121 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 122 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 123 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 124
 125 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 126 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 127 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 128 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 130 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 131 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 132
 133 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 134 #define NFC_V3_IPC_CREQ                 (1 << 0)
 135 #define NFC_V3_IPC_INT                  (1 << 31)
 136
 137 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 138
 139 struct mxc_nand_host;
 140
 141 struct mxc_nand_devtype_data {
 142         void (*preset)(struct mtd_info *);
 143         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 144         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 145         void (*send_page)(struct mtd_info *, unsigned int);
 146         void (*send_read_id)(struct mxc_nand_host *);
 147         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 148         int (*check_int)(struct mxc_nand_host *);
 149         void (*irq_control)(struct mxc_nand_host *, int);
 150         u32 (*get_ecc_status)(struct mxc_nand_host *);
 151         struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
 152         void (*select_chip)(struct mtd_info *mtd, int chip);
 153         int (*correct_data)(struct mtd_info *mtd, u_char *dat,
 154                         u_char *read_ecc, u_char *calc_ecc);
 155
 156         /*
 157          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 158          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 159          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 160          */
 161         int irqpending_quirk;
 162         int needs_ip;
 163
 164         size_t regs_offset;
 165         size_t spare0_offset;
 166         size_t axi_offset;
 167
 168         int spare_len;
 169         int eccbytes;
 170         int eccsize;
 171         int ppb_shift;
 172 };
 173
 174 struct mxc_nand_host {
 175         struct mtd_info         mtd;
 176         struct nand_chip        nand;
 177         struct device           *dev;
 178
 179         void __iomem            *spare0;
 180         void __iomem            *main_area0;
 181
 182         void __iomem            *base;
 183         void __iomem            *regs;
 184         void __iomem            *regs_axi;
 185         void __iomem            *regs_ip;
 186         int                     status_request;
 187         struct clk              *clk;
 188         int                     clk_act;
 189         int                     irq;
 190         int                     eccsize;
 191         int                     active_cs;
 192
 193         struct completion       op_completion;
 194
 195         uint8_t                 *data_buf;
 196         unsigned int            buf_start;
 197
 198         const struct mxc_nand_devtype_data *devtype_data;
 199         struct mxc_nand_platform_data pdata;
 200 };
 201
 202 /* OOB placement block for use with hardware ecc generation */
 203 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
 204         .eccbytes = 5,
 205         .eccpos = {6, 7, 8, 9, 10},
 206         .oobfree = {{0, 5}, {12, 4}, }
 207 };
 208
 209 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
 210         .eccbytes = 20,
 211         .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
 212                    38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
 213         .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
 214 };
 215
 216 /* OOB description for 512 byte pages with 16 byte OOB */
 217 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
 218         .eccbytes = 1 * 9,
 219         .eccpos = {
 220                  7,  8,  9, 10, 11, 12, 13, 14, 15
 221         },
 222         .oobfree = {
 223                 {.offset = 0, .length = 5}
 224         }
 225 };
 226
 227 /* OOB description for 2048 byte pages with 64 byte OOB */
 228 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
 229         .eccbytes = 4 * 9,
 230         .eccpos = {
 231                  7,  8,  9, 10, 11, 12, 13, 14, 15,
 232                 23, 24, 25, 26, 27, 28, 29, 30, 31,
 233                 39, 40, 41, 42, 43, 44, 45, 46, 47,
 234                 55, 56, 57, 58, 59, 60, 61, 62, 63
 235         },
 236         .oobfree = {
 237                 {.offset = 2, .length = 4},
 238                 {.offset = 16, .length = 7},
 239                 {.offset = 32, .length = 7},
 240                 {.offset = 48, .length = 7}
 241         }
 242 };
 243
 244 /* OOB description for 4096 byte pages with 128 byte OOB */
 245 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
 246         .eccbytes = 8 * 9,
 247         .eccpos = {
 248                 7,  8,  9, 10, 11, 12, 13, 14, 15,
 249                 23, 24, 25, 26, 27, 28, 29, 30, 31,
 250                 39, 40, 41, 42, 43, 44, 45, 46, 47,
 251                 55, 56, 57, 58, 59, 60, 61, 62, 63,
 252                 71, 72, 73, 74, 75, 76, 77, 78, 79,
 253                 87, 88, 89, 90, 91, 92, 93, 94, 95,
 254                 103, 104, 105, 106, 107, 108, 109, 110, 111,
 255                 119, 120, 121, 122, 123, 124, 125, 126, 127,
 256         },
 257         .oobfree = {
 258                 {.offset = 2, .length = 4},
 259                 {.offset = 16, .length = 7},
 260                 {.offset = 32, .length = 7},
 261                 {.offset = 48, .length = 7},
 262                 {.offset = 64, .length = 7},
 263                 {.offset = 80, .length = 7},
 264                 {.offset = 96, .length = 7},
 265                 {.offset = 112, .length = 7},
 266         }
 267 };
 268
 269 static const char const *part_probes[] = {
 270         "cmdlinepart", "RedBoot", "ofpart", NULL };
 271
 272 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 273 {
 274         int i;
 275         u32 *t = trg;
 276         const __iomem u32 *s = src;
 277
 278         for (i = 0; i < (size >> 2); i++)
 279                 *t++ = __raw_readl(s++);
 280 }
 281
 282 static void memcpy32_toio(void __iomem *trg, const void *src, int size)
 283 {
 284         int i;
 285         u32 __iomem *t = trg;
 286         const u32 *s = src;
 287
 288         for (i = 0; i < (size >> 2); i++)
 289                 __raw_writel(*s++, t++);
 290 }
 291
 292 static int check_int_v3(struct mxc_nand_host *host)
 293 {
 294         uint32_t tmp;
 295
 296         tmp = readl(NFC_V3_IPC);
 297         if (!(tmp & NFC_V3_IPC_INT))
 298                 return 0;
 299
 300         tmp &= ~NFC_V3_IPC_INT;
 301         writel(tmp, NFC_V3_IPC);
 302
 303         return 1;
 304 }
 305
 306 static int check_int_v1_v2(struct mxc_nand_host *host)
 307 {
 308         uint32_t tmp;
 309
 310         tmp = readw(NFC_V1_V2_CONFIG2);
 311         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 312                 return 0;
 313
 314         if (!host->devtype_data->irqpending_quirk)
 315                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 316
 317         return 1;
 318 }
 319
 320 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 321 {
 322         uint16_t tmp;
 323
 324         tmp = readw(NFC_V1_V2_CONFIG1);
 325
 326         if (activate)
 327                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 328         else
 329                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 330
 331         writew(tmp, NFC_V1_V2_CONFIG1);
 332 }
 333
 334 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 335 {
 336         uint32_t tmp;
 337
 338         tmp = readl(NFC_V3_CONFIG2);
 339
 340         if (activate)
 341                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 342         else
 343                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 344
 345         writel(tmp, NFC_V3_CONFIG2);
 346 }
 347
 348 static void irq_control(struct mxc_nand_host *host, int activate)
 349 {
 350         if (host->devtype_data->irqpending_quirk) {
 351                 if (activate)
 352                         enable_irq(host->irq);
 353                 else
 354                         disable_irq_nosync(host->irq);
 355         } else {
 356                 host->devtype_data->irq_control(host, activate);
 357         }
 358 }
 359
 360 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
 361 {
 362         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
 363 }
 364
 365 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
 366 {
 367         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
 368 }
 369
 370 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
 371 {
 372         return readl(NFC_V3_ECC_STATUS_RESULT);
 373 }
 374
 375 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 376 {
 377         struct mxc_nand_host *host = dev_id;
 378
 379         if (!host->devtype_data->check_int(host))
 380                 return IRQ_NONE;
 381
 382         irq_control(host, 0);
 383
 384         complete(&host->op_completion);
 385
 386         return IRQ_HANDLED;
 387 }
 388
 389 /* This function polls the NANDFC to wait for the basic operation to
 390  * complete by checking the INT bit of config2 register.
 391  */
 392 static void wait_op_done(struct mxc_nand_host *host, int useirq)
 393 {
 394         int max_retries = 8000;
 395
 396         if (useirq) {
 397                 if (!host->devtype_data->check_int(host)) {
 398                         INIT_COMPLETION(host->op_completion);
 399                         irq_control(host, 1);
 400                         wait_for_completion(&host->op_completion);
 401                 }
 402         } else {
 403                 while (max_retries-- > 0) {
 404                         if (host->devtype_data->check_int(host))
 405                                 break;
 406
 407                         udelay(1);
 408                 }
 409                 if (max_retries < 0)
 410                         pr_debug("%s: INT not set\n", __func__);
 411         }
 412 }
 413
 414 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 415 {
 416         /* fill command */
 417         writel(cmd, NFC_V3_FLASH_CMD);
 418
 419         /* send out command */
 420         writel(NFC_CMD, NFC_V3_LAUNCH);
 421
 422         /* Wait for operation to complete */
 423         wait_op_done(host, useirq);
 424 }
 425
 426 /* This function issues the specified command to the NAND device and
 427  * waits for completion. */
 428 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 429 {
 430         pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 431
 432         writew(cmd, NFC_V1_V2_FLASH_CMD);
 433         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 434
 435         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 436                 int max_retries = 100;
 437                 /* Reset completion is indicated by NFC_CONFIG2 */
 438                 /* being set to 0 */
 439                 while (max_retries-- > 0) {
 440                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 441                                 break;
 442                         }
 443                         udelay(1);
 444                 }
 445                 if (max_retries < 0)
 446                         pr_debug("%s: RESET failed\n", __func__);
 447         } else {
 448                 /* Wait for operation to complete */
 449                 wait_op_done(host, useirq);
 450         }
 451 }
 452
 453 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 454 {
 455         /* fill address */
 456         writel(addr, NFC_V3_FLASH_ADDR0);
 457
 458         /* send out address */
 459         writel(NFC_ADDR, NFC_V3_LAUNCH);
 460
 461         wait_op_done(host, 0);
 462 }
 463
 464 /* This function sends an address (or partial address) to the
 465  * NAND device. The address is used to select the source/destination for
 466  * a NAND command. */
 467 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 468 {
 469         pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
 470
 471         writew(addr, NFC_V1_V2_FLASH_ADDR);
 472         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 473
 474         /* Wait for operation to complete */
 475         wait_op_done(host, islast);
 476 }
 477
 478 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 479 {
 480         struct nand_chip *nand_chip = mtd->priv;
 481         struct mxc_nand_host *host = nand_chip->priv;
 482         uint32_t tmp;
 483
 484         tmp = readl(NFC_V3_CONFIG1);
 485         tmp &= ~(7 << 4);
 486         writel(tmp, NFC_V3_CONFIG1);
 487
 488         /* transfer data from NFC ram to nand */
 489         writel(ops, NFC_V3_LAUNCH);
 490
 491         wait_op_done(host, false);
 492 }
 493
 494 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 495 {
 496         struct nand_chip *nand_chip = mtd->priv;
 497         struct mxc_nand_host *host = nand_chip->priv;
 498
 499         /* NANDFC buffer 0 is used for page read/write */
 500         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 501
 502         writew(ops, NFC_V1_V2_CONFIG2);
 503
 504         /* Wait for operation to complete */
 505         wait_op_done(host, true);
 506 }
 507
 508 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 509 {
 510         struct nand_chip *nand_chip = mtd->priv;
 511         struct mxc_nand_host *host = nand_chip->priv;
 512         int bufs, i;
 513
 514         if (mtd->writesize > 512)
 515                 bufs = 4;
 516         else
 517                 bufs = 1;
 518
 519         for (i = 0; i < bufs; i++) {
 520
 521                 /* NANDFC buffer 0 is used for page read/write */
 522                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 523
 524                 writew(ops, NFC_V1_V2_CONFIG2);
 525
 526                 /* Wait for operation to complete */
 527                 wait_op_done(host, true);
 528         }
 529 }
 530
 531 static void send_read_id_v3(struct mxc_nand_host *host)
 532 {
 533         /* Read ID into main buffer */
 534         writel(NFC_ID, NFC_V3_LAUNCH);
 535
 536         wait_op_done(host, true);
 537
 538         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 539 }
 540
 541 /* Request the NANDFC to perform a read of the NAND device ID. */
 542 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 543 {
 544         struct nand_chip *this = &host->nand;
 545
 546         /* NANDFC buffer 0 is used for device ID output */
 547         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 548
 549         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 550
 551         /* Wait for operation to complete */
 552         wait_op_done(host, true);
 553
 554         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 555
 556         if (this->options & NAND_BUSWIDTH_16) {
 557                 /* compress the ID info */
 558                 host->data_buf[1] = host->data_buf[2];
 559                 host->data_buf[2] = host->data_buf[4];
 560                 host->data_buf[3] = host->data_buf[6];
 561                 host->data_buf[4] = host->data_buf[8];
 562                 host->data_buf[5] = host->data_buf[10];
 563         }
 564 }
 565
 566 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 567 {
 568         writew(NFC_STATUS, NFC_V3_LAUNCH);
 569         wait_op_done(host, true);
 570
 571         return readl(NFC_V3_CONFIG1) >> 16;
 572 }
 573
 574 /* This function requests the NANDFC to perform a read of the
 575  * NAND device status and returns the current status. */
 576 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 577 {
 578         void __iomem *main_buf = host->main_area0;
 579         uint32_t store;
 580         uint16_t ret;
 581
 582         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 583
 584         /*
 585          * The device status is stored in main_area0. To
 586          * prevent corruption of the buffer save the value
 587          * and restore it afterwards.
 588          */
 589         store = readl(main_buf);
 590
 591         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 592         wait_op_done(host, true);
 593
 594         ret = readw(main_buf);
 595
 596         writel(store, main_buf);
 597
 598         return ret;
 599 }
 600
 601 /* This functions is used by upper layer to checks if device is ready */
 602 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 603 {
 604         /*
 605          * NFC handles R/B internally. Therefore, this function
 606          * always returns status as ready.
 607          */
 608         return 1;
 609 }
 610
 611 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 612 {
 613         /*
 614          * If HW ECC is enabled, we turn it on during init. There is
 615          * no need to enable again here.
 616          */
 617 }
 618
 619 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
 620                                  u_char *read_ecc, u_char *calc_ecc)
 621 {
 622         struct nand_chip *nand_chip = mtd->priv;
 623         struct mxc_nand_host *host = nand_chip->priv;
 624
 625         /*
 626          * 1-Bit errors are automatically corrected in HW.  No need for
 627          * additional correction.  2-Bit errors cannot be corrected by
 628          * HW ECC, so we need to return failure
 629          */
 630         uint16_t ecc_status = get_ecc_status_v1(host);
 631
 632         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 633                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 634                 return -1;
 635         }
 636
 637         return 0;
 638 }
 639
 640 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
 641                                  u_char *read_ecc, u_char *calc_ecc)
 642 {
 643         struct nand_chip *nand_chip = mtd->priv;
 644         struct mxc_nand_host *host = nand_chip->priv;
 645         u32 ecc_stat, err;
 646         int no_subpages = 1;
 647         int ret = 0;
 648         u8 ecc_bit_mask, err_limit;
 649
 650         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 651         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 652
 653         no_subpages = mtd->writesize >> 9;
 654
 655         ecc_stat = host->devtype_data->get_ecc_status(host);
 656
 657         do {
 658                 err = ecc_stat & ecc_bit_mask;
 659                 if (err > err_limit) {
 660                         printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 661                         return -1;
 662                 } else {
 663                         ret += err;
 664                 }
 665                 ecc_stat >>= 4;
 666         } while (--no_subpages);
 667
 668         mtd->ecc_stats.corrected += ret;
 669         pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
 670
 671         return ret;
 672 }
 673
 674 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 675                                   u_char *ecc_code)
 676 {
 677         return 0;
 678 }
 679
 680 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 681 {
 682         struct nand_chip *nand_chip = mtd->priv;
 683         struct mxc_nand_host *host = nand_chip->priv;
 684         uint8_t ret;
 685
 686         /* Check for status request */
 687         if (host->status_request)
 688                 return host->devtype_data->get_dev_status(host) & 0xFF;
 689
 690         ret = *(uint8_t *)(host->data_buf + host->buf_start);
 691         host->buf_start++;
 692
 693         return ret;
 694 }
 695
 696 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 697 {
 698         struct nand_chip *nand_chip = mtd->priv;
 699         struct mxc_nand_host *host = nand_chip->priv;
 700         uint16_t ret;
 701
 702         ret = *(uint16_t *)(host->data_buf + host->buf_start);
 703         host->buf_start += 2;
 704
 705         return ret;
 706 }
 707
 708 /* Write data of length len to buffer buf. The data to be
 709  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 710  * Operation by the NFC, the data is written to NAND Flash */
 711 static void mxc_nand_write_buf(struct mtd_info *mtd,
 712                                 const u_char *buf, int len)
 713 {
 714         struct nand_chip *nand_chip = mtd->priv;
 715         struct mxc_nand_host *host = nand_chip->priv;
 716         u16 col = host->buf_start;
 717         int n = mtd->oobsize + mtd->writesize - col;
 718
 719         n = min(n, len);
 720
 721         memcpy(host->data_buf + col, buf, n);
 722
 723         host->buf_start += n;
 724 }
 725
 726 /* Read the data buffer from the NAND Flash. To read the data from NAND
 727  * Flash first the data output cycle is initiated by the NFC, which copies
 728  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 729  */
 730 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 731 {
 732         struct nand_chip *nand_chip = mtd->priv;
 733         struct mxc_nand_host *host = nand_chip->priv;
 734         u16 col = host->buf_start;
 735         int n = mtd->oobsize + mtd->writesize - col;
 736
 737         n = min(n, len);
 738
 739         memcpy(buf, host->data_buf + col, n);
 740
 741         host->buf_start += n;
 742 }
 743
 744 /* This function is used by upper layer for select and
 745  * deselect of the NAND chip */
 746 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
 747 {
 748         struct nand_chip *nand_chip = mtd->priv;
 749         struct mxc_nand_host *host = nand_chip->priv;
 750
 751         if (chip == -1) {
 752                 /* Disable the NFC clock */
 753                 if (host->clk_act) {
 754                         clk_disable_unprepare(host->clk);
 755                         host->clk_act = 0;
 756                 }
 757                 return;
 758         }
 759
 760         if (!host->clk_act) {
 761                 /* Enable the NFC clock */
 762                 clk_prepare_enable(host->clk);
 763                 host->clk_act = 1;
 764         }
 765 }
 766
 767 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
 768 {
 769         struct nand_chip *nand_chip = mtd->priv;
 770         struct mxc_nand_host *host = nand_chip->priv;
 771
 772         if (chip == -1) {
 773                 /* Disable the NFC clock */
 774                 if (host->clk_act) {
 775                         clk_disable_unprepare(host->clk);
 776                         host->clk_act = 0;
 777                 }
 778                 return;
 779         }
 780
 781         if (!host->clk_act) {
 782                 /* Enable the NFC clock */
 783                 clk_prepare_enable(host->clk);
 784                 host->clk_act = 1;
 785         }
 786
 787         host->active_cs = chip;
 788         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 789 }
 790
 791 /*
 792  * Function to transfer data to/from spare area.
 793  */
 794 static void copy_spare(struct mtd_info *mtd, bool bfrom)
 795 {
 796         struct nand_chip *this = mtd->priv;
 797         struct mxc_nand_host *host = this->priv;
 798         u16 i, j;
 799         u16 n = mtd->writesize >> 9;
 800         u8 *d = host->data_buf + mtd->writesize;
 801         u8 __iomem *s = host->spare0;
 802         u16 t = host->devtype_data->spare_len;
 803
 804         j = (mtd->oobsize / n >> 1) << 1;
 805
 806         if (bfrom) {
 807                 for (i = 0; i < n - 1; i++)
 808                         memcpy32_fromio(d + i * j, s + i * t, j);
 809
 810                 /* the last section */
 811                 memcpy32_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
 812         } else {
 813                 for (i = 0; i < n - 1; i++)
 814                         memcpy32_toio(&s[i * t], &d[i * j], j);
 815
 816                 /* the last section */
 817                 memcpy32_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
 818         }
 819 }
 820
 821 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 822 {
 823         struct nand_chip *nand_chip = mtd->priv;
 824         struct mxc_nand_host *host = nand_chip->priv;
 825
 826         /* Write out column address, if necessary */
 827         if (column != -1) {
 828                 /*
 829                  * MXC NANDFC can only perform full page+spare or
 830                  * spare-only read/write.  When the upper layers
 831                  * perform a read/write buf operation, the saved column
 832                   * address is used to index into the full page.
 833                  */
 834                 host->devtype_data->send_addr(host, 0, page_addr == -1);
 835                 if (mtd->writesize > 512)
 836                         /* another col addr cycle for 2k page */
 837                         host->devtype_data->send_addr(host, 0, false);
 838         }
 839
 840         /* Write out page address, if necessary */
 841         if (page_addr != -1) {
 842                 /* paddr_0 - p_addr_7 */
 843                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
 844
 845                 if (mtd->writesize > 512) {
 846                         if (mtd->size >= 0x10000000) {
 847                                 /* paddr_8 - paddr_15 */
 848                                 host->devtype_data->send_addr(host,
 849                                                 (page_addr >> 8) & 0xff,
 850                                                 false);
 851                                 host->devtype_data->send_addr(host,
 852                                                 (page_addr >> 16) & 0xff,
 853                                                 true);
 854                         } else
 855                                 /* paddr_8 - paddr_15 */
 856                                 host->devtype_data->send_addr(host,
 857                                                 (page_addr >> 8) & 0xff, true);
 858                 } else {
 859                         /* One more address cycle for higher density devices */
 860                         if (mtd->size >= 0x4000000) {
 861                                 /* paddr_8 - paddr_15 */
 862                                 host->devtype_data->send_addr(host,
 863                                                 (page_addr >> 8) & 0xff,
 864                                                 false);
 865                                 host->devtype_data->send_addr(host,
 866                                                 (page_addr >> 16) & 0xff,
 867                                                 true);
 868                         } else
 869                                 /* paddr_8 - paddr_15 */
 870                                 host->devtype_data->send_addr(host,
 871                                                 (page_addr >> 8) & 0xff, true);
 872                 }
 873         }
 874 }
 875
 876 /*
 877  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
 878  * on how much oob the nand chip has. For 8bit ecc we need at least
 879  * 26 bytes of oob data per 512 byte block.
 880  */
 881 static int get_eccsize(struct mtd_info *mtd)
 882 {
 883         int oobbytes_per_512 = 0;
 884
 885         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
 886
 887         if (oobbytes_per_512 < 26)
 888                 return 4;
 889         else
 890                 return 8;
 891 }
 892
 893 static void preset_v1(struct mtd_info *mtd)
 894 {
 895         struct nand_chip *nand_chip = mtd->priv;
 896         struct mxc_nand_host *host = nand_chip->priv;
 897         uint16_t config1 = 0;
 898
 899         if (nand_chip->ecc.mode == NAND_ECC_HW)
 900                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 901
 902         if (!host->devtype_data->irqpending_quirk)
 903                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
 904
 905         host->eccsize = 1;
 906
 907         writew(config1, NFC_V1_V2_CONFIG1);
 908         /* preset operation */
 909
 910         /* Unlock the internal RAM Buffer */
 911         writew(0x2, NFC_V1_V2_CONFIG);
 912
 913         /* Blocks to be unlocked */
 914         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
 915         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
 916
 917         /* Unlock Block Command for given address range */
 918         writew(0x4, NFC_V1_V2_WRPROT);
 919 }
 920
 921 static void preset_v2(struct mtd_info *mtd)
 922 {
 923         struct nand_chip *nand_chip = mtd->priv;
 924         struct mxc_nand_host *host = nand_chip->priv;
 925         uint16_t config1 = 0;
 926
 927         if (nand_chip->ecc.mode == NAND_ECC_HW)
 928                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 929
 930         config1 |= NFC_V2_CONFIG1_FP_INT;
 931
 932         if (!host->devtype_data->irqpending_quirk)
 933                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
 934
 935         if (mtd->writesize) {
 936                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
 937
 938                 host->eccsize = get_eccsize(mtd);
 939                 if (host->eccsize == 4)
 940                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
 941
 942                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
 943         } else {
 944                 host->eccsize = 1;
 945         }
 946
 947         writew(config1, NFC_V1_V2_CONFIG1);
 948         /* preset operation */
 949
 950         /* Unlock the internal RAM Buffer */
 951         writew(0x2, NFC_V1_V2_CONFIG);
 952
 953         /* Blocks to be unlocked */
 954         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
 955         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
 956         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
 957         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
 958         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
 959         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
 960         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
 961         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
 962
 963         /* Unlock Block Command for given address range */
 964         writew(0x4, NFC_V1_V2_WRPROT);
 965 }
 966
 967 static void preset_v3(struct mtd_info *mtd)
 968 {
 969         struct nand_chip *chip = mtd->priv;
 970         struct mxc_nand_host *host = chip->priv;
 971         uint32_t config2, config3;
 972         int i, addr_phases;
 973
 974         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
 975         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
 976
 977         /* Unlock the internal RAM Buffer */
 978         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
 979                         NFC_V3_WRPROT);
 980
 981         /* Blocks to be unlocked */
 982         for (i = 0; i < NAND_MAX_CHIPS; i++)
 983                 writel(0x0 |    (0xffff << 16),
 984                                 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
 985
 986         writel(0, NFC_V3_IPC);
 987
 988         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
 989                 NFC_V3_CONFIG2_2CMD_PHASES |
 990                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
 991                 NFC_V3_CONFIG2_ST_CMD(0x70) |
 992                 NFC_V3_CONFIG2_INT_MSK |
 993                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
 994
 995         if (chip->ecc.mode == NAND_ECC_HW)
 996                 config2 |= NFC_V3_CONFIG2_ECC_EN;
 997
 998         addr_phases = fls(chip->pagemask) >> 3;
 999
1000         if (mtd->writesize == 2048) {
1001                 config2 |= NFC_V3_CONFIG2_PS_2048;
1002                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1003         } else if (mtd->writesize == 4096) {
1004                 config2 |= NFC_V3_CONFIG2_PS_4096;
1005                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1006         } else {
1007                 config2 |= NFC_V3_CONFIG2_PS_512;
1008                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1009         }
1010
1011         if (mtd->writesize) {
1012                 config2 |= NFC_V3_CONFIG2_PPB(
1013                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1014                                 host->devtype_data->ppb_shift);
1015                 host->eccsize = get_eccsize(mtd);
1016                 if (host->eccsize == 8)
1017                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1018         }
1019
1020         writel(config2, NFC_V3_CONFIG2);
1021
1022         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1023                         NFC_V3_CONFIG3_NO_SDMA |
1024                         NFC_V3_CONFIG3_RBB_MODE |
1025                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1026                         NFC_V3_CONFIG3_ADD_OP(0);
1027
1028         if (!(chip->options & NAND_BUSWIDTH_16))
1029                 config3 |= NFC_V3_CONFIG3_FW8;
1030
1031         writel(config3, NFC_V3_CONFIG3);
1032
1033         writel(0, NFC_V3_DELAY_LINE);
1034 }
1035
1036 /* Used by the upper layer to write command to NAND Flash for
1037  * different operations to be carried out on NAND Flash */
1038 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1039                                 int column, int page_addr)
1040 {
1041         struct nand_chip *nand_chip = mtd->priv;
1042         struct mxc_nand_host *host = nand_chip->priv;
1043
1044         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1045               command, column, page_addr);
1046
1047         /* Reset command state information */
1048         host->status_request = false;
1049
1050         /* Command pre-processing step */
1051         switch (command) {
1052         case NAND_CMD_RESET:
1053                 host->devtype_data->preset(mtd);
1054                 host->devtype_data->send_cmd(host, command, false);
1055                 break;
1056
1057         case NAND_CMD_STATUS:
1058                 host->buf_start = 0;
1059                 host->status_request = true;
1060
1061                 host->devtype_data->send_cmd(host, command, true);
1062                 mxc_do_addr_cycle(mtd, column, page_addr);
1063                 break;
1064
1065         case NAND_CMD_READ0:
1066         case NAND_CMD_READOOB:
1067                 if (command == NAND_CMD_READ0)
1068                         host->buf_start = column;
1069                 else
1070                         host->buf_start = column + mtd->writesize;
1071
1072                 command = NAND_CMD_READ0; /* only READ0 is valid */
1073
1074                 host->devtype_data->send_cmd(host, command, false);
1075                 mxc_do_addr_cycle(mtd, column, page_addr);
1076
1077                 if (mtd->writesize > 512)
1078                         host->devtype_data->send_cmd(host,
1079                                         NAND_CMD_READSTART, true);
1080
1081                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1082
1083                 memcpy32_fromio(host->data_buf, host->main_area0,
1084                                 mtd->writesize);
1085                 copy_spare(mtd, true);
1086                 break;
1087
1088         case NAND_CMD_SEQIN:
1089                 if (column >= mtd->writesize)
1090                         /* call ourself to read a page */
1091                         mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1092
1093                 host->buf_start = column;
1094
1095                 host->devtype_data->send_cmd(host, command, false);
1096                 mxc_do_addr_cycle(mtd, column, page_addr);
1097                 break;
1098
1099         case NAND_CMD_PAGEPROG:
1100                 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1101                 copy_spare(mtd, false);
1102                 host->devtype_data->send_page(mtd, NFC_INPUT);
1103                 host->devtype_data->send_cmd(host, command, true);
1104                 mxc_do_addr_cycle(mtd, column, page_addr);
1105                 break;
1106
1107         case NAND_CMD_READID:
1108                 host->devtype_data->send_cmd(host, command, true);
1109                 mxc_do_addr_cycle(mtd, column, page_addr);
1110                 host->devtype_data->send_read_id(host);
1111                 host->buf_start = column;
1112                 break;
1113
1114         case NAND_CMD_ERASE1:
1115         case NAND_CMD_ERASE2:
1116                 host->devtype_data->send_cmd(host, command, false);
1117                 mxc_do_addr_cycle(mtd, column, page_addr);
1118
1119                 break;
1120         }
1121 }
1122
1123 /*
1124  * The generic flash bbt decriptors overlap with our ecc
1125  * hardware, so define some i.MX specific ones.
1126  */
1127 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1128 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1129
1130 static struct nand_bbt_descr bbt_main_descr = {
1131         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1132             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1133         .offs = 0,
1134         .len = 4,
1135         .veroffs = 4,
1136         .maxblocks = 4,
1137         .pattern = bbt_pattern,
1138 };
1139
1140 static struct nand_bbt_descr bbt_mirror_descr = {
1141         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1142             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1143         .offs = 0,
1144         .len = 4,
1145         .veroffs = 4,
1146         .maxblocks = 4,
1147         .pattern = mirror_pattern,
1148 };
1149
1150 /* v1 + irqpending_quirk: i.MX21 */
1151 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1152         .preset = preset_v1,
1153         .send_cmd = send_cmd_v1_v2,
1154         .send_addr = send_addr_v1_v2,
1155         .send_page = send_page_v1,
1156         .send_read_id = send_read_id_v1_v2,
1157         .get_dev_status = get_dev_status_v1_v2,
1158         .check_int = check_int_v1_v2,
1159         .irq_control = irq_control_v1_v2,
1160         .get_ecc_status = get_ecc_status_v1,
1161         .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1162         .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1163         .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1164         .select_chip = mxc_nand_select_chip_v1_v3,
1165         .correct_data = mxc_nand_correct_data_v1,
1166         .irqpending_quirk = 1,
1167         .needs_ip = 0,
1168         .regs_offset = 0xe00,
1169         .spare0_offset = 0x800,
1170         .spare_len = 16,
1171         .eccbytes = 3,
1172         .eccsize = 1,
1173 };
1174
1175 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1176 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1177         .preset = preset_v1,
1178         .send_cmd = send_cmd_v1_v2,
1179         .send_addr = send_addr_v1_v2,
1180         .send_page = send_page_v1,
1181         .send_read_id = send_read_id_v1_v2,
1182         .get_dev_status = get_dev_status_v1_v2,
1183         .check_int = check_int_v1_v2,
1184         .irq_control = irq_control_v1_v2,
1185         .get_ecc_status = get_ecc_status_v1,
1186         .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1187         .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1188         .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1189         .select_chip = mxc_nand_select_chip_v1_v3,
1190         .correct_data = mxc_nand_correct_data_v1,
1191         .irqpending_quirk = 0,
1192         .needs_ip = 0,
1193         .regs_offset = 0xe00,
1194         .spare0_offset = 0x800,
1195         .axi_offset = 0,
1196         .spare_len = 16,
1197         .eccbytes = 3,
1198         .eccsize = 1,
1199 };
1200
1201 /* v21: i.MX25, i.MX35 */
1202 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1203         .preset = preset_v2,
1204         .send_cmd = send_cmd_v1_v2,
1205         .send_addr = send_addr_v1_v2,
1206         .send_page = send_page_v2,
1207         .send_read_id = send_read_id_v1_v2,
1208         .get_dev_status = get_dev_status_v1_v2,
1209         .check_int = check_int_v1_v2,
1210         .irq_control = irq_control_v1_v2,
1211         .get_ecc_status = get_ecc_status_v2,
1212         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1213         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1214         .ecclayout_4k = &nandv2_hw_eccoob_4k,
1215         .select_chip = mxc_nand_select_chip_v2,
1216         .correct_data = mxc_nand_correct_data_v2_v3,
1217         .irqpending_quirk = 0,
1218         .needs_ip = 0,
1219         .regs_offset = 0x1e00,
1220         .spare0_offset = 0x1000,
1221         .axi_offset = 0,
1222         .spare_len = 64,
1223         .eccbytes = 9,
1224         .eccsize = 0,
1225 };
1226
1227 /* v3.2a: i.MX51 */
1228 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1229         .preset = preset_v3,
1230         .send_cmd = send_cmd_v3,
1231         .send_addr = send_addr_v3,
1232         .send_page = send_page_v3,
1233         .send_read_id = send_read_id_v3,
1234         .get_dev_status = get_dev_status_v3,
1235         .check_int = check_int_v3,
1236         .irq_control = irq_control_v3,
1237         .get_ecc_status = get_ecc_status_v3,
1238         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1239         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1240         .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1241         .select_chip = mxc_nand_select_chip_v1_v3,
1242         .correct_data = mxc_nand_correct_data_v2_v3,
1243         .irqpending_quirk = 0,
1244         .needs_ip = 1,
1245         .regs_offset = 0,
1246         .spare0_offset = 0x1000,
1247         .axi_offset = 0x1e00,
1248         .spare_len = 64,
1249         .eccbytes = 0,
1250         .eccsize = 0,
1251         .ppb_shift = 7,
1252 };
1253
1254 /* v3.2b: i.MX53 */
1255 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1256         .preset = preset_v3,
1257         .send_cmd = send_cmd_v3,
1258         .send_addr = send_addr_v3,
1259         .send_page = send_page_v3,
1260         .send_read_id = send_read_id_v3,
1261         .get_dev_status = get_dev_status_v3,
1262         .check_int = check_int_v3,
1263         .irq_control = irq_control_v3,
1264         .get_ecc_status = get_ecc_status_v3,
1265         .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1266         .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1267         .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1268         .select_chip = mxc_nand_select_chip_v1_v3,
1269         .correct_data = mxc_nand_correct_data_v2_v3,
1270         .irqpending_quirk = 0,
1271         .needs_ip = 1,
1272         .regs_offset = 0,
1273         .spare0_offset = 0x1000,
1274         .axi_offset = 0x1e00,
1275         .spare_len = 64,
1276         .eccbytes = 0,
1277         .eccsize = 0,
1278         .ppb_shift = 8,
1279 };
1280
1281 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1282 {
1283         return host->devtype_data == &imx21_nand_devtype_data;
1284 }
1285
1286 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1287 {
1288         return host->devtype_data == &imx27_nand_devtype_data;
1289 }
1290
1291 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1292 {
1293         return host->devtype_data == &imx25_nand_devtype_data;
1294 }
1295
1296 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1297 {
1298         return host->devtype_data == &imx51_nand_devtype_data;
1299 }
1300
1301 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1302 {
1303         return host->devtype_data == &imx53_nand_devtype_data;
1304 }
1305
1306 static struct platform_device_id mxcnd_devtype[] = {
1307         {
1308                 .name = "imx21-nand",
1309                 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1310         }, {
1311                 .name = "imx27-nand",
1312                 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1313         }, {
1314                 .name = "imx25-nand",
1315                 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1316         }, {
1317                 .name = "imx51-nand",
1318                 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1319         }, {
1320                 .name = "imx53-nand",
1321                 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1322         }, {
1323                 /* sentinel */
1324         }
1325 };
1326 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1327
1328 #ifdef CONFIG_OF_MTD
1329 static const struct of_device_id mxcnd_dt_ids[] = {
1330         {
1331                 .compatible = "fsl,imx21-nand",
1332                 .data = &imx21_nand_devtype_data,
1333         }, {
1334                 .compatible = "fsl,imx27-nand",
1335                 .data = &imx27_nand_devtype_data,
1336         }, {
1337                 .compatible = "fsl,imx25-nand",
1338                 .data = &imx25_nand_devtype_data,
1339         }, {
1340                 .compatible = "fsl,imx51-nand",
1341                 .data = &imx51_nand_devtype_data,
1342         }, {
1343                 .compatible = "fsl,imx53-nand",
1344                 .data = &imx53_nand_devtype_data,
1345         },
1346         { /* sentinel */ }
1347 };
1348
1349 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1350 {
1351         struct device_node *np = host->dev->of_node;
1352         struct mxc_nand_platform_data *pdata = &host->pdata;
1353         const struct of_device_id *of_id =
1354                 of_match_device(mxcnd_dt_ids, host->dev);
1355         int buswidth;
1356
1357         if (!np)
1358                 return 1;
1359
1360         if (of_get_nand_ecc_mode(np) >= 0)
1361                 pdata->hw_ecc = 1;
1362
1363         pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1364
1365         buswidth = of_get_nand_bus_width(np);
1366         if (buswidth < 0)
1367                 return buswidth;
1368
1369         pdata->width = buswidth / 8;
1370
1371         host->devtype_data = of_id->data;
1372
1373         return 0;
1374 }
1375 #else
1376 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1377 {
1378         return 1;
1379 }
1380 #endif
1381
1382 static int mxcnd_probe(struct platform_device *pdev)
1383 {
1384         struct nand_chip *this;
1385         struct mtd_info *mtd;
1386         struct mxc_nand_host *host;
1387         struct resource *res;
1388         int err = 0;
1389
1390         /* Allocate memory for MTD device structure and private data */
1391         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host) +
1392                         NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE, GFP_KERNEL);
1393         if (!host)
1394                 return -ENOMEM;
1395
1396         host->data_buf = (uint8_t *)(host + 1);
1397
1398         host->dev = &pdev->dev;
1399         /* structures must be linked */
1400         this = &host->nand;
1401         mtd = &host->mtd;
1402         mtd->priv = this;
1403         mtd->owner = THIS_MODULE;
1404         mtd->dev.parent = &pdev->dev;
1405         mtd->name = DRIVER_NAME;
1406
1407         /* 50 us command delay time */
1408         this->chip_delay = 5;
1409
1410         this->priv = host;
1411         this->dev_ready = mxc_nand_dev_ready;
1412         this->cmdfunc = mxc_nand_command;
1413         this->read_byte = mxc_nand_read_byte;
1414         this->read_word = mxc_nand_read_word;
1415         this->write_buf = mxc_nand_write_buf;
1416         this->read_buf = mxc_nand_read_buf;
1417
1418         host->clk = devm_clk_get(&pdev->dev, NULL);
1419         if (IS_ERR(host->clk))
1420                 return PTR_ERR(host->clk);
1421
1422         err = mxcnd_probe_dt(host);
1423         if (err > 0) {
1424                 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1425                 if (pdata) {
1426                         host->pdata = *pdata;
1427                         host->devtype_data = (struct mxc_nand_devtype_data *)
1428                                                 pdev->id_entry->driver_data;
1429                 } else {
1430                         err = -ENODEV;
1431                 }
1432         }
1433         if (err < 0)
1434                 return err;
1435
1436         if (host->devtype_data->needs_ip) {
1437                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1438                 if (!res)
1439                         return -ENODEV;
1440                 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1441                 if (IS_ERR(host->regs_ip))
1442                         return PTR_ERR(host->regs_ip);
1443
1444                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1445         } else {
1446                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1447         }
1448
1449         if (!res)
1450                 return -ENODEV;
1451
1452         host->base = devm_ioremap_resource(&pdev->dev, res);
1453         if (IS_ERR(host->base))
1454                 return PTR_ERR(host->base);
1455
1456         host->main_area0 = host->base;
1457
1458         if (host->devtype_data->regs_offset)
1459                 host->regs = host->base + host->devtype_data->regs_offset;
1460         host->spare0 = host->base + host->devtype_data->spare0_offset;
1461         if (host->devtype_data->axi_offset)
1462                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1463
1464         this->ecc.bytes = host->devtype_data->eccbytes;
1465         host->eccsize = host->devtype_data->eccsize;
1466
1467         this->select_chip = host->devtype_data->select_chip;
1468         this->ecc.size = 512;
1469         this->ecc.layout = host->devtype_data->ecclayout_512;
1470
1471         if (host->pdata.hw_ecc) {
1472                 this->ecc.calculate = mxc_nand_calculate_ecc;
1473                 this->ecc.hwctl = mxc_nand_enable_hwecc;
1474                 this->ecc.correct = host->devtype_data->correct_data;
1475                 this->ecc.mode = NAND_ECC_HW;
1476         } else {
1477                 this->ecc.mode = NAND_ECC_SOFT;
1478         }
1479
1480         /* NAND bus width determines access functions used by upper layer */
1481         if (host->pdata.width == 2)
1482                 this->options |= NAND_BUSWIDTH_16;
1483
1484         if (host->pdata.flash_bbt) {
1485                 this->bbt_td = &bbt_main_descr;
1486                 this->bbt_md = &bbt_mirror_descr;
1487                 /* update flash based bbt */
1488                 this->bbt_options |= NAND_BBT_USE_FLASH;
1489         }
1490
1491         init_completion(&host->op_completion);
1492
1493         host->irq = platform_get_irq(pdev, 0);
1494
1495         /*
1496          * Use host->devtype_data->irq_control() here instead of irq_control()
1497          * because we must not disable_irq_nosync without having requested the
1498          * irq.
1499          */
1500         host->devtype_data->irq_control(host, 0);
1501
1502         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1503                         IRQF_DISABLED, DRIVER_NAME, host);
1504         if (err)
1505                 return err;
1506
1507         clk_prepare_enable(host->clk);
1508         host->clk_act = 1;
1509
1510         /*
1511          * Now that we "own" the interrupt make sure the interrupt mask bit is
1512          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1513          * on this machine.
1514          */
1515         if (host->devtype_data->irqpending_quirk) {
1516                 disable_irq_nosync(host->irq);
1517                 host->devtype_data->irq_control(host, 1);
1518         }
1519
1520         /* first scan to find the device and get the page size */
1521         if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1522                 err = -ENXIO;
1523                 goto escan;
1524         }
1525
1526         /* Call preset again, with correct writesize this time */
1527         host->devtype_data->preset(mtd);
1528
1529         if (mtd->writesize == 2048)
1530                 this->ecc.layout = host->devtype_data->ecclayout_2k;
1531         else if (mtd->writesize == 4096)
1532                 this->ecc.layout = host->devtype_data->ecclayout_4k;
1533
1534         if (this->ecc.mode == NAND_ECC_HW) {
1535                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1536                         this->ecc.strength = 1;
1537                 else
1538                         this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1539         }
1540
1541         /* second phase scan */
1542         if (nand_scan_tail(mtd)) {
1543                 err = -ENXIO;
1544                 goto escan;
1545         }
1546
1547         /* Register the partitions */
1548         mtd_device_parse_register(mtd, part_probes,
1549                         &(struct mtd_part_parser_data){
1550                                 .of_node = pdev->dev.of_node,
1551                         },
1552                         host->pdata.parts,
1553                         host->pdata.nr_parts);
1554
1555         platform_set_drvdata(pdev, host);
1556
1557         return 0;
1558
1559 escan:
1560         if (host->clk_act)
1561                 clk_disable_unprepare(host->clk);
1562
1563         return err;
1564 }
1565
1566 static int mxcnd_remove(struct platform_device *pdev)
1567 {
1568         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1569
1570         platform_set_drvdata(pdev, NULL);
1571
1572         nand_release(&host->mtd);
1573
1574         return 0;
1575 }
1576
1577 static struct platform_driver mxcnd_driver = {
1578         .driver = {
1579                    .name = DRIVER_NAME,
1580                    .owner = THIS_MODULE,
1581                    .of_match_table = of_match_ptr(mxcnd_dt_ids),
1582         },
1583         .id_table = mxcnd_devtype,
1584         .probe = mxcnd_probe,
1585         .remove = mxcnd_remove,
1586 };
1587 module_platform_driver(mxcnd_driver);
1588
1589 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1590 MODULE_DESCRIPTION("MXC NAND MTD driver");
1591 MODULE_LICENSE("GPL");