drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *
   8  *      Additional technical information is available on
   9  *      http://www.linux-mtd.infradead.org/doc/nand.html
  10  *
  11  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  12  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  13  *
  14  *  Credits:
  15  *      David Woodhouse for adding multichip support
  16  *
  17  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  18  *      rework for 2K page size chips
  19  *
  20  *  TODO:
  21  *      Enable cached programming for 2k page size chips
  22  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  23  *      if we have HW ECC support.
  24  *      BBT table is not serialized, has to be fixed
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License version 2 as
  28  * published by the Free Software Foundation.
  29  *
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/delay.h>
  34 #include <linux/errno.h>
  35 #include <linux/err.h>
  36 #include <linux/sched.h>
  37 #include <linux/slab.h>
  38 #include <linux/types.h>
  39 #include <linux/mtd/mtd.h>
  40 #include <linux/mtd/nand.h>
  41 #include <linux/mtd/nand_ecc.h>
  42 #include <linux/mtd/nand_bch.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/bitops.h>
  45 #include <linux/leds.h>
  46 #include <linux/io.h>
  47 #include <linux/mtd/partitions.h>
  48
  49 /* Define default oob placement schemes for large and small page devices */
  50 static struct nand_ecclayout nand_oob_8 = {
  51         .eccbytes = 3,
  52         .eccpos = {0, 1, 2},
  53         .oobfree = {
  54                 {.offset = 3,
  55                  .length = 2},
  56                 {.offset = 6,
  57                  .length = 2} }
  58 };
  59
  60 static struct nand_ecclayout nand_oob_16 = {
  61         .eccbytes = 6,
  62         .eccpos = {0, 1, 2, 3, 6, 7},
  63         .oobfree = {
  64                 {.offset = 8,
  65                  . length = 8} }
  66 };
  67
  68 static struct nand_ecclayout nand_oob_64 = {
  69         .eccbytes = 24,
  70         .eccpos = {
  71                    40, 41, 42, 43, 44, 45, 46, 47,
  72                    48, 49, 50, 51, 52, 53, 54, 55,
  73                    56, 57, 58, 59, 60, 61, 62, 63},
  74         .oobfree = {
  75                 {.offset = 2,
  76                  .length = 38} }
  77 };
  78
  79 static struct nand_ecclayout nand_oob_128 = {
  80         .eccbytes = 48,
  81         .eccpos = {
  82                    80, 81, 82, 83, 84, 85, 86, 87,
  83                    88, 89, 90, 91, 92, 93, 94, 95,
  84                    96, 97, 98, 99, 100, 101, 102, 103,
  85                    104, 105, 106, 107, 108, 109, 110, 111,
  86                    112, 113, 114, 115, 116, 117, 118, 119,
  87                    120, 121, 122, 123, 124, 125, 126, 127},
  88         .oobfree = {
  89                 {.offset = 2,
  90                  .length = 78} }
  91 };
  92
  93 static int nand_get_device(struct mtd_info *mtd, int new_state);
  94
  95 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  96                              struct mtd_oob_ops *ops);
  97
  98 /*
  99  * For devices which display every fart in the system on a separate LED. Is
 100  * compiled away when LED support is disabled.
 101  */
 102 DEFINE_LED_TRIGGER(nand_led_trigger);
 103
 104 static int check_offs_len(struct mtd_info *mtd,
 105                                         loff_t ofs, uint64_t len)
 106 {
 107         struct nand_chip *chip = mtd->priv;
 108         int ret = 0;
 109
 110         /* Start address must align on block boundary */
 111         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 112                 pr_debug("%s: unaligned address\n", __func__);
 113                 ret = -EINVAL;
 114         }
 115
 116         /* Length must align on block boundary */
 117         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 118                 pr_debug("%s: length not block aligned\n", __func__);
 119                 ret = -EINVAL;
 120         }
 121
 122         return ret;
 123 }
 124
 125 /**
 126  * nand_release_device - [GENERIC] release chip
 127  * @mtd: MTD device structure
 128  *
 129  * Release chip lock and wake up anyone waiting on the device.
 130  */
 131 static void nand_release_device(struct mtd_info *mtd)
 132 {
 133         struct nand_chip *chip = mtd->priv;
 134
 135         /* Release the controller and the chip */
 136         spin_lock(&chip->controller->lock);
 137         chip->controller->active = NULL;
 138         chip->state = FL_READY;
 139         wake_up(&chip->controller->wq);
 140         spin_unlock(&chip->controller->lock);
 141 }
 142
 143 /**
 144  * nand_read_byte - [DEFAULT] read one byte from the chip
 145  * @mtd: MTD device structure
 146  *
 147  * Default read function for 8bit buswidth
 148  */
 149 static uint8_t nand_read_byte(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152         return readb(chip->IO_ADDR_R);
 153 }
 154
 155 /**
 156  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 157  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 158  * @mtd: MTD device structure
 159  *
 160  * Default read function for 16bit buswidth with endianness conversion.
 161  *
 162  */
 163 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 164 {
 165         struct nand_chip *chip = mtd->priv;
 166         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 167 }
 168
 169 /**
 170  * nand_read_word - [DEFAULT] read one word from the chip
 171  * @mtd: MTD device structure
 172  *
 173  * Default read function for 16bit buswidth without endianness conversion.
 174  */
 175 static u16 nand_read_word(struct mtd_info *mtd)
 176 {
 177         struct nand_chip *chip = mtd->priv;
 178         return readw(chip->IO_ADDR_R);
 179 }
 180
 181 /**
 182  * nand_select_chip - [DEFAULT] control CE line
 183  * @mtd: MTD device structure
 184  * @chipnr: chipnumber to select, -1 for deselect
 185  *
 186  * Default select function for 1 chip devices.
 187  */
 188 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 189 {
 190         struct nand_chip *chip = mtd->priv;
 191
 192         switch (chipnr) {
 193         case -1:
 194                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 195                 break;
 196         case 0:
 197                 break;
 198
 199         default:
 200                 BUG();
 201         }
 202 }
 203
 204 /**
 205  * nand_write_buf - [DEFAULT] write buffer to chip
 206  * @mtd: MTD device structure
 207  * @buf: data buffer
 208  * @len: number of bytes to write
 209  *
 210  * Default write function for 8bit buswidth.
 211  */
 212 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 213 {
 214         int i;
 215         struct nand_chip *chip = mtd->priv;
 216
 217         for (i = 0; i < len; i++)
 218                 writeb(buf[i], chip->IO_ADDR_W);
 219 }
 220
 221 /**
 222  * nand_read_buf - [DEFAULT] read chip data into buffer
 223  * @mtd: MTD device structure
 224  * @buf: buffer to store date
 225  * @len: number of bytes to read
 226  *
 227  * Default read function for 8bit buswidth.
 228  */
 229 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 230 {
 231         int i;
 232         struct nand_chip *chip = mtd->priv;
 233
 234         for (i = 0; i < len; i++)
 235                 buf[i] = readb(chip->IO_ADDR_R);
 236 }
 237
 238 /**
 239  * nand_write_buf16 - [DEFAULT] write buffer to chip
 240  * @mtd: MTD device structure
 241  * @buf: data buffer
 242  * @len: number of bytes to write
 243  *
 244  * Default write function for 16bit buswidth.
 245  */
 246 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 247 {
 248         int i;
 249         struct nand_chip *chip = mtd->priv;
 250         u16 *p = (u16 *) buf;
 251         len >>= 1;
 252
 253         for (i = 0; i < len; i++)
 254                 writew(p[i], chip->IO_ADDR_W);
 255
 256 }
 257
 258 /**
 259  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 260  * @mtd: MTD device structure
 261  * @buf: buffer to store date
 262  * @len: number of bytes to read
 263  *
 264  * Default read function for 16bit buswidth.
 265  */
 266 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 267 {
 268         int i;
 269         struct nand_chip *chip = mtd->priv;
 270         u16 *p = (u16 *) buf;
 271         len >>= 1;
 272
 273         for (i = 0; i < len; i++)
 274                 p[i] = readw(chip->IO_ADDR_R);
 275 }
 276
 277 /**
 278  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 279  * @mtd: MTD device structure
 280  * @ofs: offset from device start
 281  * @getchip: 0, if the chip is already selected
 282  *
 283  * Check, if the block is bad.
 284  */
 285 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 286 {
 287         int page, chipnr, res = 0, i = 0;
 288         struct nand_chip *chip = mtd->priv;
 289         u16 bad;
 290
 291         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 292                 ofs += mtd->erasesize - mtd->writesize;
 293
 294         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 295
 296         if (getchip) {
 297                 chipnr = (int)(ofs >> chip->chip_shift);
 298
 299                 nand_get_device(mtd, FL_READING);
 300
 301                 /* Select the NAND device */
 302                 chip->select_chip(mtd, chipnr);
 303         }
 304
 305         do {
 306                 if (chip->options & NAND_BUSWIDTH_16) {
 307                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 308                                         chip->badblockpos & 0xFE, page);
 309                         bad = cpu_to_le16(chip->read_word(mtd));
 310                         if (chip->badblockpos & 0x1)
 311                                 bad >>= 8;
 312                         else
 313                                 bad &= 0xFF;
 314                 } else {
 315                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 316                                         page);
 317                         bad = chip->read_byte(mtd);
 318                 }
 319
 320                 if (likely(chip->badblockbits == 8))
 321                         res = bad != 0xFF;
 322                 else
 323                         res = hweight8(bad) < chip->badblockbits;
 324                 ofs += mtd->writesize;
 325                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 326                 i++;
 327         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 328
 329         if (getchip) {
 330                 chip->select_chip(mtd, -1);
 331                 nand_release_device(mtd);
 332         }
 333
 334         return res;
 335 }
 336
 337 /**
 338  * nand_default_block_markbad - [DEFAULT] mark a block bad
 339  * @mtd: MTD device structure
 340  * @ofs: offset from device start
 341  *
 342  * This is the default implementation, which can be overridden by a hardware
 343  * specific driver. We try operations in the following order, according to our
 344  * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
 345  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 346  *  (2) update in-memory BBT
 347  *  (3) write bad block marker to OOB area of affected block
 348  *  (4) update flash-based BBT
 349  * Note that we retain the first error encountered in (3) or (4), finish the
 350  * procedures, and dump the error in the end.
 351 */
 352 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 353 {
 354         struct nand_chip *chip = mtd->priv;
 355         uint8_t buf[2] = { 0, 0 };
 356         int block, res, ret = 0, i = 0;
 357         int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
 358
 359         if (write_oob) {
 360                 struct erase_info einfo;
 361
 362                 /* Attempt erase before marking OOB */
 363                 memset(&einfo, 0, sizeof(einfo));
 364                 einfo.mtd = mtd;
 365                 einfo.addr = ofs;
 366                 einfo.len = 1 << chip->phys_erase_shift;
 367                 nand_erase_nand(mtd, &einfo, 0);
 368         }
 369
 370         /* Get block number */
 371         block = (int)(ofs >> chip->bbt_erase_shift);
 372         /* Mark block bad in memory-based BBT */
 373         if (chip->bbt)
 374                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 375
 376         /* Write bad block marker to OOB */
 377         if (write_oob) {
 378                 struct mtd_oob_ops ops;
 379                 loff_t wr_ofs = ofs;
 380
 381                 nand_get_device(mtd, FL_WRITING);
 382
 383                 ops.datbuf = NULL;
 384                 ops.oobbuf = buf;
 385                 ops.ooboffs = chip->badblockpos;
 386                 if (chip->options & NAND_BUSWIDTH_16) {
 387                         ops.ooboffs &= ~0x01;
 388                         ops.len = ops.ooblen = 2;
 389                 } else {
 390                         ops.len = ops.ooblen = 1;
 391                 }
 392                 ops.mode = MTD_OPS_PLACE_OOB;
 393
 394                 /* Write to first/last page(s) if necessary */
 395                 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 396                         wr_ofs += mtd->erasesize - mtd->writesize;
 397                 do {
 398                         res = nand_do_write_oob(mtd, wr_ofs, &ops);
 399                         if (!ret)
 400                                 ret = res;
 401
 402                         i++;
 403                         wr_ofs += mtd->writesize;
 404                 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 405
 406                 nand_release_device(mtd);
 407         }
 408
 409         /* Update flash-based bad block table */
 410         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
 411                 res = nand_update_bbt(mtd, ofs);
 412                 if (!ret)
 413                         ret = res;
 414         }
 415
 416         if (!ret)
 417                 mtd->ecc_stats.badblocks++;
 418
 419         return ret;
 420 }
 421
 422 /**
 423  * nand_check_wp - [GENERIC] check if the chip is write protected
 424  * @mtd: MTD device structure
 425  *
 426  * Check, if the device is write protected. The function expects, that the
 427  * device is already selected.
 428  */
 429 static int nand_check_wp(struct mtd_info *mtd)
 430 {
 431         struct nand_chip *chip = mtd->priv;
 432
 433         /* Broken xD cards report WP despite being writable */
 434         if (chip->options & NAND_BROKEN_XD)
 435                 return 0;
 436
 437         /* Check the WP bit */
 438         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 439         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 440 }
 441
 442 /**
 443  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 444  * @mtd: MTD device structure
 445  * @ofs: offset from device start
 446  * @getchip: 0, if the chip is already selected
 447  * @allowbbt: 1, if its allowed to access the bbt area
 448  *
 449  * Check, if the block is bad. Either by reading the bad block table or
 450  * calling of the scan function.
 451  */
 452 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 453                                int allowbbt)
 454 {
 455         struct nand_chip *chip = mtd->priv;
 456
 457         if (!chip->bbt)
 458                 return chip->block_bad(mtd, ofs, getchip);
 459
 460         /* Return info from the table */
 461         return nand_isbad_bbt(mtd, ofs, allowbbt);
 462 }
 463
 464 /**
 465  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 466  * @mtd: MTD device structure
 467  * @timeo: Timeout
 468  *
 469  * Helper function for nand_wait_ready used when needing to wait in interrupt
 470  * context.
 471  */
 472 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 473 {
 474         struct nand_chip *chip = mtd->priv;
 475         int i;
 476
 477         /* Wait for the device to get ready */
 478         for (i = 0; i < timeo; i++) {
 479                 if (chip->dev_ready(mtd))
 480                         break;
 481                 touch_softlockup_watchdog();
 482                 mdelay(1);
 483         }
 484 }
 485
 486 /* Wait for the ready pin, after a command. The timeout is caught later. */
 487 void nand_wait_ready(struct mtd_info *mtd)
 488 {
 489         struct nand_chip *chip = mtd->priv;
 490         unsigned long timeo = jiffies + msecs_to_jiffies(20);
 491
 492         /* 400ms timeout */
 493         if (in_interrupt() || oops_in_progress)
 494                 return panic_nand_wait_ready(mtd, 400);
 495
 496         led_trigger_event(nand_led_trigger, LED_FULL);
 497         /* Wait until command is processed or timeout occurs */
 498         do {
 499                 if (chip->dev_ready(mtd))
 500                         break;
 501                 touch_softlockup_watchdog();
 502         } while (time_before(jiffies, timeo));
 503         led_trigger_event(nand_led_trigger, LED_OFF);
 504 }
 505 EXPORT_SYMBOL_GPL(nand_wait_ready);
 506
 507 /**
 508  * nand_command - [DEFAULT] Send command to NAND device
 509  * @mtd: MTD device structure
 510  * @command: the command to be sent
 511  * @column: the column address for this command, -1 if none
 512  * @page_addr: the page address for this command, -1 if none
 513  *
 514  * Send command to NAND device. This function is used for small page devices
 515  * (512 Bytes per page).
 516  */
 517 static void nand_command(struct mtd_info *mtd, unsigned int command,
 518                          int column, int page_addr)
 519 {
 520         register struct nand_chip *chip = mtd->priv;
 521         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 522
 523         /* Write out the command to the device */
 524         if (command == NAND_CMD_SEQIN) {
 525                 int readcmd;
 526
 527                 if (column >= mtd->writesize) {
 528                         /* OOB area */
 529                         column -= mtd->writesize;
 530                         readcmd = NAND_CMD_READOOB;
 531                 } else if (column < 256) {
 532                         /* First 256 bytes --> READ0 */
 533                         readcmd = NAND_CMD_READ0;
 534                 } else {
 535                         column -= 256;
 536                         readcmd = NAND_CMD_READ1;
 537                 }
 538                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 539                 ctrl &= ~NAND_CTRL_CHANGE;
 540         }
 541         chip->cmd_ctrl(mtd, command, ctrl);
 542
 543         /* Address cycle, when necessary */
 544         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 545         /* Serially input address */
 546         if (column != -1) {
 547                 /* Adjust columns for 16 bit buswidth */
 548                 if (chip->options & NAND_BUSWIDTH_16)
 549                         column >>= 1;
 550                 chip->cmd_ctrl(mtd, column, ctrl);
 551                 ctrl &= ~NAND_CTRL_CHANGE;
 552         }
 553         if (page_addr != -1) {
 554                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 555                 ctrl &= ~NAND_CTRL_CHANGE;
 556                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 557                 /* One more address cycle for devices > 32MiB */
 558                 if (chip->chipsize > (32 << 20))
 559                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 560         }
 561         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 562
 563         /*
 564          * Program and erase have their own busy handlers status and sequential
 565          * in needs no delay
 566          */
 567         switch (command) {
 568
 569         case NAND_CMD_PAGEPROG:
 570         case NAND_CMD_ERASE1:
 571         case NAND_CMD_ERASE2:
 572         case NAND_CMD_SEQIN:
 573         case NAND_CMD_STATUS:
 574                 return;
 575
 576         case NAND_CMD_RESET:
 577                 if (chip->dev_ready)
 578                         break;
 579                 udelay(chip->chip_delay);
 580                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 581                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 582                 chip->cmd_ctrl(mtd,
 583                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 584                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 585                                 ;
 586                 return;
 587
 588                 /* This applies to read commands */
 589         default:
 590                 /*
 591                  * If we don't have access to the busy pin, we apply the given
 592                  * command delay
 593                  */
 594                 if (!chip->dev_ready) {
 595                         udelay(chip->chip_delay);
 596                         return;
 597                 }
 598         }
 599         /*
 600          * Apply this short delay always to ensure that we do wait tWB in
 601          * any case on any machine.
 602          */
 603         ndelay(100);
 604
 605         nand_wait_ready(mtd);
 606 }
 607
 608 /**
 609  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 610  * @mtd: MTD device structure
 611  * @command: the command to be sent
 612  * @column: the column address for this command, -1 if none
 613  * @page_addr: the page address for this command, -1 if none
 614  *
 615  * Send command to NAND device. This is the version for the new large page
 616  * devices. We don't have the separate regions as we have in the small page
 617  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 618  */
 619 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 620                             int column, int page_addr)
 621 {
 622         register struct nand_chip *chip = mtd->priv;
 623
 624         /* Emulate NAND_CMD_READOOB */
 625         if (command == NAND_CMD_READOOB) {
 626                 column += mtd->writesize;
 627                 command = NAND_CMD_READ0;
 628         }
 629
 630         /* Command latch cycle */
 631         chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 632
 633         if (column != -1 || page_addr != -1) {
 634                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 635
 636                 /* Serially input address */
 637                 if (column != -1) {
 638                         /* Adjust columns for 16 bit buswidth */
 639                         if (chip->options & NAND_BUSWIDTH_16)
 640                                 column >>= 1;
 641                         chip->cmd_ctrl(mtd, column, ctrl);
 642                         ctrl &= ~NAND_CTRL_CHANGE;
 643                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 644                 }
 645                 if (page_addr != -1) {
 646                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 647                         chip->cmd_ctrl(mtd, page_addr >> 8,
 648                                        NAND_NCE | NAND_ALE);
 649                         /* One more address cycle for devices > 128MiB */
 650                         if (chip->chipsize > (128 << 20))
 651                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 652                                                NAND_NCE | NAND_ALE);
 653                 }
 654         }
 655         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 656
 657         /*
 658          * Program and erase have their own busy handlers status, sequential
 659          * in, and deplete1 need no delay.
 660          */
 661         switch (command) {
 662
 663         case NAND_CMD_CACHEDPROG:
 664         case NAND_CMD_PAGEPROG:
 665         case NAND_CMD_ERASE1:
 666         case NAND_CMD_ERASE2:
 667         case NAND_CMD_SEQIN:
 668         case NAND_CMD_RNDIN:
 669         case NAND_CMD_STATUS:
 670                 return;
 671
 672         case NAND_CMD_RESET:
 673                 if (chip->dev_ready)
 674                         break;
 675                 udelay(chip->chip_delay);
 676                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 677                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 678                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 679                                NAND_NCE | NAND_CTRL_CHANGE);
 680                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 681                                 ;
 682                 return;
 683
 684         case NAND_CMD_RNDOUT:
 685                 /* No ready / busy check necessary */
 686                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 687                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 688                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 689                                NAND_NCE | NAND_CTRL_CHANGE);
 690                 return;
 691
 692         case NAND_CMD_READ0:
 693                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 694                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 695                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 696                                NAND_NCE | NAND_CTRL_CHANGE);
 697
 698                 /* This applies to read commands */
 699         default:
 700                 /*
 701                  * If we don't have access to the busy pin, we apply the given
 702                  * command delay.
 703                  */
 704                 if (!chip->dev_ready) {
 705                         udelay(chip->chip_delay);
 706                         return;
 707                 }
 708         }
 709
 710         /*
 711          * Apply this short delay always to ensure that we do wait tWB in
 712          * any case on any machine.
 713          */
 714         ndelay(100);
 715
 716         nand_wait_ready(mtd);
 717 }
 718
 719 /**
 720  * panic_nand_get_device - [GENERIC] Get chip for selected access
 721  * @chip: the nand chip descriptor
 722  * @mtd: MTD device structure
 723  * @new_state: the state which is requested
 724  *
 725  * Used when in panic, no locks are taken.
 726  */
 727 static void panic_nand_get_device(struct nand_chip *chip,
 728                       struct mtd_info *mtd, int new_state)
 729 {
 730         /* Hardware controller shared among independent devices */
 731         chip->controller->active = chip;
 732         chip->state = new_state;
 733 }
 734
 735 /**
 736  * nand_get_device - [GENERIC] Get chip for selected access
 737  * @mtd: MTD device structure
 738  * @new_state: the state which is requested
 739  *
 740  * Get the device and lock it for exclusive access
 741  */
 742 static int
 743 nand_get_device(struct mtd_info *mtd, int new_state)
 744 {
 745         struct nand_chip *chip = mtd->priv;
 746         spinlock_t *lock = &chip->controller->lock;
 747         wait_queue_head_t *wq = &chip->controller->wq;
 748         DECLARE_WAITQUEUE(wait, current);
 749 retry:
 750         spin_lock(lock);
 751
 752         /* Hardware controller shared among independent devices */
 753         if (!chip->controller->active)
 754                 chip->controller->active = chip;
 755
 756         if (chip->controller->active == chip && chip->state == FL_READY) {
 757                 chip->state = new_state;
 758                 spin_unlock(lock);
 759                 return 0;
 760         }
 761         if (new_state == FL_PM_SUSPENDED) {
 762                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 763                         chip->state = FL_PM_SUSPENDED;
 764                         spin_unlock(lock);
 765                         return 0;
 766                 }
 767         }
 768         set_current_state(TASK_UNINTERRUPTIBLE);
 769         add_wait_queue(wq, &wait);
 770         spin_unlock(lock);
 771         schedule();
 772         remove_wait_queue(wq, &wait);
 773         goto retry;
 774 }
 775
 776 /**
 777  * panic_nand_wait - [GENERIC] wait until the command is done
 778  * @mtd: MTD device structure
 779  * @chip: NAND chip structure
 780  * @timeo: timeout
 781  *
 782  * Wait for command done. This is a helper function for nand_wait used when
 783  * we are in interrupt context. May happen when in panic and trying to write
 784  * an oops through mtdoops.
 785  */
 786 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 787                             unsigned long timeo)
 788 {
 789         int i;
 790         for (i = 0; i < timeo; i++) {
 791                 if (chip->dev_ready) {
 792                         if (chip->dev_ready(mtd))
 793                                 break;
 794                 } else {
 795                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 796                                 break;
 797                 }
 798                 mdelay(1);
 799         }
 800 }
 801
 802 /**
 803  * nand_wait - [DEFAULT] wait until the command is done
 804  * @mtd: MTD device structure
 805  * @chip: NAND chip structure
 806  *
 807  * Wait for command done. This applies to erase and program only. Erase can
 808  * take up to 400ms and program up to 20ms according to general NAND and
 809  * SmartMedia specs.
 810  */
 811 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 812 {
 813
 814         int status, state = chip->state;
 815         unsigned long timeo = (state == FL_ERASING ? 400 : 20);
 816
 817         led_trigger_event(nand_led_trigger, LED_FULL);
 818
 819         /*
 820          * Apply this short delay always to ensure that we do wait tWB in any
 821          * case on any machine.
 822          */
 823         ndelay(100);
 824
 825         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 826
 827         if (in_interrupt() || oops_in_progress)
 828                 panic_nand_wait(mtd, chip, timeo);
 829         else {
 830                 timeo = jiffies + msecs_to_jiffies(timeo);
 831                 while (time_before(jiffies, timeo)) {
 832                         if (chip->dev_ready) {
 833                                 if (chip->dev_ready(mtd))
 834                                         break;
 835                         } else {
 836                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 837                                         break;
 838                         }
 839                         cond_resched();
 840                 }
 841         }
 842         led_trigger_event(nand_led_trigger, LED_OFF);
 843
 844         status = (int)chip->read_byte(mtd);
 845         /* This can happen if in case of timeout or buggy dev_ready */
 846         WARN_ON(!(status & NAND_STATUS_READY));
 847         return status;
 848 }
 849
 850 /**
 851  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 852  * @mtd: mtd info
 853  * @ofs: offset to start unlock from
 854  * @len: length to unlock
 855  * @invert: when = 0, unlock the range of blocks within the lower and
 856  *                    upper boundary address
 857  *          when = 1, unlock the range of blocks outside the boundaries
 858  *                    of the lower and upper boundary address
 859  *
 860  * Returs unlock status.
 861  */
 862 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 863                                         uint64_t len, int invert)
 864 {
 865         int ret = 0;
 866         int status, page;
 867         struct nand_chip *chip = mtd->priv;
 868
 869         /* Submit address of first page to unlock */
 870         page = ofs >> chip->page_shift;
 871         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 872
 873         /* Submit address of last page to unlock */
 874         page = (ofs + len) >> chip->page_shift;
 875         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 876                                 (page | invert) & chip->pagemask);
 877
 878         /* Call wait ready function */
 879         status = chip->waitfunc(mtd, chip);
 880         /* See if device thinks it succeeded */
 881         if (status & NAND_STATUS_FAIL) {
 882                 pr_debug("%s: error status = 0x%08x\n",
 883                                         __func__, status);
 884                 ret = -EIO;
 885         }
 886
 887         return ret;
 888 }
 889
 890 /**
 891  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 892  * @mtd: mtd info
 893  * @ofs: offset to start unlock from
 894  * @len: length to unlock
 895  *
 896  * Returns unlock status.
 897  */
 898 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 899 {
 900         int ret = 0;
 901         int chipnr;
 902         struct nand_chip *chip = mtd->priv;
 903
 904         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 905                         __func__, (unsigned long long)ofs, len);
 906
 907         if (check_offs_len(mtd, ofs, len))
 908                 ret = -EINVAL;
 909
 910         /* Align to last block address if size addresses end of the device */
 911         if (ofs + len == mtd->size)
 912                 len -= mtd->erasesize;
 913
 914         nand_get_device(mtd, FL_UNLOCKING);
 915
 916         /* Shift to get chip number */
 917         chipnr = ofs >> chip->chip_shift;
 918
 919         chip->select_chip(mtd, chipnr);
 920
 921         /* Check, if it is write protected */
 922         if (nand_check_wp(mtd)) {
 923                 pr_debug("%s: device is write protected!\n",
 924                                         __func__);
 925                 ret = -EIO;
 926                 goto out;
 927         }
 928
 929         ret = __nand_unlock(mtd, ofs, len, 0);
 930
 931 out:
 932         chip->select_chip(mtd, -1);
 933         nand_release_device(mtd);
 934
 935         return ret;
 936 }
 937 EXPORT_SYMBOL(nand_unlock);
 938
 939 /**
 940  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 941  * @mtd: mtd info
 942  * @ofs: offset to start unlock from
 943  * @len: length to unlock
 944  *
 945  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 946  * have this feature, but it allows only to lock all blocks, not for specified
 947  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 948  * now.
 949  *
 950  * Returns lock status.
 951  */
 952 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 953 {
 954         int ret = 0;
 955         int chipnr, status, page;
 956         struct nand_chip *chip = mtd->priv;
 957
 958         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 959                         __func__, (unsigned long long)ofs, len);
 960
 961         if (check_offs_len(mtd, ofs, len))
 962                 ret = -EINVAL;
 963
 964         nand_get_device(mtd, FL_LOCKING);
 965
 966         /* Shift to get chip number */
 967         chipnr = ofs >> chip->chip_shift;
 968
 969         chip->select_chip(mtd, chipnr);
 970
 971         /* Check, if it is write protected */
 972         if (nand_check_wp(mtd)) {
 973                 pr_debug("%s: device is write protected!\n",
 974                                         __func__);
 975                 status = MTD_ERASE_FAILED;
 976                 ret = -EIO;
 977                 goto out;
 978         }
 979
 980         /* Submit address of first page to lock */
 981         page = ofs >> chip->page_shift;
 982         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
 983
 984         /* Call wait ready function */
 985         status = chip->waitfunc(mtd, chip);
 986         /* See if device thinks it succeeded */
 987         if (status & NAND_STATUS_FAIL) {
 988                 pr_debug("%s: error status = 0x%08x\n",
 989                                         __func__, status);
 990                 ret = -EIO;
 991                 goto out;
 992         }
 993
 994         ret = __nand_unlock(mtd, ofs, len, 0x1);
 995
 996 out:
 997         chip->select_chip(mtd, -1);
 998         nand_release_device(mtd);
 999
1000         return ret;
1001 }
1002 EXPORT_SYMBOL(nand_lock);
1003
1004 /**
1005  * nand_read_page_raw - [INTERN] read raw page data without ecc
1006  * @mtd: mtd info structure
1007  * @chip: nand chip info structure
1008  * @buf: buffer to store read data
1009  * @oob_required: caller requires OOB data read to chip->oob_poi
1010  * @page: page number to read
1011  *
1012  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1013  */
1014 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1015                               uint8_t *buf, int oob_required, int page)
1016 {
1017         chip->read_buf(mtd, buf, mtd->writesize);
1018         if (oob_required)
1019                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1020         return 0;
1021 }
1022
1023 /**
1024  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1025  * @mtd: mtd info structure
1026  * @chip: nand chip info structure
1027  * @buf: buffer to store read data
1028  * @oob_required: caller requires OOB data read to chip->oob_poi
1029  * @page: page number to read
1030  *
1031  * We need a special oob layout and handling even when OOB isn't used.
1032  */
1033 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1034                                        struct nand_chip *chip, uint8_t *buf,
1035                                        int oob_required, int page)
1036 {
1037         int eccsize = chip->ecc.size;
1038         int eccbytes = chip->ecc.bytes;
1039         uint8_t *oob = chip->oob_poi;
1040         int steps, size;
1041
1042         for (steps = chip->ecc.steps; steps > 0; steps--) {
1043                 chip->read_buf(mtd, buf, eccsize);
1044                 buf += eccsize;
1045
1046                 if (chip->ecc.prepad) {
1047                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1048                         oob += chip->ecc.prepad;
1049                 }
1050
1051                 chip->read_buf(mtd, oob, eccbytes);
1052                 oob += eccbytes;
1053
1054                 if (chip->ecc.postpad) {
1055                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1056                         oob += chip->ecc.postpad;
1057                 }
1058         }
1059
1060         size = mtd->oobsize - (oob - chip->oob_poi);
1061         if (size)
1062                 chip->read_buf(mtd, oob, size);
1063
1064         return 0;
1065 }
1066
1067 /**
1068  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1069  * @mtd: mtd info structure
1070  * @chip: nand chip info structure
1071  * @buf: buffer to store read data
1072  * @oob_required: caller requires OOB data read to chip->oob_poi
1073  * @page: page number to read
1074  */
1075 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1076                                 uint8_t *buf, int oob_required, int page)
1077 {
1078         int i, eccsize = chip->ecc.size;
1079         int eccbytes = chip->ecc.bytes;
1080         int eccsteps = chip->ecc.steps;
1081         uint8_t *p = buf;
1082         uint8_t *ecc_calc = chip->buffers->ecccalc;
1083         uint8_t *ecc_code = chip->buffers->ecccode;
1084         uint32_t *eccpos = chip->ecc.layout->eccpos;
1085         unsigned int max_bitflips = 0;
1086
1087         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1088
1089         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1090                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1091
1092         for (i = 0; i < chip->ecc.total; i++)
1093                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1094
1095         eccsteps = chip->ecc.steps;
1096         p = buf;
1097
1098         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1099                 int stat;
1100
1101                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1102                 if (stat < 0) {
1103                         mtd->ecc_stats.failed++;
1104                 } else {
1105                         mtd->ecc_stats.corrected += stat;
1106                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1107                 }
1108         }
1109         return max_bitflips;
1110 }
1111
1112 /**
1113  * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1114  * @mtd: mtd info structure
1115  * @chip: nand chip info structure
1116  * @data_offs: offset of requested data within the page
1117  * @readlen: data length
1118  * @bufpoi: buffer to store read data
1119  */
1120 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1121                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1122 {
1123         int start_step, end_step, num_steps;
1124         uint32_t *eccpos = chip->ecc.layout->eccpos;
1125         uint8_t *p;
1126         int data_col_addr, i, gaps = 0;
1127         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1128         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1129         int index = 0;
1130         unsigned int max_bitflips = 0;
1131
1132         /* Column address within the page aligned to ECC size (256bytes) */
1133         start_step = data_offs / chip->ecc.size;
1134         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1135         num_steps = end_step - start_step + 1;
1136
1137         /* Data size aligned to ECC ecc.size */
1138         datafrag_len = num_steps * chip->ecc.size;
1139         eccfrag_len = num_steps * chip->ecc.bytes;
1140
1141         data_col_addr = start_step * chip->ecc.size;
1142         /* If we read not a page aligned data */
1143         if (data_col_addr != 0)
1144                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1145
1146         p = bufpoi + data_col_addr;
1147         chip->read_buf(mtd, p, datafrag_len);
1148
1149         /* Calculate ECC */
1150         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1151                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1152
1153         /*
1154          * The performance is faster if we position offsets according to
1155          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1156          */
1157         for (i = 0; i < eccfrag_len - 1; i++) {
1158                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1159                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1160                         gaps = 1;
1161                         break;
1162                 }
1163         }
1164         if (gaps) {
1165                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1166                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1167         } else {
1168                 /*
1169                  * Send the command to read the particular ECC bytes take care
1170                  * about buswidth alignment in read_buf.
1171                  */
1172                 index = start_step * chip->ecc.bytes;
1173
1174                 aligned_pos = eccpos[index] & ~(busw - 1);
1175                 aligned_len = eccfrag_len;
1176                 if (eccpos[index] & (busw - 1))
1177                         aligned_len++;
1178                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1179                         aligned_len++;
1180
1181                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1182                                         mtd->writesize + aligned_pos, -1);
1183                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1184         }
1185
1186         for (i = 0; i < eccfrag_len; i++)
1187                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1188
1189         p = bufpoi + data_col_addr;
1190         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1191                 int stat;
1192
1193                 stat = chip->ecc.correct(mtd, p,
1194                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1195                 if (stat < 0) {
1196                         mtd->ecc_stats.failed++;
1197                 } else {
1198                         mtd->ecc_stats.corrected += stat;
1199                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1200                 }
1201         }
1202         return max_bitflips;
1203 }
1204
1205 /**
1206  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1207  * @mtd: mtd info structure
1208  * @chip: nand chip info structure
1209  * @buf: buffer to store read data
1210  * @oob_required: caller requires OOB data read to chip->oob_poi
1211  * @page: page number to read
1212  *
1213  * Not for syndrome calculating ECC controllers which need a special oob layout.
1214  */
1215 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1216                                 uint8_t *buf, int oob_required, int page)
1217 {
1218         int i, eccsize = chip->ecc.size;
1219         int eccbytes = chip->ecc.bytes;
1220         int eccsteps = chip->ecc.steps;
1221         uint8_t *p = buf;
1222         uint8_t *ecc_calc = chip->buffers->ecccalc;
1223         uint8_t *ecc_code = chip->buffers->ecccode;
1224         uint32_t *eccpos = chip->ecc.layout->eccpos;
1225         unsigned int max_bitflips = 0;
1226
1227         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1228                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1229                 chip->read_buf(mtd, p, eccsize);
1230                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1231         }
1232         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1233
1234         for (i = 0; i < chip->ecc.total; i++)
1235                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1236
1237         eccsteps = chip->ecc.steps;
1238         p = buf;
1239
1240         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1241                 int stat;
1242
1243                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1244                 if (stat < 0) {
1245                         mtd->ecc_stats.failed++;
1246                 } else {
1247                         mtd->ecc_stats.corrected += stat;
1248                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1249                 }
1250         }
1251         return max_bitflips;
1252 }
1253
1254 /**
1255  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1256  * @mtd: mtd info structure
1257  * @chip: nand chip info structure
1258  * @buf: buffer to store read data
1259  * @oob_required: caller requires OOB data read to chip->oob_poi
1260  * @page: page number to read
1261  *
1262  * Hardware ECC for large page chips, require OOB to be read first. For this
1263  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1264  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1265  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1266  * the data area, by overwriting the NAND manufacturer bad block markings.
1267  */
1268 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1269         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1270 {
1271         int i, eccsize = chip->ecc.size;
1272         int eccbytes = chip->ecc.bytes;
1273         int eccsteps = chip->ecc.steps;
1274         uint8_t *p = buf;
1275         uint8_t *ecc_code = chip->buffers->ecccode;
1276         uint32_t *eccpos = chip->ecc.layout->eccpos;
1277         uint8_t *ecc_calc = chip->buffers->ecccalc;
1278         unsigned int max_bitflips = 0;
1279
1280         /* Read the OOB area first */
1281         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1282         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1283         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1284
1285         for (i = 0; i < chip->ecc.total; i++)
1286                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1287
1288         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1289                 int stat;
1290
1291                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1292                 chip->read_buf(mtd, p, eccsize);
1293                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1294
1295                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1296                 if (stat < 0) {
1297                         mtd->ecc_stats.failed++;
1298                 } else {
1299                         mtd->ecc_stats.corrected += stat;
1300                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1301                 }
1302         }
1303         return max_bitflips;
1304 }
1305
1306 /**
1307  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1308  * @mtd: mtd info structure
1309  * @chip: nand chip info structure
1310  * @buf: buffer to store read data
1311  * @oob_required: caller requires OOB data read to chip->oob_poi
1312  * @page: page number to read
1313  *
1314  * The hw generator calculates the error syndrome automatically. Therefore we
1315  * need a special oob layout and handling.
1316  */
1317 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1318                                    uint8_t *buf, int oob_required, int page)
1319 {
1320         int i, eccsize = chip->ecc.size;
1321         int eccbytes = chip->ecc.bytes;
1322         int eccsteps = chip->ecc.steps;
1323         uint8_t *p = buf;
1324         uint8_t *oob = chip->oob_poi;
1325         unsigned int max_bitflips = 0;
1326
1327         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1328                 int stat;
1329
1330                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1331                 chip->read_buf(mtd, p, eccsize);
1332
1333                 if (chip->ecc.prepad) {
1334                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1335                         oob += chip->ecc.prepad;
1336                 }
1337
1338                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1339                 chip->read_buf(mtd, oob, eccbytes);
1340                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1341
1342                 if (stat < 0) {
1343                         mtd->ecc_stats.failed++;
1344                 } else {
1345                         mtd->ecc_stats.corrected += stat;
1346                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1347                 }
1348
1349                 oob += eccbytes;
1350
1351                 if (chip->ecc.postpad) {
1352                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1353                         oob += chip->ecc.postpad;
1354                 }
1355         }
1356
1357         /* Calculate remaining oob bytes */
1358         i = mtd->oobsize - (oob - chip->oob_poi);
1359         if (i)
1360                 chip->read_buf(mtd, oob, i);
1361
1362         return max_bitflips;
1363 }
1364
1365 /**
1366  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1367  * @chip: nand chip structure
1368  * @oob: oob destination address
1369  * @ops: oob ops structure
1370  * @len: size of oob to transfer
1371  */
1372 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1373                                   struct mtd_oob_ops *ops, size_t len)
1374 {
1375         switch (ops->mode) {
1376
1377         case MTD_OPS_PLACE_OOB:
1378         case MTD_OPS_RAW:
1379                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1380                 return oob + len;
1381
1382         case MTD_OPS_AUTO_OOB: {
1383                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1384                 uint32_t boffs = 0, roffs = ops->ooboffs;
1385                 size_t bytes = 0;
1386
1387                 for (; free->length && len; free++, len -= bytes) {
1388                         /* Read request not from offset 0? */
1389                         if (unlikely(roffs)) {
1390                                 if (roffs >= free->length) {
1391                                         roffs -= free->length;
1392                                         continue;
1393                                 }
1394                                 boffs = free->offset + roffs;
1395                                 bytes = min_t(size_t, len,
1396                                               (free->length - roffs));
1397                                 roffs = 0;
1398                         } else {
1399                                 bytes = min_t(size_t, len, free->length);
1400                                 boffs = free->offset;
1401                         }
1402                         memcpy(oob, chip->oob_poi + boffs, bytes);
1403                         oob += bytes;
1404                 }
1405                 return oob;
1406         }
1407         default:
1408                 BUG();
1409         }
1410         return NULL;
1411 }
1412
1413 /**
1414  * nand_do_read_ops - [INTERN] Read data with ECC
1415  * @mtd: MTD device structure
1416  * @from: offset to read from
1417  * @ops: oob ops structure
1418  *
1419  * Internal function. Called with chip held.
1420  */
1421 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1422                             struct mtd_oob_ops *ops)
1423 {
1424         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1425         struct nand_chip *chip = mtd->priv;
1426         struct mtd_ecc_stats stats;
1427         int ret = 0;
1428         uint32_t readlen = ops->len;
1429         uint32_t oobreadlen = ops->ooblen;
1430         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1431                 mtd->oobavail : mtd->oobsize;
1432
1433         uint8_t *bufpoi, *oob, *buf;
1434         unsigned int max_bitflips = 0;
1435
1436         stats = mtd->ecc_stats;
1437
1438         chipnr = (int)(from >> chip->chip_shift);
1439         chip->select_chip(mtd, chipnr);
1440
1441         realpage = (int)(from >> chip->page_shift);
1442         page = realpage & chip->pagemask;
1443
1444         col = (int)(from & (mtd->writesize - 1));
1445
1446         buf = ops->datbuf;
1447         oob = ops->oobbuf;
1448         oob_required = oob ? 1 : 0;
1449
1450         while (1) {
1451                 bytes = min(mtd->writesize - col, readlen);
1452                 aligned = (bytes == mtd->writesize);
1453
1454                 /* Is the current page in the buffer? */
1455                 if (realpage != chip->pagebuf || oob) {
1456                         bufpoi = aligned ? buf : chip->buffers->databuf;
1457
1458                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1459
1460                         /*
1461                          * Now read the page into the buffer.  Absent an error,
1462                          * the read methods return max bitflips per ecc step.
1463                          */
1464                         if (unlikely(ops->mode == MTD_OPS_RAW))
1465                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1466                                                               oob_required,
1467                                                               page);
1468                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1469                                  !oob)
1470                                 ret = chip->ecc.read_subpage(mtd, chip,
1471                                                         col, bytes, bufpoi);
1472                         else
1473                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1474                                                           oob_required, page);
1475                         if (ret < 0) {
1476                                 if (!aligned)
1477                                         /* Invalidate page cache */
1478                                         chip->pagebuf = -1;
1479                                 break;
1480                         }
1481
1482                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1483
1484                         /* Transfer not aligned data */
1485                         if (!aligned) {
1486                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1487                                     !(mtd->ecc_stats.failed - stats.failed) &&
1488                                     (ops->mode != MTD_OPS_RAW)) {
1489                                         chip->pagebuf = realpage;
1490                                         chip->pagebuf_bitflips = ret;
1491                                 } else {
1492                                         /* Invalidate page cache */
1493                                         chip->pagebuf = -1;
1494                                 }
1495                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1496                         }
1497
1498                         buf += bytes;
1499
1500                         if (unlikely(oob)) {
1501                                 int toread = min(oobreadlen, max_oobsize);
1502
1503                                 if (toread) {
1504                                         oob = nand_transfer_oob(chip,
1505                                                 oob, ops, toread);
1506                                         oobreadlen -= toread;
1507                                 }
1508                         }
1509
1510                         if (chip->options & NAND_NEED_READRDY) {
1511                                 /* Apply delay or wait for ready/busy pin */
1512                                 if (!chip->dev_ready)
1513                                         udelay(chip->chip_delay);
1514                                 else
1515                                         nand_wait_ready(mtd);
1516                         }
1517                 } else {
1518                         memcpy(buf, chip->buffers->databuf + col, bytes);
1519                         buf += bytes;
1520                         max_bitflips = max_t(unsigned int, max_bitflips,
1521                                              chip->pagebuf_bitflips);
1522                 }
1523
1524                 readlen -= bytes;
1525
1526                 if (!readlen)
1527                         break;
1528
1529                 /* For subsequent reads align to page boundary */
1530                 col = 0;
1531                 /* Increment page address */
1532                 realpage++;
1533
1534                 page = realpage & chip->pagemask;
1535                 /* Check, if we cross a chip boundary */
1536                 if (!page) {
1537                         chipnr++;
1538                         chip->select_chip(mtd, -1);
1539                         chip->select_chip(mtd, chipnr);
1540                 }
1541         }
1542         chip->select_chip(mtd, -1);
1543
1544         ops->retlen = ops->len - (size_t) readlen;
1545         if (oob)
1546                 ops->oobretlen = ops->ooblen - oobreadlen;
1547
1548         if (ret < 0)
1549                 return ret;
1550
1551         if (mtd->ecc_stats.failed - stats.failed)
1552                 return -EBADMSG;
1553
1554         return max_bitflips;
1555 }
1556
1557 /**
1558  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1559  * @mtd: MTD device structure
1560  * @from: offset to read from
1561  * @len: number of bytes to read
1562  * @retlen: pointer to variable to store the number of read bytes
1563  * @buf: the databuffer to put data
1564  *
1565  * Get hold of the chip and call nand_do_read.
1566  */
1567 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1568                      size_t *retlen, uint8_t *buf)
1569 {
1570         struct mtd_oob_ops ops;
1571         int ret;
1572
1573         nand_get_device(mtd, FL_READING);
1574         ops.len = len;
1575         ops.datbuf = buf;
1576         ops.oobbuf = NULL;
1577         ops.mode = MTD_OPS_PLACE_OOB;
1578         ret = nand_do_read_ops(mtd, from, &ops);
1579         *retlen = ops.retlen;
1580         nand_release_device(mtd);
1581         return ret;
1582 }
1583
1584 /**
1585  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1586  * @mtd: mtd info structure
1587  * @chip: nand chip info structure
1588  * @page: page number to read
1589  */
1590 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1591                              int page)
1592 {
1593         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1594         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1595         return 0;
1596 }
1597
1598 /**
1599  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1600  *                          with syndromes
1601  * @mtd: mtd info structure
1602  * @chip: nand chip info structure
1603  * @page: page number to read
1604  */
1605 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1606                                   int page)
1607 {
1608         uint8_t *buf = chip->oob_poi;
1609         int length = mtd->oobsize;
1610         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1611         int eccsize = chip->ecc.size;
1612         uint8_t *bufpoi = buf;
1613         int i, toread, sndrnd = 0, pos;
1614
1615         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1616         for (i = 0; i < chip->ecc.steps; i++) {
1617                 if (sndrnd) {
1618                         pos = eccsize + i * (eccsize + chunk);
1619                         if (mtd->writesize > 512)
1620                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1621                         else
1622                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1623                 } else
1624                         sndrnd = 1;
1625                 toread = min_t(int, length, chunk);
1626                 chip->read_buf(mtd, bufpoi, toread);
1627                 bufpoi += toread;
1628                 length -= toread;
1629         }
1630         if (length > 0)
1631                 chip->read_buf(mtd, bufpoi, length);
1632
1633         return 0;
1634 }
1635
1636 /**
1637  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1638  * @mtd: mtd info structure
1639  * @chip: nand chip info structure
1640  * @page: page number to write
1641  */
1642 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1643                               int page)
1644 {
1645         int status = 0;
1646         const uint8_t *buf = chip->oob_poi;
1647         int length = mtd->oobsize;
1648
1649         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1650         chip->write_buf(mtd, buf, length);
1651         /* Send command to program the OOB data */
1652         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1653
1654         status = chip->waitfunc(mtd, chip);
1655
1656         return status & NAND_STATUS_FAIL ? -EIO : 0;
1657 }
1658
1659 /**
1660  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1661  *                           with syndrome - only for large page flash
1662  * @mtd: mtd info structure
1663  * @chip: nand chip info structure
1664  * @page: page number to write
1665  */
1666 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1667                                    struct nand_chip *chip, int page)
1668 {
1669         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1670         int eccsize = chip->ecc.size, length = mtd->oobsize;
1671         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1672         const uint8_t *bufpoi = chip->oob_poi;
1673
1674         /*
1675          * data-ecc-data-ecc ... ecc-oob
1676          * or
1677          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1678          */
1679         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1680                 pos = steps * (eccsize + chunk);
1681                 steps = 0;
1682         } else
1683                 pos = eccsize;
1684
1685         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1686         for (i = 0; i < steps; i++) {
1687                 if (sndcmd) {
1688                         if (mtd->writesize <= 512) {
1689                                 uint32_t fill = 0xFFFFFFFF;
1690
1691                                 len = eccsize;
1692                                 while (len > 0) {
1693                                         int num = min_t(int, len, 4);
1694                                         chip->write_buf(mtd, (uint8_t *)&fill,
1695                                                         num);
1696                                         len -= num;
1697                                 }
1698                         } else {
1699                                 pos = eccsize + i * (eccsize + chunk);
1700                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1701                         }
1702                 } else
1703                         sndcmd = 1;
1704                 len = min_t(int, length, chunk);
1705                 chip->write_buf(mtd, bufpoi, len);
1706                 bufpoi += len;
1707                 length -= len;
1708         }
1709         if (length > 0)
1710                 chip->write_buf(mtd, bufpoi, length);
1711
1712         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1713         status = chip->waitfunc(mtd, chip);
1714
1715         return status & NAND_STATUS_FAIL ? -EIO : 0;
1716 }
1717
1718 /**
1719  * nand_do_read_oob - [INTERN] NAND read out-of-band
1720  * @mtd: MTD device structure
1721  * @from: offset to read from
1722  * @ops: oob operations description structure
1723  *
1724  * NAND read out-of-band data from the spare area.
1725  */
1726 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1727                             struct mtd_oob_ops *ops)
1728 {
1729         int page, realpage, chipnr;
1730         struct nand_chip *chip = mtd->priv;
1731         struct mtd_ecc_stats stats;
1732         int readlen = ops->ooblen;
1733         int len;
1734         uint8_t *buf = ops->oobbuf;
1735         int ret = 0;
1736
1737         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1738                         __func__, (unsigned long long)from, readlen);
1739
1740         stats = mtd->ecc_stats;
1741
1742         if (ops->mode == MTD_OPS_AUTO_OOB)
1743                 len = chip->ecc.layout->oobavail;
1744         else
1745                 len = mtd->oobsize;
1746
1747         if (unlikely(ops->ooboffs >= len)) {
1748                 pr_debug("%s: attempt to start read outside oob\n",
1749                                 __func__);
1750                 return -EINVAL;
1751         }
1752
1753         /* Do not allow reads past end of device */
1754         if (unlikely(from >= mtd->size ||
1755                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1756                                         (from >> chip->page_shift)) * len)) {
1757                 pr_debug("%s: attempt to read beyond end of device\n",
1758                                 __func__);
1759                 return -EINVAL;
1760         }
1761
1762         chipnr = (int)(from >> chip->chip_shift);
1763         chip->select_chip(mtd, chipnr);
1764
1765         /* Shift to get page */
1766         realpage = (int)(from >> chip->page_shift);
1767         page = realpage & chip->pagemask;
1768
1769         while (1) {
1770                 if (ops->mode == MTD_OPS_RAW)
1771                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1772                 else
1773                         ret = chip->ecc.read_oob(mtd, chip, page);
1774
1775                 if (ret < 0)
1776                         break;
1777
1778                 len = min(len, readlen);
1779                 buf = nand_transfer_oob(chip, buf, ops, len);
1780
1781                 if (chip->options & NAND_NEED_READRDY) {
1782                         /* Apply delay or wait for ready/busy pin */
1783                         if (!chip->dev_ready)
1784                                 udelay(chip->chip_delay);
1785                         else
1786                                 nand_wait_ready(mtd);
1787                 }
1788
1789                 readlen -= len;
1790                 if (!readlen)
1791                         break;
1792
1793                 /* Increment page address */
1794                 realpage++;
1795
1796                 page = realpage & chip->pagemask;
1797                 /* Check, if we cross a chip boundary */
1798                 if (!page) {
1799                         chipnr++;
1800                         chip->select_chip(mtd, -1);
1801                         chip->select_chip(mtd, chipnr);
1802                 }
1803         }
1804         chip->select_chip(mtd, -1);
1805
1806         ops->oobretlen = ops->ooblen - readlen;
1807
1808         if (ret < 0)
1809                 return ret;
1810
1811         if (mtd->ecc_stats.failed - stats.failed)
1812                 return -EBADMSG;
1813
1814         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1815 }
1816
1817 /**
1818  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1819  * @mtd: MTD device structure
1820  * @from: offset to read from
1821  * @ops: oob operation description structure
1822  *
1823  * NAND read data and/or out-of-band data.
1824  */
1825 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1826                          struct mtd_oob_ops *ops)
1827 {
1828         int ret = -ENOTSUPP;
1829
1830         ops->retlen = 0;
1831
1832         /* Do not allow reads past end of device */
1833         if (ops->datbuf && (from + ops->len) > mtd->size) {
1834                 pr_debug("%s: attempt to read beyond end of device\n",
1835                                 __func__);
1836                 return -EINVAL;
1837         }
1838
1839         nand_get_device(mtd, FL_READING);
1840
1841         switch (ops->mode) {
1842         case MTD_OPS_PLACE_OOB:
1843         case MTD_OPS_AUTO_OOB:
1844         case MTD_OPS_RAW:
1845                 break;
1846
1847         default:
1848                 goto out;
1849         }
1850
1851         if (!ops->datbuf)
1852                 ret = nand_do_read_oob(mtd, from, ops);
1853         else
1854                 ret = nand_do_read_ops(mtd, from, ops);
1855
1856 out:
1857         nand_release_device(mtd);
1858         return ret;
1859 }
1860
1861
1862 /**
1863  * nand_write_page_raw - [INTERN] raw page write function
1864  * @mtd: mtd info structure
1865  * @chip: nand chip info structure
1866  * @buf: data buffer
1867  * @oob_required: must write chip->oob_poi to OOB
1868  *
1869  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1870  */
1871 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1872                                 const uint8_t *buf, int oob_required)
1873 {
1874         chip->write_buf(mtd, buf, mtd->writesize);
1875         if (oob_required)
1876                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1877
1878         return 0;
1879 }
1880
1881 /**
1882  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1883  * @mtd: mtd info structure
1884  * @chip: nand chip info structure
1885  * @buf: data buffer
1886  * @oob_required: must write chip->oob_poi to OOB
1887  *
1888  * We need a special oob layout and handling even when ECC isn't checked.
1889  */
1890 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1891                                         struct nand_chip *chip,
1892                                         const uint8_t *buf, int oob_required)
1893 {
1894         int eccsize = chip->ecc.size;
1895         int eccbytes = chip->ecc.bytes;
1896         uint8_t *oob = chip->oob_poi;
1897         int steps, size;
1898
1899         for (steps = chip->ecc.steps; steps > 0; steps--) {
1900                 chip->write_buf(mtd, buf, eccsize);
1901                 buf += eccsize;
1902
1903                 if (chip->ecc.prepad) {
1904                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1905                         oob += chip->ecc.prepad;
1906                 }
1907
1908                 chip->read_buf(mtd, oob, eccbytes);
1909                 oob += eccbytes;
1910
1911                 if (chip->ecc.postpad) {
1912                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1913                         oob += chip->ecc.postpad;
1914                 }
1915         }
1916
1917         size = mtd->oobsize - (oob - chip->oob_poi);
1918         if (size)
1919                 chip->write_buf(mtd, oob, size);
1920
1921         return 0;
1922 }
1923 /**
1924  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1925  * @mtd: mtd info structure
1926  * @chip: nand chip info structure
1927  * @buf: data buffer
1928  * @oob_required: must write chip->oob_poi to OOB
1929  */
1930 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1931                                   const uint8_t *buf, int oob_required)
1932 {
1933         int i, eccsize = chip->ecc.size;
1934         int eccbytes = chip->ecc.bytes;
1935         int eccsteps = chip->ecc.steps;
1936         uint8_t *ecc_calc = chip->buffers->ecccalc;
1937         const uint8_t *p = buf;
1938         uint32_t *eccpos = chip->ecc.layout->eccpos;
1939
1940         /* Software ECC calculation */
1941         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1942                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1943
1944         for (i = 0; i < chip->ecc.total; i++)
1945                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1946
1947         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1948 }
1949
1950 /**
1951  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1952  * @mtd: mtd info structure
1953  * @chip: nand chip info structure
1954  * @buf: data buffer
1955  * @oob_required: must write chip->oob_poi to OOB
1956  */
1957 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1958                                   const uint8_t *buf, int oob_required)
1959 {
1960         int i, eccsize = chip->ecc.size;
1961         int eccbytes = chip->ecc.bytes;
1962         int eccsteps = chip->ecc.steps;
1963         uint8_t *ecc_calc = chip->buffers->ecccalc;
1964         const uint8_t *p = buf;
1965         uint32_t *eccpos = chip->ecc.layout->eccpos;
1966
1967         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1968                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1969                 chip->write_buf(mtd, p, eccsize);
1970                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1971         }
1972
1973         for (i = 0; i < chip->ecc.total; i++)
1974                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1975
1976         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1977
1978         return 0;
1979 }
1980
1981
1982 /**
1983  * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
1984  * @mtd:        mtd info structure
1985  * @chip:       nand chip info structure
1986  * @column:     column address of subpage within the page
1987  * @data_len:   data length
1988  * @oob_required: must write chip->oob_poi to OOB
1989  */
1990 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
1991                                 struct nand_chip *chip, uint32_t offset,
1992                                 uint32_t data_len, const uint8_t *data_buf,
1993                                 int oob_required)
1994 {
1995         uint8_t *oob_buf  = chip->oob_poi;
1996         uint8_t *ecc_calc = chip->buffers->ecccalc;
1997         int ecc_size      = chip->ecc.size;
1998         int ecc_bytes     = chip->ecc.bytes;
1999         int ecc_steps     = chip->ecc.steps;
2000         uint32_t *eccpos  = chip->ecc.layout->eccpos;
2001         uint32_t start_step = offset / ecc_size;
2002         uint32_t end_step   = (offset + data_len - 1) / ecc_size;
2003         int oob_bytes       = mtd->oobsize / ecc_steps;
2004         int step, i;
2005
2006         for (step = 0; step < ecc_steps; step++) {
2007                 /* configure controller for WRITE access */
2008                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2009
2010                 /* write data (untouched subpages already masked by 0xFF) */
2011                 chip->write_buf(mtd, data_buf, ecc_size);
2012
2013                 /* mask ECC of un-touched subpages by padding 0xFF */
2014                 if ((step < start_step) || (step > end_step))
2015                         memset(ecc_calc, 0xff, ecc_bytes);
2016                 else
2017                         chip->ecc.calculate(mtd, data_buf, ecc_calc);
2018
2019                 /* mask OOB of un-touched subpages by padding 0xFF */
2020                 /* if oob_required, preserve OOB metadata of written subpage */
2021                 if (!oob_required || (step < start_step) || (step > end_step))
2022                         memset(oob_buf, 0xff, oob_bytes);
2023
2024                 data_buf += ecc_size;
2025                 ecc_calc += ecc_bytes;
2026                 oob_buf  += oob_bytes;
2027         }
2028
2029         /* copy calculated ECC for whole page to chip->buffer->oob */
2030         /* this include masked-value(0xFF) for unwritten subpages */
2031         ecc_calc = chip->buffers->ecccalc;
2032         for (i = 0; i < chip->ecc.total; i++)
2033                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2034
2035         /* write OOB buffer to NAND device */
2036         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2037
2038         return 0;
2039 }
2040
2041
2042 /**
2043  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2044  * @mtd: mtd info structure
2045  * @chip: nand chip info structure
2046  * @buf: data buffer
2047  * @oob_required: must write chip->oob_poi to OOB
2048  *
2049  * The hw generator calculates the error syndrome automatically. Therefore we
2050  * need a special oob layout and handling.
2051  */
2052 static int nand_write_page_syndrome(struct mtd_info *mtd,
2053                                     struct nand_chip *chip,
2054                                     const uint8_t *buf, int oob_required)
2055 {
2056         int i, eccsize = chip->ecc.size;
2057         int eccbytes = chip->ecc.bytes;
2058         int eccsteps = chip->ecc.steps;
2059         const uint8_t *p = buf;
2060         uint8_t *oob = chip->oob_poi;
2061
2062         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2063
2064                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2065                 chip->write_buf(mtd, p, eccsize);
2066
2067                 if (chip->ecc.prepad) {
2068                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2069                         oob += chip->ecc.prepad;
2070                 }
2071
2072                 chip->ecc.calculate(mtd, p, oob);
2073                 chip->write_buf(mtd, oob, eccbytes);
2074                 oob += eccbytes;
2075
2076                 if (chip->ecc.postpad) {
2077                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2078                         oob += chip->ecc.postpad;
2079                 }
2080         }
2081
2082         /* Calculate remaining oob bytes */
2083         i = mtd->oobsize - (oob - chip->oob_poi);
2084         if (i)
2085                 chip->write_buf(mtd, oob, i);
2086
2087         return 0;
2088 }
2089
2090 /**
2091  * nand_write_page - [REPLACEABLE] write one page
2092  * @mtd: MTD device structure
2093  * @chip: NAND chip descriptor
2094  * @offset: address offset within the page
2095  * @data_len: length of actual data to be written
2096  * @buf: the data to write
2097  * @oob_required: must write chip->oob_poi to OOB
2098  * @page: page number to write
2099  * @cached: cached programming
2100  * @raw: use _raw version of write_page
2101  */
2102 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2103                 uint32_t offset, int data_len, const uint8_t *buf,
2104                 int oob_required, int page, int cached, int raw)
2105 {
2106         int status, subpage;
2107
2108         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2109                 chip->ecc.write_subpage)
2110                 subpage = offset || (data_len < mtd->writesize);
2111         else
2112                 subpage = 0;
2113
2114         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2115
2116         if (unlikely(raw))
2117                 status = chip->ecc.write_page_raw(mtd, chip, buf,
2118                                                         oob_required);
2119         else if (subpage)
2120                 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2121                                                          buf, oob_required);
2122         else
2123                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2124
2125         if (status < 0)
2126                 return status;
2127
2128         /*
2129          * Cached progamming disabled for now. Not sure if it's worth the
2130          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2131          */
2132         cached = 0;
2133
2134         if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2135
2136                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2137                 status = chip->waitfunc(mtd, chip);
2138                 /*
2139                  * See if operation failed and additional status checks are
2140                  * available.
2141                  */
2142                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2143                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2144                                                page);
2145
2146                 if (status & NAND_STATUS_FAIL)
2147                         return -EIO;
2148         } else {
2149                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2150                 status = chip->waitfunc(mtd, chip);
2151         }
2152
2153         return 0;
2154 }
2155
2156 /**
2157  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2158  * @mtd: MTD device structure
2159  * @oob: oob data buffer
2160  * @len: oob data write length
2161  * @ops: oob ops structure
2162  */
2163 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2164                               struct mtd_oob_ops *ops)
2165 {
2166         struct nand_chip *chip = mtd->priv;
2167
2168         /*
2169          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2170          * data from a previous OOB read.
2171          */
2172         memset(chip->oob_poi, 0xff, mtd->oobsize);
2173
2174         switch (ops->mode) {
2175
2176         case MTD_OPS_PLACE_OOB:
2177         case MTD_OPS_RAW:
2178                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2179                 return oob + len;
2180
2181         case MTD_OPS_AUTO_OOB: {
2182                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2183                 uint32_t boffs = 0, woffs = ops->ooboffs;
2184                 size_t bytes = 0;
2185
2186                 for (; free->length && len; free++, len -= bytes) {
2187                         /* Write request not from offset 0? */
2188                         if (unlikely(woffs)) {
2189                                 if (woffs >= free->length) {
2190                                         woffs -= free->length;
2191                                         continue;
2192                                 }
2193                                 boffs = free->offset + woffs;
2194                                 bytes = min_t(size_t, len,
2195                                               (free->length - woffs));
2196                                 woffs = 0;
2197                         } else {
2198                                 bytes = min_t(size_t, len, free->length);
2199                                 boffs = free->offset;
2200                         }
2201                         memcpy(chip->oob_poi + boffs, oob, bytes);
2202                         oob += bytes;
2203                 }
2204                 return oob;
2205         }
2206         default:
2207                 BUG();
2208         }
2209         return NULL;
2210 }
2211
2212 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2213
2214 /**
2215  * nand_do_write_ops - [INTERN] NAND write with ECC
2216  * @mtd: MTD device structure
2217  * @to: offset to write to
2218  * @ops: oob operations description structure
2219  *
2220  * NAND write with ECC.
2221  */
2222 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2223                              struct mtd_oob_ops *ops)
2224 {
2225         int chipnr, realpage, page, blockmask, column;
2226         struct nand_chip *chip = mtd->priv;
2227         uint32_t writelen = ops->len;
2228
2229         uint32_t oobwritelen = ops->ooblen;
2230         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2231                                 mtd->oobavail : mtd->oobsize;
2232
2233         uint8_t *oob = ops->oobbuf;
2234         uint8_t *buf = ops->datbuf;
2235         int ret;
2236         int oob_required = oob ? 1 : 0;
2237
2238         ops->retlen = 0;
2239         if (!writelen)
2240                 return 0;
2241
2242         /* Reject writes, which are not page aligned */
2243         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2244                 pr_notice("%s: attempt to write non page aligned data\n",
2245                            __func__);
2246                 return -EINVAL;
2247         }
2248
2249         column = to & (mtd->writesize - 1);
2250
2251         chipnr = (int)(to >> chip->chip_shift);
2252         chip->select_chip(mtd, chipnr);
2253
2254         /* Check, if it is write protected */
2255         if (nand_check_wp(mtd)) {
2256                 ret = -EIO;
2257                 goto err_out;
2258         }
2259
2260         realpage = (int)(to >> chip->page_shift);
2261         page = realpage & chip->pagemask;
2262         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2263
2264         /* Invalidate the page cache, when we write to the cached page */
2265         if (to <= (chip->pagebuf << chip->page_shift) &&
2266             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2267                 chip->pagebuf = -1;
2268
2269         /* Don't allow multipage oob writes with offset */
2270         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2271                 ret = -EINVAL;
2272                 goto err_out;
2273         }
2274
2275         while (1) {
2276                 int bytes = mtd->writesize;
2277                 int cached = writelen > bytes && page != blockmask;
2278                 uint8_t *wbuf = buf;
2279
2280                 /* Partial page write? */
2281                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2282                         cached = 0;
2283                         bytes = min_t(int, bytes - column, (int) writelen);
2284                         chip->pagebuf = -1;
2285                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2286                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2287                         wbuf = chip->buffers->databuf;
2288                 }
2289
2290                 if (unlikely(oob)) {
2291                         size_t len = min(oobwritelen, oobmaxlen);
2292                         oob = nand_fill_oob(mtd, oob, len, ops);
2293                         oobwritelen -= len;
2294                 } else {
2295                         /* We still need to erase leftover OOB data */
2296                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2297                 }
2298                 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2299                                         oob_required, page, cached,
2300                                         (ops->mode == MTD_OPS_RAW));
2301                 if (ret)
2302                         break;
2303
2304                 writelen -= bytes;
2305                 if (!writelen)
2306                         break;
2307
2308                 column = 0;
2309                 buf += bytes;
2310                 realpage++;
2311
2312                 page = realpage & chip->pagemask;
2313                 /* Check, if we cross a chip boundary */
2314                 if (!page) {
2315                         chipnr++;
2316                         chip->select_chip(mtd, -1);
2317                         chip->select_chip(mtd, chipnr);
2318                 }
2319         }
2320
2321         ops->retlen = ops->len - writelen;
2322         if (unlikely(oob))
2323                 ops->oobretlen = ops->ooblen;
2324
2325 err_out:
2326         chip->select_chip(mtd, -1);
2327         return ret;
2328 }
2329
2330 /**
2331  * panic_nand_write - [MTD Interface] NAND write with ECC
2332  * @mtd: MTD device structure
2333  * @to: offset to write to
2334  * @len: number of bytes to write
2335  * @retlen: pointer to variable to store the number of written bytes
2336  * @buf: the data to write
2337  *
2338  * NAND write with ECC. Used when performing writes in interrupt context, this
2339  * may for example be called by mtdoops when writing an oops while in panic.
2340  */
2341 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2342                             size_t *retlen, const uint8_t *buf)
2343 {
2344         struct nand_chip *chip = mtd->priv;
2345         struct mtd_oob_ops ops;
2346         int ret;
2347
2348         /* Wait for the device to get ready */
2349         panic_nand_wait(mtd, chip, 400);
2350
2351         /* Grab the device */
2352         panic_nand_get_device(chip, mtd, FL_WRITING);
2353
2354         ops.len = len;
2355         ops.datbuf = (uint8_t *)buf;
2356         ops.oobbuf = NULL;
2357         ops.mode = MTD_OPS_PLACE_OOB;
2358
2359         ret = nand_do_write_ops(mtd, to, &ops);
2360
2361         *retlen = ops.retlen;
2362         return ret;
2363 }
2364
2365 /**
2366  * nand_write - [MTD Interface] NAND write with ECC
2367  * @mtd: MTD device structure
2368  * @to: offset to write to
2369  * @len: number of bytes to write
2370  * @retlen: pointer to variable to store the number of written bytes
2371  * @buf: the data to write
2372  *
2373  * NAND write with ECC.
2374  */
2375 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2376                           size_t *retlen, const uint8_t *buf)
2377 {
2378         struct mtd_oob_ops ops;
2379         int ret;
2380
2381         nand_get_device(mtd, FL_WRITING);
2382         ops.len = len;
2383         ops.datbuf = (uint8_t *)buf;
2384         ops.oobbuf = NULL;
2385         ops.mode = MTD_OPS_PLACE_OOB;
2386         ret = nand_do_write_ops(mtd, to, &ops);
2387         *retlen = ops.retlen;
2388         nand_release_device(mtd);
2389         return ret;
2390 }
2391
2392 /**
2393  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2394  * @mtd: MTD device structure
2395  * @to: offset to write to
2396  * @ops: oob operation description structure
2397  *
2398  * NAND write out-of-band.
2399  */
2400 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2401                              struct mtd_oob_ops *ops)
2402 {
2403         int chipnr, page, status, len;
2404         struct nand_chip *chip = mtd->priv;
2405
2406         pr_debug("%s: to = 0x%08x, len = %i\n",
2407                          __func__, (unsigned int)to, (int)ops->ooblen);
2408
2409         if (ops->mode == MTD_OPS_AUTO_OOB)
2410                 len = chip->ecc.layout->oobavail;
2411         else
2412                 len = mtd->oobsize;
2413
2414         /* Do not allow write past end of page */
2415         if ((ops->ooboffs + ops->ooblen) > len) {
2416                 pr_debug("%s: attempt to write past end of page\n",
2417                                 __func__);
2418                 return -EINVAL;
2419         }
2420
2421         if (unlikely(ops->ooboffs >= len)) {
2422                 pr_debug("%s: attempt to start write outside oob\n",
2423                                 __func__);
2424                 return -EINVAL;
2425         }
2426
2427         /* Do not allow write past end of device */
2428         if (unlikely(to >= mtd->size ||
2429                      ops->ooboffs + ops->ooblen >
2430                         ((mtd->size >> chip->page_shift) -
2431                          (to >> chip->page_shift)) * len)) {
2432                 pr_debug("%s: attempt to write beyond end of device\n",
2433                                 __func__);
2434                 return -EINVAL;
2435         }
2436
2437         chipnr = (int)(to >> chip->chip_shift);
2438         chip->select_chip(mtd, chipnr);
2439
2440         /* Shift to get page */
2441         page = (int)(to >> chip->page_shift);
2442
2443         /*
2444          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2445          * of my DiskOnChip 2000 test units) will clear the whole data page too
2446          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2447          * it in the doc2000 driver in August 1999.  dwmw2.
2448          */
2449         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2450
2451         /* Check, if it is write protected */
2452         if (nand_check_wp(mtd)) {
2453                 chip->select_chip(mtd, -1);
2454                 return -EROFS;
2455         }
2456
2457         /* Invalidate the page cache, if we write to the cached page */
2458         if (page == chip->pagebuf)
2459                 chip->pagebuf = -1;
2460
2461         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2462
2463         if (ops->mode == MTD_OPS_RAW)
2464                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2465         else
2466                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2467
2468         chip->select_chip(mtd, -1);
2469
2470         if (status)
2471                 return status;
2472
2473         ops->oobretlen = ops->ooblen;
2474
2475         return 0;
2476 }
2477
2478 /**
2479  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2480  * @mtd: MTD device structure
2481  * @to: offset to write to
2482  * @ops: oob operation description structure
2483  */
2484 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2485                           struct mtd_oob_ops *ops)
2486 {
2487         int ret = -ENOTSUPP;
2488
2489         ops->retlen = 0;
2490
2491         /* Do not allow writes past end of device */
2492         if (ops->datbuf && (to + ops->len) > mtd->size) {
2493                 pr_debug("%s: attempt to write beyond end of device\n",
2494                                 __func__);
2495                 return -EINVAL;
2496         }
2497
2498         nand_get_device(mtd, FL_WRITING);
2499
2500         switch (ops->mode) {
2501         case MTD_OPS_PLACE_OOB:
2502         case MTD_OPS_AUTO_OOB:
2503         case MTD_OPS_RAW:
2504                 break;
2505
2506         default:
2507                 goto out;
2508         }
2509
2510         if (!ops->datbuf)
2511                 ret = nand_do_write_oob(mtd, to, ops);
2512         else
2513                 ret = nand_do_write_ops(mtd, to, ops);
2514
2515 out:
2516         nand_release_device(mtd);
2517         return ret;
2518 }
2519
2520 /**
2521  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2522  * @mtd: MTD device structure
2523  * @page: the page address of the block which will be erased
2524  *
2525  * Standard erase command for NAND chips.
2526  */
2527 static void single_erase_cmd(struct mtd_info *mtd, int page)
2528 {
2529         struct nand_chip *chip = mtd->priv;
2530         /* Send commands to erase a block */
2531         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2532         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2533 }
2534
2535 /**
2536  * nand_erase - [MTD Interface] erase block(s)
2537  * @mtd: MTD device structure
2538  * @instr: erase instruction
2539  *
2540  * Erase one ore more blocks.
2541  */
2542 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2543 {
2544         return nand_erase_nand(mtd, instr, 0);
2545 }
2546
2547 /**
2548  * nand_erase_nand - [INTERN] erase block(s)
2549  * @mtd: MTD device structure
2550  * @instr: erase instruction
2551  * @allowbbt: allow erasing the bbt area
2552  *
2553  * Erase one ore more blocks.
2554  */
2555 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2556                     int allowbbt)
2557 {
2558         int page, status, pages_per_block, ret, chipnr;
2559         struct nand_chip *chip = mtd->priv;
2560         loff_t len;
2561
2562         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2563                         __func__, (unsigned long long)instr->addr,
2564                         (unsigned long long)instr->len);
2565
2566         if (check_offs_len(mtd, instr->addr, instr->len))
2567                 return -EINVAL;
2568
2569         /* Grab the lock and see if the device is available */
2570         nand_get_device(mtd, FL_ERASING);
2571
2572         /* Shift to get first page */
2573         page = (int)(instr->addr >> chip->page_shift);
2574         chipnr = (int)(instr->addr >> chip->chip_shift);
2575
2576         /* Calculate pages in each block */
2577         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2578
2579         /* Select the NAND device */
2580         chip->select_chip(mtd, chipnr);
2581
2582         /* Check, if it is write protected */
2583         if (nand_check_wp(mtd)) {
2584                 pr_debug("%s: device is write protected!\n",
2585                                 __func__);
2586                 instr->state = MTD_ERASE_FAILED;
2587                 goto erase_exit;
2588         }
2589
2590         /* Loop through the pages */
2591         len = instr->len;
2592
2593         instr->state = MTD_ERASING;
2594
2595         while (len) {
2596                 /* Check if we have a bad block, we do not erase bad blocks! */
2597                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2598                                         chip->page_shift, 0, allowbbt)) {
2599                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2600                                     __func__, page);
2601                         instr->state = MTD_ERASE_FAILED;
2602                         goto erase_exit;
2603                 }
2604
2605                 /*
2606                  * Invalidate the page cache, if we erase the block which
2607                  * contains the current cached page.
2608                  */
2609                 if (page <= chip->pagebuf && chip->pagebuf <
2610                     (page + pages_per_block))
2611                         chip->pagebuf = -1;
2612
2613                 chip->erase_cmd(mtd, page & chip->pagemask);
2614
2615                 status = chip->waitfunc(mtd, chip);
2616
2617                 /*
2618                  * See if operation failed and additional status checks are
2619                  * available
2620                  */
2621                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2622                         status = chip->errstat(mtd, chip, FL_ERASING,
2623                                                status, page);
2624
2625                 /* See if block erase succeeded */
2626                 if (status & NAND_STATUS_FAIL) {
2627                         pr_debug("%s: failed erase, page 0x%08x\n",
2628                                         __func__, page);
2629                         instr->state = MTD_ERASE_FAILED;
2630                         instr->fail_addr =
2631                                 ((loff_t)page << chip->page_shift);
2632                         goto erase_exit;
2633                 }
2634
2635                 /* Increment page address and decrement length */
2636                 len -= (1 << chip->phys_erase_shift);
2637                 page += pages_per_block;
2638
2639                 /* Check, if we cross a chip boundary */
2640                 if (len && !(page & chip->pagemask)) {
2641                         chipnr++;
2642                         chip->select_chip(mtd, -1);
2643                         chip->select_chip(mtd, chipnr);
2644                 }
2645         }
2646         instr->state = MTD_ERASE_DONE;
2647
2648 erase_exit:
2649
2650         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2651
2652         /* Deselect and wake up anyone waiting on the device */
2653         chip->select_chip(mtd, -1);
2654         nand_release_device(mtd);
2655
2656         /* Do call back function */
2657         if (!ret)
2658                 mtd_erase_callback(instr);
2659
2660         /* Return more or less happy */
2661         return ret;
2662 }
2663
2664 /**
2665  * nand_sync - [MTD Interface] sync
2666  * @mtd: MTD device structure
2667  *
2668  * Sync is actually a wait for chip ready function.
2669  */
2670 static void nand_sync(struct mtd_info *mtd)
2671 {
2672         pr_debug("%s: called\n", __func__);
2673
2674         /* Grab the lock and see if the device is available */
2675         nand_get_device(mtd, FL_SYNCING);
2676         /* Release it and go back */
2677         nand_release_device(mtd);
2678 }
2679
2680 /**
2681  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2682  * @mtd: MTD device structure
2683  * @offs: offset relative to mtd start
2684  */
2685 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2686 {
2687         return nand_block_checkbad(mtd, offs, 1, 0);
2688 }
2689
2690 /**
2691  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2692  * @mtd: MTD device structure
2693  * @ofs: offset relative to mtd start
2694  */
2695 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2696 {
2697         struct nand_chip *chip = mtd->priv;
2698         int ret;
2699
2700         ret = nand_block_isbad(mtd, ofs);
2701         if (ret) {
2702                 /* If it was bad already, return success and do nothing */
2703                 if (ret > 0)
2704                         return 0;
2705                 return ret;
2706         }
2707
2708         return chip->block_markbad(mtd, ofs);
2709 }
2710
2711 /**
2712  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2713  * @mtd: MTD device structure
2714  * @chip: nand chip info structure
2715  * @addr: feature address.
2716  * @subfeature_param: the subfeature parameters, a four bytes array.
2717  */
2718 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2719                         int addr, uint8_t *subfeature_param)
2720 {
2721         int status;
2722
2723         if (!chip->onfi_version)
2724                 return -EINVAL;
2725
2726         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2727         chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2728         status = chip->waitfunc(mtd, chip);
2729         if (status & NAND_STATUS_FAIL)
2730                 return -EIO;
2731         return 0;
2732 }
2733
2734 /**
2735  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2736  * @mtd: MTD device structure
2737  * @chip: nand chip info structure
2738  * @addr: feature address.
2739  * @subfeature_param: the subfeature parameters, a four bytes array.
2740  */
2741 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2742                         int addr, uint8_t *subfeature_param)
2743 {
2744         if (!chip->onfi_version)
2745                 return -EINVAL;
2746
2747         /* clear the sub feature parameters */
2748         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2749
2750         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2751         chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2752         return 0;
2753 }
2754
2755 /**
2756  * nand_suspend - [MTD Interface] Suspend the NAND flash
2757  * @mtd: MTD device structure
2758  */
2759 static int nand_suspend(struct mtd_info *mtd)
2760 {
2761         return nand_get_device(mtd, FL_PM_SUSPENDED);
2762 }
2763
2764 /**
2765  * nand_resume - [MTD Interface] Resume the NAND flash
2766  * @mtd: MTD device structure
2767  */
2768 static void nand_resume(struct mtd_info *mtd)
2769 {
2770         struct nand_chip *chip = mtd->priv;
2771
2772         if (chip->state == FL_PM_SUSPENDED)
2773                 nand_release_device(mtd);
2774         else
2775                 pr_err("%s called for a chip which is not in suspended state\n",
2776                         __func__);
2777 }
2778
2779 /* Set default functions */
2780 static void nand_set_defaults(struct nand_chip *chip, int busw)
2781 {
2782         /* check for proper chip_delay setup, set 20us if not */
2783         if (!chip->chip_delay)
2784                 chip->chip_delay = 20;
2785
2786         /* check, if a user supplied command function given */
2787         if (chip->cmdfunc == NULL)
2788                 chip->cmdfunc = nand_command;
2789
2790         /* check, if a user supplied wait function given */
2791         if (chip->waitfunc == NULL)
2792                 chip->waitfunc = nand_wait;
2793
2794         if (!chip->select_chip)
2795                 chip->select_chip = nand_select_chip;
2796         if (!chip->read_byte)
2797                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2798         if (!chip->read_word)
2799                 chip->read_word = nand_read_word;
2800         if (!chip->block_bad)
2801                 chip->block_bad = nand_block_bad;
2802         if (!chip->block_markbad)
2803                 chip->block_markbad = nand_default_block_markbad;
2804         if (!chip->write_buf)
2805                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2806         if (!chip->read_buf)
2807                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2808         if (!chip->scan_bbt)
2809                 chip->scan_bbt = nand_default_bbt;
2810
2811         if (!chip->controller) {
2812                 chip->controller = &chip->hwcontrol;
2813                 spin_lock_init(&chip->controller->lock);
2814                 init_waitqueue_head(&chip->controller->wq);
2815         }
2816
2817 }
2818
2819 /* Sanitize ONFI strings so we can safely print them */
2820 static void sanitize_string(uint8_t *s, size_t len)
2821 {
2822         ssize_t i;
2823
2824         /* Null terminate */
2825         s[len - 1] = 0;
2826
2827         /* Remove non printable chars */
2828         for (i = 0; i < len - 1; i++) {
2829                 if (s[i] < ' ' || s[i] > 127)
2830                         s[i] = '?';
2831         }
2832
2833         /* Remove trailing spaces */
2834         strim(s);
2835 }
2836
2837 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2838 {
2839         int i;
2840         while (len--) {
2841                 crc ^= *p++ << 8;
2842                 for (i = 0; i < 8; i++)
2843                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2844         }
2845
2846         return crc;
2847 }
2848
2849 /*
2850  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2851  */
2852 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2853                                         int *busw)
2854 {
2855         struct nand_onfi_params *p = &chip->onfi_params;
2856         int i;
2857         int val;
2858
2859         /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
2860         if (chip->options & NAND_BUSWIDTH_16) {
2861                 pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
2862                 return 0;
2863         }
2864         /* Try ONFI for unknown chip or LP */
2865         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2866         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2867                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2868                 return 0;
2869
2870         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2871         for (i = 0; i < 3; i++) {
2872                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2873                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2874                                 le16_to_cpu(p->crc)) {
2875                         pr_info("ONFI param page %d valid\n", i);
2876                         break;
2877                 }
2878         }
2879
2880         if (i == 3)
2881                 return 0;
2882
2883         /* Check version */
2884         val = le16_to_cpu(p->revision);
2885         if (val & (1 << 5))
2886                 chip->onfi_version = 23;
2887         else if (val & (1 << 4))
2888                 chip->onfi_version = 22;
2889         else if (val & (1 << 3))
2890                 chip->onfi_version = 21;
2891         else if (val & (1 << 2))
2892                 chip->onfi_version = 20;
2893         else if (val & (1 << 1))
2894                 chip->onfi_version = 10;
2895
2896         if (!chip->onfi_version) {
2897                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2898                 return 0;
2899         }
2900
2901         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2902         sanitize_string(p->model, sizeof(p->model));
2903         if (!mtd->name)
2904                 mtd->name = p->model;
2905         mtd->writesize = le32_to_cpu(p->byte_per_page);
2906         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2907         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2908         chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2909         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2910         *busw = 0;
2911         if (le16_to_cpu(p->features) & 1)
2912                 *busw = NAND_BUSWIDTH_16;
2913
2914         pr_info("ONFI flash detected\n");
2915         return 1;
2916 }
2917
2918 /*
2919  * nand_id_has_period - Check if an ID string has a given wraparound period
2920  * @id_data: the ID string
2921  * @arrlen: the length of the @id_data array
2922  * @period: the period of repitition
2923  *
2924  * Check if an ID string is repeated within a given sequence of bytes at
2925  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2926  * period of 3). This is a helper function for nand_id_len(). Returns non-zero
2927  * if the repetition has a period of @period; otherwise, returns zero.
2928  */
2929 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2930 {
2931         int i, j;
2932         for (i = 0; i < period; i++)
2933                 for (j = i + period; j < arrlen; j += period)
2934                         if (id_data[i] != id_data[j])
2935                                 return 0;
2936         return 1;
2937 }
2938
2939 /*
2940  * nand_id_len - Get the length of an ID string returned by CMD_READID
2941  * @id_data: the ID string
2942  * @arrlen: the length of the @id_data array
2943
2944  * Returns the length of the ID string, according to known wraparound/trailing
2945  * zero patterns. If no pattern exists, returns the length of the array.
2946  */
2947 static int nand_id_len(u8 *id_data, int arrlen)
2948 {
2949         int last_nonzero, period;
2950
2951         /* Find last non-zero byte */
2952         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2953                 if (id_data[last_nonzero])
2954                         break;
2955
2956         /* All zeros */
2957         if (last_nonzero < 0)
2958                 return 0;
2959
2960         /* Calculate wraparound period */
2961         for (period = 1; period < arrlen; period++)
2962                 if (nand_id_has_period(id_data, arrlen, period))
2963                         break;
2964
2965         /* There's a repeated pattern */
2966         if (period < arrlen)
2967                 return period;
2968
2969         /* There are trailing zeros */
2970         if (last_nonzero < arrlen - 1)
2971                 return last_nonzero + 1;
2972
2973         /* No pattern detected */
2974         return arrlen;
2975 }
2976
2977 /*
2978  * Many new NAND share similar device ID codes, which represent the size of the
2979  * chip. The rest of the parameters must be decoded according to generic or
2980  * manufacturer-specific "extended ID" decoding patterns.
2981  */
2982 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2983                                 u8 id_data[8], int *busw)
2984 {
2985         int extid, id_len;
2986         /* The 3rd id byte holds MLC / multichip data */
2987         chip->cellinfo = id_data[2];
2988         /* The 4th id byte is the important one */
2989         extid = id_data[3];
2990
2991         id_len = nand_id_len(id_data, 8);
2992
2993         /*
2994          * Field definitions are in the following datasheets:
2995          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2996          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2997          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
2998          *
2999          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3000          * ID to decide what to do.
3001          */
3002         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3003                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3004                         id_data[5] != 0x00) {
3005                 /* Calc pagesize */
3006                 mtd->writesize = 2048 << (extid & 0x03);
3007                 extid >>= 2;
3008                 /* Calc oobsize */
3009                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3010                 case 1:
3011                         mtd->oobsize = 128;
3012                         break;
3013                 case 2:
3014                         mtd->oobsize = 218;
3015                         break;
3016                 case 3:
3017                         mtd->oobsize = 400;
3018                         break;
3019                 case 4:
3020                         mtd->oobsize = 436;
3021                         break;
3022                 case 5:
3023                         mtd->oobsize = 512;
3024                         break;
3025                 case 6:
3026                 default: /* Other cases are "reserved" (unknown) */
3027                         mtd->oobsize = 640;
3028                         break;
3029                 }
3030                 extid >>= 2;
3031                 /* Calc blocksize */
3032                 mtd->erasesize = (128 * 1024) <<
3033                         (((extid >> 1) & 0x04) | (extid & 0x03));
3034                 *busw = 0;
3035         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3036                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3037                 unsigned int tmp;
3038
3039                 /* Calc pagesize */
3040                 mtd->writesize = 2048 << (extid & 0x03);
3041                 extid >>= 2;
3042                 /* Calc oobsize */
3043                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3044                 case 0:
3045                         mtd->oobsize = 128;
3046                         break;
3047                 case 1:
3048                         mtd->oobsize = 224;
3049                         break;
3050                 case 2:
3051                         mtd->oobsize = 448;
3052                         break;
3053                 case 3:
3054                         mtd->oobsize = 64;
3055                         break;
3056                 case 4:
3057                         mtd->oobsize = 32;
3058                         break;
3059                 case 5:
3060                         mtd->oobsize = 16;
3061                         break;
3062                 default:
3063                         mtd->oobsize = 640;
3064                         break;
3065                 }
3066                 extid >>= 2;
3067                 /* Calc blocksize */
3068                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3069                 if (tmp < 0x03)
3070                         mtd->erasesize = (128 * 1024) << tmp;
3071                 else if (tmp == 0x03)
3072                         mtd->erasesize = 768 * 1024;
3073                 else
3074                         mtd->erasesize = (64 * 1024) << tmp;
3075                 *busw = 0;
3076         } else {
3077                 /* Calc pagesize */
3078                 mtd->writesize = 1024 << (extid & 0x03);
3079                 extid >>= 2;
3080                 /* Calc oobsize */
3081                 mtd->oobsize = (8 << (extid & 0x01)) *
3082                         (mtd->writesize >> 9);
3083                 extid >>= 2;
3084                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3085                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3086                 extid >>= 2;
3087                 /* Get buswidth information */
3088                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3089         }
3090 }
3091
3092 /*
3093  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3094  * decodes a matching ID table entry and assigns the MTD size parameters for
3095  * the chip.
3096  */
3097 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3098                                 struct nand_flash_dev *type, u8 id_data[8],
3099                                 int *busw)
3100 {
3101         int maf_id = id_data[0];
3102
3103         mtd->erasesize = type->erasesize;
3104         mtd->writesize = type->pagesize;
3105         mtd->oobsize = mtd->writesize / 32;
3106         *busw = type->options & NAND_BUSWIDTH_16;
3107
3108         /*
3109          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3110          * some Spansion chips have erasesize that conflicts with size
3111          * listed in nand_ids table.
3112          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3113          */
3114         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3115                         && id_data[6] == 0x00 && id_data[7] == 0x00
3116                         && mtd->writesize == 512) {
3117                 mtd->erasesize = 128 * 1024;
3118                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3119         }
3120 }
3121
3122 /*
3123  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3124  * heuristic patterns using various detected parameters (e.g., manufacturer,
3125  * page size, cell-type information).
3126  */
3127 static void nand_decode_bbm_options(struct mtd_info *mtd,
3128                                     struct nand_chip *chip, u8 id_data[8])
3129 {
3130         int maf_id = id_data[0];
3131
3132         /* Set the bad block position */
3133         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3134                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3135         else
3136                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3137
3138         /*
3139          * Bad block marker is stored in the last page of each block on Samsung
3140          * and Hynix MLC devices; stored in first two pages of each block on
3141          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3142          * AMD/Spansion, and Macronix.  All others scan only the first page.
3143          */
3144         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3145                         (maf_id == NAND_MFR_SAMSUNG ||
3146                          maf_id == NAND_MFR_HYNIX))
3147                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3148         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3149                                 (maf_id == NAND_MFR_SAMSUNG ||
3150                                  maf_id == NAND_MFR_HYNIX ||
3151                                  maf_id == NAND_MFR_TOSHIBA ||
3152                                  maf_id == NAND_MFR_AMD ||
3153                                  maf_id == NAND_MFR_MACRONIX)) ||
3154                         (mtd->writesize == 2048 &&
3155                          maf_id == NAND_MFR_MICRON))
3156                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3157 }
3158
3159 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3160 {
3161         return type->id_len;
3162 }
3163
3164 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3165                    struct nand_flash_dev *type, u8 *id_data, int *busw)
3166 {
3167         if (!strncmp(type->id, id_data, type->id_len)) {
3168                 mtd->writesize = type->pagesize;
3169                 mtd->erasesize = type->erasesize;
3170                 mtd->oobsize = type->oobsize;
3171
3172                 chip->cellinfo = id_data[2];
3173                 chip->chipsize = (uint64_t)type->chipsize << 20;
3174                 chip->options |= type->options;
3175
3176                 *busw = type->options & NAND_BUSWIDTH_16;
3177
3178                 return true;
3179         }
3180         return false;
3181 }
3182
3183 /*
3184  * Get the flash and manufacturer id and lookup if the type is supported.
3185  */
3186 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3187                                                   struct nand_chip *chip,
3188                                                   int busw,
3189                                                   int *maf_id, int *dev_id,
3190                                                   struct nand_flash_dev *type)
3191 {
3192         int i, maf_idx;
3193         u8 id_data[8];
3194
3195         /* Select the device */
3196         chip->select_chip(mtd, 0);
3197
3198         /*
3199          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3200          * after power-up.
3201          */
3202         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3203
3204         /* Send the command for reading device ID */
3205         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3206
3207         /* Read manufacturer and device IDs */
3208         *maf_id = chip->read_byte(mtd);
3209         *dev_id = chip->read_byte(mtd);
3210
3211         /*
3212          * Try again to make sure, as some systems the bus-hold or other
3213          * interface concerns can cause random data which looks like a
3214          * possibly credible NAND flash to appear. If the two results do
3215          * not match, ignore the device completely.
3216          */
3217
3218         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3219
3220         /* Read entire ID string */
3221         for (i = 0; i < 8; i++)
3222                 id_data[i] = chip->read_byte(mtd);
3223
3224         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3225                 pr_info("%s: second ID read did not match "
3226                         "%02x,%02x against %02x,%02x\n", __func__,
3227                         *maf_id, *dev_id, id_data[0], id_data[1]);
3228                 return ERR_PTR(-ENODEV);
3229         }
3230
3231         if (!type)
3232                 type = nand_flash_ids;
3233
3234         for (; type->name != NULL; type++) {
3235                 if (is_full_id_nand(type)) {
3236                         if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3237                                 goto ident_done;
3238                 } else if (*dev_id == type->dev_id) {
3239                                 break;
3240                 }
3241         }
3242
3243         chip->onfi_version = 0;
3244         if (!type->name || !type->pagesize) {
3245                 /* Check is chip is ONFI compliant */
3246                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3247                         goto ident_done;
3248         }
3249
3250         if (!type->name)
3251                 return ERR_PTR(-ENODEV);
3252
3253         if (!mtd->name)
3254                 mtd->name = type->name;
3255
3256         chip->chipsize = (uint64_t)type->chipsize << 20;
3257
3258         if (!type->pagesize && chip->init_size) {
3259                 /* Set the pagesize, oobsize, erasesize by the driver */
3260                 busw = chip->init_size(mtd, chip, id_data);
3261         } else if (!type->pagesize) {
3262                 /* Decode parameters from extended ID */
3263                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3264         } else {
3265                 nand_decode_id(mtd, chip, type, id_data, &busw);
3266         }
3267         /* Get chip options */
3268         chip->options |= type->options;
3269
3270         /*
3271          * Check if chip is not a Samsung device. Do not clear the
3272          * options for chips which do not have an extended id.
3273          */
3274         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3275                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3276 ident_done:
3277
3278         /* Try to identify manufacturer */
3279         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3280                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3281                         break;
3282         }
3283
3284         if (chip->options & NAND_BUSWIDTH_AUTO) {
3285                 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3286                 chip->options |= busw;
3287                 nand_set_defaults(chip, busw);
3288         } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3289                 /*
3290                  * Check, if buswidth is correct. Hardware drivers should set
3291                  * chip correct!
3292                  */
3293                 pr_info("NAND device: Manufacturer ID:"
3294                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3295                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3296                 pr_warn("NAND bus width %d instead %d bit\n",
3297                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3298                            busw ? 16 : 8);
3299                 return ERR_PTR(-EINVAL);
3300         }
3301
3302         nand_decode_bbm_options(mtd, chip, id_data);
3303
3304         /* Calculate the address shift from the page size */
3305         chip->page_shift = ffs(mtd->writesize) - 1;
3306         /* Convert chipsize to number of pages per chip -1 */
3307         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3308
3309         chip->bbt_erase_shift = chip->phys_erase_shift =
3310                 ffs(mtd->erasesize) - 1;
3311         if (chip->chipsize & 0xffffffff)
3312                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3313         else {
3314                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3315                 chip->chip_shift += 32 - 1;
3316         }
3317
3318         chip->badblockbits = 8;
3319         chip->erase_cmd = single_erase_cmd;
3320
3321         /* Do not replace user supplied command function! */
3322         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3323                 chip->cmdfunc = nand_command_lp;
3324
3325         pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3326                 " %dMiB, page size: %d, OOB size: %d\n",
3327                 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3328                 chip->onfi_version ? chip->onfi_params.model : type->name,
3329                 (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
3330
3331         return type;
3332 }
3333
3334 /**
3335  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3336  * @mtd: MTD device structure
3337  * @maxchips: number of chips to scan for
3338  * @table: alternative NAND ID table
3339  *
3340  * This is the first phase of the normal nand_scan() function. It reads the
3341  * flash ID and sets up MTD fields accordingly.
3342  *
3343  * The mtd->owner field must be set to the module of the caller.
3344  */
3345 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3346                     struct nand_flash_dev *table)
3347 {
3348         int i, busw, nand_maf_id, nand_dev_id;
3349         struct nand_chip *chip = mtd->priv;
3350         struct nand_flash_dev *type;
3351
3352         /* Get buswidth to select the correct functions */
3353         busw = chip->options & NAND_BUSWIDTH_16;
3354         /* Set the default functions */
3355         nand_set_defaults(chip, busw);
3356
3357         /* Read the flash type */
3358         type = nand_get_flash_type(mtd, chip, busw,
3359                                 &nand_maf_id, &nand_dev_id, table);
3360
3361         if (IS_ERR(type)) {
3362                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3363                         pr_warn("No NAND device found\n");
3364                 chip->select_chip(mtd, -1);
3365                 return PTR_ERR(type);
3366         }
3367
3368         chip->select_chip(mtd, -1);
3369
3370         /* Check for a chip array */
3371         for (i = 1; i < maxchips; i++) {
3372                 chip->select_chip(mtd, i);
3373                 /* See comment in nand_get_flash_type for reset */
3374                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3375                 /* Send the command for reading device ID */
3376                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3377                 /* Read manufacturer and device IDs */
3378                 if (nand_maf_id != chip->read_byte(mtd) ||
3379                     nand_dev_id != chip->read_byte(mtd)) {
3380                         chip->select_chip(mtd, -1);
3381                         break;
3382                 }
3383                 chip->select_chip(mtd, -1);
3384         }
3385         if (i > 1)
3386                 pr_info("%d NAND chips detected\n", i);
3387
3388         /* Store the number of chips and calc total size for mtd */
3389         chip->numchips = i;
3390         mtd->size = i * chip->chipsize;
3391
3392         return 0;
3393 }
3394 EXPORT_SYMBOL(nand_scan_ident);
3395
3396
3397 /**
3398  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3399  * @mtd: MTD device structure
3400  *
3401  * This is the second phase of the normal nand_scan() function. It fills out
3402  * all the uninitialized function pointers with the defaults and scans for a
3403  * bad block table if appropriate.
3404  */
3405 int nand_scan_tail(struct mtd_info *mtd)
3406 {
3407         int i;
3408         struct nand_chip *chip = mtd->priv;
3409
3410         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3411         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3412                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3413
3414         if (!(chip->options & NAND_OWN_BUFFERS))
3415                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3416         if (!chip->buffers)
3417                 return -ENOMEM;
3418
3419         /* Set the internal oob buffer location, just after the page data */
3420         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3421
3422         /*
3423          * If no default placement scheme is given, select an appropriate one.
3424          */
3425         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3426                 switch (mtd->oobsize) {
3427                 case 8:
3428                         chip->ecc.layout = &nand_oob_8;
3429                         break;
3430                 case 16:
3431                         chip->ecc.layout = &nand_oob_16;
3432                         break;
3433                 case 64:
3434                         chip->ecc.layout = &nand_oob_64;
3435                         break;
3436                 case 128:
3437                         chip->ecc.layout = &nand_oob_128;
3438                         break;
3439                 default:
3440                         pr_warn("No oob scheme defined for oobsize %d\n",
3441                                    mtd->oobsize);
3442                         BUG();
3443                 }
3444         }
3445
3446         if (!chip->write_page)
3447                 chip->write_page = nand_write_page;
3448
3449         /* set for ONFI nand */
3450         if (!chip->onfi_set_features)
3451                 chip->onfi_set_features = nand_onfi_set_features;
3452         if (!chip->onfi_get_features)
3453                 chip->onfi_get_features = nand_onfi_get_features;
3454
3455         /*
3456          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3457          * selected and we have 256 byte pagesize fallback to software ECC
3458          */
3459
3460         switch (chip->ecc.mode) {
3461         case NAND_ECC_HW_OOB_FIRST:
3462                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3463                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3464                      !chip->ecc.hwctl) {
3465                         pr_warn("No ECC functions supplied; "
3466                                    "hardware ECC not possible\n");
3467                         BUG();
3468                 }
3469                 if (!chip->ecc.read_page)
3470                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3471
3472         case NAND_ECC_HW:
3473                 /* Use standard hwecc read page function? */
3474                 if (!chip->ecc.read_page)
3475                         chip->ecc.read_page = nand_read_page_hwecc;
3476                 if (!chip->ecc.write_page)
3477                         chip->ecc.write_page = nand_write_page_hwecc;
3478                 if (!chip->ecc.read_page_raw)
3479                         chip->ecc.read_page_raw = nand_read_page_raw;
3480                 if (!chip->ecc.write_page_raw)
3481                         chip->ecc.write_page_raw = nand_write_page_raw;
3482                 if (!chip->ecc.read_oob)
3483                         chip->ecc.read_oob = nand_read_oob_std;
3484                 if (!chip->ecc.write_oob)
3485                         chip->ecc.write_oob = nand_write_oob_std;
3486                 if (!chip->ecc.read_subpage)
3487                         chip->ecc.read_subpage = nand_read_subpage;
3488                 if (!chip->ecc.write_subpage)
3489                         chip->ecc.write_subpage = nand_write_subpage_hwecc;
3490
3491         case NAND_ECC_HW_SYNDROME:
3492                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3493                      !chip->ecc.hwctl) &&
3494                     (!chip->ecc.read_page ||
3495                      chip->ecc.read_page == nand_read_page_hwecc ||
3496                      !chip->ecc.write_page ||
3497                      chip->ecc.write_page == nand_write_page_hwecc)) {
3498                         pr_warn("No ECC functions supplied; "
3499                                    "hardware ECC not possible\n");
3500                         BUG();
3501                 }
3502                 /* Use standard syndrome read/write page function? */
3503                 if (!chip->ecc.read_page)
3504                         chip->ecc.read_page = nand_read_page_syndrome;
3505                 if (!chip->ecc.write_page)
3506                         chip->ecc.write_page = nand_write_page_syndrome;
3507                 if (!chip->ecc.read_page_raw)
3508                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3509                 if (!chip->ecc.write_page_raw)
3510                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3511                 if (!chip->ecc.read_oob)
3512                         chip->ecc.read_oob = nand_read_oob_syndrome;
3513                 if (!chip->ecc.write_oob)
3514                         chip->ecc.write_oob = nand_write_oob_syndrome;
3515
3516                 if (mtd->writesize >= chip->ecc.size) {
3517                         if (!chip->ecc.strength) {
3518                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3519                                 BUG();
3520                         }
3521                         break;
3522                 }
3523                 pr_warn("%d byte HW ECC not possible on "
3524                            "%d byte page size, fallback to SW ECC\n",
3525                            chip->ecc.size, mtd->writesize);
3526                 chip->ecc.mode = NAND_ECC_SOFT;
3527
3528         case NAND_ECC_SOFT:
3529                 chip->ecc.calculate = nand_calculate_ecc;
3530                 chip->ecc.correct = nand_correct_data;
3531                 chip->ecc.read_page = nand_read_page_swecc;
3532                 chip->ecc.read_subpage = nand_read_subpage;
3533                 chip->ecc.write_page = nand_write_page_swecc;
3534                 chip->ecc.read_page_raw = nand_read_page_raw;
3535                 chip->ecc.write_page_raw = nand_write_page_raw;
3536                 chip->ecc.read_oob = nand_read_oob_std;
3537                 chip->ecc.write_oob = nand_write_oob_std;
3538                 if (!chip->ecc.size)
3539                         chip->ecc.size = 256;
3540                 chip->ecc.bytes = 3;
3541                 chip->ecc.strength = 1;
3542                 break;
3543
3544         case NAND_ECC_SOFT_BCH:
3545                 if (!mtd_nand_has_bch()) {
3546                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3547                         BUG();
3548                 }
3549                 chip->ecc.calculate = nand_bch_calculate_ecc;
3550                 chip->ecc.correct = nand_bch_correct_data;
3551                 chip->ecc.read_page = nand_read_page_swecc;
3552                 chip->ecc.read_subpage = nand_read_subpage;
3553                 chip->ecc.write_page = nand_write_page_swecc;
3554                 chip->ecc.read_page_raw = nand_read_page_raw;
3555                 chip->ecc.write_page_raw = nand_write_page_raw;
3556                 chip->ecc.read_oob = nand_read_oob_std;
3557                 chip->ecc.write_oob = nand_write_oob_std;
3558                 /*
3559                  * Board driver should supply ecc.size and ecc.bytes values to
3560                  * select how many bits are correctable; see nand_bch_init()
3561                  * for details. Otherwise, default to 4 bits for large page
3562                  * devices.
3563                  */
3564                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3565                         chip->ecc.size = 512;
3566                         chip->ecc.bytes = 7;
3567                 }
3568                 chip->ecc.priv = nand_bch_init(mtd,
3569                                                chip->ecc.size,
3570                                                chip->ecc.bytes,
3571                                                &chip->ecc.layout);
3572                 if (!chip->ecc.priv) {
3573                         pr_warn("BCH ECC initialization failed!\n");
3574                         BUG();
3575                 }
3576                 chip->ecc.strength =
3577                         chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3578                 break;
3579
3580         case NAND_ECC_NONE:
3581                 pr_warn("NAND_ECC_NONE selected by board driver. "
3582                            "This is not recommended!\n");
3583                 chip->ecc.read_page = nand_read_page_raw;
3584                 chip->ecc.write_page = nand_write_page_raw;
3585                 chip->ecc.read_oob = nand_read_oob_std;
3586                 chip->ecc.read_page_raw = nand_read_page_raw;
3587                 chip->ecc.write_page_raw = nand_write_page_raw;
3588                 chip->ecc.write_oob = nand_write_oob_std;
3589                 chip->ecc.size = mtd->writesize;
3590                 chip->ecc.bytes = 0;
3591                 chip->ecc.strength = 0;
3592                 break;
3593
3594         default:
3595                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3596                 BUG();
3597         }
3598
3599         /* For many systems, the standard OOB write also works for raw */
3600         if (!chip->ecc.read_oob_raw)
3601                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3602         if (!chip->ecc.write_oob_raw)
3603                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3604
3605         /*
3606          * The number of bytes available for a client to place data into
3607          * the out of band area.
3608          */
3609         chip->ecc.layout->oobavail = 0;
3610         for (i = 0; chip->ecc.layout->oobfree[i].length
3611                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3612                 chip->ecc.layout->oobavail +=
3613                         chip->ecc.layout->oobfree[i].length;
3614         mtd->oobavail = chip->ecc.layout->oobavail;
3615
3616         /*
3617          * Set the number of read / write steps for one page depending on ECC
3618          * mode.
3619          */
3620         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3621         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3622                 pr_warn("Invalid ECC parameters\n");
3623                 BUG();
3624         }
3625         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3626
3627         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3628         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3629             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3630                 switch (chip->ecc.steps) {
3631                 case 2:
3632                         mtd->subpage_sft = 1;
3633                         break;
3634                 case 4:
3635                 case 8:
3636                 case 16:
3637                         mtd->subpage_sft = 2;
3638                         break;
3639                 }
3640         }
3641         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3642
3643         /* Initialize state */
3644         chip->state = FL_READY;
3645
3646         /* Invalidate the pagebuffer reference */
3647         chip->pagebuf = -1;
3648
3649         /* Large page NAND with SOFT_ECC should support subpage reads */
3650         if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3651                 chip->options |= NAND_SUBPAGE_READ;
3652
3653         /* Fill in remaining MTD driver data */
3654         mtd->type = MTD_NANDFLASH;
3655         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3656                                                 MTD_CAP_NANDFLASH;
3657         mtd->_erase = nand_erase;
3658         mtd->_point = NULL;
3659         mtd->_unpoint = NULL;
3660         mtd->_read = nand_read;
3661         mtd->_write = nand_write;
3662         mtd->_panic_write = panic_nand_write;
3663         mtd->_read_oob = nand_read_oob;
3664         mtd->_write_oob = nand_write_oob;
3665         mtd->_sync = nand_sync;
3666         mtd->_lock = NULL;
3667         mtd->_unlock = NULL;
3668         mtd->_suspend = nand_suspend;
3669         mtd->_resume = nand_resume;
3670         mtd->_block_isbad = nand_block_isbad;
3671         mtd->_block_markbad = nand_block_markbad;
3672         mtd->writebufsize = mtd->writesize;
3673
3674         /* propagate ecc info to mtd_info */
3675         mtd->ecclayout = chip->ecc.layout;
3676         mtd->ecc_strength = chip->ecc.strength;
3677         /*
3678          * Initialize bitflip_threshold to its default prior scan_bbt() call.
3679          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3680          * properly set.
3681          */
3682         if (!mtd->bitflip_threshold)
3683                 mtd->bitflip_threshold = mtd->ecc_strength;
3684
3685         /* Check, if we should skip the bad block table scan */
3686         if (chip->options & NAND_SKIP_BBTSCAN)
3687                 return 0;
3688
3689         /* Build bad block table */
3690         return chip->scan_bbt(mtd);
3691 }
3692 EXPORT_SYMBOL(nand_scan_tail);
3693
3694 /*
3695  * is_module_text_address() isn't exported, and it's mostly a pointless
3696  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3697  * to call us from in-kernel code if the core NAND support is modular.
3698  */
3699 #ifdef MODULE
3700 #define caller_is_module() (1)
3701 #else
3702 #define caller_is_module() \
3703         is_module_text_address((unsigned long)__builtin_return_address(0))
3704 #endif
3705
3706 /**
3707  * nand_scan - [NAND Interface] Scan for the NAND device
3708  * @mtd: MTD device structure
3709  * @maxchips: number of chips to scan for
3710  *
3711  * This fills out all the uninitialized function pointers with the defaults.
3712  * The flash ID is read and the mtd/chip structures are filled with the
3713  * appropriate values. The mtd->owner field must be set to the module of the
3714  * caller.
3715  */
3716 int nand_scan(struct mtd_info *mtd, int maxchips)
3717 {
3718         int ret;
3719
3720         /* Many callers got this wrong, so check for it for a while... */
3721         if (!mtd->owner && caller_is_module()) {
3722                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3723                 BUG();
3724         }
3725
3726         ret = nand_scan_ident(mtd, maxchips, NULL);
3727         if (!ret)
3728                 ret = nand_scan_tail(mtd);
3729         return ret;
3730 }
3731 EXPORT_SYMBOL(nand_scan);
3732
3733 /**
3734  * nand_release - [NAND Interface] Free resources held by the NAND device
3735  * @mtd: MTD device structure
3736  */
3737 void nand_release(struct mtd_info *mtd)
3738 {
3739         struct nand_chip *chip = mtd->priv;
3740
3741         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3742                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3743
3744         mtd_device_unregister(mtd);
3745
3746         /* Free bad block table memory */
3747         kfree(chip->bbt);
3748         if (!(chip->options & NAND_OWN_BUFFERS))
3749                 kfree(chip->buffers);
3750
3751         /* Free bad block descriptor memory */
3752         if (chip->badblock_pattern && chip->badblock_pattern->options
3753                         & NAND_BBT_DYNAMICSTRUCT)
3754                 kfree(chip->badblock_pattern);
3755 }
3756 EXPORT_SYMBOL_GPL(nand_release);
3757
3758 static int __init nand_base_init(void)
3759 {
3760         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3761         return 0;
3762 }
3763
3764 static void __exit nand_base_exit(void)
3765 {
3766         led_trigger_unregister_simple(nand_led_trigger);
3767 }
3768
3769 module_init(nand_base_init);
3770 module_exit(nand_base_exit);
3771
3772 MODULE_LICENSE("GPL");
3773 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3774 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3775 MODULE_DESCRIPTION("Generic NAND flash driver code");