drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/delay.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/sched.h>
  19 #include <linux/mtd/mtd.h>
  20 #include <linux/mtd/nand.h>
  21 #include <linux/mtd/partitions.h>
  22 #include <linux/omap-dma.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27
  28 #include <linux/bch.h>
  29 #include <linux/platform_data/elm.h>
  30
  31 #include <linux/platform_data/mtd-nand-omap2.h>
  32
  33 #define DRIVER_NAME     "omap2-nand"
  34 #define OMAP_NAND_TIMEOUT_MS    5000
  35
  36 #define NAND_Ecc_P1e            (1 << 0)
  37 #define NAND_Ecc_P2e            (1 << 1)
  38 #define NAND_Ecc_P4e            (1 << 2)
  39 #define NAND_Ecc_P8e            (1 << 3)
  40 #define NAND_Ecc_P16e           (1 << 4)
  41 #define NAND_Ecc_P32e           (1 << 5)
  42 #define NAND_Ecc_P64e           (1 << 6)
  43 #define NAND_Ecc_P128e          (1 << 7)
  44 #define NAND_Ecc_P256e          (1 << 8)
  45 #define NAND_Ecc_P512e          (1 << 9)
  46 #define NAND_Ecc_P1024e         (1 << 10)
  47 #define NAND_Ecc_P2048e         (1 << 11)
  48
  49 #define NAND_Ecc_P1o            (1 << 16)
  50 #define NAND_Ecc_P2o            (1 << 17)
  51 #define NAND_Ecc_P4o            (1 << 18)
  52 #define NAND_Ecc_P8o            (1 << 19)
  53 #define NAND_Ecc_P16o           (1 << 20)
  54 #define NAND_Ecc_P32o           (1 << 21)
  55 #define NAND_Ecc_P64o           (1 << 22)
  56 #define NAND_Ecc_P128o          (1 << 23)
  57 #define NAND_Ecc_P256o          (1 << 24)
  58 #define NAND_Ecc_P512o          (1 << 25)
  59 #define NAND_Ecc_P1024o         (1 << 26)
  60 #define NAND_Ecc_P2048o         (1 << 27)
  61
  62 #define TF(value)       (value ? 1 : 0)
  63
  64 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  65 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  66 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  67 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  68 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  69 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  70 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  71 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  72
  73 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  74 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  75 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  76 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  77 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  78 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  79 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  80 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  81
  82 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  83 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  84 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  85 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  86 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  87 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  88 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  89 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  90
  91 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  92 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  93 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  94 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  95 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  96 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  97 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  98 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  99
 100 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
 101 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
 102
 103 #define PREFETCH_CONFIG1_CS_SHIFT       24
 104 #define ECC_CONFIG_CS_SHIFT             1
 105 #define CS_MASK                         0x7
 106 #define ENABLE_PREFETCH                 (0x1 << 7)
 107 #define DMA_MPU_MODE_SHIFT              2
 108 #define ECCSIZE0_SHIFT                  12
 109 #define ECCSIZE1_SHIFT                  22
 110 #define ECC1RESULTSIZE                  0x1
 111 #define ECCCLEAR                        0x100
 112 #define ECC1                            0x1
 113 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 114 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 115 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 116 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 117 #define STATUS_BUFF_EMPTY               0x00000001
 118
 119 #define OMAP24XX_DMA_GPMC               4
 120
 121 #define BCH8_MAX_ERROR          8       /* upto 8 bit correctable */
 122 #define BCH4_MAX_ERROR          4       /* upto 4 bit correctable */
 123
 124 #define SECTOR_BYTES            512
 125 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
 126 #define BCH4_BIT_PAD            4
 127 #define BCH8_ECC_MAX            ((SECTOR_BYTES + BCH8_ECC_OOB_BYTES) * 8)
 128 #define BCH4_ECC_MAX            ((SECTOR_BYTES + BCH4_ECC_OOB_BYTES) * 8)
 129
 130 /* GPMC ecc engine settings for read */
 131 #define BCH_WRAPMODE_1          1       /* BCH wrap mode 1 */
 132 #define BCH8R_ECC_SIZE0         0x1a    /* ecc_size0 = 26 */
 133 #define BCH8R_ECC_SIZE1         0x2     /* ecc_size1 = 2 */
 134 #define BCH4R_ECC_SIZE0         0xd     /* ecc_size0 = 13 */
 135 #define BCH4R_ECC_SIZE1         0x3     /* ecc_size1 = 3 */
 136
 137 /* GPMC ecc engine settings for write */
 138 #define BCH_WRAPMODE_6          6       /* BCH wrap mode 6 */
 139 #define BCH_ECC_SIZE0           0x0     /* ecc_size0 = 0, no oob protection */
 140 #define BCH_ECC_SIZE1           0x20    /* ecc_size1 = 32 */
 141
 142 #define BADBLOCK_MARKER_LENGTH          2
 143 #define OMAP_ECC_BCH8_POLYNOMIAL        0x201b
 144
 145 #ifdef CONFIG_MTD_NAND_OMAP_BCH
 146 static u_char bch8_vector[] = {0xf3, 0xdb, 0x14, 0x16, 0x8b, 0xd2, 0xbe, 0xcc,
 147         0xac, 0x6b, 0xff, 0x99, 0x7b};
 148 static u_char bch4_vector[] = {0x00, 0x6b, 0x31, 0xdd, 0x41, 0xbc, 0x10};
 149 #endif
 150
 151 /* oob info generated runtime depending on ecc algorithm and layout selected */
 152 static struct nand_ecclayout omap_oobinfo;
 153
 154 struct omap_nand_info {
 155         struct nand_hw_control          controller;
 156         struct omap_nand_platform_data  *pdata;
 157         struct mtd_info                 mtd;
 158         struct nand_chip                nand;
 159         struct platform_device          *pdev;
 160
 161         int                             gpmc_cs;
 162         unsigned long                   phys_base;
 163         unsigned long                   mem_size;
 164         struct completion               comp;
 165         struct dma_chan                 *dma;
 166         int                             gpmc_irq_fifo;
 167         int                             gpmc_irq_count;
 168         enum {
 169                 OMAP_NAND_IO_READ = 0,  /* read */
 170                 OMAP_NAND_IO_WRITE,     /* write */
 171         } iomode;
 172         u_char                          *buf;
 173         int                                     buf_len;
 174         struct gpmc_nand_regs           reg;
 175         /* fields specific for BCHx_HW ECC scheme */
 176         struct bch_control             *bch;
 177         bool                            is_elm_used;
 178         struct device                   *elm_dev;
 179         struct device_node              *of_node;
 180 };
 181
 182 /**
 183  * omap_prefetch_enable - configures and starts prefetch transfer
 184  * @cs: cs (chip select) number
 185  * @fifo_th: fifo threshold to be used for read/ write
 186  * @dma_mode: dma mode enable (1) or disable (0)
 187  * @u32_count: number of bytes to be transferred
 188  * @is_write: prefetch read(0) or write post(1) mode
 189  */
 190 static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
 191         unsigned int u32_count, int is_write, struct omap_nand_info *info)
 192 {
 193         u32 val;
 194
 195         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 196                 return -1;
 197
 198         if (readl(info->reg.gpmc_prefetch_control))
 199                 return -EBUSY;
 200
 201         /* Set the amount of bytes to be prefetched */
 202         writel(u32_count, info->reg.gpmc_prefetch_config2);
 203
 204         /* Set dma/mpu mode, the prefetch read / post write and
 205          * enable the engine. Set which cs is has requested for.
 206          */
 207         val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
 208                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
 209                 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
 210         writel(val, info->reg.gpmc_prefetch_config1);
 211
 212         /*  Start the prefetch engine */
 213         writel(0x1, info->reg.gpmc_prefetch_control);
 214
 215         return 0;
 216 }
 217
 218 /**
 219  * omap_prefetch_reset - disables and stops the prefetch engine
 220  */
 221 static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
 222 {
 223         u32 config1;
 224
 225         /* check if the same module/cs is trying to reset */
 226         config1 = readl(info->reg.gpmc_prefetch_config1);
 227         if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
 228                 return -EINVAL;
 229
 230         /* Stop the PFPW engine */
 231         writel(0x0, info->reg.gpmc_prefetch_control);
 232
 233         /* Reset/disable the PFPW engine */
 234         writel(0x0, info->reg.gpmc_prefetch_config1);
 235
 236         return 0;
 237 }
 238
 239 /**
 240  * omap_hwcontrol - hardware specific access to control-lines
 241  * @mtd: MTD device structure
 242  * @cmd: command to device
 243  * @ctrl:
 244  * NAND_NCE: bit 0 -> don't care
 245  * NAND_CLE: bit 1 -> Command Latch
 246  * NAND_ALE: bit 2 -> Address Latch
 247  *
 248  * NOTE: boards may use different bits for these!!
 249  */
 250 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 251 {
 252         struct omap_nand_info *info = container_of(mtd,
 253                                         struct omap_nand_info, mtd);
 254
 255         if (cmd != NAND_CMD_NONE) {
 256                 if (ctrl & NAND_CLE)
 257                         writeb(cmd, info->reg.gpmc_nand_command);
 258
 259                 else if (ctrl & NAND_ALE)
 260                         writeb(cmd, info->reg.gpmc_nand_address);
 261
 262                 else /* NAND_NCE */
 263                         writeb(cmd, info->reg.gpmc_nand_data);
 264         }
 265 }
 266
 267 /**
 268  * omap_read_buf8 - read data from NAND controller into buffer
 269  * @mtd: MTD device structure
 270  * @buf: buffer to store date
 271  * @len: number of bytes to read
 272  */
 273 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 274 {
 275         struct nand_chip *nand = mtd->priv;
 276
 277         ioread8_rep(nand->IO_ADDR_R, buf, len);
 278 }
 279
 280 /**
 281  * omap_write_buf8 - write buffer to NAND controller
 282  * @mtd: MTD device structure
 283  * @buf: data buffer
 284  * @len: number of bytes to write
 285  */
 286 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 287 {
 288         struct omap_nand_info *info = container_of(mtd,
 289                                                 struct omap_nand_info, mtd);
 290         u_char *p = (u_char *)buf;
 291         u32     status = 0;
 292
 293         while (len--) {
 294                 iowrite8(*p++, info->nand.IO_ADDR_W);
 295                 /* wait until buffer is available for write */
 296                 do {
 297                         status = readl(info->reg.gpmc_status) &
 298                                         STATUS_BUFF_EMPTY;
 299                 } while (!status);
 300         }
 301 }
 302
 303 /**
 304  * omap_read_buf16 - read data from NAND controller into buffer
 305  * @mtd: MTD device structure
 306  * @buf: buffer to store date
 307  * @len: number of bytes to read
 308  */
 309 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 310 {
 311         struct nand_chip *nand = mtd->priv;
 312
 313         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 314 }
 315
 316 /**
 317  * omap_write_buf16 - write buffer to NAND controller
 318  * @mtd: MTD device structure
 319  * @buf: data buffer
 320  * @len: number of bytes to write
 321  */
 322 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 323 {
 324         struct omap_nand_info *info = container_of(mtd,
 325                                                 struct omap_nand_info, mtd);
 326         u16 *p = (u16 *) buf;
 327         u32     status = 0;
 328         /* FIXME try bursts of writesw() or DMA ... */
 329         len >>= 1;
 330
 331         while (len--) {
 332                 iowrite16(*p++, info->nand.IO_ADDR_W);
 333                 /* wait until buffer is available for write */
 334                 do {
 335                         status = readl(info->reg.gpmc_status) &
 336                                         STATUS_BUFF_EMPTY;
 337                 } while (!status);
 338         }
 339 }
 340
 341 /**
 342  * omap_read_buf_pref - read data from NAND controller into buffer
 343  * @mtd: MTD device structure
 344  * @buf: buffer to store date
 345  * @len: number of bytes to read
 346  */
 347 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 348 {
 349         struct omap_nand_info *info = container_of(mtd,
 350                                                 struct omap_nand_info, mtd);
 351         uint32_t r_count = 0;
 352         int ret = 0;
 353         u32 *p = (u32 *)buf;
 354
 355         /* take care of subpage reads */
 356         if (len % 4) {
 357                 if (info->nand.options & NAND_BUSWIDTH_16)
 358                         omap_read_buf16(mtd, buf, len % 4);
 359                 else
 360                         omap_read_buf8(mtd, buf, len % 4);
 361                 p = (u32 *) (buf + len % 4);
 362                 len -= len % 4;
 363         }
 364
 365         /* configure and start prefetch transfer */
 366         ret = omap_prefetch_enable(info->gpmc_cs,
 367                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
 368         if (ret) {
 369                 /* PFPW engine is busy, use cpu copy method */
 370                 if (info->nand.options & NAND_BUSWIDTH_16)
 371                         omap_read_buf16(mtd, (u_char *)p, len);
 372                 else
 373                         omap_read_buf8(mtd, (u_char *)p, len);
 374         } else {
 375                 do {
 376                         r_count = readl(info->reg.gpmc_prefetch_status);
 377                         r_count = PREFETCH_STATUS_FIFO_CNT(r_count);
 378                         r_count = r_count >> 2;
 379                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 380                         p += r_count;
 381                         len -= r_count << 2;
 382                 } while (len);
 383                 /* disable and stop the PFPW engine */
 384                 omap_prefetch_reset(info->gpmc_cs, info);
 385         }
 386 }
 387
 388 /**
 389  * omap_write_buf_pref - write buffer to NAND controller
 390  * @mtd: MTD device structure
 391  * @buf: data buffer
 392  * @len: number of bytes to write
 393  */
 394 static void omap_write_buf_pref(struct mtd_info *mtd,
 395                                         const u_char *buf, int len)
 396 {
 397         struct omap_nand_info *info = container_of(mtd,
 398                                                 struct omap_nand_info, mtd);
 399         uint32_t w_count = 0;
 400         int i = 0, ret = 0;
 401         u16 *p = (u16 *)buf;
 402         unsigned long tim, limit;
 403         u32 val;
 404
 405         /* take care of subpage writes */
 406         if (len % 2 != 0) {
 407                 writeb(*buf, info->nand.IO_ADDR_W);
 408                 p = (u16 *)(buf + 1);
 409                 len--;
 410         }
 411
 412         /*  configure and start prefetch transfer */
 413         ret = omap_prefetch_enable(info->gpmc_cs,
 414                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
 415         if (ret) {
 416                 /* PFPW engine is busy, use cpu copy method */
 417                 if (info->nand.options & NAND_BUSWIDTH_16)
 418                         omap_write_buf16(mtd, (u_char *)p, len);
 419                 else
 420                         omap_write_buf8(mtd, (u_char *)p, len);
 421         } else {
 422                 while (len) {
 423                         w_count = readl(info->reg.gpmc_prefetch_status);
 424                         w_count = PREFETCH_STATUS_FIFO_CNT(w_count);
 425                         w_count = w_count >> 1;
 426                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 427                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 428                 }
 429                 /* wait for data to flushed-out before reset the prefetch */
 430                 tim = 0;
 431                 limit = (loops_per_jiffy *
 432                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 433                 do {
 434                         cpu_relax();
 435                         val = readl(info->reg.gpmc_prefetch_status);
 436                         val = PREFETCH_STATUS_COUNT(val);
 437                 } while (val && (tim++ < limit));
 438
 439                 /* disable and stop the PFPW engine */
 440                 omap_prefetch_reset(info->gpmc_cs, info);
 441         }
 442 }
 443
 444 /*
 445  * omap_nand_dma_callback: callback on the completion of dma transfer
 446  * @data: pointer to completion data structure
 447  */
 448 static void omap_nand_dma_callback(void *data)
 449 {
 450         complete((struct completion *) data);
 451 }
 452
 453 /*
 454  * omap_nand_dma_transfer: configure and start dma transfer
 455  * @mtd: MTD device structure
 456  * @addr: virtual address in RAM of source/destination
 457  * @len: number of data bytes to be transferred
 458  * @is_write: flag for read/write operation
 459  */
 460 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 461                                         unsigned int len, int is_write)
 462 {
 463         struct omap_nand_info *info = container_of(mtd,
 464                                         struct omap_nand_info, mtd);
 465         struct dma_async_tx_descriptor *tx;
 466         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 467                                                         DMA_FROM_DEVICE;
 468         struct scatterlist sg;
 469         unsigned long tim, limit;
 470         unsigned n;
 471         int ret;
 472         u32 val;
 473
 474         if (addr >= high_memory) {
 475                 struct page *p1;
 476
 477                 if (((size_t)addr & PAGE_MASK) !=
 478                         ((size_t)(addr + len - 1) & PAGE_MASK))
 479                         goto out_copy;
 480                 p1 = vmalloc_to_page(addr);
 481                 if (!p1)
 482                         goto out_copy;
 483                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 484         }
 485
 486         sg_init_one(&sg, addr, len);
 487         n = dma_map_sg(info->dma->device->dev, &sg, 1, dir);
 488         if (n == 0) {
 489                 dev_err(&info->pdev->dev,
 490                         "Couldn't DMA map a %d byte buffer\n", len);
 491                 goto out_copy;
 492         }
 493
 494         tx = dmaengine_prep_slave_sg(info->dma, &sg, n,
 495                 is_write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 496                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 497         if (!tx)
 498                 goto out_copy_unmap;
 499
 500         tx->callback = omap_nand_dma_callback;
 501         tx->callback_param = &info->comp;
 502         dmaengine_submit(tx);
 503
 504         /*  configure and start prefetch transfer */
 505         ret = omap_prefetch_enable(info->gpmc_cs,
 506                 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
 507         if (ret)
 508                 /* PFPW engine is busy, use cpu copy method */
 509                 goto out_copy_unmap;
 510
 511         init_completion(&info->comp);
 512         dma_async_issue_pending(info->dma);
 513
 514         /* setup and start DMA using dma_addr */
 515         wait_for_completion(&info->comp);
 516         tim = 0;
 517         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 518
 519         do {
 520                 cpu_relax();
 521                 val = readl(info->reg.gpmc_prefetch_status);
 522                 val = PREFETCH_STATUS_COUNT(val);
 523         } while (val && (tim++ < limit));
 524
 525         /* disable and stop the PFPW engine */
 526         omap_prefetch_reset(info->gpmc_cs, info);
 527
 528         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 529         return 0;
 530
 531 out_copy_unmap:
 532         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
 533 out_copy:
 534         if (info->nand.options & NAND_BUSWIDTH_16)
 535                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 536                         : omap_write_buf16(mtd, (u_char *) addr, len);
 537         else
 538                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 539                         : omap_write_buf8(mtd, (u_char *) addr, len);
 540         return 0;
 541 }
 542
 543 /**
 544  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 545  * @mtd: MTD device structure
 546  * @buf: buffer to store date
 547  * @len: number of bytes to read
 548  */
 549 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 550 {
 551         if (len <= mtd->oobsize)
 552                 omap_read_buf_pref(mtd, buf, len);
 553         else
 554                 /* start transfer in DMA mode */
 555                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 556 }
 557
 558 /**
 559  * omap_write_buf_dma_pref - write buffer to NAND controller
 560  * @mtd: MTD device structure
 561  * @buf: data buffer
 562  * @len: number of bytes to write
 563  */
 564 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 565                                         const u_char *buf, int len)
 566 {
 567         if (len <= mtd->oobsize)
 568                 omap_write_buf_pref(mtd, buf, len);
 569         else
 570                 /* start transfer in DMA mode */
 571                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 572 }
 573
 574 /*
 575  * omap_nand_irq - GPMC irq handler
 576  * @this_irq: gpmc irq number
 577  * @dev: omap_nand_info structure pointer is passed here
 578  */
 579 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 580 {
 581         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 582         u32 bytes;
 583
 584         bytes = readl(info->reg.gpmc_prefetch_status);
 585         bytes = PREFETCH_STATUS_FIFO_CNT(bytes);
 586         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 587         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 588                 if (this_irq == info->gpmc_irq_count)
 589                         goto done;
 590
 591                 if (info->buf_len && (info->buf_len < bytes))
 592                         bytes = info->buf_len;
 593                 else if (!info->buf_len)
 594                         bytes = 0;
 595                 iowrite32_rep(info->nand.IO_ADDR_W,
 596                                                 (u32 *)info->buf, bytes >> 2);
 597                 info->buf = info->buf + bytes;
 598                 info->buf_len -= bytes;
 599
 600         } else {
 601                 ioread32_rep(info->nand.IO_ADDR_R,
 602                                                 (u32 *)info->buf, bytes >> 2);
 603                 info->buf = info->buf + bytes;
 604
 605                 if (this_irq == info->gpmc_irq_count)
 606                         goto done;
 607         }
 608
 609         return IRQ_HANDLED;
 610
 611 done:
 612         complete(&info->comp);
 613
 614         disable_irq_nosync(info->gpmc_irq_fifo);
 615         disable_irq_nosync(info->gpmc_irq_count);
 616
 617         return IRQ_HANDLED;
 618 }
 619
 620 /*
 621  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 622  * @mtd: MTD device structure
 623  * @buf: buffer to store date
 624  * @len: number of bytes to read
 625  */
 626 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 627 {
 628         struct omap_nand_info *info = container_of(mtd,
 629                                                 struct omap_nand_info, mtd);
 630         int ret = 0;
 631
 632         if (len <= mtd->oobsize) {
 633                 omap_read_buf_pref(mtd, buf, len);
 634                 return;
 635         }
 636
 637         info->iomode = OMAP_NAND_IO_READ;
 638         info->buf = buf;
 639         init_completion(&info->comp);
 640
 641         /*  configure and start prefetch transfer */
 642         ret = omap_prefetch_enable(info->gpmc_cs,
 643                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
 644         if (ret)
 645                 /* PFPW engine is busy, use cpu copy method */
 646                 goto out_copy;
 647
 648         info->buf_len = len;
 649
 650         enable_irq(info->gpmc_irq_count);
 651         enable_irq(info->gpmc_irq_fifo);
 652
 653         /* waiting for read to complete */
 654         wait_for_completion(&info->comp);
 655
 656         /* disable and stop the PFPW engine */
 657         omap_prefetch_reset(info->gpmc_cs, info);
 658         return;
 659
 660 out_copy:
 661         if (info->nand.options & NAND_BUSWIDTH_16)
 662                 omap_read_buf16(mtd, buf, len);
 663         else
 664                 omap_read_buf8(mtd, buf, len);
 665 }
 666
 667 /*
 668  * omap_write_buf_irq_pref - write buffer to NAND controller
 669  * @mtd: MTD device structure
 670  * @buf: data buffer
 671  * @len: number of bytes to write
 672  */
 673 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 674                                         const u_char *buf, int len)
 675 {
 676         struct omap_nand_info *info = container_of(mtd,
 677                                                 struct omap_nand_info, mtd);
 678         int ret = 0;
 679         unsigned long tim, limit;
 680         u32 val;
 681
 682         if (len <= mtd->oobsize) {
 683                 omap_write_buf_pref(mtd, buf, len);
 684                 return;
 685         }
 686
 687         info->iomode = OMAP_NAND_IO_WRITE;
 688         info->buf = (u_char *) buf;
 689         init_completion(&info->comp);
 690
 691         /* configure and start prefetch transfer : size=24 */
 692         ret = omap_prefetch_enable(info->gpmc_cs,
 693                 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
 694         if (ret)
 695                 /* PFPW engine is busy, use cpu copy method */
 696                 goto out_copy;
 697
 698         info->buf_len = len;
 699
 700         enable_irq(info->gpmc_irq_count);
 701         enable_irq(info->gpmc_irq_fifo);
 702
 703         /* waiting for write to complete */
 704         wait_for_completion(&info->comp);
 705
 706         /* wait for data to flushed-out before reset the prefetch */
 707         tim = 0;
 708         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 709         do {
 710                 val = readl(info->reg.gpmc_prefetch_status);
 711                 val = PREFETCH_STATUS_COUNT(val);
 712                 cpu_relax();
 713         } while (val && (tim++ < limit));
 714
 715         /* disable and stop the PFPW engine */
 716         omap_prefetch_reset(info->gpmc_cs, info);
 717         return;
 718
 719 out_copy:
 720         if (info->nand.options & NAND_BUSWIDTH_16)
 721                 omap_write_buf16(mtd, buf, len);
 722         else
 723                 omap_write_buf8(mtd, buf, len);
 724 }
 725
 726 /**
 727  * gen_true_ecc - This function will generate true ECC value
 728  * @ecc_buf: buffer to store ecc code
 729  *
 730  * This generated true ECC value can be used when correcting
 731  * data read from NAND flash memory core
 732  */
 733 static void gen_true_ecc(u8 *ecc_buf)
 734 {
 735         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 736                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 737
 738         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 739                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 740         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 741                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 742         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 743                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 744 }
 745
 746 /**
 747  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 748  * @ecc_data1:  ecc code from nand spare area
 749  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 750  * @page_data:  page data
 751  *
 752  * This function compares two ECC's and indicates if there is an error.
 753  * If the error can be corrected it will be corrected to the buffer.
 754  * If there is no error, %0 is returned. If there is an error but it
 755  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 756  */
 757 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 758                             u8 *ecc_data2,      /* read from register */
 759                             u8 *page_data)
 760 {
 761         uint    i;
 762         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 763         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 764         u8      ecc_bit[24];
 765         u8      ecc_sum = 0;
 766         u8      find_bit = 0;
 767         uint    find_byte = 0;
 768         int     isEccFF;
 769
 770         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 771
 772         gen_true_ecc(ecc_data1);
 773         gen_true_ecc(ecc_data2);
 774
 775         for (i = 0; i <= 2; i++) {
 776                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 777                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 778         }
 779
 780         for (i = 0; i < 8; i++) {
 781                 tmp0_bit[i]     = *ecc_data1 % 2;
 782                 *ecc_data1      = *ecc_data1 / 2;
 783         }
 784
 785         for (i = 0; i < 8; i++) {
 786                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 787                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 788         }
 789
 790         for (i = 0; i < 8; i++) {
 791                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 792                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 793         }
 794
 795         for (i = 0; i < 8; i++) {
 796                 comp0_bit[i]     = *ecc_data2 % 2;
 797                 *ecc_data2       = *ecc_data2 / 2;
 798         }
 799
 800         for (i = 0; i < 8; i++) {
 801                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 802                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 803         }
 804
 805         for (i = 0; i < 8; i++) {
 806                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 807                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 808         }
 809
 810         for (i = 0; i < 6; i++)
 811                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 812
 813         for (i = 0; i < 8; i++)
 814                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 815
 816         for (i = 0; i < 8; i++)
 817                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 818
 819         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 820         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 821
 822         for (i = 0; i < 24; i++)
 823                 ecc_sum += ecc_bit[i];
 824
 825         switch (ecc_sum) {
 826         case 0:
 827                 /* Not reached because this function is not called if
 828                  *  ECC values are equal
 829                  */
 830                 return 0;
 831
 832         case 1:
 833                 /* Uncorrectable error */
 834                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 835                 return -1;
 836
 837         case 11:
 838                 /* UN-Correctable error */
 839                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 840                 return -1;
 841
 842         case 12:
 843                 /* Correctable error */
 844                 find_byte = (ecc_bit[23] << 8) +
 845                             (ecc_bit[21] << 7) +
 846                             (ecc_bit[19] << 6) +
 847                             (ecc_bit[17] << 5) +
 848                             (ecc_bit[15] << 4) +
 849                             (ecc_bit[13] << 3) +
 850                             (ecc_bit[11] << 2) +
 851                             (ecc_bit[9]  << 1) +
 852                             ecc_bit[7];
 853
 854                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 855
 856                 pr_debug("Correcting single bit ECC error at offset: "
 857                                 "%d, bit: %d\n", find_byte, find_bit);
 858
 859                 page_data[find_byte] ^= (1 << find_bit);
 860
 861                 return 1;
 862         default:
 863                 if (isEccFF) {
 864                         if (ecc_data2[0] == 0 &&
 865                             ecc_data2[1] == 0 &&
 866                             ecc_data2[2] == 0)
 867                                 return 0;
 868                 }
 869                 pr_debug("UNCORRECTED_ERROR default\n");
 870                 return -1;
 871         }
 872 }
 873
 874 /**
 875  * omap_correct_data - Compares the ECC read with HW generated ECC
 876  * @mtd: MTD device structure
 877  * @dat: page data
 878  * @read_ecc: ecc read from nand flash
 879  * @calc_ecc: ecc read from HW ECC registers
 880  *
 881  * Compares the ecc read from nand spare area with ECC registers values
 882  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 883  * detection and correction. If there are no errors, %0 is returned. If
 884  * there were errors and all of the errors were corrected, the number of
 885  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 886  * returned.
 887  */
 888 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 889                                 u_char *read_ecc, u_char *calc_ecc)
 890 {
 891         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 892                                                         mtd);
 893         int blockCnt = 0, i = 0, ret = 0;
 894         int stat = 0;
 895
 896         /* Ex NAND_ECC_HW12_2048 */
 897         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 898                         (info->nand.ecc.size  == 2048))
 899                 blockCnt = 4;
 900         else
 901                 blockCnt = 1;
 902
 903         for (i = 0; i < blockCnt; i++) {
 904                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 905                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 906                         if (ret < 0)
 907                                 return ret;
 908                         /* keep track of the number of corrected errors */
 909                         stat += ret;
 910                 }
 911                 read_ecc += 3;
 912                 calc_ecc += 3;
 913                 dat      += 512;
 914         }
 915         return stat;
 916 }
 917
 918 /**
 919  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 920  * @mtd: MTD device structure
 921  * @dat: The pointer to data on which ecc is computed
 922  * @ecc_code: The ecc_code buffer
 923  *
 924  * Using noninverted ECC can be considered ugly since writing a blank
 925  * page ie. padding will clear the ECC bytes. This is no problem as long
 926  * nobody is trying to write data on the seemingly unused page. Reading
 927  * an erased page will produce an ECC mismatch between generated and read
 928  * ECC bytes that has to be dealt with separately.
 929  */
 930 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 931                                 u_char *ecc_code)
 932 {
 933         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 934                                                         mtd);
 935         u32 val;
 936
 937         val = readl(info->reg.gpmc_ecc_config);
 938         if (((val >> ECC_CONFIG_CS_SHIFT)  & ~CS_MASK) != info->gpmc_cs)
 939                 return -EINVAL;
 940
 941         /* read ecc result */
 942         val = readl(info->reg.gpmc_ecc1_result);
 943         *ecc_code++ = val;          /* P128e, ..., P1e */
 944         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
 945         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
 946         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
 947
 948         return 0;
 949 }
 950
 951 /**
 952  * omap_enable_hwecc - This function enables the hardware ecc functionality
 953  * @mtd: MTD device structure
 954  * @mode: Read/Write mode
 955  */
 956 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 957 {
 958         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 959                                                         mtd);
 960         struct nand_chip *chip = mtd->priv;
 961         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 962         u32 val;
 963
 964         /* clear ecc and enable bits */
 965         val = ECCCLEAR | ECC1;
 966         writel(val, info->reg.gpmc_ecc_control);
 967
 968         /* program ecc and result sizes */
 969         val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
 970                          ECC1RESULTSIZE);
 971         writel(val, info->reg.gpmc_ecc_size_config);
 972
 973         switch (mode) {
 974         case NAND_ECC_READ:
 975         case NAND_ECC_WRITE:
 976                 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
 977                 break;
 978         case NAND_ECC_READSYN:
 979                 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
 980                 break;
 981         default:
 982                 dev_info(&info->pdev->dev,
 983                         "error: unrecognized Mode[%d]!\n", mode);
 984                 break;
 985         }
 986
 987         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
 988         val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
 989         writel(val, info->reg.gpmc_ecc_config);
 990 }
 991
 992 /**
 993  * omap_wait - wait until the command is done
 994  * @mtd: MTD device structure
 995  * @chip: NAND Chip structure
 996  *
 997  * Wait function is called during Program and erase operations and
 998  * the way it is called from MTD layer, we should wait till the NAND
 999  * chip is ready after the programming/erase operation has completed.
1000  *
1001  * Erase can take up to 400ms and program up to 20ms according to
1002  * general NAND and SmartMedia specs
1003  */
1004 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
1005 {
1006         struct nand_chip *this = mtd->priv;
1007         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1008                                                         mtd);
1009         unsigned long timeo = jiffies;
1010         int status, state = this->state;
1011
1012         if (state == FL_ERASING)
1013                 timeo += msecs_to_jiffies(400);
1014         else
1015                 timeo += msecs_to_jiffies(20);
1016
1017         writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
1018         while (time_before(jiffies, timeo)) {
1019                 status = readb(info->reg.gpmc_nand_data);
1020                 if (status & NAND_STATUS_READY)
1021                         break;
1022                 cond_resched();
1023         }
1024
1025         status = readb(info->reg.gpmc_nand_data);
1026         return status;
1027 }
1028
1029 /**
1030  * omap_dev_ready - calls the platform specific dev_ready function
1031  * @mtd: MTD device structure
1032  */
1033 static int omap_dev_ready(struct mtd_info *mtd)
1034 {
1035         unsigned int val = 0;
1036         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1037                                                         mtd);
1038
1039         val = readl(info->reg.gpmc_status);
1040
1041         if ((val & 0x100) == 0x100) {
1042                 return 1;
1043         } else {
1044                 return 0;
1045         }
1046 }
1047
1048 #if defined(CONFIG_MTD_NAND_ECC_BCH) || defined(CONFIG_MTD_NAND_OMAP_BCH)
1049 /**
1050  * omap3_enable_hwecc_bch - Program OMAP3 GPMC to perform BCH ECC correction
1051  * @mtd: MTD device structure
1052  * @mode: Read/Write mode
1053  *
1054  * When using BCH, sector size is hardcoded to 512 bytes.
1055  * Using wrapping mode 6 both for reading and writing if ELM module not uses
1056  * for error correction.
1057  * On writing,
1058  * eccsize0 = 0  (no additional protected byte in spare area)
1059  * eccsize1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1060  */
1061 static void omap3_enable_hwecc_bch(struct mtd_info *mtd, int mode)
1062 {
1063         int nerrors;
1064         unsigned int dev_width, nsectors;
1065         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1066                                                    mtd);
1067         struct nand_chip *chip = mtd->priv;
1068         u32 val, wr_mode;
1069         unsigned int ecc_size1, ecc_size0;
1070
1071         /* Using wrapping mode 6 for writing */
1072         wr_mode = BCH_WRAPMODE_6;
1073
1074         /*
1075          * ECC engine enabled for valid ecc_size0 nibbles
1076          * and disabled for ecc_size1 nibbles.
1077          */
1078         ecc_size0 = BCH_ECC_SIZE0;
1079         ecc_size1 = BCH_ECC_SIZE1;
1080
1081         /* Perform ecc calculation on 512-byte sector */
1082         nsectors = 1;
1083
1084         /* Update number of error correction */
1085         nerrors = info->nand.ecc.strength;
1086
1087         /* Multi sector reading/writing for NAND flash with page size < 4096 */
1088         if (info->is_elm_used && (mtd->writesize <= 4096)) {
1089                 if (mode == NAND_ECC_READ) {
1090                         /* Using wrapping mode 1 for reading */
1091                         wr_mode = BCH_WRAPMODE_1;
1092
1093                         /*
1094                          * ECC engine enabled for ecc_size0 nibbles
1095                          * and disabled for ecc_size1 nibbles.
1096                          */
1097                         ecc_size0 = (nerrors == 8) ?
1098                                 BCH8R_ECC_SIZE0 : BCH4R_ECC_SIZE0;
1099                         ecc_size1 = (nerrors == 8) ?
1100                                 BCH8R_ECC_SIZE1 : BCH4R_ECC_SIZE1;
1101                 }
1102
1103                 /* Perform ecc calculation for one page (< 4096) */
1104                 nsectors = info->nand.ecc.steps;
1105         }
1106
1107         writel(ECC1, info->reg.gpmc_ecc_control);
1108
1109         /* Configure ecc size for BCH */
1110         val = (ecc_size1 << ECCSIZE1_SHIFT) | (ecc_size0 << ECCSIZE0_SHIFT);
1111         writel(val, info->reg.gpmc_ecc_size_config);
1112
1113         dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
1114
1115         /* BCH configuration */
1116         val = ((1                        << 16) | /* enable BCH */
1117                (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1118                (wr_mode                  <<  8) | /* wrap mode */
1119                (dev_width                <<  7) | /* bus width */
1120                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1121                (info->gpmc_cs            <<  1) | /* ECC CS */
1122                (0x1));                            /* enable ECC */
1123
1124         writel(val, info->reg.gpmc_ecc_config);
1125
1126         /* Clear ecc and enable bits */
1127         writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
1128 }
1129 #endif
1130
1131 #ifdef CONFIG_MTD_NAND_ECC_BCH
1132 /**
1133  * omap3_calculate_ecc_bch4 - Generate 7 bytes of ECC bytes
1134  * @mtd: MTD device structure
1135  * @dat: The pointer to data on which ecc is computed
1136  * @ecc_code: The ecc_code buffer
1137  */
1138 static int omap3_calculate_ecc_bch4(struct mtd_info *mtd, const u_char *dat,
1139                                     u_char *ecc_code)
1140 {
1141         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1142                                                    mtd);
1143         unsigned long nsectors, val1, val2;
1144         int i;
1145
1146         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1147
1148         for (i = 0; i < nsectors; i++) {
1149
1150                 /* Read hw-computed remainder */
1151                 val1 = readl(info->reg.gpmc_bch_result0[i]);
1152                 val2 = readl(info->reg.gpmc_bch_result1[i]);
1153
1154                 /*
1155                  * Add constant polynomial to remainder, in order to get an ecc
1156                  * sequence of 0xFFs for a buffer filled with 0xFFs; and
1157                  * left-justify the resulting polynomial.
1158                  */
1159                 *ecc_code++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1160                 *ecc_code++ = 0x13 ^ ((val2 >>  4) & 0xFF);
1161                 *ecc_code++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1162                 *ecc_code++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1163                 *ecc_code++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1164                 *ecc_code++ = 0xac ^ ((val1 >> 4) & 0xFF);
1165                 *ecc_code++ = 0x7f ^ ((val1 & 0xF) << 4);
1166         }
1167
1168         return 0;
1169 }
1170
1171 /**
1172  * omap3_calculate_ecc_bch8 - Generate 13 bytes of ECC bytes
1173  * @mtd: MTD device structure
1174  * @dat: The pointer to data on which ecc is computed
1175  * @ecc_code: The ecc_code buffer
1176  */
1177 static int omap3_calculate_ecc_bch8(struct mtd_info *mtd, const u_char *dat,
1178                                     u_char *ecc_code)
1179 {
1180         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1181                                                    mtd);
1182         unsigned long nsectors, val1, val2, val3, val4;
1183         int i;
1184
1185         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1186
1187         for (i = 0; i < nsectors; i++) {
1188
1189                 /* Read hw-computed remainder */
1190                 val1 = readl(info->reg.gpmc_bch_result0[i]);
1191                 val2 = readl(info->reg.gpmc_bch_result1[i]);
1192                 val3 = readl(info->reg.gpmc_bch_result2[i]);
1193                 val4 = readl(info->reg.gpmc_bch_result3[i]);
1194
1195                 /*
1196                  * Add constant polynomial to remainder, in order to get an ecc
1197                  * sequence of 0xFFs for a buffer filled with 0xFFs.
1198                  */
1199                 *ecc_code++ = 0xef ^ (val4 & 0xFF);
1200                 *ecc_code++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1201                 *ecc_code++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1202                 *ecc_code++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1203                 *ecc_code++ = 0xed ^ (val3 & 0xFF);
1204                 *ecc_code++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1205                 *ecc_code++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1206                 *ecc_code++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1207                 *ecc_code++ = 0x97 ^ (val2 & 0xFF);
1208                 *ecc_code++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1209                 *ecc_code++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1210                 *ecc_code++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1211                 *ecc_code++ = 0xb5 ^ (val1 & 0xFF);
1212         }
1213
1214         return 0;
1215 }
1216 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1217
1218 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1219 /**
1220  * omap3_calculate_ecc_bch - Generate bytes of ECC bytes
1221  * @mtd:        MTD device structure
1222  * @dat:        The pointer to data on which ecc is computed
1223  * @ecc_code:   The ecc_code buffer
1224  *
1225  * Support calculating of BCH4/8 ecc vectors for the page
1226  */
1227 static int omap3_calculate_ecc_bch(struct mtd_info *mtd, const u_char *dat,
1228                                     u_char *ecc_code)
1229 {
1230         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1231                                                    mtd);
1232         unsigned long nsectors, bch_val1, bch_val2, bch_val3, bch_val4;
1233         int i, eccbchtsel;
1234
1235         nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1;
1236         /*
1237          * find BCH scheme used
1238          * 0 -> BCH4
1239          * 1 -> BCH8
1240          */
1241         eccbchtsel = ((readl(info->reg.gpmc_ecc_config) >> 12) & 0x3);
1242
1243         for (i = 0; i < nsectors; i++) {
1244
1245                 /* Read hw-computed remainder */
1246                 bch_val1 = readl(info->reg.gpmc_bch_result0[i]);
1247                 bch_val2 = readl(info->reg.gpmc_bch_result1[i]);
1248                 if (eccbchtsel) {
1249                         bch_val3 = readl(info->reg.gpmc_bch_result2[i]);
1250                         bch_val4 = readl(info->reg.gpmc_bch_result3[i]);
1251                 }
1252
1253                 if (eccbchtsel) {
1254                         /* BCH8 ecc scheme */
1255                         *ecc_code++ = (bch_val4 & 0xFF);
1256                         *ecc_code++ = ((bch_val3 >> 24) & 0xFF);
1257                         *ecc_code++ = ((bch_val3 >> 16) & 0xFF);
1258                         *ecc_code++ = ((bch_val3 >> 8) & 0xFF);
1259                         *ecc_code++ = (bch_val3 & 0xFF);
1260                         *ecc_code++ = ((bch_val2 >> 24) & 0xFF);
1261                         *ecc_code++ = ((bch_val2 >> 16) & 0xFF);
1262                         *ecc_code++ = ((bch_val2 >> 8) & 0xFF);
1263                         *ecc_code++ = (bch_val2 & 0xFF);
1264                         *ecc_code++ = ((bch_val1 >> 24) & 0xFF);
1265                         *ecc_code++ = ((bch_val1 >> 16) & 0xFF);
1266                         *ecc_code++ = ((bch_val1 >> 8) & 0xFF);
1267                         *ecc_code++ = (bch_val1 & 0xFF);
1268                         /*
1269                          * Setting 14th byte to zero to handle
1270                          * erased page & maintain compatibility
1271                          * with RBL
1272                          */
1273                         *ecc_code++ = 0x0;
1274                 } else {
1275                         /* BCH4 ecc scheme */
1276                         *ecc_code++ = ((bch_val2 >> 12) & 0xFF);
1277                         *ecc_code++ = ((bch_val2 >> 4) & 0xFF);
1278                         *ecc_code++ = ((bch_val2 & 0xF) << 4) |
1279                                 ((bch_val1 >> 28) & 0xF);
1280                         *ecc_code++ = ((bch_val1 >> 20) & 0xFF);
1281                         *ecc_code++ = ((bch_val1 >> 12) & 0xFF);
1282                         *ecc_code++ = ((bch_val1 >> 4) & 0xFF);
1283                         *ecc_code++ = ((bch_val1 & 0xF) << 4);
1284                         /*
1285                          * Setting 8th byte to zero to handle
1286                          * erased page
1287                          */
1288                         *ecc_code++ = 0x0;
1289                 }
1290         }
1291
1292         return 0;
1293 }
1294
1295 /**
1296  * erased_sector_bitflips - count bit flips
1297  * @data:       data sector buffer
1298  * @oob:        oob buffer
1299  * @info:       omap_nand_info
1300  *
1301  * Check the bit flips in erased page falls below correctable level.
1302  * If falls below, report the page as erased with correctable bit
1303  * flip, else report as uncorrectable page.
1304  */
1305 static int erased_sector_bitflips(u_char *data, u_char *oob,
1306                 struct omap_nand_info *info)
1307 {
1308         int flip_bits = 0, i;
1309
1310         for (i = 0; i < info->nand.ecc.size; i++) {
1311                 flip_bits += hweight8(~data[i]);
1312                 if (flip_bits > info->nand.ecc.strength)
1313                         return 0;
1314         }
1315
1316         for (i = 0; i < info->nand.ecc.bytes - 1; i++) {
1317                 flip_bits += hweight8(~oob[i]);
1318                 if (flip_bits > info->nand.ecc.strength)
1319                         return 0;
1320         }
1321
1322         /*
1323          * Bit flips falls in correctable level.
1324          * Fill data area with 0xFF
1325          */
1326         if (flip_bits) {
1327                 memset(data, 0xFF, info->nand.ecc.size);
1328                 memset(oob, 0xFF, info->nand.ecc.bytes);
1329         }
1330
1331         return flip_bits;
1332 }
1333
1334 /**
1335  * omap_elm_correct_data - corrects page data area in case error reported
1336  * @mtd:        MTD device structure
1337  * @data:       page data
1338  * @read_ecc:   ecc read from nand flash
1339  * @calc_ecc:   ecc read from HW ECC registers
1340  *
1341  * Calculated ecc vector reported as zero in case of non-error pages.
1342  * In case of error/erased pages non-zero error vector is reported.
1343  * In case of non-zero ecc vector, check read_ecc at fixed offset
1344  * (x = 13/7 in case of BCH8/4 == 0) to find page programmed or not.
1345  * To handle bit flips in this data, count the number of 0's in
1346  * read_ecc[x] and check if it greater than 4. If it is less, it is
1347  * programmed page, else erased page.
1348  *
1349  * 1. If page is erased, check with standard ecc vector (ecc vector
1350  * for erased page to find any bit flip). If check fails, bit flip
1351  * is present in erased page. Count the bit flips in erased page and
1352  * if it falls under correctable level, report page with 0xFF and
1353  * update the correctable bit information.
1354  * 2. If error is reported on programmed page, update elm error
1355  * vector and correct the page with ELM error correction routine.
1356  *
1357  */
1358 static int omap_elm_correct_data(struct mtd_info *mtd, u_char *data,
1359                                 u_char *read_ecc, u_char *calc_ecc)
1360 {
1361         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1362                         mtd);
1363         int eccsteps = info->nand.ecc.steps;
1364         int i , j, stat = 0;
1365         int eccsize, eccflag, ecc_vector_size;
1366         struct elm_errorvec err_vec[ERROR_VECTOR_MAX];
1367         u_char *ecc_vec = calc_ecc;
1368         u_char *spare_ecc = read_ecc;
1369         u_char *erased_ecc_vec;
1370         enum bch_ecc type;
1371         bool is_error_reported = false;
1372
1373         /* Initialize elm error vector to zero */
1374         memset(err_vec, 0, sizeof(err_vec));
1375
1376         if (info->nand.ecc.strength == BCH8_MAX_ERROR) {
1377                 type = BCH8_ECC;
1378                 erased_ecc_vec = bch8_vector;
1379         } else {
1380                 type = BCH4_ECC;
1381                 erased_ecc_vec = bch4_vector;
1382         }
1383
1384         ecc_vector_size = info->nand.ecc.bytes;
1385
1386         /*
1387          * Remove extra byte padding for BCH8 RBL
1388          * compatibility and erased page handling
1389          */
1390         eccsize = ecc_vector_size - 1;
1391
1392         for (i = 0; i < eccsteps ; i++) {
1393                 eccflag = 0;    /* initialize eccflag */
1394
1395                 /*
1396                  * Check any error reported,
1397                  * In case of error, non zero ecc reported.
1398                  */
1399
1400                 for (j = 0; (j < eccsize); j++) {
1401                         if (calc_ecc[j] != 0) {
1402                                 eccflag = 1; /* non zero ecc, error present */
1403                                 break;
1404                         }
1405                 }
1406
1407                 if (eccflag == 1) {
1408                         /*
1409                          * Set threshold to minimum of 4, half of ecc.strength/2
1410                          * to allow max bit flip in byte to 4
1411                          */
1412                         unsigned int threshold = min_t(unsigned int, 4,
1413                                         info->nand.ecc.strength / 2);
1414
1415                         /*
1416                          * Check data area is programmed by counting
1417                          * number of 0's at fixed offset in spare area.
1418                          * Checking count of 0's against threshold.
1419                          * In case programmed page expects at least threshold
1420                          * zeros in byte.
1421                          * If zeros are less than threshold for programmed page/
1422                          * zeros are more than threshold erased page, either
1423                          * case page reported as uncorrectable.
1424                          */
1425                         if (hweight8(~read_ecc[eccsize]) >= threshold) {
1426                                 /*
1427                                  * Update elm error vector as
1428                                  * data area is programmed
1429                                  */
1430                                 err_vec[i].error_reported = true;
1431                                 is_error_reported = true;
1432                         } else {
1433                                 /* Error reported in erased page */
1434                                 int bitflip_count;
1435                                 u_char *buf = &data[info->nand.ecc.size * i];
1436
1437                                 if (memcmp(calc_ecc, erased_ecc_vec, eccsize)) {
1438                                         bitflip_count = erased_sector_bitflips(
1439                                                         buf, read_ecc, info);
1440
1441                                         if (bitflip_count)
1442                                                 stat += bitflip_count;
1443                                         else
1444                                                 return -EINVAL;
1445                                 }
1446                         }
1447                 }
1448
1449                 /* Update the ecc vector */
1450                 calc_ecc += ecc_vector_size;
1451                 read_ecc += ecc_vector_size;
1452         }
1453
1454         /* Check if any error reported */
1455         if (!is_error_reported)
1456                 return 0;
1457
1458         /* Decode BCH error using ELM module */
1459         elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
1460
1461         for (i = 0; i < eccsteps; i++) {
1462                 if (err_vec[i].error_reported) {
1463                         for (j = 0; j < err_vec[i].error_count; j++) {
1464                                 u32 bit_pos, byte_pos, error_max, pos;
1465
1466                                 if (type == BCH8_ECC)
1467                                         error_max = BCH8_ECC_MAX;
1468                                 else
1469                                         error_max = BCH4_ECC_MAX;
1470
1471                                 if (info->nand.ecc.strength == BCH8_MAX_ERROR)
1472                                         pos = err_vec[i].error_loc[j];
1473                                 else
1474                                         /* Add 4 to take care 4 bit padding */
1475                                         pos = err_vec[i].error_loc[j] +
1476                                                 BCH4_BIT_PAD;
1477
1478                                 /* Calculate bit position of error */
1479                                 bit_pos = pos % 8;
1480
1481                                 /* Calculate byte position of error */
1482                                 byte_pos = (error_max - pos - 1) / 8;
1483
1484                                 if (pos < error_max) {
1485                                         if (byte_pos < 512)
1486                                                 data[byte_pos] ^= 1 << bit_pos;
1487                                         else
1488                                                 spare_ecc[byte_pos - 512] ^=
1489                                                         1 << bit_pos;
1490                                 }
1491                                 /* else, not interested to correct ecc */
1492                         }
1493                 }
1494
1495                 /* Update number of correctable errors */
1496                 stat += err_vec[i].error_count;
1497
1498                 /* Update page data with sector size */
1499                 data += info->nand.ecc.size;
1500                 spare_ecc += ecc_vector_size;
1501         }
1502
1503         for (i = 0; i < eccsteps; i++)
1504                 /* Return error if uncorrectable error present */
1505                 if (err_vec[i].error_uncorrectable)
1506                         return -EINVAL;
1507
1508         return stat;
1509 }
1510 #endif /* CONFIG_MTD_NAND_OMAP_BCH */
1511
1512 #ifdef CONFIG_MTD_NAND_ECC_BCH
1513 /**
1514  * omap3_correct_data_bch - Decode received data and correct errors
1515  * @mtd: MTD device structure
1516  * @data: page data
1517  * @read_ecc: ecc read from nand flash
1518  * @calc_ecc: ecc read from HW ECC registers
1519  */
1520 static int omap3_correct_data_bch(struct mtd_info *mtd, u_char *data,
1521                                   u_char *read_ecc, u_char *calc_ecc)
1522 {
1523         int i, count;
1524         /* cannot correct more than 8 errors */
1525         unsigned int errloc[8];
1526         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1527                                                    mtd);
1528
1529         count = decode_bch(info->bch, NULL, 512, read_ecc, calc_ecc, NULL,
1530                            errloc);
1531         if (count > 0) {
1532                 /* correct errors */
1533                 for (i = 0; i < count; i++) {
1534                         /* correct data only, not ecc bytes */
1535                         if (errloc[i] < 8*512)
1536                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
1537                         pr_debug("corrected bitflip %u\n", errloc[i]);
1538                 }
1539         } else if (count < 0) {
1540                 pr_err("ecc unrecoverable error\n");
1541         }
1542         return count;
1543 }
1544 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1545
1546 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1547 /**
1548  * omap_write_page_bch - BCH ecc based write page function for entire page
1549  * @mtd:                mtd info structure
1550  * @chip:               nand chip info structure
1551  * @buf:                data buffer
1552  * @oob_required:       must write chip->oob_poi to OOB
1553  *
1554  * Custom write page method evolved to support multi sector writing in one shot
1555  */
1556 static int omap_write_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1557                                   const uint8_t *buf, int oob_required)
1558 {
1559         int i;
1560         uint8_t *ecc_calc = chip->buffers->ecccalc;
1561         uint32_t *eccpos = chip->ecc.layout->eccpos;
1562
1563         /* Enable GPMC ecc engine */
1564         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1565
1566         /* Write data */
1567         chip->write_buf(mtd, buf, mtd->writesize);
1568
1569         /* Update ecc vector from GPMC result registers */
1570         chip->ecc.calculate(mtd, buf, &ecc_calc[0]);
1571
1572         for (i = 0; i < chip->ecc.total; i++)
1573                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1574
1575         /* Write ecc vector to OOB area */
1576         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1577         return 0;
1578 }
1579
1580 /**
1581  * omap_read_page_bch - BCH ecc based page read function for entire page
1582  * @mtd:                mtd info structure
1583  * @chip:               nand chip info structure
1584  * @buf:                buffer to store read data
1585  * @oob_required:       caller requires OOB data read to chip->oob_poi
1586  * @page:               page number to read
1587  *
1588  * For BCH ecc scheme, GPMC used for syndrome calculation and ELM module
1589  * used for error correction.
1590  * Custom method evolved to support ELM error correction & multi sector
1591  * reading. On reading page data area is read along with OOB data with
1592  * ecc engine enabled. ecc vector updated after read of OOB data.
1593  * For non error pages ecc vector reported as zero.
1594  */
1595 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
1596                                 uint8_t *buf, int oob_required, int page)
1597 {
1598         uint8_t *ecc_calc = chip->buffers->ecccalc;
1599         uint8_t *ecc_code = chip->buffers->ecccode;
1600         uint32_t *eccpos = chip->ecc.layout->eccpos;
1601         uint8_t *oob = &chip->oob_poi[eccpos[0]];
1602         uint32_t oob_pos = mtd->writesize + chip->ecc.layout->eccpos[0];
1603         int stat;
1604         unsigned int max_bitflips = 0;
1605
1606         /* Enable GPMC ecc engine */
1607         chip->ecc.hwctl(mtd, NAND_ECC_READ);
1608
1609         /* Read data */
1610         chip->read_buf(mtd, buf, mtd->writesize);
1611
1612         /* Read oob bytes */
1613         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
1614         chip->read_buf(mtd, oob, chip->ecc.total);
1615
1616         /* Calculate ecc bytes */
1617         chip->ecc.calculate(mtd, buf, ecc_calc);
1618
1619         memcpy(ecc_code, &chip->oob_poi[eccpos[0]], chip->ecc.total);
1620
1621         stat = chip->ecc.correct(mtd, buf, ecc_code, ecc_calc);
1622
1623         if (stat < 0) {
1624                 mtd->ecc_stats.failed++;
1625         } else {
1626                 mtd->ecc_stats.corrected += stat;
1627                 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1628         }
1629
1630         return max_bitflips;
1631 }
1632
1633 /**
1634  * is_elm_present - checks for presence of ELM module by scanning DT nodes
1635  * @omap_nand_info: NAND device structure containing platform data
1636  * @bch_type: 0x0=BCH4, 0x1=BCH8, 0x2=BCH16
1637  */
1638 static int is_elm_present(struct omap_nand_info *info,
1639                         struct device_node *elm_node, enum bch_ecc bch_type)
1640 {
1641         struct platform_device *pdev;
1642         info->is_elm_used = false;
1643         /* check whether elm-id is passed via DT */
1644         if (!elm_node) {
1645                 pr_err("nand: error: ELM DT node not found\n");
1646                 return -ENODEV;
1647         }
1648         pdev = of_find_device_by_node(elm_node);
1649         /* check whether ELM device is registered */
1650         if (!pdev) {
1651                 pr_err("nand: error: ELM device not found\n");
1652                 return -ENODEV;
1653         }
1654         /* ELM module available, now configure it */
1655         info->elm_dev = &pdev->dev;
1656         if (elm_config(info->elm_dev, bch_type))
1657                 return -ENODEV;
1658         info->is_elm_used = true;
1659         return 0;
1660 }
1661 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1662
1663 #ifdef CONFIG_MTD_NAND_ECC_BCH
1664 /**
1665  * omap3_free_bch - Release BCH ecc resources
1666  * @mtd: MTD device structure
1667  */
1668 static void omap3_free_bch(struct mtd_info *mtd)
1669 {
1670         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1671                                                    mtd);
1672         if (info->bch) {
1673                 free_bch(info->bch);
1674                 info->bch = NULL;
1675         }
1676 }
1677
1678 #else
1679
1680 static void omap3_free_bch(struct mtd_info *mtd)
1681 {
1682 }
1683 #endif /* CONFIG_MTD_NAND_ECC_BCH */
1684
1685 static int omap_nand_probe(struct platform_device *pdev)
1686 {
1687         struct omap_nand_info           *info;
1688         struct omap_nand_platform_data  *pdata;
1689         struct mtd_info                 *mtd;
1690         struct nand_chip                *nand_chip;
1691         struct nand_ecclayout           *ecclayout;
1692         int                             err;
1693         int                             i;
1694         dma_cap_mask_t                  mask;
1695         unsigned                        sig;
1696         struct resource                 *res;
1697         struct mtd_part_parser_data     ppdata = {};
1698
1699         pdata = dev_get_platdata(&pdev->dev);
1700         if (pdata == NULL) {
1701                 dev_err(&pdev->dev, "platform data missing\n");
1702                 return -ENODEV;
1703         }
1704
1705         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
1706         if (!info)
1707                 return -ENOMEM;
1708
1709         platform_set_drvdata(pdev, info);
1710
1711         spin_lock_init(&info->controller.lock);
1712         init_waitqueue_head(&info->controller.wq);
1713
1714         info->pdev              = pdev;
1715         info->gpmc_cs           = pdata->cs;
1716         info->reg               = pdata->reg;
1717         info->bch               = NULL;
1718         info->of_node           = pdata->of_node;
1719         mtd                     = &info->mtd;
1720         mtd->priv               = &info->nand;
1721         mtd->name               = dev_name(&pdev->dev);
1722         mtd->owner              = THIS_MODULE;
1723         nand_chip               = &info->nand;
1724         nand_chip->options      |= NAND_SKIP_BBTSCAN;
1725
1726         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1727         if (res == NULL) {
1728                 err = -EINVAL;
1729                 dev_err(&pdev->dev, "error getting memory resource\n");
1730                 goto out_free_info;
1731         }
1732
1733         info->phys_base = res->start;
1734         info->mem_size = resource_size(res);
1735
1736         if (!request_mem_region(info->phys_base, info->mem_size,
1737                                 pdev->dev.driver->name)) {
1738                 err = -EBUSY;
1739                 goto out_free_info;
1740         }
1741
1742         nand_chip->IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
1743         if (!nand_chip->IO_ADDR_R) {
1744                 err = -ENOMEM;
1745                 goto out_release_mem_region;
1746         }
1747
1748         nand_chip->controller = &info->controller;
1749
1750         nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
1751         nand_chip->cmd_ctrl  = omap_hwcontrol;
1752
1753         /*
1754          * If RDY/BSY line is connected to OMAP then use the omap ready
1755          * function and the generic nand_wait function which reads the status
1756          * register after monitoring the RDY/BSY line. Otherwise use a standard
1757          * chip delay which is slightly more than tR (AC Timing) of the NAND
1758          * device and read status register until you get a failure or success
1759          */
1760         if (pdata->dev_ready) {
1761                 nand_chip->dev_ready = omap_dev_ready;
1762                 nand_chip->chip_delay = 0;
1763         } else {
1764                 nand_chip->waitfunc = omap_wait;
1765                 nand_chip->chip_delay = 50;
1766         }
1767
1768         /* scan NAND device connected to chip controller */
1769         nand_chip->options |= pdata->devsize & NAND_BUSWIDTH_16;
1770         if (nand_scan_ident(mtd, 1, NULL)) {
1771                 pr_err("nand device scan failed, may be bus-width mismatch\n");
1772                 err = -ENXIO;
1773                 goto out_release_mem_region;
1774         }
1775
1776         /* check for small page devices */
1777         if ((mtd->oobsize < 64) && (pdata->ecc_opt != OMAP_ECC_HAM1_CODE_HW)) {
1778                 pr_err("small page devices are not supported\n");
1779                 err = -EINVAL;
1780                 goto out_release_mem_region;
1781         }
1782
1783         /* re-populate low-level callbacks based on xfer modes */
1784         switch (pdata->xfer_type) {
1785         case NAND_OMAP_PREFETCH_POLLED:
1786                 nand_chip->read_buf   = omap_read_buf_pref;
1787                 nand_chip->write_buf  = omap_write_buf_pref;
1788                 break;
1789
1790         case NAND_OMAP_POLLED:
1791                 if (nand_chip->options & NAND_BUSWIDTH_16) {
1792                         nand_chip->read_buf   = omap_read_buf16;
1793                         nand_chip->write_buf  = omap_write_buf16;
1794                 } else {
1795                         nand_chip->read_buf   = omap_read_buf8;
1796                         nand_chip->write_buf  = omap_write_buf8;
1797                 }
1798                 break;
1799
1800         case NAND_OMAP_PREFETCH_DMA:
1801                 dma_cap_zero(mask);
1802                 dma_cap_set(DMA_SLAVE, mask);
1803                 sig = OMAP24XX_DMA_GPMC;
1804                 info->dma = dma_request_channel(mask, omap_dma_filter_fn, &sig);
1805                 if (!info->dma) {
1806                         dev_err(&pdev->dev, "DMA engine request failed\n");
1807                         err = -ENXIO;
1808                         goto out_release_mem_region;
1809                 } else {
1810                         struct dma_slave_config cfg;
1811
1812                         memset(&cfg, 0, sizeof(cfg));
1813                         cfg.src_addr = info->phys_base;
1814                         cfg.dst_addr = info->phys_base;
1815                         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1816                         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1817                         cfg.src_maxburst = 16;
1818                         cfg.dst_maxburst = 16;
1819                         err = dmaengine_slave_config(info->dma, &cfg);
1820                         if (err) {
1821                                 dev_err(&pdev->dev, "DMA engine slave config failed: %d\n",
1822                                         err);
1823                                 goto out_release_mem_region;
1824                         }
1825                         nand_chip->read_buf   = omap_read_buf_dma_pref;
1826                         nand_chip->write_buf  = omap_write_buf_dma_pref;
1827                 }
1828                 break;
1829
1830         case NAND_OMAP_PREFETCH_IRQ:
1831                 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1832                 if (info->gpmc_irq_fifo <= 0) {
1833                         dev_err(&pdev->dev, "error getting fifo irq\n");
1834                         err = -ENODEV;
1835                         goto out_release_mem_region;
1836                 }
1837                 err = request_irq(info->gpmc_irq_fifo,  omap_nand_irq,
1838                                         IRQF_SHARED, "gpmc-nand-fifo", info);
1839                 if (err) {
1840                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1841                                                 info->gpmc_irq_fifo, err);
1842                         info->gpmc_irq_fifo = 0;
1843                         goto out_release_mem_region;
1844                 }
1845
1846                 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1847                 if (info->gpmc_irq_count <= 0) {
1848                         dev_err(&pdev->dev, "error getting count irq\n");
1849                         err = -ENODEV;
1850                         goto out_release_mem_region;
1851                 }
1852                 err = request_irq(info->gpmc_irq_count, omap_nand_irq,
1853                                         IRQF_SHARED, "gpmc-nand-count", info);
1854                 if (err) {
1855                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1856                                                 info->gpmc_irq_count, err);
1857                         info->gpmc_irq_count = 0;
1858                         goto out_release_mem_region;
1859                 }
1860
1861                 nand_chip->read_buf  = omap_read_buf_irq_pref;
1862                 nand_chip->write_buf = omap_write_buf_irq_pref;
1863
1864                 break;
1865
1866         default:
1867                 dev_err(&pdev->dev,
1868                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1869                 err = -EINVAL;
1870                 goto out_release_mem_region;
1871         }
1872
1873         /* populate MTD interface based on ECC scheme */
1874         nand_chip->ecc.layout   = &omap_oobinfo;
1875         ecclayout               = &omap_oobinfo;
1876         switch (pdata->ecc_opt) {
1877         case OMAP_ECC_HAM1_CODE_HW:
1878                 pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
1879                 nand_chip->ecc.mode             = NAND_ECC_HW;
1880                 nand_chip->ecc.bytes            = 3;
1881                 nand_chip->ecc.size             = 512;
1882                 nand_chip->ecc.strength         = 1;
1883                 nand_chip->ecc.calculate        = omap_calculate_ecc;
1884                 nand_chip->ecc.hwctl            = omap_enable_hwecc;
1885                 nand_chip->ecc.correct          = omap_correct_data;
1886                 /* define ECC layout */
1887                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1888                                                         (mtd->writesize /
1889                                                         nand_chip->ecc.size);
1890                 if (nand_chip->options & NAND_BUSWIDTH_16)
1891                         ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
1892                 else
1893                         ecclayout->eccpos[0]    = 1;
1894                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1895                                                         ecclayout->eccbytes;
1896                 break;
1897
1898         case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW:
1899 #ifdef CONFIG_MTD_NAND_ECC_BCH
1900                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n");
1901                 nand_chip->ecc.mode             = NAND_ECC_HW;
1902                 nand_chip->ecc.size             = 512;
1903                 nand_chip->ecc.bytes            = 7;
1904                 nand_chip->ecc.strength         = 4;
1905                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1906                 nand_chip->ecc.correct          = omap3_correct_data_bch;
1907                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch4;
1908                 /* define ECC layout */
1909                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1910                                                         (mtd->writesize /
1911                                                         nand_chip->ecc.size);
1912                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1913                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1914                                                         ecclayout->eccbytes;
1915                 /* software bch library is used for locating errors */
1916                 info->bch = init_bch(nand_chip->ecc.bytes,
1917                                         nand_chip->ecc.strength,
1918                                         OMAP_ECC_BCH8_POLYNOMIAL);
1919                 if (!info->bch) {
1920                         pr_err("nand: error: unable to use s/w BCH library\n");
1921                         err = -EINVAL;
1922                 }
1923                 break;
1924 #else
1925                 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1926                 err = -EINVAL;
1927                 goto out_release_mem_region;
1928 #endif
1929
1930         case OMAP_ECC_BCH4_CODE_HW:
1931 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1932                 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n");
1933                 nand_chip->ecc.mode             = NAND_ECC_HW;
1934                 nand_chip->ecc.size             = 512;
1935                 /* 14th bit is kept reserved for ROM-code compatibility */
1936                 nand_chip->ecc.bytes            = 7 + 1;
1937                 nand_chip->ecc.strength         = 4;
1938                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1939                 nand_chip->ecc.correct          = omap_elm_correct_data;
1940                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch;
1941                 nand_chip->ecc.read_page        = omap_read_page_bch;
1942                 nand_chip->ecc.write_page       = omap_write_page_bch;
1943                 /* define ECC layout */
1944                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1945                                                         (mtd->writesize /
1946                                                         nand_chip->ecc.size);
1947                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1948                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1949                                                         ecclayout->eccbytes;
1950                 /* This ECC scheme requires ELM H/W block */
1951                 if (is_elm_present(info, pdata->elm_of_node, BCH4_ECC) < 0) {
1952                         pr_err("nand: error: could not initialize ELM\n");
1953                         err = -ENODEV;
1954                         goto out_release_mem_region;
1955                 }
1956                 break;
1957 #else
1958                 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
1959                 err = -EINVAL;
1960                 goto out_release_mem_region;
1961 #endif
1962
1963         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
1964 #ifdef CONFIG_MTD_NAND_ECC_BCH
1965                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
1966                 nand_chip->ecc.mode             = NAND_ECC_HW;
1967                 nand_chip->ecc.size             = 512;
1968                 nand_chip->ecc.bytes            = 13;
1969                 nand_chip->ecc.strength         = 8;
1970                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
1971                 nand_chip->ecc.correct          = omap3_correct_data_bch;
1972                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch8;
1973                 /* define ECC layout */
1974                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
1975                                                         (mtd->writesize /
1976                                                         nand_chip->ecc.size);
1977                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
1978                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
1979                                                         ecclayout->eccbytes;
1980                 /* software bch library is used for locating errors */
1981                 info->bch = init_bch(nand_chip->ecc.bytes,
1982                                         nand_chip->ecc.strength,
1983                                         OMAP_ECC_BCH8_POLYNOMIAL);
1984                 if (!info->bch) {
1985                         pr_err("nand: error: unable to use s/w BCH library\n");
1986                         err = -EINVAL;
1987                         goto out_release_mem_region;
1988                 }
1989                 break;
1990 #else
1991                 pr_err("nand: error: CONFIG_MTD_NAND_ECC_BCH not enabled\n");
1992                 err = -EINVAL;
1993                 goto out_release_mem_region;
1994 #endif
1995
1996         case OMAP_ECC_BCH8_CODE_HW:
1997 #ifdef CONFIG_MTD_NAND_OMAP_BCH
1998                 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n");
1999                 nand_chip->ecc.mode             = NAND_ECC_HW;
2000                 nand_chip->ecc.size             = 512;
2001                 /* 14th bit is kept reserved for ROM-code compatibility */
2002                 nand_chip->ecc.bytes            = 13 + 1;
2003                 nand_chip->ecc.strength         = 8;
2004                 nand_chip->ecc.hwctl            = omap3_enable_hwecc_bch;
2005                 nand_chip->ecc.correct          = omap_elm_correct_data;
2006                 nand_chip->ecc.calculate        = omap3_calculate_ecc_bch;
2007                 nand_chip->ecc.read_page        = omap_read_page_bch;
2008                 nand_chip->ecc.write_page       = omap_write_page_bch;
2009                 /* This ECC scheme requires ELM H/W block */
2010                 if (is_elm_present(info, pdata->elm_of_node, BCH8_ECC) < 0) {
2011                         pr_err("nand: error: could not initialize ELM\n");
2012                         goto out_release_mem_region;
2013                 }
2014                 /* define ECC layout */
2015                 ecclayout->eccbytes             = nand_chip->ecc.bytes *
2016                                                         (mtd->writesize /
2017                                                         nand_chip->ecc.size);
2018                 ecclayout->eccpos[0]            = BADBLOCK_MARKER_LENGTH;
2019                 ecclayout->oobfree->offset      = ecclayout->eccpos[0] +
2020                                                         ecclayout->eccbytes;
2021                 break;
2022 #else
2023                 pr_err("nand: error: CONFIG_MTD_NAND_OMAP_BCH not enabled\n");
2024                 err = -EINVAL;
2025                 goto out_release_mem_region;
2026 #endif
2027
2028         default:
2029                 pr_err("nand: error: invalid or unsupported ECC scheme\n");
2030                 err = -EINVAL;
2031                 goto out_release_mem_region;
2032         }
2033
2034         /* populate remaining ECC layout data */
2035         ecclayout->oobfree->length = mtd->oobsize - (BADBLOCK_MARKER_LENGTH +
2036                                                         ecclayout->eccbytes);
2037         for (i = 1; i < ecclayout->eccbytes; i++)
2038                 ecclayout->eccpos[i] = ecclayout->eccpos[0] + i;
2039         /* check if NAND device's OOB is enough to store ECC signatures */
2040         if (mtd->oobsize < (ecclayout->eccbytes + BADBLOCK_MARKER_LENGTH)) {
2041                 pr_err("not enough OOB bytes required = %d, available=%d\n",
2042                                            ecclayout->eccbytes, mtd->oobsize);
2043                 err = -EINVAL;
2044                 goto out_release_mem_region;
2045         }
2046
2047         /* second phase scan */
2048         if (nand_scan_tail(mtd)) {
2049                 err = -ENXIO;
2050                 goto out_release_mem_region;
2051         }
2052
2053         ppdata.of_node = pdata->of_node;
2054         mtd_device_parse_register(mtd, NULL, &ppdata, pdata->parts,
2055                                   pdata->nr_parts);
2056
2057         platform_set_drvdata(pdev, mtd);
2058
2059         return 0;
2060
2061 out_release_mem_region:
2062         if (info->dma)
2063                 dma_release_channel(info->dma);
2064         if (info->gpmc_irq_count > 0)
2065                 free_irq(info->gpmc_irq_count, info);
2066         if (info->gpmc_irq_fifo > 0)
2067                 free_irq(info->gpmc_irq_fifo, info);
2068         release_mem_region(info->phys_base, info->mem_size);
2069 out_free_info:
2070         omap3_free_bch(mtd);
2071         kfree(info);
2072
2073         return err;
2074 }
2075
2076 static int omap_nand_remove(struct platform_device *pdev)
2077 {
2078         struct mtd_info *mtd = platform_get_drvdata(pdev);
2079         struct nand_chip *nand_chip = mtd->priv;
2080         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
2081                                                         mtd);
2082         omap3_free_bch(mtd);
2083
2084         if (info->dma)
2085                 dma_release_channel(info->dma);
2086
2087         if (info->gpmc_irq_count > 0)
2088                 free_irq(info->gpmc_irq_count, info);
2089         if (info->gpmc_irq_fifo > 0)
2090                 free_irq(info->gpmc_irq_fifo, info);
2091
2092         /* Release NAND device, its internal structures and partitions */
2093         nand_release(mtd);
2094         iounmap(nand_chip->IO_ADDR_R);
2095         release_mem_region(info->phys_base, info->mem_size);
2096         kfree(info);
2097         return 0;
2098 }
2099
2100 static struct platform_driver omap_nand_driver = {
2101         .probe          = omap_nand_probe,
2102         .remove         = omap_nand_remove,
2103         .driver         = {
2104                 .name   = DRIVER_NAME,
2105                 .owner  = THIS_MODULE,
2106         },
2107 };
2108
2109 module_platform_driver(omap_nand_driver);
2110
2111 MODULE_ALIAS("platform:" DRIVER_NAME);
2112 MODULE_LICENSE("GPL");
2113 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");