drivers/net/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17 #include <linux/ethtool.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/crc32.h>
  22
  23
  24 #include "bnx2x.h"
  25 #include "bnx2x_cmn.h"
  26 #include "bnx2x_dump.h"
  27
  28 /* Note: in the format strings below %s is replaced by the queue-name which is
  29  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  30  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  31  */
  32 #define MAX_QUEUE_NAME_LEN      4
  33 static const struct {
  34         long offset;
  35         int size;
  36         char string[ETH_GSTRING_LEN];
  37 } bnx2x_q_stats_arr[] = {
  38 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  39         { Q_STATS_OFFSET32(error_bytes_received_hi),
  40                                                 8, "[%s]: rx_error_bytes" },
  41         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  42                                                 8, "[%s]: rx_ucast_packets" },
  43         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  44                                                 8, "[%s]: rx_mcast_packets" },
  45         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  46                                                 8, "[%s]: rx_bcast_packets" },
  47         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  48         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  49                                          4, "[%s]: rx_phy_ip_err_discards"},
  50         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  51                                          4, "[%s]: rx_skb_alloc_discard" },
  52         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  53
  54 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  55         { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  56                                                 8, "[%s]: tx_ucast_packets" },
  57         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_mcast_packets" },
  59         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_bcast_packets" }
  61 };
  62
  63 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  64
  65 static const struct {
  66         long offset;
  67         int size;
  68         u32 flags;
  69 #define STATS_FLAGS_PORT                1
  70 #define STATS_FLAGS_FUNC                2
  71 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  72         char string[ETH_GSTRING_LEN];
  73 } bnx2x_stats_arr[] = {
  74 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  75                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  76         { STATS_OFFSET32(error_bytes_received_hi),
  77                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  78         { STATS_OFFSET32(total_unicast_packets_received_hi),
  79                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  80         { STATS_OFFSET32(total_multicast_packets_received_hi),
  81                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  82         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  83                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  84         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  85                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  86         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  87                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  88         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  89                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  90         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  91                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  92 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  93                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  94         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
  95                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
  96         { STATS_OFFSET32(no_buff_discard_hi),
  97                                 8, STATS_FLAGS_BOTH, "rx_discards" },
  98         { STATS_OFFSET32(mac_filter_discard),
  99                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 100         { STATS_OFFSET32(xxoverflow_discard),
 101                                 4, STATS_FLAGS_PORT, "rx_fw_discards" },
 102         { STATS_OFFSET32(brb_drop_hi),
 103                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 104         { STATS_OFFSET32(brb_truncate_hi),
 105                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 106         { STATS_OFFSET32(pause_frames_received_hi),
 107                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 108         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 109                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 110         { STATS_OFFSET32(nig_timer_max),
 111                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 112 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 113                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 114         { STATS_OFFSET32(rx_skb_alloc_failed),
 115                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 116         { STATS_OFFSET32(hw_csum_err),
 117                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 118
 119         { STATS_OFFSET32(total_bytes_transmitted_hi),
 120                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 121         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 122                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 123         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 124                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 125         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 126                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 127         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 128                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 129         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 130                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 131         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 132                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 133 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 134                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 135         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 136                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 137         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 138                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 139         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 140                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 141         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 142                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 143         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 144                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 145         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 146                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 147         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 148                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 149         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 150                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 151         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 152                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 153 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 154                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 155         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 156                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 157         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 158                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 159         { STATS_OFFSET32(pause_frames_sent_hi),
 160                                 8, STATS_FLAGS_PORT, "tx_pause_frames" }
 161 };
 162
 163 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 164
 165 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 166 {
 167         struct bnx2x *bp = netdev_priv(dev);
 168         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 169         /* Dual Media boards present all available port types */
 170         cmd->supported = bp->port.supported[cfg_idx] |
 171                 (bp->port.supported[cfg_idx ^ 1] &
 172                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 173         cmd->advertising = bp->port.advertising[cfg_idx];
 174
 175         if ((bp->state == BNX2X_STATE_OPEN) &&
 176             !(bp->flags & MF_FUNC_DIS) &&
 177             (bp->link_vars.link_up)) {
 178                 cmd->speed = bp->link_vars.line_speed;
 179                 cmd->duplex = bp->link_vars.duplex;
 180         } else {
 181
 182                 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
 183                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 184         }
 185
 186         if (IS_MF(bp))
 187                 cmd->speed = bnx2x_get_mf_speed(bp);
 188
 189         if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 190                 cmd->port = PORT_TP;
 191         else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 192                 cmd->port = PORT_FIBRE;
 193         else
 194                 BNX2X_ERR("XGXS PHY Failure detected\n");
 195
 196         cmd->phy_address = bp->mdio.prtad;
 197         cmd->transceiver = XCVR_INTERNAL;
 198
 199         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 200                 cmd->autoneg = AUTONEG_ENABLE;
 201         else
 202                 cmd->autoneg = AUTONEG_DISABLE;
 203
 204         cmd->maxtxpkt = 0;
 205         cmd->maxrxpkt = 0;
 206
 207         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 208            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
 209            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 210            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 211            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
 212            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 213            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 214
 215         return 0;
 216 }
 217
 218 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 219 {
 220         struct bnx2x *bp = netdev_priv(dev);
 221         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 222         u32 speed;
 223
 224         if (IS_MF_SD(bp))
 225                 return 0;
 226
 227         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 228            "  supported 0x%x  advertising 0x%x  speed %d speed_hi %d\n"
 229            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 230            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 231            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
 232            cmd->speed_hi,
 233            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 234            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 235
 236         speed = cmd->speed;
 237         speed |= (cmd->speed_hi << 16);
 238
 239         if (IS_MF_SI(bp)) {
 240                 u32 param = 0;
 241                 u32 line_speed = bp->link_vars.line_speed;
 242
 243                 /* use 10G if no link detected */
 244                 if (!line_speed)
 245                         line_speed = 10000;
 246
 247                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 248                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 249                                        "is required, please upgrade BC\n",
 250                                        REQ_BC_VER_4_SET_MF_BW);
 251                         return -EINVAL;
 252                 }
 253                 if (line_speed < speed) {
 254                         BNX2X_DEV_INFO("New speed should be less or equal "
 255                                        "to actual line speed\n");
 256                         return -EINVAL;
 257                 }
 258                 /* load old values */
 259                 param = bp->mf_config[BP_VN(bp)];
 260
 261                 /* leave only MIN value */
 262                 param &= FUNC_MF_CFG_MIN_BW_MASK;
 263
 264                 /* set new MAX value */
 265                 param |= (((speed * 100) / line_speed)
 266                                  << FUNC_MF_CFG_MAX_BW_SHIFT)
 267                                   & FUNC_MF_CFG_MAX_BW_MASK;
 268
 269                 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, param);
 270                 return 0;
 271         }
 272
 273         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 274         old_multi_phy_config = bp->link_params.multi_phy_config;
 275         switch (cmd->port) {
 276         case PORT_TP:
 277                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 278                         break; /* no port change */
 279
 280                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 281                       bp->port.supported[1] & SUPPORTED_TP)) {
 282                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 283                         return -EINVAL;
 284                 }
 285                 bp->link_params.multi_phy_config &=
 286                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 287                 if (bp->link_params.multi_phy_config &
 288                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 289                         bp->link_params.multi_phy_config |=
 290                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 291                 else
 292                         bp->link_params.multi_phy_config |=
 293                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 294                 break;
 295         case PORT_FIBRE:
 296                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 297                         break; /* no port change */
 298
 299                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 300                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 301                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 302                         return -EINVAL;
 303                 }
 304                 bp->link_params.multi_phy_config &=
 305                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 306                 if (bp->link_params.multi_phy_config &
 307                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 308                         bp->link_params.multi_phy_config |=
 309                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 310                 else
 311                         bp->link_params.multi_phy_config |=
 312                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 313                 break;
 314         default:
 315                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 316                 return -EINVAL;
 317         }
 318         /* Save new config in case command complete successuly */
 319         new_multi_phy_config = bp->link_params.multi_phy_config;
 320         /* Get the new cfg_idx */
 321         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 322         /* Restore old config in case command failed */
 323         bp->link_params.multi_phy_config = old_multi_phy_config;
 324         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 325
 326         if (cmd->autoneg == AUTONEG_ENABLE) {
 327                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 328                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 329                         return -EINVAL;
 330                 }
 331
 332                 /* advertise the requested speed and duplex if supported */
 333                 cmd->advertising &= bp->port.supported[cfg_idx];
 334
 335                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 336                 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
 337                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
 338                                          cmd->advertising);
 339
 340         } else { /* forced speed */
 341                 /* advertise the requested speed and duplex if supported */
 342                 switch (speed) {
 343                 case SPEED_10:
 344                         if (cmd->duplex == DUPLEX_FULL) {
 345                                 if (!(bp->port.supported[cfg_idx] &
 346                                       SUPPORTED_10baseT_Full)) {
 347                                         DP(NETIF_MSG_LINK,
 348                                            "10M full not supported\n");
 349                                         return -EINVAL;
 350                                 }
 351
 352                                 advertising = (ADVERTISED_10baseT_Full |
 353                                                ADVERTISED_TP);
 354                         } else {
 355                                 if (!(bp->port.supported[cfg_idx] &
 356                                       SUPPORTED_10baseT_Half)) {
 357                                         DP(NETIF_MSG_LINK,
 358                                            "10M half not supported\n");
 359                                         return -EINVAL;
 360                                 }
 361
 362                                 advertising = (ADVERTISED_10baseT_Half |
 363                                                ADVERTISED_TP);
 364                         }
 365                         break;
 366
 367                 case SPEED_100:
 368                         if (cmd->duplex == DUPLEX_FULL) {
 369                                 if (!(bp->port.supported[cfg_idx] &
 370                                                 SUPPORTED_100baseT_Full)) {
 371                                         DP(NETIF_MSG_LINK,
 372                                            "100M full not supported\n");
 373                                         return -EINVAL;
 374                                 }
 375
 376                                 advertising = (ADVERTISED_100baseT_Full |
 377                                                ADVERTISED_TP);
 378                         } else {
 379                                 if (!(bp->port.supported[cfg_idx] &
 380                                                 SUPPORTED_100baseT_Half)) {
 381                                         DP(NETIF_MSG_LINK,
 382                                            "100M half not supported\n");
 383                                         return -EINVAL;
 384                                 }
 385
 386                                 advertising = (ADVERTISED_100baseT_Half |
 387                                                ADVERTISED_TP);
 388                         }
 389                         break;
 390
 391                 case SPEED_1000:
 392                         if (cmd->duplex != DUPLEX_FULL) {
 393                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 394                                 return -EINVAL;
 395                         }
 396
 397                         if (!(bp->port.supported[cfg_idx] &
 398                               SUPPORTED_1000baseT_Full)) {
 399                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 400                                 return -EINVAL;
 401                         }
 402
 403                         advertising = (ADVERTISED_1000baseT_Full |
 404                                        ADVERTISED_TP);
 405                         break;
 406
 407                 case SPEED_2500:
 408                         if (cmd->duplex != DUPLEX_FULL) {
 409                                 DP(NETIF_MSG_LINK,
 410                                    "2.5G half not supported\n");
 411                                 return -EINVAL;
 412                         }
 413
 414                         if (!(bp->port.supported[cfg_idx]
 415                               & SUPPORTED_2500baseX_Full)) {
 416                                 DP(NETIF_MSG_LINK,
 417                                    "2.5G full not supported\n");
 418                                 return -EINVAL;
 419                         }
 420
 421                         advertising = (ADVERTISED_2500baseX_Full |
 422                                        ADVERTISED_TP);
 423                         break;
 424
 425                 case SPEED_10000:
 426                         if (cmd->duplex != DUPLEX_FULL) {
 427                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 428                                 return -EINVAL;
 429                         }
 430
 431                         if (!(bp->port.supported[cfg_idx]
 432                               & SUPPORTED_10000baseT_Full)) {
 433                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 434                                 return -EINVAL;
 435                         }
 436
 437                         advertising = (ADVERTISED_10000baseT_Full |
 438                                        ADVERTISED_FIBRE);
 439                         break;
 440
 441                 default:
 442                         DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
 443                         return -EINVAL;
 444                 }
 445
 446                 bp->link_params.req_line_speed[cfg_idx] = speed;
 447                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 448                 bp->port.advertising[cfg_idx] = advertising;
 449         }
 450
 451         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 452            DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
 453            bp->link_params.req_line_speed[cfg_idx],
 454            bp->link_params.req_duplex[cfg_idx],
 455            bp->port.advertising[cfg_idx]);
 456
 457         /* Set new config */
 458         bp->link_params.multi_phy_config = new_multi_phy_config;
 459         if (netif_running(dev)) {
 460                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 461                 bnx2x_link_set(bp);
 462         }
 463
 464         return 0;
 465 }
 466
 467 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 468 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 469 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 470
 471 static int bnx2x_get_regs_len(struct net_device *dev)
 472 {
 473         struct bnx2x *bp = netdev_priv(dev);
 474         int regdump_len = 0;
 475         int i;
 476
 477         if (CHIP_IS_E1(bp)) {
 478                 for (i = 0; i < REGS_COUNT; i++)
 479                         if (IS_E1_ONLINE(reg_addrs[i].info))
 480                                 regdump_len += reg_addrs[i].size;
 481
 482                 for (i = 0; i < WREGS_COUNT_E1; i++)
 483                         if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
 484                                 regdump_len += wreg_addrs_e1[i].size *
 485                                         (1 + wreg_addrs_e1[i].read_regs_count);
 486
 487         } else if (CHIP_IS_E1H(bp)) {
 488                 for (i = 0; i < REGS_COUNT; i++)
 489                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 490                                 regdump_len += reg_addrs[i].size;
 491
 492                 for (i = 0; i < WREGS_COUNT_E1H; i++)
 493                         if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
 494                                 regdump_len += wreg_addrs_e1h[i].size *
 495                                         (1 + wreg_addrs_e1h[i].read_regs_count);
 496         } else if (CHIP_IS_E2(bp)) {
 497                 for (i = 0; i < REGS_COUNT; i++)
 498                         if (IS_E2_ONLINE(reg_addrs[i].info))
 499                                 regdump_len += reg_addrs[i].size;
 500
 501                 for (i = 0; i < WREGS_COUNT_E2; i++)
 502                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
 503                                 regdump_len += wreg_addrs_e2[i].size *
 504                                         (1 + wreg_addrs_e2[i].read_regs_count);
 505         }
 506         regdump_len *= 4;
 507         regdump_len += sizeof(struct dump_hdr);
 508
 509         return regdump_len;
 510 }
 511
 512 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
 513 {
 514         u32 i, j, k, n;
 515
 516         for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
 517                 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 518                         REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
 519                         for (k = 0; k < PAGE_READ_REGS_E2; k++)
 520                                 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
 521                                         for (n = 0; n <
 522                                               page_read_regs_e2[k].size; n++)
 523                                                 *p++ = REG_RD(bp,
 524                                         page_read_regs_e2[k].addr + n*4);
 525                 }
 526         }
 527 }
 528
 529 static void bnx2x_get_regs(struct net_device *dev,
 530                            struct ethtool_regs *regs, void *_p)
 531 {
 532         u32 *p = _p, i, j;
 533         struct bnx2x *bp = netdev_priv(dev);
 534         struct dump_hdr dump_hdr = {0};
 535
 536         regs->version = 0;
 537         memset(p, 0, regs->len);
 538
 539         if (!netif_running(bp->dev))
 540                 return;
 541
 542         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 543         dump_hdr.dump_sign = dump_sign_all;
 544         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 545         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 546         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 547         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 548
 549         if (CHIP_IS_E1(bp))
 550                 dump_hdr.info = RI_E1_ONLINE;
 551         else if (CHIP_IS_E1H(bp))
 552                 dump_hdr.info = RI_E1H_ONLINE;
 553         else if (CHIP_IS_E2(bp))
 554                 dump_hdr.info = RI_E2_ONLINE |
 555                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 556
 557         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 558         p += dump_hdr.hdr_size + 1;
 559
 560         if (CHIP_IS_E1(bp)) {
 561                 for (i = 0; i < REGS_COUNT; i++)
 562                         if (IS_E1_ONLINE(reg_addrs[i].info))
 563                                 for (j = 0; j < reg_addrs[i].size; j++)
 564                                         *p++ = REG_RD(bp,
 565                                                       reg_addrs[i].addr + j*4);
 566
 567         } else if (CHIP_IS_E1H(bp)) {
 568                 for (i = 0; i < REGS_COUNT; i++)
 569                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 570                                 for (j = 0; j < reg_addrs[i].size; j++)
 571                                         *p++ = REG_RD(bp,
 572                                                       reg_addrs[i].addr + j*4);
 573
 574         } else if (CHIP_IS_E2(bp)) {
 575                 for (i = 0; i < REGS_COUNT; i++)
 576                         if (IS_E2_ONLINE(reg_addrs[i].info))
 577                                 for (j = 0; j < reg_addrs[i].size; j++)
 578                                         *p++ = REG_RD(bp,
 579                                               reg_addrs[i].addr + j*4);
 580
 581                 bnx2x_read_pages_regs_e2(bp, p);
 582         }
 583 }
 584
 585 #define PHY_FW_VER_LEN                  20
 586
 587 static void bnx2x_get_drvinfo(struct net_device *dev,
 588                               struct ethtool_drvinfo *info)
 589 {
 590         struct bnx2x *bp = netdev_priv(dev);
 591         u8 phy_fw_ver[PHY_FW_VER_LEN];
 592
 593         strcpy(info->driver, DRV_MODULE_NAME);
 594         strcpy(info->version, DRV_MODULE_VERSION);
 595
 596         phy_fw_ver[0] = '\0';
 597         if (bp->port.pmf) {
 598                 bnx2x_acquire_phy_lock(bp);
 599                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 600                                              (bp->state != BNX2X_STATE_CLOSED),
 601                                              phy_fw_ver, PHY_FW_VER_LEN);
 602                 bnx2x_release_phy_lock(bp);
 603         }
 604
 605         strncpy(info->fw_version, bp->fw_ver, 32);
 606         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 607                  "bc %d.%d.%d%s%s",
 608                  (bp->common.bc_ver & 0xff0000) >> 16,
 609                  (bp->common.bc_ver & 0xff00) >> 8,
 610                  (bp->common.bc_ver & 0xff),
 611                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 612         strcpy(info->bus_info, pci_name(bp->pdev));
 613         info->n_stats = BNX2X_NUM_STATS;
 614         info->testinfo_len = BNX2X_NUM_TESTS;
 615         info->eedump_len = bp->common.flash_size;
 616         info->regdump_len = bnx2x_get_regs_len(dev);
 617 }
 618
 619 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 620 {
 621         struct bnx2x *bp = netdev_priv(dev);
 622
 623         if (bp->flags & NO_WOL_FLAG) {
 624                 wol->supported = 0;
 625                 wol->wolopts = 0;
 626         } else {
 627                 wol->supported = WAKE_MAGIC;
 628                 if (bp->wol)
 629                         wol->wolopts = WAKE_MAGIC;
 630                 else
 631                         wol->wolopts = 0;
 632         }
 633         memset(&wol->sopass, 0, sizeof(wol->sopass));
 634 }
 635
 636 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 637 {
 638         struct bnx2x *bp = netdev_priv(dev);
 639
 640         if (wol->wolopts & ~WAKE_MAGIC)
 641                 return -EINVAL;
 642
 643         if (wol->wolopts & WAKE_MAGIC) {
 644                 if (bp->flags & NO_WOL_FLAG)
 645                         return -EINVAL;
 646
 647                 bp->wol = 1;
 648         } else
 649                 bp->wol = 0;
 650
 651         return 0;
 652 }
 653
 654 static u32 bnx2x_get_msglevel(struct net_device *dev)
 655 {
 656         struct bnx2x *bp = netdev_priv(dev);
 657
 658         return bp->msg_enable;
 659 }
 660
 661 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 662 {
 663         struct bnx2x *bp = netdev_priv(dev);
 664
 665         if (capable(CAP_NET_ADMIN))
 666                 bp->msg_enable = level;
 667 }
 668
 669 static int bnx2x_nway_reset(struct net_device *dev)
 670 {
 671         struct bnx2x *bp = netdev_priv(dev);
 672
 673         if (!bp->port.pmf)
 674                 return 0;
 675
 676         if (netif_running(dev)) {
 677                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 678                 bnx2x_link_set(bp);
 679         }
 680
 681         return 0;
 682 }
 683
 684 static u32 bnx2x_get_link(struct net_device *dev)
 685 {
 686         struct bnx2x *bp = netdev_priv(dev);
 687
 688         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 689                 return 0;
 690
 691         return bp->link_vars.link_up;
 692 }
 693
 694 static int bnx2x_get_eeprom_len(struct net_device *dev)
 695 {
 696         struct bnx2x *bp = netdev_priv(dev);
 697
 698         return bp->common.flash_size;
 699 }
 700
 701 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 702 {
 703         int port = BP_PORT(bp);
 704         int count, i;
 705         u32 val = 0;
 706
 707         /* adjust timeout for emulation/FPGA */
 708         count = NVRAM_TIMEOUT_COUNT;
 709         if (CHIP_REV_IS_SLOW(bp))
 710                 count *= 100;
 711
 712         /* request access to nvram interface */
 713         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 714                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 715
 716         for (i = 0; i < count*10; i++) {
 717                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 718                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 719                         break;
 720
 721                 udelay(5);
 722         }
 723
 724         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 725                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 726                 return -EBUSY;
 727         }
 728
 729         return 0;
 730 }
 731
 732 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 733 {
 734         int port = BP_PORT(bp);
 735         int count, i;
 736         u32 val = 0;
 737
 738         /* adjust timeout for emulation/FPGA */
 739         count = NVRAM_TIMEOUT_COUNT;
 740         if (CHIP_REV_IS_SLOW(bp))
 741                 count *= 100;
 742
 743         /* relinquish nvram interface */
 744         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 745                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 746
 747         for (i = 0; i < count*10; i++) {
 748                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 749                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 750                         break;
 751
 752                 udelay(5);
 753         }
 754
 755         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 756                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 757                 return -EBUSY;
 758         }
 759
 760         return 0;
 761 }
 762
 763 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 764 {
 765         u32 val;
 766
 767         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 768
 769         /* enable both bits, even on read */
 770         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 771                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 772                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 773 }
 774
 775 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 776 {
 777         u32 val;
 778
 779         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 780
 781         /* disable both bits, even after read */
 782         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 783                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 784                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 785 }
 786
 787 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 788                                   u32 cmd_flags)
 789 {
 790         int count, i, rc;
 791         u32 val;
 792
 793         /* build the command word */
 794         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 795
 796         /* need to clear DONE bit separately */
 797         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 798
 799         /* address of the NVRAM to read from */
 800         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 801                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 802
 803         /* issue a read command */
 804         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 805
 806         /* adjust timeout for emulation/FPGA */
 807         count = NVRAM_TIMEOUT_COUNT;
 808         if (CHIP_REV_IS_SLOW(bp))
 809                 count *= 100;
 810
 811         /* wait for completion */
 812         *ret_val = 0;
 813         rc = -EBUSY;
 814         for (i = 0; i < count; i++) {
 815                 udelay(5);
 816                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 817
 818                 if (val & MCPR_NVM_COMMAND_DONE) {
 819                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 820                         /* we read nvram data in cpu order
 821                          * but ethtool sees it as an array of bytes
 822                          * converting to big-endian will do the work */
 823                         *ret_val = cpu_to_be32(val);
 824                         rc = 0;
 825                         break;
 826                 }
 827         }
 828
 829         return rc;
 830 }
 831
 832 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 833                             int buf_size)
 834 {
 835         int rc;
 836         u32 cmd_flags;
 837         __be32 val;
 838
 839         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 840                 DP(BNX2X_MSG_NVM,
 841                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 842                    offset, buf_size);
 843                 return -EINVAL;
 844         }
 845
 846         if (offset + buf_size > bp->common.flash_size) {
 847                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 848                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 849                    offset, buf_size, bp->common.flash_size);
 850                 return -EINVAL;
 851         }
 852
 853         /* request access to nvram interface */
 854         rc = bnx2x_acquire_nvram_lock(bp);
 855         if (rc)
 856                 return rc;
 857
 858         /* enable access to nvram interface */
 859         bnx2x_enable_nvram_access(bp);
 860
 861         /* read the first word(s) */
 862         cmd_flags = MCPR_NVM_COMMAND_FIRST;
 863         while ((buf_size > sizeof(u32)) && (rc == 0)) {
 864                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 865                 memcpy(ret_buf, &val, 4);
 866
 867                 /* advance to the next dword */
 868                 offset += sizeof(u32);
 869                 ret_buf += sizeof(u32);
 870                 buf_size -= sizeof(u32);
 871                 cmd_flags = 0;
 872         }
 873
 874         if (rc == 0) {
 875                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
 876                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 877                 memcpy(ret_buf, &val, 4);
 878         }
 879
 880         /* disable access to nvram interface */
 881         bnx2x_disable_nvram_access(bp);
 882         bnx2x_release_nvram_lock(bp);
 883
 884         return rc;
 885 }
 886
 887 static int bnx2x_get_eeprom(struct net_device *dev,
 888                             struct ethtool_eeprom *eeprom, u8 *eebuf)
 889 {
 890         struct bnx2x *bp = netdev_priv(dev);
 891         int rc;
 892
 893         if (!netif_running(dev))
 894                 return -EAGAIN;
 895
 896         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
 897            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
 898            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
 899            eeprom->len, eeprom->len);
 900
 901         /* parameters already validated in ethtool_get_eeprom */
 902
 903         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
 904
 905         return rc;
 906 }
 907
 908 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
 909                                    u32 cmd_flags)
 910 {
 911         int count, i, rc;
 912
 913         /* build the command word */
 914         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
 915
 916         /* need to clear DONE bit separately */
 917         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 918
 919         /* write the data */
 920         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
 921
 922         /* address of the NVRAM to write to */
 923         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 924                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 925
 926         /* issue the write command */
 927         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 928
 929         /* adjust timeout for emulation/FPGA */
 930         count = NVRAM_TIMEOUT_COUNT;
 931         if (CHIP_REV_IS_SLOW(bp))
 932                 count *= 100;
 933
 934         /* wait for completion */
 935         rc = -EBUSY;
 936         for (i = 0; i < count; i++) {
 937                 udelay(5);
 938                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 939                 if (val & MCPR_NVM_COMMAND_DONE) {
 940                         rc = 0;
 941                         break;
 942                 }
 943         }
 944
 945         return rc;
 946 }
 947
 948 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
 949
 950 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
 951                               int buf_size)
 952 {
 953         int rc;
 954         u32 cmd_flags;
 955         u32 align_offset;
 956         __be32 val;
 957
 958         if (offset + buf_size > bp->common.flash_size) {
 959                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 960                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 961                    offset, buf_size, bp->common.flash_size);
 962                 return -EINVAL;
 963         }
 964
 965         /* request access to nvram interface */
 966         rc = bnx2x_acquire_nvram_lock(bp);
 967         if (rc)
 968                 return rc;
 969
 970         /* enable access to nvram interface */
 971         bnx2x_enable_nvram_access(bp);
 972
 973         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
 974         align_offset = (offset & ~0x03);
 975         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
 976
 977         if (rc == 0) {
 978                 val &= ~(0xff << BYTE_OFFSET(offset));
 979                 val |= (*data_buf << BYTE_OFFSET(offset));
 980
 981                 /* nvram data is returned as an array of bytes
 982                  * convert it back to cpu order */
 983                 val = be32_to_cpu(val);
 984
 985                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
 986                                              cmd_flags);
 987         }
 988
 989         /* disable access to nvram interface */
 990         bnx2x_disable_nvram_access(bp);
 991         bnx2x_release_nvram_lock(bp);
 992
 993         return rc;
 994 }
 995
 996 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
 997                              int buf_size)
 998 {
 999         int rc;
1000         u32 cmd_flags;
1001         u32 val;
1002         u32 written_so_far;
1003
1004         if (buf_size == 1)      /* ethtool */
1005                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1006
1007         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1008                 DP(BNX2X_MSG_NVM,
1009                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1010                    offset, buf_size);
1011                 return -EINVAL;
1012         }
1013
1014         if (offset + buf_size > bp->common.flash_size) {
1015                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1016                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1017                    offset, buf_size, bp->common.flash_size);
1018                 return -EINVAL;
1019         }
1020
1021         /* request access to nvram interface */
1022         rc = bnx2x_acquire_nvram_lock(bp);
1023         if (rc)
1024                 return rc;
1025
1026         /* enable access to nvram interface */
1027         bnx2x_enable_nvram_access(bp);
1028
1029         written_so_far = 0;
1030         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1031         while ((written_so_far < buf_size) && (rc == 0)) {
1032                 if (written_so_far == (buf_size - sizeof(u32)))
1033                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1034                 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1035                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1036                 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1037                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1038
1039                 memcpy(&val, data_buf, 4);
1040
1041                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1042
1043                 /* advance to the next dword */
1044                 offset += sizeof(u32);
1045                 data_buf += sizeof(u32);
1046                 written_so_far += sizeof(u32);
1047                 cmd_flags = 0;
1048         }
1049
1050         /* disable access to nvram interface */
1051         bnx2x_disable_nvram_access(bp);
1052         bnx2x_release_nvram_lock(bp);
1053
1054         return rc;
1055 }
1056
1057 static int bnx2x_set_eeprom(struct net_device *dev,
1058                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1059 {
1060         struct bnx2x *bp = netdev_priv(dev);
1061         int port = BP_PORT(bp);
1062         int rc = 0;
1063         u32 ext_phy_config;
1064         if (!netif_running(dev))
1065                 return -EAGAIN;
1066
1067         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1068            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1069            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1070            eeprom->len, eeprom->len);
1071
1072         /* parameters already validated in ethtool_set_eeprom */
1073
1074         /* PHY eeprom can be accessed only by the PMF */
1075         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1076             !bp->port.pmf)
1077                 return -EINVAL;
1078
1079         ext_phy_config =
1080                 SHMEM_RD(bp,
1081                          dev_info.port_hw_config[port].external_phy_config);
1082
1083         if (eeprom->magic == 0x50485950) {
1084                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1085                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1086
1087                 bnx2x_acquire_phy_lock(bp);
1088                 rc |= bnx2x_link_reset(&bp->link_params,
1089                                        &bp->link_vars, 0);
1090                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1091                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1092                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1093                                        MISC_REGISTERS_GPIO_HIGH, port);
1094                 bnx2x_release_phy_lock(bp);
1095                 bnx2x_link_report(bp);
1096
1097         } else if (eeprom->magic == 0x50485952) {
1098                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1099                 if (bp->state == BNX2X_STATE_OPEN) {
1100                         bnx2x_acquire_phy_lock(bp);
1101                         rc |= bnx2x_link_reset(&bp->link_params,
1102                                                &bp->link_vars, 1);
1103
1104                         rc |= bnx2x_phy_init(&bp->link_params,
1105                                              &bp->link_vars);
1106                         bnx2x_release_phy_lock(bp);
1107                         bnx2x_calc_fc_adv(bp);
1108                 }
1109         } else if (eeprom->magic == 0x53985943) {
1110                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1111                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1112                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1113
1114                         /* DSP Remove Download Mode */
1115                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1116                                        MISC_REGISTERS_GPIO_LOW, port);
1117
1118                         bnx2x_acquire_phy_lock(bp);
1119
1120                         bnx2x_sfx7101_sp_sw_reset(bp,
1121                                                 &bp->link_params.phy[EXT_PHY1]);
1122
1123                         /* wait 0.5 sec to allow it to run */
1124                         msleep(500);
1125                         bnx2x_ext_phy_hw_reset(bp, port);
1126                         msleep(500);
1127                         bnx2x_release_phy_lock(bp);
1128                 }
1129         } else
1130                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1131
1132         return rc;
1133 }
1134
1135 static int bnx2x_get_coalesce(struct net_device *dev,
1136                               struct ethtool_coalesce *coal)
1137 {
1138         struct bnx2x *bp = netdev_priv(dev);
1139
1140         memset(coal, 0, sizeof(struct ethtool_coalesce));
1141
1142         coal->rx_coalesce_usecs = bp->rx_ticks;
1143         coal->tx_coalesce_usecs = bp->tx_ticks;
1144
1145         return 0;
1146 }
1147
1148 static int bnx2x_set_coalesce(struct net_device *dev,
1149                               struct ethtool_coalesce *coal)
1150 {
1151         struct bnx2x *bp = netdev_priv(dev);
1152
1153         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1154         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1155                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1156
1157         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1158         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1159                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1160
1161         if (netif_running(dev))
1162                 bnx2x_update_coalesce(bp);
1163
1164         return 0;
1165 }
1166
1167 static void bnx2x_get_ringparam(struct net_device *dev,
1168                                 struct ethtool_ringparam *ering)
1169 {
1170         struct bnx2x *bp = netdev_priv(dev);
1171
1172         ering->rx_max_pending = MAX_RX_AVAIL;
1173         ering->rx_mini_max_pending = 0;
1174         ering->rx_jumbo_max_pending = 0;
1175
1176         if (bp->rx_ring_size)
1177                 ering->rx_pending = bp->rx_ring_size;
1178         else
1179                 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1180                         ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1181                 else
1182                         ering->rx_pending = MAX_RX_AVAIL;
1183
1184         ering->rx_mini_pending = 0;
1185         ering->rx_jumbo_pending = 0;
1186
1187         ering->tx_max_pending = MAX_TX_AVAIL;
1188         ering->tx_pending = bp->tx_ring_size;
1189 }
1190
1191 static int bnx2x_set_ringparam(struct net_device *dev,
1192                                struct ethtool_ringparam *ering)
1193 {
1194         struct bnx2x *bp = netdev_priv(dev);
1195         int rc = 0;
1196
1197         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1198                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1199                 return -EAGAIN;
1200         }
1201
1202         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1203             (ering->rx_pending < MIN_RX_AVAIL) ||
1204             (ering->tx_pending > MAX_TX_AVAIL) ||
1205             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1206                 return -EINVAL;
1207
1208         bp->rx_ring_size = ering->rx_pending;
1209         bp->tx_ring_size = ering->tx_pending;
1210
1211         if (netif_running(dev)) {
1212                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1213                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1214         }
1215
1216         return rc;
1217 }
1218
1219 static void bnx2x_get_pauseparam(struct net_device *dev,
1220                                  struct ethtool_pauseparam *epause)
1221 {
1222         struct bnx2x *bp = netdev_priv(dev);
1223         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1224         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1225                            BNX2X_FLOW_CTRL_AUTO);
1226
1227         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1228                             BNX2X_FLOW_CTRL_RX);
1229         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1230                             BNX2X_FLOW_CTRL_TX);
1231
1232         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1233            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1234            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1235 }
1236
1237 static int bnx2x_set_pauseparam(struct net_device *dev,
1238                                 struct ethtool_pauseparam *epause)
1239 {
1240         struct bnx2x *bp = netdev_priv(dev);
1241         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1242         if (IS_MF(bp))
1243                 return 0;
1244
1245         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1246            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1247            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1248
1249         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1250
1251         if (epause->rx_pause)
1252                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1253
1254         if (epause->tx_pause)
1255                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1256
1257         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1258                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1259
1260         if (epause->autoneg) {
1261                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1262                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1263                         return -EINVAL;
1264                 }
1265
1266                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1267                         bp->link_params.req_flow_ctrl[cfg_idx] =
1268                                 BNX2X_FLOW_CTRL_AUTO;
1269                 }
1270         }
1271
1272         DP(NETIF_MSG_LINK,
1273            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1274
1275         if (netif_running(dev)) {
1276                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1277                 bnx2x_link_set(bp);
1278         }
1279
1280         return 0;
1281 }
1282
1283 static int bnx2x_set_flags(struct net_device *dev, u32 data)
1284 {
1285         struct bnx2x *bp = netdev_priv(dev);
1286         int changed = 0;
1287         int rc = 0;
1288
1289         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1290                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1291                 return -EAGAIN;
1292         }
1293
1294         if (!(data & ETH_FLAG_RXVLAN))
1295                 return -EINVAL;
1296
1297         if ((data & ETH_FLAG_LRO) && bp->rx_csum && bp->disable_tpa)
1298                 return -EINVAL;
1299
1300         rc = ethtool_op_set_flags(dev, data, ETH_FLAG_LRO | ETH_FLAG_RXVLAN |
1301                                         ETH_FLAG_TXVLAN | ETH_FLAG_RXHASH);
1302         if (rc)
1303                 return rc;
1304
1305         /* TPA requires Rx CSUM offloading */
1306         if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1307                 if (!(bp->flags & TPA_ENABLE_FLAG)) {
1308                         bp->flags |= TPA_ENABLE_FLAG;
1309                         changed = 1;
1310                 }
1311         } else if (bp->flags & TPA_ENABLE_FLAG) {
1312                 dev->features &= ~NETIF_F_LRO;
1313                 bp->flags &= ~TPA_ENABLE_FLAG;
1314                 changed = 1;
1315         }
1316
1317         if (changed && netif_running(dev)) {
1318                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1319                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1320         }
1321
1322         return rc;
1323 }
1324
1325 static u32 bnx2x_get_rx_csum(struct net_device *dev)
1326 {
1327         struct bnx2x *bp = netdev_priv(dev);
1328
1329         return bp->rx_csum;
1330 }
1331
1332 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1333 {
1334         struct bnx2x *bp = netdev_priv(dev);
1335         int rc = 0;
1336
1337         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1338                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1339                 return -EAGAIN;
1340         }
1341
1342         bp->rx_csum = data;
1343
1344         /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1345            TPA'ed packets will be discarded due to wrong TCP CSUM */
1346         if (!data) {
1347                 u32 flags = ethtool_op_get_flags(dev);
1348
1349                 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1350         }
1351
1352         return rc;
1353 }
1354
1355 static int bnx2x_set_tso(struct net_device *dev, u32 data)
1356 {
1357         if (data) {
1358                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1359                 dev->features |= NETIF_F_TSO6;
1360         } else {
1361                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1362                 dev->features &= ~NETIF_F_TSO6;
1363         }
1364
1365         return 0;
1366 }
1367
1368 static const struct {
1369         char string[ETH_GSTRING_LEN];
1370 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1371         { "register_test (offline)" },
1372         { "memory_test (offline)" },
1373         { "loopback_test (offline)" },
1374         { "nvram_test (online)" },
1375         { "interrupt_test (online)" },
1376         { "link_test (online)" },
1377         { "idle check (online)" }
1378 };
1379
1380 static int bnx2x_test_registers(struct bnx2x *bp)
1381 {
1382         int idx, i, rc = -ENODEV;
1383         u32 wr_val = 0;
1384         int port = BP_PORT(bp);
1385         static const struct {
1386                 u32 offset0;
1387                 u32 offset1;
1388                 u32 mask;
1389         } reg_tbl[] = {
1390 /* 0 */         { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
1391                 { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
1392                 { HC_REG_AGG_INT_0,                    4, 0x000003ff },
1393                 { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
1394                 { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
1395                 { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
1396                 { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
1397                 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
1398                 { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
1399                 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
1400 /* 10 */        { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
1401                 { QM_REG_CONNNUM_0,                    4, 0x000fffff },
1402                 { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
1403                 { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
1404                 { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
1405                 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1406                 { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
1407                 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
1408                 { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
1409                 { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
1410 /* 20 */        { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
1411                 { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
1412                 { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
1413                 { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
1414                 { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
1415                 { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
1416                 { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
1417                 { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
1418                 { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
1419                 { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
1420 /* 30 */        { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
1421                 { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
1422                 { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
1423                 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1424                 { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
1425                 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1426                 { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
1427
1428                 { 0xffffffff, 0, 0x00000000 }
1429         };
1430
1431         if (!netif_running(bp->dev))
1432                 return rc;
1433
1434         /* Repeat the test twice:
1435            First by writing 0x00000000, second by writing 0xffffffff */
1436         for (idx = 0; idx < 2; idx++) {
1437
1438                 switch (idx) {
1439                 case 0:
1440                         wr_val = 0;
1441                         break;
1442                 case 1:
1443                         wr_val = 0xffffffff;
1444                         break;
1445                 }
1446
1447                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1448                         u32 offset, mask, save_val, val;
1449                         if (CHIP_IS_E2(bp) &&
1450                             reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1451                                 continue;
1452
1453                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1454                         mask = reg_tbl[i].mask;
1455
1456                         save_val = REG_RD(bp, offset);
1457
1458                         REG_WR(bp, offset, wr_val & mask);
1459
1460                         val = REG_RD(bp, offset);
1461
1462                         /* Restore the original register's value */
1463                         REG_WR(bp, offset, save_val);
1464
1465                         /* verify value is as expected */
1466                         if ((val & mask) != (wr_val & mask)) {
1467                                 DP(NETIF_MSG_PROBE,
1468                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1469                                    offset, val, wr_val, mask);
1470                                 goto test_reg_exit;
1471                         }
1472                 }
1473         }
1474
1475         rc = 0;
1476
1477 test_reg_exit:
1478         return rc;
1479 }
1480
1481 static int bnx2x_test_memory(struct bnx2x *bp)
1482 {
1483         int i, j, rc = -ENODEV;
1484         u32 val;
1485         static const struct {
1486                 u32 offset;
1487                 int size;
1488         } mem_tbl[] = {
1489                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1490                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1491                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1492                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1493                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1494                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1495                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1496
1497                 { 0xffffffff, 0 }
1498         };
1499         static const struct {
1500                 char *name;
1501                 u32 offset;
1502                 u32 e1_mask;
1503                 u32 e1h_mask;
1504                 u32 e2_mask;
1505         } prty_tbl[] = {
1506                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0,   0 },
1507                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2, 0 },
1508                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0,   0 },
1509                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0,   0 },
1510                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0,   0 },
1511                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0,   0 },
1512
1513                 { NULL, 0xffffffff, 0, 0, 0 }
1514         };
1515
1516         if (!netif_running(bp->dev))
1517                 return rc;
1518
1519         /* pre-Check the parity status */
1520         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1521                 val = REG_RD(bp, prty_tbl[i].offset);
1522                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1523                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1524                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1525                         DP(NETIF_MSG_HW,
1526                            "%s is 0x%x\n", prty_tbl[i].name, val);
1527                         goto test_mem_exit;
1528                 }
1529         }
1530
1531         /* Go through all the memories */
1532         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1533                 for (j = 0; j < mem_tbl[i].size; j++)
1534                         REG_RD(bp, mem_tbl[i].offset + j*4);
1535
1536         /* Check the parity status */
1537         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1538                 val = REG_RD(bp, prty_tbl[i].offset);
1539                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1540                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1541                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1542                         DP(NETIF_MSG_HW,
1543                            "%s is 0x%x\n", prty_tbl[i].name, val);
1544                         goto test_mem_exit;
1545                 }
1546         }
1547
1548         rc = 0;
1549
1550 test_mem_exit:
1551         return rc;
1552 }
1553
1554 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1555 {
1556         int cnt = 1400;
1557
1558         if (link_up)
1559                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1560                         msleep(10);
1561 }
1562
1563 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1564 {
1565         unsigned int pkt_size, num_pkts, i;
1566         struct sk_buff *skb;
1567         unsigned char *packet;
1568         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1569         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1570         u16 tx_start_idx, tx_idx;
1571         u16 rx_start_idx, rx_idx;
1572         u16 pkt_prod, bd_prod;
1573         struct sw_tx_bd *tx_buf;
1574         struct eth_tx_start_bd *tx_start_bd;
1575         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1576         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1577         dma_addr_t mapping;
1578         union eth_rx_cqe *cqe;
1579         u8 cqe_fp_flags;
1580         struct sw_rx_bd *rx_buf;
1581         u16 len;
1582         int rc = -ENODEV;
1583
1584         /* check the loopback mode */
1585         switch (loopback_mode) {
1586         case BNX2X_PHY_LOOPBACK:
1587                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1588                         return -EINVAL;
1589                 break;
1590         case BNX2X_MAC_LOOPBACK:
1591                 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1592                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1593                 break;
1594         default:
1595                 return -EINVAL;
1596         }
1597
1598         /* prepare the loopback packet */
1599         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1600                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1601         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1602         if (!skb) {
1603                 rc = -ENOMEM;
1604                 goto test_loopback_exit;
1605         }
1606         packet = skb_put(skb, pkt_size);
1607         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1608         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1609         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1610         for (i = ETH_HLEN; i < pkt_size; i++)
1611                 packet[i] = (unsigned char) (i & 0xff);
1612
1613         /* send the loopback packet */
1614         num_pkts = 0;
1615         tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1616         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1617
1618         pkt_prod = fp_tx->tx_pkt_prod++;
1619         tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1620         tx_buf->first_bd = fp_tx->tx_bd_prod;
1621         tx_buf->skb = skb;
1622         tx_buf->flags = 0;
1623
1624         bd_prod = TX_BD(fp_tx->tx_bd_prod);
1625         tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1626         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1627                                  skb_headlen(skb), DMA_TO_DEVICE);
1628         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1629         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1630         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1631         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1632         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1633         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1634         SET_FLAG(tx_start_bd->general_data,
1635                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1636                  UNICAST_ADDRESS);
1637         SET_FLAG(tx_start_bd->general_data,
1638                  ETH_TX_START_BD_HDR_NBDS,
1639                  1);
1640
1641         /* turn on parsing and get a BD */
1642         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1643
1644         pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1645         pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1646
1647         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1648         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1649
1650         wmb();
1651
1652         fp_tx->tx_db.data.prod += 2;
1653         barrier();
1654         DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1655
1656         mmiowb();
1657
1658         num_pkts++;
1659         fp_tx->tx_bd_prod += 2; /* start + pbd */
1660
1661         udelay(100);
1662
1663         tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1664         if (tx_idx != tx_start_idx + num_pkts)
1665                 goto test_loopback_exit;
1666
1667         /* Unlike HC IGU won't generate an interrupt for status block
1668          * updates that have been performed while interrupts were
1669          * disabled.
1670          */
1671         if (bp->common.int_block == INT_BLOCK_IGU) {
1672                 /* Disable local BHes to prevent a dead-lock situation between
1673                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1674                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1675                  */
1676                 local_bh_disable();
1677                 bnx2x_tx_int(fp_tx);
1678                 local_bh_enable();
1679         }
1680
1681         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1682         if (rx_idx != rx_start_idx + num_pkts)
1683                 goto test_loopback_exit;
1684
1685         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1686         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1687         if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1688                 goto test_loopback_rx_exit;
1689
1690         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1691         if (len != pkt_size)
1692                 goto test_loopback_rx_exit;
1693
1694         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1695         skb = rx_buf->skb;
1696         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1697         for (i = ETH_HLEN; i < pkt_size; i++)
1698                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1699                         goto test_loopback_rx_exit;
1700
1701         rc = 0;
1702
1703 test_loopback_rx_exit:
1704
1705         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1706         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1707         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1708         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1709
1710         /* Update producers */
1711         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1712                              fp_rx->rx_sge_prod);
1713
1714 test_loopback_exit:
1715         bp->link_params.loopback_mode = LOOPBACK_NONE;
1716
1717         return rc;
1718 }
1719
1720 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1721 {
1722         int rc = 0, res;
1723
1724         if (BP_NOMCP(bp))
1725                 return rc;
1726
1727         if (!netif_running(bp->dev))
1728                 return BNX2X_LOOPBACK_FAILED;
1729
1730         bnx2x_netif_stop(bp, 1);
1731         bnx2x_acquire_phy_lock(bp);
1732
1733         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1734         if (res) {
1735                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1736                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1737         }
1738
1739         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1740         if (res) {
1741                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1742                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1743         }
1744
1745         bnx2x_release_phy_lock(bp);
1746         bnx2x_netif_start(bp);
1747
1748         return rc;
1749 }
1750
1751 #define CRC32_RESIDUAL                  0xdebb20e3
1752
1753 static int bnx2x_test_nvram(struct bnx2x *bp)
1754 {
1755         static const struct {
1756                 int offset;
1757                 int size;
1758         } nvram_tbl[] = {
1759                 {     0,  0x14 }, /* bootstrap */
1760                 {  0x14,  0xec }, /* dir */
1761                 { 0x100, 0x350 }, /* manuf_info */
1762                 { 0x450,  0xf0 }, /* feature_info */
1763                 { 0x640,  0x64 }, /* upgrade_key_info */
1764                 { 0x6a4,  0x64 },
1765                 { 0x708,  0x70 }, /* manuf_key_info */
1766                 { 0x778,  0x70 },
1767                 {     0,     0 }
1768         };
1769         __be32 buf[0x350 / 4];
1770         u8 *data = (u8 *)buf;
1771         int i, rc;
1772         u32 magic, crc;
1773
1774         if (BP_NOMCP(bp))
1775                 return 0;
1776
1777         rc = bnx2x_nvram_read(bp, 0, data, 4);
1778         if (rc) {
1779                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1780                 goto test_nvram_exit;
1781         }
1782
1783         magic = be32_to_cpu(buf[0]);
1784         if (magic != 0x669955aa) {
1785                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1786                 rc = -ENODEV;
1787                 goto test_nvram_exit;
1788         }
1789
1790         for (i = 0; nvram_tbl[i].size; i++) {
1791
1792                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1793                                       nvram_tbl[i].size);
1794                 if (rc) {
1795                         DP(NETIF_MSG_PROBE,
1796                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1797                         goto test_nvram_exit;
1798                 }
1799
1800                 crc = ether_crc_le(nvram_tbl[i].size, data);
1801                 if (crc != CRC32_RESIDUAL) {
1802                         DP(NETIF_MSG_PROBE,
1803                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1804                         rc = -ENODEV;
1805                         goto test_nvram_exit;
1806                 }
1807         }
1808
1809 test_nvram_exit:
1810         return rc;
1811 }
1812
1813 static int bnx2x_test_intr(struct bnx2x *bp)
1814 {
1815         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1816         int i, rc;
1817
1818         if (!netif_running(bp->dev))
1819                 return -ENODEV;
1820
1821         config->hdr.length = 0;
1822         if (CHIP_IS_E1(bp))
1823                 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1824         else
1825                 config->hdr.offset = BP_FUNC(bp);
1826         config->hdr.client_id = bp->fp->cl_id;
1827         config->hdr.reserved1 = 0;
1828
1829         bp->set_mac_pending = 1;
1830         smp_wmb();
1831         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1832                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1833                            U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1834         if (rc == 0) {
1835                 for (i = 0; i < 10; i++) {
1836                         if (!bp->set_mac_pending)
1837                                 break;
1838                         smp_rmb();
1839                         msleep_interruptible(10);
1840                 }
1841                 if (i == 10)
1842                         rc = -ENODEV;
1843         }
1844
1845         return rc;
1846 }
1847
1848 static void bnx2x_self_test(struct net_device *dev,
1849                             struct ethtool_test *etest, u64 *buf)
1850 {
1851         struct bnx2x *bp = netdev_priv(dev);
1852         u8 is_serdes;
1853         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1854                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1855                 etest->flags |= ETH_TEST_FL_FAILED;
1856                 return;
1857         }
1858
1859         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1860
1861         if (!netif_running(dev))
1862                 return;
1863
1864         /* offline tests are not supported in MF mode */
1865         if (IS_MF(bp))
1866                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1867         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1868
1869         if (etest->flags & ETH_TEST_FL_OFFLINE) {
1870                 int port = BP_PORT(bp);
1871                 u32 val;
1872                 u8 link_up;
1873
1874                 /* save current value of input enable for TX port IF */
1875                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1876                 /* disable input for TX port IF */
1877                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1878
1879                 link_up = bp->link_vars.link_up;
1880
1881                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1882                 bnx2x_nic_load(bp, LOAD_DIAG);
1883                 /* wait until link state is restored */
1884                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1885
1886                 if (bnx2x_test_registers(bp) != 0) {
1887                         buf[0] = 1;
1888                         etest->flags |= ETH_TEST_FL_FAILED;
1889                 }
1890                 if (bnx2x_test_memory(bp) != 0) {
1891                         buf[1] = 1;
1892                         etest->flags |= ETH_TEST_FL_FAILED;
1893                 }
1894
1895                 buf[2] = bnx2x_test_loopback(bp, link_up);
1896                 if (buf[2] != 0)
1897                         etest->flags |= ETH_TEST_FL_FAILED;
1898
1899                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1900
1901                 /* restore input for TX port IF */
1902                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1903
1904                 bnx2x_nic_load(bp, LOAD_NORMAL);
1905                 /* wait until link state is restored */
1906                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1907         }
1908         if (bnx2x_test_nvram(bp) != 0) {
1909                 buf[3] = 1;
1910                 etest->flags |= ETH_TEST_FL_FAILED;
1911         }
1912         if (bnx2x_test_intr(bp) != 0) {
1913                 buf[4] = 1;
1914                 etest->flags |= ETH_TEST_FL_FAILED;
1915         }
1916         if (bp->port.pmf)
1917                 if (bnx2x_link_test(bp, is_serdes) != 0) {
1918                         buf[5] = 1;
1919                         etest->flags |= ETH_TEST_FL_FAILED;
1920                 }
1921
1922 #ifdef BNX2X_EXTRA_DEBUG
1923         bnx2x_panic_dump(bp);
1924 #endif
1925 }
1926
1927 #define IS_PORT_STAT(i) \
1928         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1929 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1930 #define IS_MF_MODE_STAT(bp) \
1931                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1932
1933 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1934 {
1935         struct bnx2x *bp = netdev_priv(dev);
1936         int i, num_stats;
1937
1938         switch (stringset) {
1939         case ETH_SS_STATS:
1940                 if (is_multi(bp)) {
1941                         num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1942                                 BNX2X_NUM_Q_STATS;
1943                         if (!IS_MF_MODE_STAT(bp))
1944                                 num_stats += BNX2X_NUM_STATS;
1945                 } else {
1946                         if (IS_MF_MODE_STAT(bp)) {
1947                                 num_stats = 0;
1948                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
1949                                         if (IS_FUNC_STAT(i))
1950                                                 num_stats++;
1951                         } else
1952                                 num_stats = BNX2X_NUM_STATS;
1953                 }
1954                 return num_stats;
1955
1956         case ETH_SS_TEST:
1957                 return BNX2X_NUM_TESTS;
1958
1959         default:
1960                 return -EINVAL;
1961         }
1962 }
1963
1964 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1965 {
1966         struct bnx2x *bp = netdev_priv(dev);
1967         int i, j, k;
1968         char queue_name[MAX_QUEUE_NAME_LEN+1];
1969
1970         switch (stringset) {
1971         case ETH_SS_STATS:
1972                 if (is_multi(bp)) {
1973                         k = 0;
1974                         for_each_napi_queue(bp, i) {
1975                                 memset(queue_name, 0, sizeof(queue_name));
1976
1977                                 if (IS_FCOE_IDX(i))
1978                                         sprintf(queue_name, "fcoe");
1979                                 else
1980                                         sprintf(queue_name, "%d", i);
1981
1982                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1983                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1984                                                 ETH_GSTRING_LEN,
1985                                                 bnx2x_q_stats_arr[j].string,
1986                                                 queue_name);
1987                                 k += BNX2X_NUM_Q_STATS;
1988                         }
1989                         if (IS_MF_MODE_STAT(bp))
1990                                 break;
1991                         for (j = 0; j < BNX2X_NUM_STATS; j++)
1992                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1993                                        bnx2x_stats_arr[j].string);
1994                 } else {
1995                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1996                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1997                                         continue;
1998                                 strcpy(buf + j*ETH_GSTRING_LEN,
1999                                        bnx2x_stats_arr[i].string);
2000                                 j++;
2001                         }
2002                 }
2003                 break;
2004
2005         case ETH_SS_TEST:
2006                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2007                 break;
2008         }
2009 }
2010
2011 static void bnx2x_get_ethtool_stats(struct net_device *dev,
2012                                     struct ethtool_stats *stats, u64 *buf)
2013 {
2014         struct bnx2x *bp = netdev_priv(dev);
2015         u32 *hw_stats, *offset;
2016         int i, j, k;
2017
2018         if (is_multi(bp)) {
2019                 k = 0;
2020                 for_each_napi_queue(bp, i) {
2021                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2022                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2023                                 if (bnx2x_q_stats_arr[j].size == 0) {
2024                                         /* skip this counter */
2025                                         buf[k + j] = 0;
2026                                         continue;
2027                                 }
2028                                 offset = (hw_stats +
2029                                           bnx2x_q_stats_arr[j].offset);
2030                                 if (bnx2x_q_stats_arr[j].size == 4) {
2031                                         /* 4-byte counter */
2032                                         buf[k + j] = (u64) *offset;
2033                                         continue;
2034                                 }
2035                                 /* 8-byte counter */
2036                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2037                         }
2038                         k += BNX2X_NUM_Q_STATS;
2039                 }
2040                 if (IS_MF_MODE_STAT(bp))
2041                         return;
2042                 hw_stats = (u32 *)&bp->eth_stats;
2043                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2044                         if (bnx2x_stats_arr[j].size == 0) {
2045                                 /* skip this counter */
2046                                 buf[k + j] = 0;
2047                                 continue;
2048                         }
2049                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2050                         if (bnx2x_stats_arr[j].size == 4) {
2051                                 /* 4-byte counter */
2052                                 buf[k + j] = (u64) *offset;
2053                                 continue;
2054                         }
2055                         /* 8-byte counter */
2056                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2057                 }
2058         } else {
2059                 hw_stats = (u32 *)&bp->eth_stats;
2060                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2061                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2062                                 continue;
2063                         if (bnx2x_stats_arr[i].size == 0) {
2064                                 /* skip this counter */
2065                                 buf[j] = 0;
2066                                 j++;
2067                                 continue;
2068                         }
2069                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2070                         if (bnx2x_stats_arr[i].size == 4) {
2071                                 /* 4-byte counter */
2072                                 buf[j] = (u64) *offset;
2073                                 j++;
2074                                 continue;
2075                         }
2076                         /* 8-byte counter */
2077                         buf[j] = HILO_U64(*offset, *(offset + 1));
2078                         j++;
2079                 }
2080         }
2081 }
2082
2083 static int bnx2x_phys_id(struct net_device *dev, u32 data)
2084 {
2085         struct bnx2x *bp = netdev_priv(dev);
2086         int i;
2087
2088         if (!netif_running(dev))
2089                 return 0;
2090
2091         if (!bp->port.pmf)
2092                 return 0;
2093
2094         if (data == 0)
2095                 data = 2;
2096
2097         for (i = 0; i < (data * 2); i++) {
2098                 if ((i % 2) == 0)
2099                         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2100                                       LED_MODE_OPER, SPEED_1000);
2101                 else
2102                         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2103                                       LED_MODE_OFF, 0);
2104
2105                 msleep_interruptible(500);
2106                 if (signal_pending(current))
2107                         break;
2108         }
2109
2110         if (bp->link_vars.link_up)
2111                 bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER,
2112                               bp->link_vars.line_speed);
2113
2114         return 0;
2115 }
2116
2117 static const struct ethtool_ops bnx2x_ethtool_ops = {
2118         .get_settings           = bnx2x_get_settings,
2119         .set_settings           = bnx2x_set_settings,
2120         .get_drvinfo            = bnx2x_get_drvinfo,
2121         .get_regs_len           = bnx2x_get_regs_len,
2122         .get_regs               = bnx2x_get_regs,
2123         .get_wol                = bnx2x_get_wol,
2124         .set_wol                = bnx2x_set_wol,
2125         .get_msglevel           = bnx2x_get_msglevel,
2126         .set_msglevel           = bnx2x_set_msglevel,
2127         .nway_reset             = bnx2x_nway_reset,
2128         .get_link               = bnx2x_get_link,
2129         .get_eeprom_len         = bnx2x_get_eeprom_len,
2130         .get_eeprom             = bnx2x_get_eeprom,
2131         .set_eeprom             = bnx2x_set_eeprom,
2132         .get_coalesce           = bnx2x_get_coalesce,
2133         .set_coalesce           = bnx2x_set_coalesce,
2134         .get_ringparam          = bnx2x_get_ringparam,
2135         .set_ringparam          = bnx2x_set_ringparam,
2136         .get_pauseparam         = bnx2x_get_pauseparam,
2137         .set_pauseparam         = bnx2x_set_pauseparam,
2138         .get_rx_csum            = bnx2x_get_rx_csum,
2139         .set_rx_csum            = bnx2x_set_rx_csum,
2140         .get_tx_csum            = ethtool_op_get_tx_csum,
2141         .set_tx_csum            = ethtool_op_set_tx_hw_csum,
2142         .set_flags              = bnx2x_set_flags,
2143         .get_flags              = ethtool_op_get_flags,
2144         .get_sg                 = ethtool_op_get_sg,
2145         .set_sg                 = ethtool_op_set_sg,
2146         .get_tso                = ethtool_op_get_tso,
2147         .set_tso                = bnx2x_set_tso,
2148         .self_test              = bnx2x_self_test,
2149         .get_sset_count         = bnx2x_get_sset_count,
2150         .get_strings            = bnx2x_get_strings,
2151         .phys_id                = bnx2x_phys_id,
2152         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2153 };
2154
2155 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2156 {
2157         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2158 }