drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40 #define WC_LANE_MAX                     4
  41 #define I2C_SWITCH_WIDTH                2
  42 #define I2C_BSC0                        0
  43 #define I2C_BSC1                        1
  44 #define I2C_WA_RETRY_CNT                3
  45 #define MCPR_IMC_COMMAND_READ_OP        1
  46 #define MCPR_IMC_COMMAND_WRITE_OP       2
  47
  48 /***********************************************************/
  49 /*                      Shortcut definitions               */
  50 /***********************************************************/
  51
  52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  53
  54 #define NIG_STATUS_EMAC0_MI_INT \
  55                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  56 #define NIG_STATUS_XGXS0_LINK10G \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  58 #define NIG_STATUS_XGXS0_LINK_STATUS \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  62 #define NIG_STATUS_SERDES0_LINK_STATUS \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  64 #define NIG_MASK_MI_INT \
  65                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  66 #define NIG_MASK_XGXS0_LINK10G \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  68 #define NIG_MASK_XGXS0_LINK_STATUS \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  70 #define NIG_MASK_SERDES0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  72
  73 #define MDIO_AN_CL73_OR_37_COMPLETE \
  74                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  75                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  76
  77 #define XGXS_RESET_BITS \
  78         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  83
  84 #define SERDES_RESET_BITS \
  85         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  89
  90 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  91 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  92 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  93 #define AUTONEG_PARALLEL \
  94                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  95 #define AUTONEG_SGMII_FIBER_AUTODET \
  96                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  97 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  98
  99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 100                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 103 #define GP_STATUS_SPEED_MASK \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 105 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 106 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 107 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 108 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 109 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 110 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 111 #define GP_STATUS_10G_HIG \
 112                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 113 #define GP_STATUS_10G_CX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 116 #define GP_STATUS_10G_KX4 \
 117                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 119 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 121 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 122 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 123 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 124 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 125 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 126 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 127 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 128 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 129 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 130 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 131 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 132 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 133 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 134 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 135 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 136 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 137
 138
 139
 140 /* */
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163
 164 /* BRB thresholds for E2*/
 165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 167
 168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 170
 171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 173
 174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 176
 177 /* BRB thresholds for E3A0 */
 178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 180
 181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 183
 184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 186
 187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 189
 190
 191 /* BRB thresholds for E3B0 2 port mode*/
 192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 194
 195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 197
 198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 200
 201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 203
 204 /* only for E3B0*/
 205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 207
 208 /* Lossy +Lossless GUARANTIED == GUART */
 209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 210 /* Lossless +Lossless*/
 211 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 212 /* Lossy +Lossy*/
 213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 214
 215 /* Lossy +Lossless*/
 216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 217 /* Lossless +Lossless*/
 218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 219 /* Lossy +Lossy*/
 220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 222
 223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 225
 226 /* BRB thresholds for E3B0 4 port mode */
 227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 229
 230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 232
 233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 235
 236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 238
 239
 240 /* only for E3B0*/
 241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 243 #define PFC_E3B0_4P_LB_GUART                            120
 244
 245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 247
 248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 250
 251 #define DCBX_INVALID_COS                                        (0xFF)
 252
 253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 254 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 257 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 258
 259 #define MAX_PACKET_SIZE                                 (9700)
 260 #define WC_UC_TIMEOUT                                   100
 261
 262 /**********************************************************/
 263 /*                     INTERFACE                          */
 264 /**********************************************************/
 265
 266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 267         bnx2x_cl45_write(_bp, _phy, \
 268                 (_phy)->def_md_devad, \
 269                 (_bank + (_addr & 0xf)), \
 270                 _val)
 271
 272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 273         bnx2x_cl45_read(_bp, _phy, \
 274                 (_phy)->def_md_devad, \
 275                 (_bank + (_addr & 0xf)), \
 276                 _val)
 277
 278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 279 {
 280         u32 val = REG_RD(bp, reg);
 281
 282         val |= bits;
 283         REG_WR(bp, reg, val);
 284         return val;
 285 }
 286
 287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 288 {
 289         u32 val = REG_RD(bp, reg);
 290
 291         val &= ~bits;
 292         REG_WR(bp, reg, val);
 293         return val;
 294 }
 295
 296 /******************************************************************/
 297 /*                      EPIO/GPIO section                         */
 298 /******************************************************************/
 299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 300 {
 301         u32 epio_mask, gp_oenable;
 302         *en = 0;
 303         /* Sanity check */
 304         if (epio_pin > 31) {
 305                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 306                 return;
 307         }
 308
 309         epio_mask = 1 << epio_pin;
 310         /* Set this EPIO to output */
 311         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 312         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 313
 314         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 315 }
 316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 317 {
 318         u32 epio_mask, gp_output, gp_oenable;
 319
 320         /* Sanity check */
 321         if (epio_pin > 31) {
 322                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 323                 return;
 324         }
 325         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 326         epio_mask = 1 << epio_pin;
 327         /* Set this EPIO to output */
 328         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 329         if (en)
 330                 gp_output |= epio_mask;
 331         else
 332                 gp_output &= ~epio_mask;
 333
 334         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 335
 336         /* Set the value for this EPIO */
 337         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 338         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 339 }
 340
 341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 342 {
 343         if (pin_cfg == PIN_CFG_NA)
 344                 return;
 345         if (pin_cfg >= PIN_CFG_EPIO0) {
 346                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 347         } else {
 348                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 349                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 350                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 351         }
 352 }
 353
 354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 355 {
 356         if (pin_cfg == PIN_CFG_NA)
 357                 return -EINVAL;
 358         if (pin_cfg >= PIN_CFG_EPIO0) {
 359                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 360         } else {
 361                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 362                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 363                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 364         }
 365         return 0;
 366
 367 }
 368 /******************************************************************/
 369 /*                              ETS section                       */
 370 /******************************************************************/
 371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 372 {
 373         /* ETS disabled configuration*/
 374         struct bnx2x *bp = params->bp;
 375
 376         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 377
 378         /*
 379          * mapping between entry  priority to client number (0,1,2 -debug and
 380          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 381          * 3bits client num.
 382          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 383          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 384          */
 385
 386         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 387         /*
 388          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 389          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 390          * COS0 entry, 4 - COS1 entry.
 391          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 392          * bit4   bit3    bit2   bit1     bit0
 393          * MCP and debug are strict
 394          */
 395
 396         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 397         /* defines which entries (clients) are subjected to WFQ arbitration */
 398         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 399         /*
 400          * For strict priority entries defines the number of consecutive
 401          * slots for the highest priority.
 402          */
 403         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 404         /*
 405          * mapping between the CREDIT_WEIGHT registers and actual client
 406          * numbers
 407          */
 408         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 409         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 410         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 411
 412         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 414         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 415         /* ETS mode disable */
 416         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 417         /*
 418          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 419          * weight for COS0/COS1.
 420          */
 421         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 422         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 423         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 424         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 425         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 426         /* Defines the number of consecutive slots for the strict priority */
 427         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 428 }
 429 /******************************************************************************
 430 * Description:
 431 *       Getting min_w_val will be set according to line speed .
 432 *.
 433 ******************************************************************************/
 434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 435 {
 436         u32 min_w_val = 0;
 437         /* Calculate min_w_val.*/
 438         if (vars->link_up) {
 439                 if (SPEED_20000 == vars->line_speed)
 440                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 441                 else
 442                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 443         } else
 444                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 445         /**
 446          *  If the link isn't up (static configuration for example ) The
 447          *  link will be according to 20GBPS.
 448         */
 449         return min_w_val;
 450 }
 451 /******************************************************************************
 452 * Description:
 453 *       Getting credit upper bound form min_w_val.
 454 *.
 455 ******************************************************************************/
 456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 457 {
 458         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 459                                                 MAX_PACKET_SIZE);
 460         return credit_upper_bound;
 461 }
 462 /******************************************************************************
 463 * Description:
 464 *       Set credit upper bound for NIG.
 465 *.
 466 ******************************************************************************/
 467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 468         const struct link_params *params,
 469         const u32 min_w_val)
 470 {
 471         struct bnx2x *bp = params->bp;
 472         const u8 port = params->port;
 473         const u32 credit_upper_bound =
 474             bnx2x_ets_get_credit_upper_bound(min_w_val);
 475
 476         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 477                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 478         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 479                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 480         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 481                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 482         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 483                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 484         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 485                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 486         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 487                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 488
 489         if (0 == port) {
 490                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 491                         credit_upper_bound);
 492                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 493                         credit_upper_bound);
 494                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 495                         credit_upper_bound);
 496         }
 497 }
 498 /******************************************************************************
 499 * Description:
 500 *       Will return the NIG ETS registers to init values.Except
 501 *       credit_upper_bound.
 502 *       That isn't used in this configuration (No WFQ is enabled) and will be
 503 *       configured acording to spec
 504 *.
 505 ******************************************************************************/
 506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 507                                         const struct link_vars *vars)
 508 {
 509         struct bnx2x *bp = params->bp;
 510         const u8 port = params->port;
 511         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 512         /**
 513          * mapping between entry  priority to client number (0,1,2 -debug and
 514          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 515          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 516          * reset value or init tool
 517          */
 518         if (port) {
 519                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 520                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 521         } else {
 522                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 523                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 524         }
 525         /**
 526         * For strict priority entries defines the number of consecutive
 527         * slots for the highest priority.
 528         */
 529         /* TODO_ETS - Should be done by reset value or init tool */
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 531                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 532         /**
 533          * mapping between the CREDIT_WEIGHT registers and actual client
 534          * numbers
 535          */
 536         /* TODO_ETS - Should be done by reset value or init tool */
 537         if (port) {
 538                 /*Port 1 has 6 COS*/
 539                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 541         } else {
 542                 /*Port 0 has 9 COS*/
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 544                        0x43210876);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 546         }
 547
 548         /**
 549          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 550          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 551          * COS0 entry, 4 - COS1 entry.
 552          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 553          * bit4   bit3    bit2   bit1     bit0
 554          * MCP and debug are strict
 555          */
 556         if (port)
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 558         else
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 560         /* defines which entries (clients) are subjected to WFQ arbitration */
 561         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 562                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 563
 564         /**
 565         * Please notice the register address are note continuous and a
 566         * for here is note appropriate.In 2 port mode port0 only COS0-5
 567         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 568         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 569         * are never used for WFQ
 570         */
 571         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 572                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 573         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 574                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 575         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 576                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 578                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 579         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 580                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 581         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 582                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 583         if (0 == port) {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 586                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 587         }
 588
 589         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 590 }
 591 /******************************************************************************
 592 * Description:
 593 *       Set credit upper bound for PBF.
 594 *.
 595 ******************************************************************************/
 596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 597         const struct link_params *params,
 598         const u32 min_w_val)
 599 {
 600         struct bnx2x *bp = params->bp;
 601         const u32 credit_upper_bound =
 602             bnx2x_ets_get_credit_upper_bound(min_w_val);
 603         const u8 port = params->port;
 604         u32 base_upper_bound = 0;
 605         u8 max_cos = 0;
 606         u8 i = 0;
 607         /**
 608         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 609         * port mode port1 has COS0-2 that can be used for WFQ.
 610         */
 611         if (0 == port) {
 612                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 613                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 614         } else {
 615                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 616                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 617         }
 618
 619         for (i = 0; i < max_cos; i++)
 620                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 621 }
 622
 623 /******************************************************************************
 624 * Description:
 625 *       Will return the PBF ETS registers to init values.Except
 626 *       credit_upper_bound.
 627 *       That isn't used in this configuration (No WFQ is enabled) and will be
 628 *       configured acording to spec
 629 *.
 630 ******************************************************************************/
 631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 632 {
 633         struct bnx2x *bp = params->bp;
 634         const u8 port = params->port;
 635         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 636         u8 i = 0;
 637         u32 base_weight = 0;
 638         u8 max_cos = 0;
 639
 640         /**
 641          * mapping between entry  priority to client number 0 - COS0
 642          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 643          * TODO_ETS - Should be done by reset value or init tool
 644          */
 645         if (port)
 646                 /*  0x688 (|011|0 10|00 1|000) */
 647                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 648         else
 649                 /*  (10 1|100 |011|0 10|00 1|000) */
 650                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 651
 652         /* TODO_ETS - Should be done by reset value or init tool */
 653         if (port)
 654                 /* 0x688 (|011|0 10|00 1|000)*/
 655                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 656         else
 657         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 658         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 659
 660         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 661                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 662
 663
 664         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 665                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 666
 667         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 668                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 669         /**
 670         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 671         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 672         */
 673         if (0 == port) {
 674                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 675                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 676         } else {
 677                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 678                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 679         }
 680
 681         for (i = 0; i < max_cos; i++)
 682                 REG_WR(bp, base_weight + (0x4 * i), 0);
 683
 684         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 685 }
 686 /******************************************************************************
 687 * Description:
 688 *       E3B0 disable will return basicly the values to init values.
 689 *.
 690 ******************************************************************************/
 691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 692                                    const struct link_vars *vars)
 693 {
 694         struct bnx2x *bp = params->bp;
 695
 696         if (!CHIP_IS_E3B0(bp)) {
 697                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
 698                                    "\n");
 699                 return -EINVAL;
 700         }
 701
 702         bnx2x_ets_e3b0_nig_disabled(params, vars);
 703
 704         bnx2x_ets_e3b0_pbf_disabled(params);
 705
 706         return 0;
 707 }
 708
 709 /******************************************************************************
 710 * Description:
 711 *       Disable will return basicly the values to init values.
 712 *.
 713 ******************************************************************************/
 714 int bnx2x_ets_disabled(struct link_params *params,
 715                       struct link_vars *vars)
 716 {
 717         struct bnx2x *bp = params->bp;
 718         int bnx2x_status = 0;
 719
 720         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 721                 bnx2x_ets_e2e3a0_disabled(params);
 722         else if (CHIP_IS_E3B0(bp))
 723                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 724         else {
 725                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 726                 return -EINVAL;
 727         }
 728
 729         return bnx2x_status;
 730 }
 731
 732 /******************************************************************************
 733 * Description
 734 *       Set the COS mappimg to SP and BW until this point all the COS are not
 735 *       set as SP or BW.
 736 ******************************************************************************/
 737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 738                                   const struct bnx2x_ets_params *ets_params,
 739                                   const u8 cos_sp_bitmap,
 740                                   const u8 cos_bw_bitmap)
 741 {
 742         struct bnx2x *bp = params->bp;
 743         const u8 port = params->port;
 744         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 745         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 746         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 747         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 748
 749         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 750                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 751
 752         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 753                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 754
 755         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 756                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 757                nig_cli_subject2wfq_bitmap);
 758
 759         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 760                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 761                pbf_cli_subject2wfq_bitmap);
 762
 763         return 0;
 764 }
 765
 766 /******************************************************************************
 767 * Description:
 768 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 769 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 770 ******************************************************************************/
 771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 772                                      const u8 cos_entry,
 773                                      const u32 min_w_val_nig,
 774                                      const u32 min_w_val_pbf,
 775                                      const u16 total_bw,
 776                                      const u8 bw,
 777                                      const u8 port)
 778 {
 779         u32 nig_reg_adress_crd_weight = 0;
 780         u32 pbf_reg_adress_crd_weight = 0;
 781         /* Calculate and set BW for this COS*/
 782         const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
 783         const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
 784
 785         switch (cos_entry) {
 786         case 0:
 787             nig_reg_adress_crd_weight =
 788                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 789                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 790              pbf_reg_adress_crd_weight = (port) ?
 791                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 792              break;
 793         case 1:
 794              nig_reg_adress_crd_weight = (port) ?
 795                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 796                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 797              pbf_reg_adress_crd_weight = (port) ?
 798                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 799              break;
 800         case 2:
 801              nig_reg_adress_crd_weight = (port) ?
 802                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 803                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 804
 805                  pbf_reg_adress_crd_weight = (port) ?
 806                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 807              break;
 808         case 3:
 809             if (port)
 810                         return -EINVAL;
 811              nig_reg_adress_crd_weight =
 812                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 813              pbf_reg_adress_crd_weight =
 814                  PBF_REG_COS3_WEIGHT_P0;
 815              break;
 816         case 4:
 817             if (port)
 818                 return -EINVAL;
 819              nig_reg_adress_crd_weight =
 820                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 821              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 822              break;
 823         case 5:
 824             if (port)
 825                 return -EINVAL;
 826              nig_reg_adress_crd_weight =
 827                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 828              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 829              break;
 830         }
 831
 832         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 833
 834         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 835
 836         return 0;
 837 }
 838 /******************************************************************************
 839 * Description:
 840 *       Calculate the total BW.A value of 0 isn't legal.
 841 *.
 842 ******************************************************************************/
 843 static int bnx2x_ets_e3b0_get_total_bw(
 844         const struct link_params *params,
 845         const struct bnx2x_ets_params *ets_params,
 846         u16 *total_bw)
 847 {
 848         struct bnx2x *bp = params->bp;
 849         u8 cos_idx = 0;
 850
 851         *total_bw = 0 ;
 852         /* Calculate total BW requested */
 853         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 854                 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
 855
 856                         if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
 857                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 858                                                    "was set to 0\n");
 859                         return -EINVAL;
 860                 }
 861                 *total_bw +=
 862                     ets_params->cos[cos_idx].params.bw_params.bw;
 863             }
 864         }
 865
 866         /*Check taotl BW is valid */
 867         if ((100 != *total_bw) || (0 == *total_bw)) {
 868                 if (0 == *total_bw) {
 869                         DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
 870                                            "shouldn't be 0\n");
 871                         return -EINVAL;
 872                 }
 873                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
 874                                    "100\n");
 875                 /**
 876                 *   We can handle a case whre the BW isn't 100 this can happen
 877                 *   if the TC are joined.
 878                 */
 879         }
 880         return 0;
 881 }
 882
 883 /******************************************************************************
 884 * Description:
 885 *       Invalidate all the sp_pri_to_cos.
 886 *.
 887 ******************************************************************************/
 888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 889 {
 890         u8 pri = 0;
 891         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 892                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 893 }
 894 /******************************************************************************
 895 * Description:
 896 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 897 *       according to sp_pri_to_cos.
 898 *.
 899 ******************************************************************************/
 900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 901                                             u8 *sp_pri_to_cos, const u8 pri,
 902                                             const u8 cos_entry)
 903 {
 904         struct bnx2x *bp = params->bp;
 905         const u8 port = params->port;
 906         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 907                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 908
 909         if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
 910                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 911                                    "parameter There can't be two COS's with"
 912                                    "the same strict pri\n");
 913                 return -EINVAL;
 914         }
 915
 916         if (pri > max_num_of_cos) {
 917                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
 918                                "parameter Illegal strict priority\n");
 919             return -EINVAL;
 920         }
 921
 922         sp_pri_to_cos[pri] = cos_entry;
 923         return 0;
 924
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Returns the correct value according to COS and priority in
 930 *       the sp_pri_cli register.
 931 *.
 932 ******************************************************************************/
 933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 934                                          const u8 pri_set,
 935                                          const u8 pri_offset,
 936                                          const u8 entry_size)
 937 {
 938         u64 pri_cli_nig = 0;
 939         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 940                                                     (pri_set + pri_offset));
 941
 942         return pri_cli_nig;
 943 }
 944 /******************************************************************************
 945 * Description:
 946 *       Returns the correct value according to COS and priority in the
 947 *       sp_pri_cli register for NIG.
 948 *.
 949 ******************************************************************************/
 950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 951 {
 952         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 953         const u8 nig_cos_offset = 3;
 954         const u8 nig_pri_offset = 3;
 955
 956         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 957                 nig_pri_offset, 4);
 958
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for PBF.
 964 *.
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 967 {
 968         const u8 pbf_cos_offset = 0;
 969         const u8 pbf_pri_offset = 0;
 970
 971         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 972                 pbf_pri_offset, 3);
 973
 974 }
 975
 976 /******************************************************************************
 977 * Description:
 978 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 979 *       according to sp_pri_to_cos.(which COS has higher priority)
 980 *.
 981 ******************************************************************************/
 982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 983                                              u8 *sp_pri_to_cos)
 984 {
 985         struct bnx2x *bp = params->bp;
 986         u8 i = 0;
 987         const u8 port = params->port;
 988         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 989         u64 pri_cli_nig = 0x210;
 990         u32 pri_cli_pbf = 0x0;
 991         u8 pri_set = 0;
 992         u8 pri_bitmask = 0;
 993         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 994                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 995
 996         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
 997
 998         /* Set all the strict priority first */
 999         for (i = 0; i < max_num_of_cos; i++) {
1000                 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001                         if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1002                                 DP(NETIF_MSG_LINK,
1003                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004                                            "invalid cos entry\n");
1005                                 return -EINVAL;
1006                         }
1007
1008                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009                             sp_pri_to_cos[i], pri_set);
1010
1011                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012                             sp_pri_to_cos[i], pri_set);
1013                         pri_bitmask = 1 << sp_pri_to_cos[i];
1014                         /* COS is used remove it from bitmap.*/
1015                         if (0 == (pri_bitmask & cos_bit_to_set)) {
1016                                 DP(NETIF_MSG_LINK,
1017                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018                                         "invalid There can't be two COS's with"
1019                                         " the same strict pri\n");
1020                                 return -EINVAL;
1021                         }
1022                         cos_bit_to_set &= ~pri_bitmask;
1023                         pri_set++;
1024                 }
1025         }
1026
1027         /* Set all the Non strict priority i= COS*/
1028         for (i = 0; i < max_num_of_cos; i++) {
1029                 pri_bitmask = 1 << i;
1030                 /* Check if COS was already used for SP */
1031                 if (pri_bitmask & cos_bit_to_set) {
1032                         /* COS wasn't used for SP */
1033                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1034                             i, pri_set);
1035
1036                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1037                             i, pri_set);
1038                         /* COS is used remove it from bitmap.*/
1039                         cos_bit_to_set &= ~pri_bitmask;
1040                         pri_set++;
1041                 }
1042         }
1043
1044         if (pri_set != max_num_of_cos) {
1045                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046                                    "entries were set\n");
1047                 return -EINVAL;
1048         }
1049
1050         if (port) {
1051                 /* Only 6 usable clients*/
1052                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1053                        (u32)pri_cli_nig);
1054
1055                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1056         } else {
1057                 /* Only 9 usable clients*/
1058                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1060
1061                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1062                        pri_cli_nig_lsb);
1063                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1064                        pri_cli_nig_msb);
1065
1066                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1067         }
1068         return 0;
1069 }
1070
1071 /******************************************************************************
1072 * Description:
1073 *       Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076                          const struct link_vars *vars,
1077                          const struct bnx2x_ets_params *ets_params)
1078 {
1079         struct bnx2x *bp = params->bp;
1080         int bnx2x_status = 0;
1081         const u8 port = params->port;
1082         u16 total_bw = 0;
1083         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085         u8 cos_bw_bitmap = 0;
1086         u8 cos_sp_bitmap = 0;
1087         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1090         u8 cos_entry = 0;
1091
1092         if (!CHIP_IS_E3B0(bp)) {
1093                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1094                                    "\n");
1095                 return -EINVAL;
1096         }
1097
1098         if ((ets_params->num_of_cos > max_num_of_cos)) {
1099                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100                                    "isn't supported\n");
1101                 return -EINVAL;
1102         }
1103
1104         /* Prepare sp strict priority parameters*/
1105         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1106
1107         /* Prepare BW parameters*/
1108         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1109                                                    &total_bw);
1110         if (0 != bnx2x_status) {
1111                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1112                                    "\n");
1113                 return -EINVAL;
1114         }
1115
1116         /**
1117          *  Upper bound is set according to current link speed (min_w_val
1118          *  should be the same for upper bound and COS credit val).
1119          */
1120         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1122
1123
1124         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126                         cos_bw_bitmap |= (1 << cos_entry);
1127                         /**
1128                          * The function also sets the BW in HW(not the mappin
1129                          * yet)
1130                          */
1131                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1133                                 total_bw,
1134                                 ets_params->cos[cos_entry].params.bw_params.bw,
1135                                  port);
1136                 } else if (bnx2x_cos_state_strict ==
1137                         ets_params->cos[cos_entry].state){
1138                         cos_sp_bitmap |= (1 << cos_entry);
1139
1140                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1141                                 params,
1142                                 sp_pri_to_cos,
1143                                 ets_params->cos[cos_entry].params.sp_params.pri,
1144                                 cos_entry);
1145
1146                 } else {
1147                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1148                                            " valid\n");
1149                         return -EINVAL;
1150                 }
1151                 if (0 != bnx2x_status) {
1152                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1153                                            "failed\n");
1154                         return bnx2x_status;
1155                 }
1156         }
1157
1158         /* Set SP register (which COS has higher priority) */
1159         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1160                                                          sp_pri_to_cos);
1161
1162         if (0 != bnx2x_status) {
1163                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1164                                    "failed\n");
1165                 return bnx2x_status;
1166         }
1167
1168         /* Set client mapping of BW and strict */
1169         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1170                                               cos_sp_bitmap,
1171                                               cos_bw_bitmap);
1172
1173         if (0 != bnx2x_status) {
1174                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175                 return bnx2x_status;
1176         }
1177         return 0;
1178 }
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1180 {
1181         /* ETS disabled configuration */
1182         struct bnx2x *bp = params->bp;
1183         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1184         /*
1185          * defines which entries (clients) are subjected to WFQ arbitration
1186          * COS0 0x8
1187          * COS1 0x10
1188          */
1189         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1190         /*
1191          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192          * client numbers (WEIGHT_0 does not actually have to represent
1193          * client 0)
1194          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1195          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1196          */
1197         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1198
1199         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1203
1204         /* ETS mode enabled*/
1205         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1206
1207         /* Defines the number of consecutive slots for the strict priority */
1208         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1209         /*
1210          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1212          * entry, 4 - COS1 entry.
1213          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214          * bit4   bit3    bit2     bit1    bit0
1215          * MCP and debug are strict
1216          */
1217         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1218
1219         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1224 }
1225
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1227                         const u32 cos1_bw)
1228 {
1229         /* ETS disabled configuration*/
1230         struct bnx2x *bp = params->bp;
1231         const u32 total_bw = cos0_bw + cos1_bw;
1232         u32 cos0_credit_weight = 0;
1233         u32 cos1_credit_weight = 0;
1234
1235         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1236
1237         if ((0 == total_bw) ||
1238             (0 == cos0_bw) ||
1239             (0 == cos1_bw)) {
1240                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1241                 return;
1242         }
1243
1244         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1245                 total_bw;
1246         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1247                 total_bw;
1248
1249         bnx2x_ets_bw_limit_common(params);
1250
1251         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1253
1254         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1256 }
1257
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1259 {
1260         /* ETS disabled configuration*/
1261         struct bnx2x *bp = params->bp;
1262         u32 val = 0;
1263
1264         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1265         /*
1266          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267          * as strict.  Bits 0,1,2 - debug and management entries,
1268          * 3 - COS0 entry, 4 - COS1 entry.
1269          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270          *  bit4   bit3   bit2      bit1     bit0
1271          * MCP and debug are strict
1272          */
1273         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1274         /*
1275          * For strict priority entries defines the number of consecutive slots
1276          * for the highest priority.
1277          */
1278         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279         /* ETS mode disable */
1280         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281         /* Defines the number of consecutive slots for the strict priority */
1282         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1283
1284         /* Defines the number of consecutive slots for the strict priority */
1285         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1286
1287         /*
1288          * mapping between entry  priority to client number (0,1,2 -debug and
1289          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1290          * 3bits client num.
1291          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1292          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1293          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1294          */
1295         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1297
1298         return 0;
1299 }
1300 /******************************************************************/
1301 /*                      PFC section                               */
1302 /******************************************************************/
1303
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305                                   struct link_vars *vars,
1306                                   u8 is_lb)
1307 {
1308         struct bnx2x *bp = params->bp;
1309         u32 xmac_base;
1310         u32 pause_val, pfc0_val, pfc1_val;
1311
1312         /* XMAC base adrr */
1313         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1314
1315         /* Initialize pause and pfc registers */
1316         pause_val = 0x18000;
1317         pfc0_val = 0xFFFF8000;
1318         pfc1_val = 0x2;
1319
1320         /* No PFC support */
1321         if (!(params->feature_config_flags &
1322               FEATURE_CONFIG_PFC_ENABLED)) {
1323
1324                 /*
1325                  * RX flow control - Process pause frame in receive direction
1326                  */
1327                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1329
1330                 /*
1331                  * TX flow control - Send pause packet when buffer is full
1332                  */
1333                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335         } else {/* PFC support */
1336                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1340         }
1341
1342         /* Write pause and PFC registers */
1343         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1346
1347         udelay(30);
1348 }
1349
1350
1351 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
1352                                      u32 pfc_frames_sent[2],
1353                                      u32 pfc_frames_received[2])
1354 {
1355         /* Read pfc statistic */
1356         struct bnx2x *bp = params->bp;
1357         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1358                 NIG_REG_INGRESS_BMAC0_MEM;
1359
1360         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
1361
1362         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
1363                                         pfc_frames_sent, 2);
1364
1365         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
1366                                         pfc_frames_received, 2);
1367
1368 }
1369 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1370                                     u32 pfc_frames_sent[2],
1371                                     u32 pfc_frames_received[2])
1372 {
1373         /* Read pfc statistic */
1374         struct bnx2x *bp = params->bp;
1375         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1376         u32 val_xon = 0;
1377         u32 val_xoff = 0;
1378
1379         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1380
1381         /* PFC received frames */
1382         val_xoff = REG_RD(bp, emac_base +
1383                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1384         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1385         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1386         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1387
1388         pfc_frames_received[0] = val_xon + val_xoff;
1389
1390         /* PFC received sent */
1391         val_xoff = REG_RD(bp, emac_base +
1392                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1393         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1394         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1395         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1396
1397         pfc_frames_sent[0] = val_xon + val_xoff;
1398 }
1399
1400 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1401                          u32 pfc_frames_sent[2],
1402                          u32 pfc_frames_received[2])
1403 {
1404         /* Read pfc statistic */
1405         struct bnx2x *bp = params->bp;
1406         u32 val = 0;
1407         DP(NETIF_MSG_LINK, "pfc statistic\n");
1408
1409         if (!vars->link_up)
1410                 return;
1411
1412         val = REG_RD(bp, MISC_REG_RESET_REG_2);
1413         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1414             == 0) {
1415                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
1416                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1417                                         pfc_frames_received);
1418         } else {
1419                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
1420                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
1421                                          pfc_frames_received);
1422         }
1423 }
1424 /******************************************************************/
1425 /*                      MAC/PBF section                           */
1426 /******************************************************************/
1427 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1428 {
1429         u32 mode, emac_base;
1430         /**
1431          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1432          * (a value of 49==0x31) and make sure that the AUTO poll is off
1433          */
1434
1435         if (CHIP_IS_E2(bp))
1436                 emac_base = GRCBASE_EMAC0;
1437         else
1438                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1439         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1440         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1441                   EMAC_MDIO_MODE_CLOCK_CNT);
1442         if (USES_WARPCORE(bp))
1443                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1444         else
1445                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1446
1447         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1448         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1449
1450         udelay(40);
1451 }
1452
1453 static void bnx2x_emac_init(struct link_params *params,
1454                             struct link_vars *vars)
1455 {
1456         /* reset and unreset the emac core */
1457         struct bnx2x *bp = params->bp;
1458         u8 port = params->port;
1459         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1460         u32 val;
1461         u16 timeout;
1462
1463         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1464                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1465         udelay(5);
1466         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1467                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1468
1469         /* init emac - use read-modify-write */
1470         /* self clear reset */
1471         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1472         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1473
1474         timeout = 200;
1475         do {
1476                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1477                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1478                 if (!timeout) {
1479                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1480                         return;
1481                 }
1482                 timeout--;
1483         } while (val & EMAC_MODE_RESET);
1484         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1485         /* Set mac address */
1486         val = ((params->mac_addr[0] << 8) |
1487                 params->mac_addr[1]);
1488         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1489
1490         val = ((params->mac_addr[2] << 24) |
1491                (params->mac_addr[3] << 16) |
1492                (params->mac_addr[4] << 8) |
1493                 params->mac_addr[5]);
1494         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1495 }
1496
1497 static void bnx2x_set_xumac_nig(struct link_params *params,
1498                                 u16 tx_pause_en,
1499                                 u8 enable)
1500 {
1501         struct bnx2x *bp = params->bp;
1502
1503         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1504                enable);
1505         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1506                enable);
1507         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1508                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1509 }
1510
1511 static void bnx2x_umac_enable(struct link_params *params,
1512                             struct link_vars *vars, u8 lb)
1513 {
1514         u32 val;
1515         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1516         struct bnx2x *bp = params->bp;
1517         /* Reset UMAC */
1518         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1519                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1520         usleep_range(1000, 1000);
1521
1522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1523                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1524
1525         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1526
1527         /**
1528          * This register determines on which events the MAC will assert
1529          * error on the i/f to the NIG along w/ EOP.
1530          */
1531
1532         /**
1533          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1534          * params->port*0x14,      0xfffff.
1535          */
1536         /* This register opens the gate for the UMAC despite its name */
1537         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1538
1539         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1540                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1541                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1542                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1543         switch (vars->line_speed) {
1544         case SPEED_10:
1545                 val |= (0<<2);
1546                 break;
1547         case SPEED_100:
1548                 val |= (1<<2);
1549                 break;
1550         case SPEED_1000:
1551                 val |= (2<<2);
1552                 break;
1553         case SPEED_2500:
1554                 val |= (3<<2);
1555                 break;
1556         default:
1557                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1558                                vars->line_speed);
1559                 break;
1560         }
1561         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1562         udelay(50);
1563
1564         /* Enable RX and TX */
1565         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1566         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1567                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1568         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1569         udelay(50);
1570
1571         /* Remove SW Reset */
1572         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1573
1574         /* Check loopback mode */
1575         if (lb)
1576                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1577         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1578
1579         /*
1580          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1581          * length used by the MAC receive logic to check frames.
1582          */
1583         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1584         bnx2x_set_xumac_nig(params,
1585                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1586         vars->mac_type = MAC_TYPE_UMAC;
1587
1588 }
1589
1590 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1591 {
1592         u32 port4mode_ovwr_val;
1593         /* Check 4-port override enabled */
1594         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1595         if (port4mode_ovwr_val & (1<<0)) {
1596                 /* Return 4-port mode override value */
1597                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1598         }
1599         /* Return 4-port mode from input pin */
1600         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1601 }
1602
1603 /* Define the XMAC mode */
1604 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1605 {
1606         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1607
1608         /**
1609         * In 4-port mode, need to set the mode only once, so if XMAC is
1610         * already out of reset, it means the mode has already been set,
1611         * and it must not* reset the XMAC again, since it controls both
1612         * ports of the path
1613         **/
1614
1615         if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1616              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1617                 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1618                                    " in 4-port mode\n");
1619                 return;
1620         }
1621
1622         /* Hard reset */
1623         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1624                MISC_REGISTERS_RESET_REG_2_XMAC);
1625         usleep_range(1000, 1000);
1626
1627         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1628                MISC_REGISTERS_RESET_REG_2_XMAC);
1629         if (is_port4mode) {
1630                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1631
1632                 /*  Set the number of ports on the system side to up to 2 */
1633                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1634
1635                 /* Set the number of ports on the Warp Core to 10G */
1636                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1637         } else {
1638                 /*  Set the number of ports on the system side to 1 */
1639                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1640                 if (max_speed == SPEED_10000) {
1641                         DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1642                                            " port per path\n");
1643                         /* Set the number of ports on the Warp Core to 10G */
1644                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1645                 } else {
1646                         DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1647                                            " per path\n");
1648                         /* Set the number of ports on the Warp Core to 20G */
1649                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1650                 }
1651         }
1652         /* Soft reset */
1653         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1654                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1655         usleep_range(1000, 1000);
1656
1657         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1658                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1659
1660 }
1661
1662 static void bnx2x_xmac_disable(struct link_params *params)
1663 {
1664         u8 port = params->port;
1665         struct bnx2x *bp = params->bp;
1666         u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1667
1668         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1669             MISC_REGISTERS_RESET_REG_2_XMAC) {
1670                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1671                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1672                 usleep_range(1000, 1000);
1673                 bnx2x_set_xumac_nig(params, 0, 0);
1674                 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1675                        XMAC_CTRL_REG_SOFT_RESET);
1676         }
1677 }
1678
1679 static int bnx2x_xmac_enable(struct link_params *params,
1680                              struct link_vars *vars, u8 lb)
1681 {
1682         u32 val, xmac_base;
1683         struct bnx2x *bp = params->bp;
1684         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1685
1686         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1687
1688         bnx2x_xmac_init(bp, vars->line_speed);
1689
1690         /*
1691          * This register determines on which events the MAC will assert
1692          * error on the i/f to the NIG along w/ EOP.
1693          */
1694
1695         /*
1696          * This register tells the NIG whether to send traffic to UMAC
1697          * or XMAC
1698          */
1699         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1700
1701         /* Set Max packet size */
1702         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1703
1704         /* CRC append for Tx packets */
1705         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1706
1707         /* update PFC */
1708         bnx2x_update_pfc_xmac(params, vars, 0);
1709
1710         /* Enable TX and RX */
1711         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1712
1713         /* Check loopback mode */
1714         if (lb)
1715                 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1716         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1717         bnx2x_set_xumac_nig(params,
1718                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1719
1720         vars->mac_type = MAC_TYPE_XMAC;
1721
1722         return 0;
1723 }
1724 static int bnx2x_emac_enable(struct link_params *params,
1725                              struct link_vars *vars, u8 lb)
1726 {
1727         struct bnx2x *bp = params->bp;
1728         u8 port = params->port;
1729         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1730         u32 val;
1731
1732         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1733
1734         /* enable emac and not bmac */
1735         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1736
1737         /* ASIC */
1738         if (vars->phy_flags & PHY_XGXS_FLAG) {
1739                 u32 ser_lane = ((params->lane_config &
1740                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1741                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1742
1743                 DP(NETIF_MSG_LINK, "XGXS\n");
1744                 /* select the master lanes (out of 0-3) */
1745                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1746                 /* select XGXS */
1747                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1748
1749         } else { /* SerDes */
1750                 DP(NETIF_MSG_LINK, "SerDes\n");
1751                 /* select SerDes */
1752                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1753         }
1754
1755         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1756                       EMAC_RX_MODE_RESET);
1757         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1758                       EMAC_TX_MODE_RESET);
1759
1760         if (CHIP_REV_IS_SLOW(bp)) {
1761                 /* config GMII mode */
1762                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1763                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1764         } else { /* ASIC */
1765                 /* pause enable/disable */
1766                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1767                                EMAC_RX_MODE_FLOW_EN);
1768
1769                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1770                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1771                                 EMAC_TX_MODE_FLOW_EN));
1772                 if (!(params->feature_config_flags &
1773                       FEATURE_CONFIG_PFC_ENABLED)) {
1774                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1775                                 bnx2x_bits_en(bp, emac_base +
1776                                               EMAC_REG_EMAC_RX_MODE,
1777                                               EMAC_RX_MODE_FLOW_EN);
1778
1779                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1780                                 bnx2x_bits_en(bp, emac_base +
1781                                               EMAC_REG_EMAC_TX_MODE,
1782                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1783                                                EMAC_TX_MODE_FLOW_EN));
1784                 } else
1785                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1786                                       EMAC_TX_MODE_FLOW_EN);
1787         }
1788
1789         /* KEEP_VLAN_TAG, promiscuous */
1790         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1791         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1792
1793         /*
1794          * Setting this bit causes MAC control frames (except for pause
1795          * frames) to be passed on for processing. This setting has no
1796          * affect on the operation of the pause frames. This bit effects
1797          * all packets regardless of RX Parser packet sorting logic.
1798          * Turn the PFC off to make sure we are in Xon state before
1799          * enabling it.
1800          */
1801         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1802         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1803                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1804                 /* Enable PFC again */
1805                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1806                         EMAC_REG_RX_PFC_MODE_RX_EN |
1807                         EMAC_REG_RX_PFC_MODE_TX_EN |
1808                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1809
1810                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1811                         ((0x0101 <<
1812                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1813                          (0x00ff <<
1814                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1815                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1816         }
1817         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1818
1819         /* Set Loopback */
1820         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1821         if (lb)
1822                 val |= 0x810;
1823         else
1824                 val &= ~0x810;
1825         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1826
1827         /* enable emac */
1828         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1829
1830         /* enable emac for jumbo packets */
1831         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1832                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1833                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1834
1835         /* strip CRC */
1836         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1837
1838         /* disable the NIG in/out to the bmac */
1839         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1840         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1841         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1842
1843         /* enable the NIG in/out to the emac */
1844         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1845         val = 0;
1846         if ((params->feature_config_flags &
1847               FEATURE_CONFIG_PFC_ENABLED) ||
1848             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1849                 val = 1;
1850
1851         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1852         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1853
1854         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1855
1856         vars->mac_type = MAC_TYPE_EMAC;
1857         return 0;
1858 }
1859
1860 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1861                                    struct link_vars *vars)
1862 {
1863         u32 wb_data[2];
1864         struct bnx2x *bp = params->bp;
1865         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1866                 NIG_REG_INGRESS_BMAC0_MEM;
1867
1868         u32 val = 0x14;
1869         if ((!(params->feature_config_flags &
1870               FEATURE_CONFIG_PFC_ENABLED)) &&
1871                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1872                 /* Enable BigMAC to react on received Pause packets */
1873                 val |= (1<<5);
1874         wb_data[0] = val;
1875         wb_data[1] = 0;
1876         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1877
1878         /* tx control */
1879         val = 0xc0;
1880         if (!(params->feature_config_flags &
1881               FEATURE_CONFIG_PFC_ENABLED) &&
1882                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1883                 val |= 0x800000;
1884         wb_data[0] = val;
1885         wb_data[1] = 0;
1886         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1887 }
1888
1889 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1890                                    struct link_vars *vars,
1891                                    u8 is_lb)
1892 {
1893         /*
1894          * Set rx control: Strip CRC and enable BigMAC to relay
1895          * control packets to the system as well
1896          */
1897         u32 wb_data[2];
1898         struct bnx2x *bp = params->bp;
1899         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1900                 NIG_REG_INGRESS_BMAC0_MEM;
1901         u32 val = 0x14;
1902
1903         if ((!(params->feature_config_flags &
1904               FEATURE_CONFIG_PFC_ENABLED)) &&
1905                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1906                 /* Enable BigMAC to react on received Pause packets */
1907                 val |= (1<<5);
1908         wb_data[0] = val;
1909         wb_data[1] = 0;
1910         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1911         udelay(30);
1912
1913         /* Tx control */
1914         val = 0xc0;
1915         if (!(params->feature_config_flags &
1916                                 FEATURE_CONFIG_PFC_ENABLED) &&
1917             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1918                 val |= 0x800000;
1919         wb_data[0] = val;
1920         wb_data[1] = 0;
1921         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1922
1923         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1924                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1925                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1926                 wb_data[0] = 0x0;
1927                 wb_data[0] |= (1<<0);  /* RX */
1928                 wb_data[0] |= (1<<1);  /* TX */
1929                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1930                 wb_data[0] |= (1<<3);  /* 8 cos */
1931                 wb_data[0] |= (1<<5);  /* STATS */
1932                 wb_data[1] = 0;
1933                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1934                             wb_data, 2);
1935                 /* Clear the force Xon */
1936                 wb_data[0] &= ~(1<<2);
1937         } else {
1938                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1939                 /* disable PFC RX & TX & STATS and set 8 COS */
1940                 wb_data[0] = 0x8;
1941                 wb_data[1] = 0;
1942         }
1943
1944         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1945
1946         /*
1947          * Set Time (based unit is 512 bit time) between automatic
1948          * re-sending of PP packets amd enable automatic re-send of
1949          * Per-Priroity Packet as long as pp_gen is asserted and
1950          * pp_disable is low.
1951          */
1952         val = 0x8000;
1953         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1954                 val |= (1<<16); /* enable automatic re-send */
1955
1956         wb_data[0] = val;
1957         wb_data[1] = 0;
1958         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1959                     wb_data, 2);
1960
1961         /* mac control */
1962         val = 0x3; /* Enable RX and TX */
1963         if (is_lb) {
1964                 val |= 0x4; /* Local loopback */
1965                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1966         }
1967         /* When PFC enabled, Pass pause frames towards the NIG. */
1968         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1969                 val |= ((1<<6)|(1<<5));
1970
1971         wb_data[0] = val;
1972         wb_data[1] = 0;
1973         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1974 }
1975
1976
1977 /* PFC BRB internal port configuration params */
1978 struct bnx2x_pfc_brb_threshold_val {
1979         u32 pause_xoff;
1980         u32 pause_xon;
1981         u32 full_xoff;
1982         u32 full_xon;
1983 };
1984
1985 struct bnx2x_pfc_brb_e3b0_val {
1986         u32 full_lb_xoff_th;
1987         u32 full_lb_xon_threshold;
1988         u32 lb_guarantied;
1989         u32 mac_0_class_t_guarantied;
1990         u32 mac_0_class_t_guarantied_hyst;
1991         u32 mac_1_class_t_guarantied;
1992         u32 mac_1_class_t_guarantied_hyst;
1993 };
1994
1995 struct bnx2x_pfc_brb_th_val {
1996         struct bnx2x_pfc_brb_threshold_val pauseable_th;
1997         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
1998 };
1999 static int bnx2x_pfc_brb_get_config_params(
2000                                 struct link_params *params,
2001                                 struct bnx2x_pfc_brb_th_val *config_val)
2002 {
2003         struct bnx2x *bp = params->bp;
2004         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2005         if (CHIP_IS_E2(bp)) {
2006                 config_val->pauseable_th.pause_xoff =
2007                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2008                 config_val->pauseable_th.pause_xon =
2009                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2010                 config_val->pauseable_th.full_xoff =
2011                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2012                 config_val->pauseable_th.full_xon =
2013                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2014                 /* non pause able*/
2015                 config_val->non_pauseable_th.pause_xoff =
2016                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2017                 config_val->non_pauseable_th.pause_xon =
2018                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2019                 config_val->non_pauseable_th.full_xoff =
2020                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2021                 config_val->non_pauseable_th.full_xon =
2022                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2023         } else if (CHIP_IS_E3A0(bp)) {
2024                 config_val->pauseable_th.pause_xoff =
2025                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2026                 config_val->pauseable_th.pause_xon =
2027                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2028                 config_val->pauseable_th.full_xoff =
2029                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2030                 config_val->pauseable_th.full_xon =
2031                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2032                 /* non pause able*/
2033                 config_val->non_pauseable_th.pause_xoff =
2034                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2035                 config_val->non_pauseable_th.pause_xon =
2036                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2037                 config_val->non_pauseable_th.full_xoff =
2038                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2039                 config_val->non_pauseable_th.full_xon =
2040                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2041         } else if (CHIP_IS_E3B0(bp)) {
2042                 if (params->phy[INT_PHY].flags &
2043                     FLAGS_4_PORT_MODE) {
2044                         config_val->pauseable_th.pause_xoff =
2045                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2046                         config_val->pauseable_th.pause_xon =
2047                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2048                         config_val->pauseable_th.full_xoff =
2049                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2050                         config_val->pauseable_th.full_xon =
2051                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2052                         /* non pause able*/
2053                         config_val->non_pauseable_th.pause_xoff =
2054                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2055                         config_val->non_pauseable_th.pause_xon =
2056                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2057                         config_val->non_pauseable_th.full_xoff =
2058                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2059                         config_val->non_pauseable_th.full_xon =
2060                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2061             } else {
2062                 config_val->pauseable_th.pause_xoff =
2063                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2064                 config_val->pauseable_th.pause_xon =
2065                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2066                 config_val->pauseable_th.full_xoff =
2067                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2068                 config_val->pauseable_th.full_xon =
2069                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2070                 /* non pause able*/
2071                 config_val->non_pauseable_th.pause_xoff =
2072                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2073                 config_val->non_pauseable_th.pause_xon =
2074                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2075                 config_val->non_pauseable_th.full_xoff =
2076                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2077                 config_val->non_pauseable_th.full_xon =
2078                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2079             }
2080         } else
2081             return -EINVAL;
2082
2083         return 0;
2084 }
2085
2086
2087 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2088                                                  struct bnx2x_pfc_brb_e3b0_val
2089                                                  *e3b0_val,
2090                                                  u32 cos0_pauseable,
2091                                                  u32 cos1_pauseable)
2092 {
2093         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2094                 e3b0_val->full_lb_xoff_th =
2095                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2096                 e3b0_val->full_lb_xon_threshold =
2097                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2098                 e3b0_val->lb_guarantied =
2099                     PFC_E3B0_4P_LB_GUART;
2100                 e3b0_val->mac_0_class_t_guarantied =
2101                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2102                 e3b0_val->mac_0_class_t_guarantied_hyst =
2103                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2104                 e3b0_val->mac_1_class_t_guarantied =
2105                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2106                 e3b0_val->mac_1_class_t_guarantied_hyst =
2107                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2108         } else {
2109                 e3b0_val->full_lb_xoff_th =
2110                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2111                 e3b0_val->full_lb_xon_threshold =
2112                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2113                 e3b0_val->mac_0_class_t_guarantied_hyst =
2114                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2115                 e3b0_val->mac_1_class_t_guarantied =
2116                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2117                 e3b0_val->mac_1_class_t_guarantied_hyst =
2118                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2119
2120                 if (cos0_pauseable != cos1_pauseable) {
2121                         /* nonpauseable= Lossy + pauseable = Lossless*/
2122                         e3b0_val->lb_guarantied =
2123                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2124                         e3b0_val->mac_0_class_t_guarantied =
2125                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2126                 } else if (cos0_pauseable) {
2127                         /* Lossless +Lossless*/
2128                         e3b0_val->lb_guarantied =
2129                             PFC_E3B0_2P_PAUSE_LB_GUART;
2130                         e3b0_val->mac_0_class_t_guarantied =
2131                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2132                 } else {
2133                         /* Lossy +Lossy*/
2134                         e3b0_val->lb_guarantied =
2135                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2136                         e3b0_val->mac_0_class_t_guarantied =
2137                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2138                 }
2139         }
2140 }
2141 static int bnx2x_update_pfc_brb(struct link_params *params,
2142                                 struct link_vars *vars,
2143                                 struct bnx2x_nig_brb_pfc_port_params
2144                                 *pfc_params)
2145 {
2146         struct bnx2x *bp = params->bp;
2147         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2148         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2149             &config_val.pauseable_th;
2150         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2151         int set_pfc = params->feature_config_flags &
2152                 FEATURE_CONFIG_PFC_ENABLED;
2153         int bnx2x_status = 0;
2154         u8 port = params->port;
2155
2156         /* default - pause configuration */
2157         reg_th_config = &config_val.pauseable_th;
2158         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2159         if (0 != bnx2x_status)
2160                 return bnx2x_status;
2161
2162         if (set_pfc && pfc_params)
2163                 /* First COS */
2164                 if (!pfc_params->cos0_pauseable)
2165                         reg_th_config = &config_val.non_pauseable_th;
2166         /*
2167          * The number of free blocks below which the pause signal to class 0
2168          * of MAC #n is asserted. n=0,1
2169          */
2170         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2171                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2172                reg_th_config->pause_xoff);
2173         /*
2174          * The number of free blocks above which the pause signal to class 0
2175          * of MAC #n is de-asserted. n=0,1
2176          */
2177         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2178                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2179         /*
2180          * The number of free blocks below which the full signal to class 0
2181          * of MAC #n is asserted. n=0,1
2182          */
2183         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2184                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2185         /*
2186          * The number of free blocks above which the full signal to class 0
2187          * of MAC #n is de-asserted. n=0,1
2188          */
2189         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2190                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2191
2192         if (set_pfc && pfc_params) {
2193                 /* Second COS */
2194                 if (pfc_params->cos1_pauseable)
2195                         reg_th_config = &config_val.pauseable_th;
2196                 else
2197                         reg_th_config = &config_val.non_pauseable_th;
2198                 /*
2199                  * The number of free blocks below which the pause signal to
2200                  * class 1 of MAC #n is asserted. n=0,1
2201                 **/
2202                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2203                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2204                        reg_th_config->pause_xoff);
2205                 /*
2206                  * The number of free blocks above which the pause signal to
2207                  * class 1 of MAC #n is de-asserted. n=0,1
2208                  */
2209                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2210                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2211                        reg_th_config->pause_xon);
2212                 /*
2213                  * The number of free blocks below which the full signal to
2214                  * class 1 of MAC #n is asserted. n=0,1
2215                  */
2216                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2217                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2218                        reg_th_config->full_xoff);
2219                 /*
2220                  * The number of free blocks above which the full signal to
2221                  * class 1 of MAC #n is de-asserted. n=0,1
2222                  */
2223                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2224                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
2225                        reg_th_config->full_xon);
2226
2227
2228                 if (CHIP_IS_E3B0(bp)) {
2229                         /*Should be done by init tool */
2230                         /*
2231                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2232                         * reset value
2233                         * 944
2234                         */
2235
2236                         /**
2237                          * The hysteresis on the guarantied buffer space for the Lb port
2238                          * before signaling XON.
2239                          **/
2240                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2241
2242                         bnx2x_pfc_brb_get_e3b0_config_params(
2243                             params,
2244                             &e3b0_val,
2245                             pfc_params->cos0_pauseable,
2246                             pfc_params->cos1_pauseable);
2247                         /**
2248                          * The number of free blocks below which the full signal to the
2249                          * LB port is asserted.
2250                         */
2251                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2252                                    e3b0_val.full_lb_xoff_th);
2253                         /**
2254                          * The number of free blocks above which the full signal to the
2255                          * LB port is de-asserted.
2256                         */
2257                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2258                                    e3b0_val.full_lb_xon_threshold);
2259                         /**
2260                         * The number of blocks guarantied for the MAC #n port. n=0,1
2261                         */
2262
2263                         /*The number of blocks guarantied for the LB port.*/
2264                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2265                                e3b0_val.lb_guarantied);
2266
2267                         /**
2268                          * The number of blocks guarantied for the MAC #n port.
2269                         */
2270                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2271                                    2 * e3b0_val.mac_0_class_t_guarantied);
2272                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2273                                    2 * e3b0_val.mac_1_class_t_guarantied);
2274                         /**
2275                          * The number of blocks guarantied for class #t in MAC0. t=0,1
2276                         */
2277                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2278                                e3b0_val.mac_0_class_t_guarantied);
2279                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2280                                e3b0_val.mac_0_class_t_guarantied);
2281                         /**
2282                          * The hysteresis on the guarantied buffer space for class in
2283                          * MAC0.  t=0,1
2284                         */
2285                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2286                                e3b0_val.mac_0_class_t_guarantied_hyst);
2287                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2288                                e3b0_val.mac_0_class_t_guarantied_hyst);
2289
2290                         /**
2291                          * The number of blocks guarantied for class #t in MAC1.t=0,1
2292                         */
2293                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2294                                e3b0_val.mac_1_class_t_guarantied);
2295                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2296                                e3b0_val.mac_1_class_t_guarantied);
2297                         /**
2298                          * The hysteresis on the guarantied buffer space for class #t
2299                         * in MAC1.  t=0,1
2300                         */
2301                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2302                                e3b0_val.mac_1_class_t_guarantied_hyst);
2303                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2304                                e3b0_val.mac_1_class_t_guarantied_hyst);
2305
2306             }
2307
2308         }
2309
2310         return bnx2x_status;
2311 }
2312
2313 /******************************************************************************
2314 * Description:
2315 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2316 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2317 ******************************************************************************/
2318 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2319                                               u8 cos_entry,
2320                                               u32 priority_mask, u8 port)
2321 {
2322         u32 nig_reg_rx_priority_mask_add = 0;
2323
2324         switch (cos_entry) {
2325         case 0:
2326              nig_reg_rx_priority_mask_add = (port) ?
2327                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2328                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2329              break;
2330         case 1:
2331             nig_reg_rx_priority_mask_add = (port) ?
2332                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2333                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2334             break;
2335         case 2:
2336             nig_reg_rx_priority_mask_add = (port) ?
2337                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2338                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2339             break;
2340         case 3:
2341             if (port)
2342                 return -EINVAL;
2343             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2344             break;
2345         case 4:
2346             if (port)
2347                 return -EINVAL;
2348             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2349             break;
2350         case 5:
2351             if (port)
2352                 return -EINVAL;
2353             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2354             break;
2355         }
2356
2357         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2358
2359         return 0;
2360 }
2361 static void bnx2x_update_pfc_nig(struct link_params *params,
2362                 struct link_vars *vars,
2363                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2364 {
2365         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2366         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2367         u32 pkt_priority_to_cos = 0;
2368         struct bnx2x *bp = params->bp;
2369         u8 port = params->port;
2370
2371         int set_pfc = params->feature_config_flags &
2372                 FEATURE_CONFIG_PFC_ENABLED;
2373         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2374
2375         /*
2376          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2377          * MAC control frames (that are not pause packets)
2378          * will be forwarded to the XCM.
2379          */
2380         xcm_mask = REG_RD(bp,
2381                                 port ? NIG_REG_LLH1_XCM_MASK :
2382                                 NIG_REG_LLH0_XCM_MASK);
2383         /*
2384          * nig params will override non PFC params, since it's possible to
2385          * do transition from PFC to SAFC
2386          */
2387         if (set_pfc) {
2388                 pause_enable = 0;
2389                 llfc_out_en = 0;
2390                 llfc_enable = 0;
2391                 if (CHIP_IS_E3(bp))
2392                         ppp_enable = 0;
2393                 else
2394                 ppp_enable = 1;
2395                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2396                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2397                 xcm0_out_en = 0;
2398                 p0_hwpfc_enable = 1;
2399         } else  {
2400                 if (nig_params) {
2401                         llfc_out_en = nig_params->llfc_out_en;
2402                         llfc_enable = nig_params->llfc_enable;
2403                         pause_enable = nig_params->pause_enable;
2404                 } else  /*defaul non PFC mode - PAUSE */
2405                         pause_enable = 1;
2406
2407                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2408                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2409                 xcm0_out_en = 1;
2410         }
2411
2412         if (CHIP_IS_E3(bp))
2413                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2414                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2415         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2416                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2417         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2418                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2419         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2420                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2421
2422         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2423                NIG_REG_PPP_ENABLE_0, ppp_enable);
2424
2425         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2426                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2427
2428         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2429
2430         /* output enable for RX_XCM # IF */
2431         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2432
2433         /* HW PFC TX enable */
2434         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2435
2436         if (nig_params) {
2437                 u8 i = 0;
2438                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2439
2440                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2441                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2442                 nig_params->rx_cos_priority_mask[i], port);
2443
2444                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2445                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2446                        nig_params->llfc_high_priority_classes);
2447
2448                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2449                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2450                        nig_params->llfc_low_priority_classes);
2451         }
2452         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2453                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2454                pkt_priority_to_cos);
2455 }
2456
2457 int bnx2x_update_pfc(struct link_params *params,
2458                       struct link_vars *vars,
2459                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2460 {
2461         /*
2462          * The PFC and pause are orthogonal to one another, meaning when
2463          * PFC is enabled, the pause are disabled, and when PFC is
2464          * disabled, pause are set according to the pause result.
2465          */
2466         u32 val;
2467         struct bnx2x *bp = params->bp;
2468         int bnx2x_status = 0;
2469         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2470         /* update NIG params */
2471         bnx2x_update_pfc_nig(params, vars, pfc_params);
2472
2473         /* update BRB params */
2474         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2475         if (0 != bnx2x_status)
2476                 return bnx2x_status;
2477
2478         if (!vars->link_up)
2479                 return bnx2x_status;
2480
2481         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2482         if (CHIP_IS_E3(bp))
2483                 bnx2x_update_pfc_xmac(params, vars, 0);
2484         else {
2485                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2486                 if ((val &
2487                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2488                     == 0) {
2489                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2490                         bnx2x_emac_enable(params, vars, 0);
2491                         return bnx2x_status;
2492                 }
2493
2494                 if (CHIP_IS_E2(bp))
2495                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2496                 else
2497                         bnx2x_update_pfc_bmac1(params, vars);
2498
2499                 val = 0;
2500                 if ((params->feature_config_flags &
2501                      FEATURE_CONFIG_PFC_ENABLED) ||
2502                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2503                         val = 1;
2504                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2505         }
2506         return bnx2x_status;
2507 }
2508
2509
2510 static int bnx2x_bmac1_enable(struct link_params *params,
2511                               struct link_vars *vars,
2512                               u8 is_lb)
2513 {
2514         struct bnx2x *bp = params->bp;
2515         u8 port = params->port;
2516         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2517                                NIG_REG_INGRESS_BMAC0_MEM;
2518         u32 wb_data[2];
2519         u32 val;
2520
2521         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2522
2523         /* XGXS control */
2524         wb_data[0] = 0x3c;
2525         wb_data[1] = 0;
2526         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2527                     wb_data, 2);
2528
2529         /* tx MAC SA */
2530         wb_data[0] = ((params->mac_addr[2] << 24) |
2531                        (params->mac_addr[3] << 16) |
2532                        (params->mac_addr[4] << 8) |
2533                         params->mac_addr[5]);
2534         wb_data[1] = ((params->mac_addr[0] << 8) |
2535                         params->mac_addr[1]);
2536         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2537
2538         /* mac control */
2539         val = 0x3;
2540         if (is_lb) {
2541                 val |= 0x4;
2542                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2543         }
2544         wb_data[0] = val;
2545         wb_data[1] = 0;
2546         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2547
2548         /* set rx mtu */
2549         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2550         wb_data[1] = 0;
2551         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2552
2553         bnx2x_update_pfc_bmac1(params, vars);
2554
2555         /* set tx mtu */
2556         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2557         wb_data[1] = 0;
2558         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2559
2560         /* set cnt max size */
2561         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2562         wb_data[1] = 0;
2563         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2564
2565         /* configure safc */
2566         wb_data[0] = 0x1000200;
2567         wb_data[1] = 0;
2568         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2569                     wb_data, 2);
2570
2571         if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2572                 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
2573                             wb_data, 2);
2574                 if (wb_data[0] > 0)
2575                         return -ESRCH;
2576         }
2577         return 0;
2578 }
2579
2580 static int bnx2x_bmac2_enable(struct link_params *params,
2581                               struct link_vars *vars,
2582                               u8 is_lb)
2583 {
2584         struct bnx2x *bp = params->bp;
2585         u8 port = params->port;
2586         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2587                                NIG_REG_INGRESS_BMAC0_MEM;
2588         u32 wb_data[2];
2589
2590         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2591
2592         wb_data[0] = 0;
2593         wb_data[1] = 0;
2594         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2595         udelay(30);
2596
2597         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2598         wb_data[0] = 0x3c;
2599         wb_data[1] = 0;
2600         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2601                     wb_data, 2);
2602
2603         udelay(30);
2604
2605         /* tx MAC SA */
2606         wb_data[0] = ((params->mac_addr[2] << 24) |
2607                        (params->mac_addr[3] << 16) |
2608                        (params->mac_addr[4] << 8) |
2609                         params->mac_addr[5]);
2610         wb_data[1] = ((params->mac_addr[0] << 8) |
2611                         params->mac_addr[1]);
2612         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2613                     wb_data, 2);
2614
2615         udelay(30);
2616
2617         /* Configure SAFC */
2618         wb_data[0] = 0x1000200;
2619         wb_data[1] = 0;
2620         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2621                     wb_data, 2);
2622         udelay(30);
2623
2624         /* set rx mtu */
2625         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2626         wb_data[1] = 0;
2627         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2628         udelay(30);
2629
2630         /* set tx mtu */
2631         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2632         wb_data[1] = 0;
2633         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2634         udelay(30);
2635         /* set cnt max size */
2636         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2637         wb_data[1] = 0;
2638         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2639         udelay(30);
2640         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2641
2642         if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2643                 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
2644                             wb_data, 2);
2645                 if (wb_data[0] > 0) {
2646                         DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
2647                                        wb_data[0]);
2648                         return -ESRCH;
2649                 }
2650         }
2651
2652         return 0;
2653 }
2654
2655 static int bnx2x_bmac_enable(struct link_params *params,
2656                              struct link_vars *vars,
2657                              u8 is_lb)
2658 {
2659         int rc = 0;
2660         u8 port = params->port;
2661         struct bnx2x *bp = params->bp;
2662         u32 val;
2663         /* reset and unreset the BigMac */
2664         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2665                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2666         msleep(1);
2667
2668         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2669                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2670
2671         /* enable access for bmac registers */
2672         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2673
2674         /* Enable BMAC according to BMAC type*/
2675         if (CHIP_IS_E2(bp))
2676                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2677         else
2678                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2679         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2680         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2681         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2682         val = 0;
2683         if ((params->feature_config_flags &
2684               FEATURE_CONFIG_PFC_ENABLED) ||
2685             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2686                 val = 1;
2687         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2688         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2689         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2690         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2691         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2692         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2693
2694         vars->mac_type = MAC_TYPE_BMAC;
2695         return rc;
2696 }
2697
2698
2699 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2700 {
2701         struct bnx2x *bp = params->bp;
2702
2703         REG_WR(bp, params->shmem_base +
2704                offsetof(struct shmem_region,
2705                         port_mb[params->port].link_status), link_status);
2706 }
2707
2708 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2709 {
2710         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2711                         NIG_REG_INGRESS_BMAC0_MEM;
2712         u32 wb_data[2];
2713         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2714
2715         /* Only if the bmac is out of reset */
2716         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2717                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2718             nig_bmac_enable) {
2719
2720                 if (CHIP_IS_E2(bp)) {
2721                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2722                         REG_RD_DMAE(bp, bmac_addr +
2723                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2724                                     wb_data, 2);
2725                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2726                         REG_WR_DMAE(bp, bmac_addr +
2727                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2728                                     wb_data, 2);
2729                 } else {
2730                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2731                         REG_RD_DMAE(bp, bmac_addr +
2732                                         BIGMAC_REGISTER_BMAC_CONTROL,
2733                                         wb_data, 2);
2734                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2735                         REG_WR_DMAE(bp, bmac_addr +
2736                                         BIGMAC_REGISTER_BMAC_CONTROL,
2737                                         wb_data, 2);
2738                 }
2739                 msleep(1);
2740         }
2741 }
2742
2743 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2744                             u32 line_speed)
2745 {
2746         struct bnx2x *bp = params->bp;
2747         u8 port = params->port;
2748         u32 init_crd, crd;
2749         u32 count = 1000;
2750
2751         /* disable port */
2752         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2753
2754         /* wait for init credit */
2755         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2756         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2757         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2758
2759         while ((init_crd != crd) && count) {
2760                 msleep(5);
2761
2762                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2763                 count--;
2764         }
2765         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2766         if (init_crd != crd) {
2767                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2768                           init_crd, crd);
2769                 return -EINVAL;
2770         }
2771
2772         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2773             line_speed == SPEED_10 ||
2774             line_speed == SPEED_100 ||
2775             line_speed == SPEED_1000 ||
2776             line_speed == SPEED_2500) {
2777                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2778                 /* update threshold */
2779                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2780                 /* update init credit */
2781                 init_crd = 778;         /* (800-18-4) */
2782
2783         } else {
2784                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2785                               ETH_OVREHEAD)/16;
2786                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2787                 /* update threshold */
2788                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2789                 /* update init credit */
2790                 switch (line_speed) {
2791                 case SPEED_10000:
2792                         init_crd = thresh + 553 - 22;
2793                         break;
2794                 default:
2795                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2796                                   line_speed);
2797                         return -EINVAL;
2798                 }
2799         }
2800         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2801         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2802                  line_speed, init_crd);
2803
2804         /* probe the credit changes */
2805         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2806         msleep(5);
2807         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2808
2809         /* enable port */
2810         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2811         return 0;
2812 }
2813
2814 /**
2815  * bnx2x_get_emac_base - retrive emac base address
2816  *
2817  * @bp:                 driver handle
2818  * @mdc_mdio_access:    access type
2819  * @port:               port id
2820  *
2821  * This function selects the MDC/MDIO access (through emac0 or
2822  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2823  * phy has a default access mode, which could also be overridden
2824  * by nvram configuration. This parameter, whether this is the
2825  * default phy configuration, or the nvram overrun
2826  * configuration, is passed here as mdc_mdio_access and selects
2827  * the emac_base for the CL45 read/writes operations
2828  */
2829 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2830                                u32 mdc_mdio_access, u8 port)
2831 {
2832         u32 emac_base = 0;
2833         switch (mdc_mdio_access) {
2834         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2835                 break;
2836         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2837                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2838                         emac_base = GRCBASE_EMAC1;
2839                 else
2840                         emac_base = GRCBASE_EMAC0;
2841                 break;
2842         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2843                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2844                         emac_base = GRCBASE_EMAC0;
2845                 else
2846                         emac_base = GRCBASE_EMAC1;
2847                 break;
2848         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2849                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2850                 break;
2851         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2852                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2853                 break;
2854         default:
2855                 break;
2856         }
2857         return emac_base;
2858
2859 }
2860
2861 /******************************************************************/
2862 /*                      CL22 access functions                     */
2863 /******************************************************************/
2864 static int bnx2x_cl22_write(struct bnx2x *bp,
2865                                        struct bnx2x_phy *phy,
2866                                        u16 reg, u16 val)
2867 {
2868         u32 tmp, mode;
2869         u8 i;
2870         int rc = 0;
2871         /* Switch to CL22 */
2872         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2873         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2874                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2875
2876         /* address */
2877         tmp = ((phy->addr << 21) | (reg << 16) | val |
2878                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2879                EMAC_MDIO_COMM_START_BUSY);
2880         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2881
2882         for (i = 0; i < 50; i++) {
2883                 udelay(10);
2884
2885                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2886                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2887                         udelay(5);
2888                         break;
2889                 }
2890         }
2891         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2892                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2893                 rc = -EFAULT;
2894         }
2895         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2896         return rc;
2897 }
2898
2899 static int bnx2x_cl22_read(struct bnx2x *bp,
2900                                       struct bnx2x_phy *phy,
2901                                       u16 reg, u16 *ret_val)
2902 {
2903         u32 val, mode;
2904         u16 i;
2905         int rc = 0;
2906
2907         /* Switch to CL22 */
2908         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2909         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2910                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2911
2912         /* address */
2913         val = ((phy->addr << 21) | (reg << 16) |
2914                EMAC_MDIO_COMM_COMMAND_READ_22 |
2915                EMAC_MDIO_COMM_START_BUSY);
2916         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2917
2918         for (i = 0; i < 50; i++) {
2919                 udelay(10);
2920
2921                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2922                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2923                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2924                         udelay(5);
2925                         break;
2926                 }
2927         }
2928         if (val & EMAC_MDIO_COMM_START_BUSY) {
2929                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2930
2931                 *ret_val = 0;
2932                 rc = -EFAULT;
2933         }
2934         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2935         return rc;
2936 }
2937
2938 /******************************************************************/
2939 /*                      CL45 access functions                     */
2940 /******************************************************************/
2941 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2942                            u8 devad, u16 reg, u16 *ret_val)
2943 {
2944         u32 val;
2945         u16 i;
2946         int rc = 0;
2947
2948         /* address */
2949         val = ((phy->addr << 21) | (devad << 16) | reg |
2950                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2951                EMAC_MDIO_COMM_START_BUSY);
2952         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2953
2954         for (i = 0; i < 50; i++) {
2955                 udelay(10);
2956
2957                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2958                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2959                         udelay(5);
2960                         break;
2961                 }
2962         }
2963         if (val & EMAC_MDIO_COMM_START_BUSY) {
2964                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2965                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2966                 *ret_val = 0;
2967                 rc = -EFAULT;
2968         } else {
2969                 /* data */
2970                 val = ((phy->addr << 21) | (devad << 16) |
2971                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2972                        EMAC_MDIO_COMM_START_BUSY);
2973                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2974
2975                 for (i = 0; i < 50; i++) {
2976                         udelay(10);
2977
2978                         val = REG_RD(bp, phy->mdio_ctrl +
2979                                      EMAC_REG_EMAC_MDIO_COMM);
2980                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2981                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2982                                 break;
2983                         }
2984                 }
2985                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2986                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2987                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2988                         *ret_val = 0;
2989                         rc = -EFAULT;
2990                 }
2991         }
2992         /* Work around for E3 A0 */
2993         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2994                 phy->flags ^= FLAGS_DUMMY_READ;
2995                 if (phy->flags & FLAGS_DUMMY_READ) {
2996                         u16 temp_val;
2997                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2998                 }
2999         }
3000
3001         return rc;
3002 }
3003
3004 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3005                             u8 devad, u16 reg, u16 val)
3006 {
3007         u32 tmp;
3008         u8 i;
3009         int rc = 0;
3010
3011         /* address */
3012
3013         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3014                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3015                EMAC_MDIO_COMM_START_BUSY);
3016         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3017
3018         for (i = 0; i < 50; i++) {
3019                 udelay(10);
3020
3021                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3022                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3023                         udelay(5);
3024                         break;
3025                 }
3026         }
3027         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3028                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3029                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3030                 rc = -EFAULT;
3031
3032         } else {
3033                 /* data */
3034                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3035                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3036                        EMAC_MDIO_COMM_START_BUSY);
3037                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3038
3039                 for (i = 0; i < 50; i++) {
3040                         udelay(10);
3041
3042                         tmp = REG_RD(bp, phy->mdio_ctrl +
3043                                      EMAC_REG_EMAC_MDIO_COMM);
3044                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3045                                 udelay(5);
3046                                 break;
3047                         }
3048                 }
3049                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3050                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3051                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3052                         rc = -EFAULT;
3053                 }
3054         }
3055         /* Work around for E3 A0 */
3056         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3057                 phy->flags ^= FLAGS_DUMMY_READ;
3058                 if (phy->flags & FLAGS_DUMMY_READ) {
3059                         u16 temp_val;
3060                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3061                 }
3062         }
3063
3064         return rc;
3065 }
3066
3067
3068 /******************************************************************/
3069 /*                      BSC access functions from E3              */
3070 /******************************************************************/
3071 static void bnx2x_bsc_module_sel(struct link_params *params)
3072 {
3073         int idx;
3074         u32 board_cfg, sfp_ctrl;
3075         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3076         struct bnx2x *bp = params->bp;
3077         u8 port = params->port;
3078         /* Read I2C output PINs */
3079         board_cfg = REG_RD(bp, params->shmem_base +
3080                            offsetof(struct shmem_region,
3081                                     dev_info.shared_hw_config.board));
3082         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3083         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3084                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3085
3086         /* Read I2C output value */
3087         sfp_ctrl = REG_RD(bp, params->shmem_base +
3088                           offsetof(struct shmem_region,
3089                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3090         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3091         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3092         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3093         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3094                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3095 }
3096
3097 static int bnx2x_bsc_read(struct link_params *params,
3098                           struct bnx2x_phy *phy,
3099                           u8 sl_devid,
3100                           u16 sl_addr,
3101                           u8 lc_addr,
3102                           u8 xfer_cnt,
3103                           u32 *data_array)
3104 {
3105         u32 val, i;
3106         int rc = 0;
3107         struct bnx2x *bp = params->bp;
3108
3109         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3110                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3111                 return -EINVAL;
3112         }
3113
3114         if (xfer_cnt > 16) {
3115                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3116                                         xfer_cnt);
3117                 return -EINVAL;
3118         }
3119         bnx2x_bsc_module_sel(params);
3120
3121         xfer_cnt = 16 - lc_addr;
3122
3123         /* enable the engine */
3124         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3125         val |= MCPR_IMC_COMMAND_ENABLE;
3126         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3127
3128         /* program slave device ID */
3129         val = (sl_devid << 16) | sl_addr;
3130         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3131
3132         /* start xfer with 0 byte to update the address pointer ???*/
3133         val = (MCPR_IMC_COMMAND_ENABLE) |
3134               (MCPR_IMC_COMMAND_WRITE_OP <<
3135                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3136                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3137         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3138
3139         /* poll for completion */
3140         i = 0;
3141         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3142         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3143                 udelay(10);
3144                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3145                 if (i++ > 1000) {
3146                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3147                                                                 i);
3148                         rc = -EFAULT;
3149                         break;
3150                 }
3151         }
3152         if (rc == -EFAULT)
3153                 return rc;
3154
3155         /* start xfer with read op */
3156         val = (MCPR_IMC_COMMAND_ENABLE) |
3157                 (MCPR_IMC_COMMAND_READ_OP <<
3158                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3159                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3160                   (xfer_cnt);
3161         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3162
3163         /* poll for completion */
3164         i = 0;
3165         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3166         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3167                 udelay(10);
3168                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3169                 if (i++ > 1000) {
3170                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3171                         rc = -EFAULT;
3172                         break;
3173                 }
3174         }
3175         if (rc == -EFAULT)
3176                 return rc;
3177
3178         for (i = (lc_addr >> 2); i < 4; i++) {
3179                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3180 #ifdef __BIG_ENDIAN
3181                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3182                                 ((data_array[i] & 0x0000ff00) << 8) |
3183                                 ((data_array[i] & 0x00ff0000) >> 8) |
3184                                 ((data_array[i] & 0xff000000) >> 24);
3185 #endif
3186         }
3187         return rc;
3188 }
3189
3190 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3191                                      u8 devad, u16 reg, u16 or_val)
3192 {
3193         u16 val;
3194         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3195         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3196 }
3197
3198 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3199                    u8 devad, u16 reg, u16 *ret_val)
3200 {
3201         u8 phy_index;
3202         /*
3203          * Probe for the phy according to the given phy_addr, and execute
3204          * the read request on it
3205          */
3206         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3207                 if (params->phy[phy_index].addr == phy_addr) {
3208                         return bnx2x_cl45_read(params->bp,
3209                                                &params->phy[phy_index], devad,
3210                                                reg, ret_val);
3211                 }
3212         }
3213         return -EINVAL;
3214 }
3215
3216 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3217                     u8 devad, u16 reg, u16 val)
3218 {
3219         u8 phy_index;
3220         /*
3221          * Probe for the phy according to the given phy_addr, and execute
3222          * the write request on it
3223          */
3224         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3225                 if (params->phy[phy_index].addr == phy_addr) {
3226                         return bnx2x_cl45_write(params->bp,
3227                                                 &params->phy[phy_index], devad,
3228                                                 reg, val);
3229                 }
3230         }
3231         return -EINVAL;
3232 }
3233 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3234                                   struct link_params *params)
3235 {
3236         u8 lane = 0;
3237         struct bnx2x *bp = params->bp;
3238         u32 path_swap, path_swap_ovr;
3239         u8 path, port;
3240
3241         path = BP_PATH(bp);
3242         port = params->port;
3243
3244         if (bnx2x_is_4_port_mode(bp)) {
3245                 u32 port_swap, port_swap_ovr;
3246
3247                 /*figure out path swap value */
3248                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3249                 if (path_swap_ovr & 0x1)
3250                         path_swap = (path_swap_ovr & 0x2);
3251                 else
3252                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3253
3254                 if (path_swap)
3255                         path = path ^ 1;
3256
3257                 /*figure out port swap value */
3258                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3259                 if (port_swap_ovr & 0x1)
3260                         port_swap = (port_swap_ovr & 0x2);
3261                 else
3262                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3263
3264                 if (port_swap)
3265                         port = port ^ 1;
3266
3267                 lane = (port<<1) + path;
3268         } else { /* two port mode - no port swap */
3269
3270                 /*figure out path swap value */
3271                 path_swap_ovr =
3272                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3273                 if (path_swap_ovr & 0x1) {
3274                         path_swap = (path_swap_ovr & 0x2);
3275                 } else {
3276                         path_swap =
3277                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3278                 }
3279                 if (path_swap)
3280                         path = path ^ 1;
3281
3282                 lane = path << 1 ;
3283         }
3284         return lane;
3285 }
3286
3287 static void bnx2x_set_aer_mmd(struct link_params *params,
3288                               struct bnx2x_phy *phy)
3289 {
3290         u32 ser_lane;
3291         u16 offset, aer_val;
3292         struct bnx2x *bp = params->bp;
3293         ser_lane = ((params->lane_config &
3294                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3295                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3296
3297         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3298                 (phy->addr + ser_lane) : 0;
3299
3300         if (USES_WARPCORE(bp)) {
3301                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3302                 /*
3303                  * In Dual-lane mode, two lanes are joined together,
3304                  * so in order to configure them, the AER broadcast method is
3305                  * used here.
3306                  * 0x200 is the broadcast address for lanes 0,1
3307                  * 0x201 is the broadcast address for lanes 2,3
3308                  */
3309                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3310                         aer_val = (aer_val >> 1) | 0x200;
3311         } else if (CHIP_IS_E2(bp))
3312                 aer_val = 0x3800 + offset - 1;
3313         else
3314                 aer_val = 0x3800 + offset;
3315         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3316         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3317                           MDIO_AER_BLOCK_AER_REG, aer_val);
3318
3319 }
3320
3321 /******************************************************************/
3322 /*                      Internal phy section                      */
3323 /******************************************************************/
3324
3325 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3326 {
3327         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3328
3329         /* Set Clause 22 */
3330         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3331         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3332         udelay(500);
3333         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3334         udelay(500);
3335          /* Set Clause 45 */
3336         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3337 }
3338
3339 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3340 {
3341         u32 val;
3342
3343         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3344
3345         val = SERDES_RESET_BITS << (port*16);
3346
3347         /* reset and unreset the SerDes/XGXS */
3348         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3349         udelay(500);
3350         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3351
3352         bnx2x_set_serdes_access(bp, port);
3353
3354         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3355                DEFAULT_PHY_DEV_ADDR);
3356 }
3357
3358 static void bnx2x_xgxs_deassert(struct link_params *params)
3359 {
3360         struct bnx2x *bp = params->bp;
3361         u8 port;
3362         u32 val;
3363         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3364         port = params->port;
3365
3366         val = XGXS_RESET_BITS << (port*16);
3367
3368         /* reset and unreset the SerDes/XGXS */
3369         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3370         udelay(500);
3371         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3372
3373         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3374         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3375                params->phy[INT_PHY].def_md_devad);
3376 }
3377
3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3379                                      struct link_params *params, u16 *ieee_fc)
3380 {
3381         struct bnx2x *bp = params->bp;
3382         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3383         /**
3384          * resolve pause mode and advertisement Please refer to Table
3385          * 28B-3 of the 802.3ab-1999 spec
3386          */
3387
3388         switch (phy->req_flow_ctrl) {
3389         case BNX2X_FLOW_CTRL_AUTO:
3390                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3391                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3392                 else
3393                         *ieee_fc |=
3394                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3395                 break;
3396
3397         case BNX2X_FLOW_CTRL_TX:
3398                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3399                 break;
3400
3401         case BNX2X_FLOW_CTRL_RX:
3402         case BNX2X_FLOW_CTRL_BOTH:
3403                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3404                 break;
3405
3406         case BNX2X_FLOW_CTRL_NONE:
3407         default:
3408                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3409                 break;
3410         }
3411         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3412 }
3413
3414 static void set_phy_vars(struct link_params *params,
3415                          struct link_vars *vars)
3416 {
3417         struct bnx2x *bp = params->bp;
3418         u8 actual_phy_idx, phy_index, link_cfg_idx;
3419         u8 phy_config_swapped = params->multi_phy_config &
3420                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3421         for (phy_index = INT_PHY; phy_index < params->num_phys;
3422               phy_index++) {
3423                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3424                 actual_phy_idx = phy_index;
3425                 if (phy_config_swapped) {
3426                         if (phy_index == EXT_PHY1)
3427                                 actual_phy_idx = EXT_PHY2;
3428                         else if (phy_index == EXT_PHY2)
3429                                 actual_phy_idx = EXT_PHY1;
3430                 }
3431                 params->phy[actual_phy_idx].req_flow_ctrl =
3432                         params->req_flow_ctrl[link_cfg_idx];
3433
3434                 params->phy[actual_phy_idx].req_line_speed =
3435                         params->req_line_speed[link_cfg_idx];
3436
3437                 params->phy[actual_phy_idx].speed_cap_mask =
3438                         params->speed_cap_mask[link_cfg_idx];
3439
3440                 params->phy[actual_phy_idx].req_duplex =
3441                         params->req_duplex[link_cfg_idx];
3442
3443                 if (params->req_line_speed[link_cfg_idx] ==
3444                     SPEED_AUTO_NEG)
3445                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3446
3447                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3448                            " speed_cap_mask %x\n",
3449                            params->phy[actual_phy_idx].req_flow_ctrl,
3450                            params->phy[actual_phy_idx].req_line_speed,
3451                            params->phy[actual_phy_idx].speed_cap_mask);
3452         }
3453 }
3454
3455 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3456                                     struct bnx2x_phy *phy,
3457                                     struct link_vars *vars)
3458 {
3459         u16 val;
3460         struct bnx2x *bp = params->bp;
3461         /* read modify write pause advertizing */
3462         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3463
3464         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3465
3466         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3467         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3468         if ((vars->ieee_fc &
3469             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3470             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3471                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3472         }
3473         if ((vars->ieee_fc &
3474             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3475             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3476                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3477         }
3478         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3479         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3480 }
3481
3482 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3483 {                                               /*  LD      LP   */
3484         switch (pause_result) {                 /* ASYM P ASYM P */
3485         case 0xb:                               /*   1  0   1  1 */
3486                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3487                 break;
3488
3489         case 0xe:                               /*   1  1   1  0 */
3490                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3491                 break;
3492
3493         case 0x5:                               /*   0  1   0  1 */
3494         case 0x7:                               /*   0  1   1  1 */
3495         case 0xd:                               /*   1  1   0  1 */
3496         case 0xf:                               /*   1  1   1  1 */
3497                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3498                 break;
3499
3500         default:
3501                 break;
3502         }
3503         if (pause_result & (1<<0))
3504                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3505         if (pause_result & (1<<1))
3506                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3507 }
3508
3509 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3510                                    struct link_params *params,
3511                                    struct link_vars *vars)
3512 {
3513         struct bnx2x *bp = params->bp;
3514         u16 ld_pause;           /* local */
3515         u16 lp_pause;           /* link partner */
3516         u16 pause_result;
3517         u8 ret = 0;
3518         /* read twice */
3519
3520         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3521
3522         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3523                 vars->flow_ctrl = phy->req_flow_ctrl;
3524         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3525                 vars->flow_ctrl = params->req_fc_auto_adv;
3526         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3527                 ret = 1;
3528                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616) {
3529                         bnx2x_cl22_read(bp, phy,
3530                                         0x4, &ld_pause);
3531                         bnx2x_cl22_read(bp, phy,
3532                                         0x5, &lp_pause);
3533                 } else {
3534                         bnx2x_cl45_read(bp, phy,
3535                                         MDIO_AN_DEVAD,
3536                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3537                         bnx2x_cl45_read(bp, phy,
3538                                         MDIO_AN_DEVAD,
3539                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3540                 }
3541                 pause_result = (ld_pause &
3542                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3543                 pause_result |= (lp_pause &
3544                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3545                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3546                    pause_result);
3547                 bnx2x_pause_resolve(vars, pause_result);
3548         }
3549         return ret;
3550 }
3551 /******************************************************************/
3552 /*                      Warpcore section                          */
3553 /******************************************************************/
3554 /* The init_internal_warpcore should mirror the xgxs,
3555  * i.e. reset the lane (if needed), set aer for the
3556  * init configuration, and set/clear SGMII flag. Internal
3557  * phy init is done purely in phy_init stage.
3558  */
3559 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3560                                         struct link_params *params,
3561                                         struct link_vars *vars) {
3562         u16 val16 = 0, lane;
3563         struct bnx2x *bp = params->bp;
3564         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3565         /* Check adding advertisement for 1G KX */
3566         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3567              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3568             (vars->line_speed == SPEED_1000)) {
3569                 u16 sd_digital;
3570                 val16 |= (1<<5);
3571
3572                 /* Enable CL37 1G Parallel Detect */
3573                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3574                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3575                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3576                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3577                                  (sd_digital | 0x1));
3578
3579                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3580         }
3581         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3582              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3583             (vars->line_speed ==  SPEED_10000)) {
3584                 /* Check adding advertisement for 10G KR */
3585                 val16 |= (1<<7);
3586                 /* Enable 10G Parallel Detect */
3587                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3588                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3589
3590                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3591         }
3592
3593         /* Set Transmit PMD settings */
3594         lane = bnx2x_get_warpcore_lane(phy, params);
3595         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3596                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3597                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3598                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3599                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3600         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3601                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3602                          0x03f0);
3603         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3604                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3605                          0x03f0);
3606         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3607                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3608                          0x383f);
3609
3610         /* Advertised speeds */
3611         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3612                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3613
3614         /* Advertise pause */
3615         bnx2x_ext_phy_set_pause(params, phy, vars);
3616
3617         /* Enable Autoneg */
3618         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3619                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3620
3621         /* Over 1G - AN local device user page 1 */
3622         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3623                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3624
3625         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3626                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3627
3628         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3629                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3630 }
3631
3632 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3633                                       struct link_params *params,
3634                                       struct link_vars *vars)
3635 {
3636         struct bnx2x *bp = params->bp;
3637         u16 val;
3638
3639         /* Disable Autoneg */
3640         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3641                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3642
3643         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3644                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3645
3646         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3647                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3648
3649         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3651
3652         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3653                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3654
3655         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3656                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3657
3658         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3659                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3660
3661         /* Disable CL36 PCS Tx */
3662         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3663                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3664
3665         /* Double Wide Single Data Rate @ pll rate */
3666         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3667                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3668
3669         /* Leave cl72 training enable, needed for KR */
3670         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3671                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3672                 0x2);
3673
3674         /* Leave CL72 enabled */
3675         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3676                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3677                          &val);
3678         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3679                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3680                          val | 0x3800);
3681
3682         /* Set speed via PMA/PMD register */
3683         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3684                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3685
3686         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3687                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3688
3689         /*Enable encoded forced speed */
3690         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3691                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3692
3693         /* Turn TX scramble payload only the 64/66 scrambler */
3694         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3695                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3696
3697         /* Turn RX scramble payload only the 64/66 scrambler */
3698         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3699                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3700
3701         /* set and clear loopback to cause a reset to 64/66 decoder */
3702         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3703                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3704         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3705                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3706
3707 }
3708
3709 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3710                                        struct link_params *params,
3711                                        u8 is_xfi)
3712 {
3713         struct bnx2x *bp = params->bp;
3714         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3715         /* Hold rxSeqStart */
3716         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3717                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3718         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3719                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3720
3721         /* Hold tx_fifo_reset */
3722         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3723                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3724         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3725                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3726
3727         /* Disable CL73 AN */
3728         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3729
3730         /* Disable 100FX Enable and Auto-Detect */
3731         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3732                         MDIO_WC_REG_FX100_CTRL1, &val);
3733         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3734                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3735
3736         /* Disable 100FX Idle detect */
3737         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3738                         MDIO_WC_REG_FX100_CTRL3, &val);
3739         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3740                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3741
3742         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3743         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3744                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3745         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3746                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3747
3748         /* Turn off auto-detect & fiber mode */
3749         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3750                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3751         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3752                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3753                          (val & 0xFFEE));
3754
3755         /* Set filter_force_link, disable_false_link and parallel_detect */
3756         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3757                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3758         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3759                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3760                          ((val | 0x0006) & 0xFFFE));
3761
3762         /* Set XFI / SFI */
3763         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3764                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3765
3766         misc1_val &= ~(0x1f);
3767
3768         if (is_xfi) {
3769                 misc1_val |= 0x5;
3770                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3771                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3772                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3773                 tx_driver_val =
3774                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3775                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3776                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3777
3778         } else {
3779                 misc1_val |= 0x9;
3780                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3781                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3782                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3783                 tx_driver_val =
3784                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3785                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3786                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3787         }
3788         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3789                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3790
3791         /* Set Transmit PMD settings */
3792         lane = bnx2x_get_warpcore_lane(phy, params);
3793         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3794                          MDIO_WC_REG_TX_FIR_TAP,
3795                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3796         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3797                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3798                          tx_driver_val);
3799
3800         /* Enable fiber mode, enable and invert sig_det */
3801         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3802                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3803         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3804                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3805
3806         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3807         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3808                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3809         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3810                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3811
3812         /* 10G XFI Full Duplex */
3813         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3815
3816         /* Release tx_fifo_reset */
3817         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3818                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3819         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3820                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3821
3822         /* Release rxSeqStart */
3823         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3824                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3825         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3826                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3827 }
3828
3829 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3830                                        struct bnx2x_phy *phy)
3831 {
3832         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3833 }
3834
3835 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3836                                          struct bnx2x_phy *phy,
3837                                          u16 lane)
3838 {
3839         /* Rx0 anaRxControl1G */
3840         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3841                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3842
3843         /* Rx2 anaRxControl1G */
3844         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3845                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3846
3847         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3848                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3849
3850         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3851                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3852
3853         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3854                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3855
3856         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3858
3859         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3860                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3861
3862         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3863                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3864
3865         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3866                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3867
3868         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3869                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3870
3871         /* Serdes Digital Misc1 */
3872         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3873                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3874
3875         /* Serdes Digital4 Misc3 */
3876         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3878
3879         /* Set Transmit PMD settings */
3880         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3881                          MDIO_WC_REG_TX_FIR_TAP,
3882                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3883                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3884                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3885                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3886         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3887                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3888                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3889                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3890                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3891 }
3892
3893 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3894                                            struct link_params *params,
3895                                            u8 fiber_mode)
3896 {
3897         struct bnx2x *bp = params->bp;
3898         u16 val16, digctrl_kx1, digctrl_kx2;
3899         u8 lane;
3900
3901         lane = bnx2x_get_warpcore_lane(phy, params);
3902
3903         /* Clear XFI clock comp in non-10G single lane mode. */
3904         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3905                         MDIO_WC_REG_RX66_CONTROL, &val16);
3906         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3907                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3908
3909         if (phy->req_line_speed == SPEED_AUTO_NEG) {
3910                 /* SGMII Autoneg */
3911                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3912                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3913                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3914                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3915                                  val16 | 0x1000);
3916                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3917         } else {
3918                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3919                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3920                 val16 &= 0xcfbf;
3921                 switch (phy->req_line_speed) {
3922                 case SPEED_10:
3923                         break;
3924                 case SPEED_100:
3925                         val16 |= 0x2000;
3926                         break;
3927                 case SPEED_1000:
3928                         val16 |= 0x0040;
3929                         break;
3930                 default:
3931                         DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3932                                            "\n", phy->req_line_speed);
3933                         return;
3934                 }
3935
3936                 if (phy->req_duplex == DUPLEX_FULL)
3937                         val16 |= 0x0100;
3938
3939                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3940                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3941
3942                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3943                                phy->req_line_speed);
3944                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3945                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3946                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
3947         }
3948
3949         /* SGMII Slave mode and disable signal detect */
3950         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3951                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3952         if (fiber_mode)
3953                 digctrl_kx1 = 1;
3954         else
3955                 digctrl_kx1 &= 0xff4a;
3956
3957         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3958                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3959                         digctrl_kx1);
3960
3961         /* Turn off parallel detect */
3962         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3963                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3964         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3965                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3966                         (digctrl_kx2 & ~(1<<2)));
3967
3968         /* Re-enable parallel detect */
3969         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3970                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3971                         (digctrl_kx2 | (1<<2)));
3972
3973         /* Enable autodet */
3974         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3975                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3976                         (digctrl_kx1 | 0x10));
3977 }
3978
3979 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
3980                                       struct bnx2x_phy *phy,
3981                                       u8 reset)
3982 {
3983         u16 val;
3984         /* Take lane out of reset after configuration is finished */
3985         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3986                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
3987         if (reset)
3988                 val |= 0xC000;
3989         else
3990                 val &= 0x3FFF;
3991         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3992                          MDIO_WC_REG_DIGITAL5_MISC6, val);
3993         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
3995 }
3996
3997
3998         /* Clear SFI/XFI link settings registers */
3999 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4000                                       struct link_params *params,
4001                                       u16 lane)
4002 {
4003         struct bnx2x *bp = params->bp;
4004         u16 val16;
4005
4006         /* Set XFI clock comp as default. */
4007         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4008                         MDIO_WC_REG_RX66_CONTROL, &val16);
4009         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4010                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4011
4012         bnx2x_warpcore_reset_lane(bp, phy, 1);
4013         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4014         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4015                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4016         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4017                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4018         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4019                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4020         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4021                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4022         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4023                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4024         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4025                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4026         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4027                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4028         lane = bnx2x_get_warpcore_lane(phy, params);
4029         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4030                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4031         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4032                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4033         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4034                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4035         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4037         bnx2x_warpcore_reset_lane(bp, phy, 0);
4038 }
4039
4040 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4041                                                 u32 chip_id,
4042                                                 u32 shmem_base, u8 port,
4043                                                 u8 *gpio_num, u8 *gpio_port)
4044 {
4045         u32 cfg_pin;
4046         *gpio_num = 0;
4047         *gpio_port = 0;
4048         if (CHIP_IS_E3(bp)) {
4049                 cfg_pin = (REG_RD(bp, shmem_base +
4050                                 offsetof(struct shmem_region,
4051                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4052                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4053                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4054
4055                 /*
4056                  * Should not happen. This function called upon interrupt
4057                  * triggered by GPIO ( since EPIO can only generate interrupts
4058                  * to MCP).
4059                  * So if this function was called and none of the GPIOs was set,
4060                  * it means the shit hit the fan.
4061                  */
4062                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4063                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4064                         DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4065                                            "module detect indication\n",
4066                                        cfg_pin);
4067                         return -EINVAL;
4068                 }
4069
4070                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4071                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4072         } else {
4073                 *gpio_num = MISC_REGISTERS_GPIO_3;
4074                 *gpio_port = port;
4075         }
4076         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4077         return 0;
4078 }
4079
4080 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4081                                        struct link_params *params)
4082 {
4083         struct bnx2x *bp = params->bp;
4084         u8 gpio_num, gpio_port;
4085         u32 gpio_val;
4086         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4087                                       params->shmem_base, params->port,
4088                                       &gpio_num, &gpio_port) != 0)
4089                 return 0;
4090         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4091
4092         /* Call the handling function in case module is detected */
4093         if (gpio_val == 0)
4094                 return 1;
4095         else
4096                 return 0;
4097 }
4098
4099 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4100                                        struct link_params *params,
4101                                        struct link_vars *vars)
4102 {
4103         struct bnx2x *bp = params->bp;
4104         u32 serdes_net_if;
4105         u8 fiber_mode;
4106         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4107         serdes_net_if = (REG_RD(bp, params->shmem_base +
4108                          offsetof(struct shmem_region, dev_info.
4109                                   port_hw_config[params->port].default_cfg)) &
4110                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4111         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4112                            "serdes_net_if = 0x%x\n",
4113                        vars->line_speed, serdes_net_if);
4114         bnx2x_set_aer_mmd(params, phy);
4115
4116         vars->phy_flags |= PHY_XGXS_FLAG;
4117         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4118             (phy->req_line_speed &&
4119              ((phy->req_line_speed == SPEED_100) ||
4120               (phy->req_line_speed == SPEED_10)))) {
4121                 vars->phy_flags |= PHY_SGMII_FLAG;
4122                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4123                 bnx2x_warpcore_clear_regs(phy, params, lane);
4124                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4125         } else {
4126                 switch (serdes_net_if) {
4127                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4128                         /* Enable KR Auto Neg */
4129                         if (params->loopback_mode == LOOPBACK_NONE)
4130                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4131                         else {
4132                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4133                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4134                         }
4135                         break;
4136
4137                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4138                         bnx2x_warpcore_clear_regs(phy, params, lane);
4139                         if (vars->line_speed == SPEED_10000) {
4140                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4141                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4142                         } else {
4143                                 if (SINGLE_MEDIA_DIRECT(params)) {
4144                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4145                                         fiber_mode = 1;
4146                                 } else {
4147                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4148                                         fiber_mode = 0;
4149                                 }
4150                                 bnx2x_warpcore_set_sgmii_speed(phy,
4151                                                                 params,
4152                                                                 fiber_mode);
4153                         }
4154
4155                         break;
4156
4157                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4158
4159                         bnx2x_warpcore_clear_regs(phy, params, lane);
4160                         if (vars->line_speed == SPEED_10000) {
4161                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4162                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4163                         } else if (vars->line_speed == SPEED_1000) {
4164                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4165                                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4166                         }
4167                         /* Issue Module detection */
4168                         if (bnx2x_is_sfp_module_plugged(phy, params))
4169                                 bnx2x_sfp_module_detection(phy, params);
4170                         break;
4171
4172                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4173                         if (vars->line_speed != SPEED_20000) {
4174                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4175                                 return;
4176                         }
4177                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4178                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4179                         /* Issue Module detection */
4180
4181                         bnx2x_sfp_module_detection(phy, params);
4182                         break;
4183
4184                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4185                         if (vars->line_speed != SPEED_20000) {
4186                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4187                                 return;
4188                         }
4189                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4190                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4191                         break;
4192
4193                 default:
4194                         DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4195                                            "0x%x\n", serdes_net_if);
4196                         return;
4197                 }
4198         }
4199
4200         /* Take lane out of reset after configuration is finished */
4201         bnx2x_warpcore_reset_lane(bp, phy, 0);
4202         DP(NETIF_MSG_LINK, "Exit config init\n");
4203 }
4204
4205 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4206                                          struct bnx2x_phy *phy,
4207                                          u8 tx_en)
4208 {
4209         struct bnx2x *bp = params->bp;
4210         u32 cfg_pin;
4211         u8 port = params->port;
4212
4213         cfg_pin = REG_RD(bp, params->shmem_base +
4214                                 offsetof(struct shmem_region,
4215                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4216                                 PORT_HW_CFG_TX_LASER_MASK;
4217         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4218         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4219         /* For 20G, the expected pin to be used is 3 pins after the current */
4220
4221         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4222         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4223                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4224 }
4225
4226 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4227                                       struct link_params *params)
4228 {
4229         struct bnx2x *bp = params->bp;
4230         u16 val16;
4231         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4232         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4233         bnx2x_set_aer_mmd(params, phy);
4234         /* Global register */
4235         bnx2x_warpcore_reset_lane(bp, phy, 1);
4236
4237         /* Clear loopback settings (if any) */
4238         /* 10G & 20G */
4239         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4240                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4241         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4242                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4243                          0xBFFF);
4244
4245         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4246                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4247         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4248                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4249
4250         /* Update those 1-copy registers */
4251         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4252                           MDIO_AER_BLOCK_AER_REG, 0);
4253                 /* Enable 1G MDIO (1-copy) */
4254         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4255                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4256                         &val16);
4257         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4258                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4259                          val16 & ~0x10);
4260
4261         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4262                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4263         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4264                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4265                          val16 & 0xff00);
4266
4267 }
4268
4269 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4270                                         struct link_params *params)
4271 {
4272         struct bnx2x *bp = params->bp;
4273         u16 val16;
4274         u32 lane;
4275         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4276                        params->loopback_mode, phy->req_line_speed);
4277
4278         if (phy->req_line_speed < SPEED_10000) {
4279                 /* 10/100/1000 */
4280
4281                 /* Update those 1-copy registers */
4282                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4283                                   MDIO_AER_BLOCK_AER_REG, 0);
4284                 /* Enable 1G MDIO (1-copy) */
4285                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4286                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4287                                 &val16);
4288                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4289                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4290                                 val16 | 0x10);
4291                 /* Set 1G loopback based on lane (1-copy) */
4292                 lane = bnx2x_get_warpcore_lane(phy, params);
4293                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4294                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4295                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4296                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4297                                 val16 | (1<<lane));
4298
4299                 /* Switch back to 4-copy registers */
4300                 bnx2x_set_aer_mmd(params, phy);
4301                 /* Global loopback, not recommended. */
4302                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4303                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4304                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4305                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4306                                 0x4000);
4307         } else {
4308                 /* 10G & 20G */
4309                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4310                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4311                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4312                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4313                                  0x4000);
4314
4315                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4316                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4317                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4318                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4319         }
4320 }
4321
4322
4323 void bnx2x_link_status_update(struct link_params *params,
4324                               struct link_vars *vars)
4325 {
4326         struct bnx2x *bp = params->bp;
4327         u8 link_10g_plus;
4328         u8 port = params->port;
4329         u32 sync_offset, media_types;
4330         /* Update PHY configuration */
4331         set_phy_vars(params, vars);
4332
4333         vars->link_status = REG_RD(bp, params->shmem_base +
4334                                    offsetof(struct shmem_region,
4335                                             port_mb[port].link_status));
4336
4337         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4338         vars->phy_flags = PHY_XGXS_FLAG;
4339         if (vars->link_up) {
4340                 DP(NETIF_MSG_LINK, "phy link up\n");
4341
4342                 vars->phy_link_up = 1;
4343                 vars->duplex = DUPLEX_FULL;
4344                 switch (vars->link_status &
4345                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4346                         case LINK_10THD:
4347                                 vars->duplex = DUPLEX_HALF;
4348                                 /* fall thru */
4349                         case LINK_10TFD:
4350                                 vars->line_speed = SPEED_10;
4351                                 break;
4352
4353                         case LINK_100TXHD:
4354                                 vars->duplex = DUPLEX_HALF;
4355                                 /* fall thru */
4356                         case LINK_100T4:
4357                         case LINK_100TXFD:
4358                                 vars->line_speed = SPEED_100;
4359                                 break;
4360
4361                         case LINK_1000THD:
4362                                 vars->duplex = DUPLEX_HALF;
4363                                 /* fall thru */
4364                         case LINK_1000TFD:
4365                                 vars->line_speed = SPEED_1000;
4366                                 break;
4367
4368                         case LINK_2500THD:
4369                                 vars->duplex = DUPLEX_HALF;
4370                                 /* fall thru */
4371                         case LINK_2500TFD:
4372                                 vars->line_speed = SPEED_2500;
4373                                 break;
4374
4375                         case LINK_10GTFD:
4376                                 vars->line_speed = SPEED_10000;
4377                                 break;
4378                         case LINK_20GTFD:
4379                                 vars->line_speed = SPEED_20000;
4380                                 break;
4381                         default:
4382                                 break;
4383                 }
4384                 vars->flow_ctrl = 0;
4385                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4386                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4387
4388                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4389                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4390
4391                 if (!vars->flow_ctrl)
4392                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4393
4394                 if (vars->line_speed &&
4395                     ((vars->line_speed == SPEED_10) ||
4396                      (vars->line_speed == SPEED_100))) {
4397                         vars->phy_flags |= PHY_SGMII_FLAG;
4398                 } else {
4399                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4400                 }
4401                 if (vars->line_speed &&
4402                     USES_WARPCORE(bp) &&
4403                     (vars->line_speed == SPEED_1000))
4404                         vars->phy_flags |= PHY_SGMII_FLAG;
4405                 /* anything 10 and over uses the bmac */
4406                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4407
4408                 if (link_10g_plus) {
4409                         if (USES_WARPCORE(bp))
4410                                 vars->mac_type = MAC_TYPE_XMAC;
4411                         else
4412                                 vars->mac_type = MAC_TYPE_BMAC;
4413                 } else {
4414                         if (USES_WARPCORE(bp))
4415                                 vars->mac_type = MAC_TYPE_UMAC;
4416                         else
4417                                 vars->mac_type = MAC_TYPE_EMAC;
4418                 }
4419         } else { /* link down */
4420                 DP(NETIF_MSG_LINK, "phy link down\n");
4421
4422                 vars->phy_link_up = 0;
4423
4424                 vars->line_speed = 0;
4425                 vars->duplex = DUPLEX_FULL;
4426                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4427
4428                 /* indicate no mac active */
4429                 vars->mac_type = MAC_TYPE_NONE;
4430         }
4431
4432         /* Sync media type */
4433         sync_offset = params->shmem_base +
4434                         offsetof(struct shmem_region,
4435                                  dev_info.port_hw_config[port].media_type);
4436         media_types = REG_RD(bp, sync_offset);
4437
4438         params->phy[INT_PHY].media_type =
4439                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4440                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4441         params->phy[EXT_PHY1].media_type =
4442                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4443                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4444         params->phy[EXT_PHY2].media_type =
4445                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4446                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4447         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4448
4449         /* Sync AEU offset */
4450         sync_offset = params->shmem_base +
4451                         offsetof(struct shmem_region,
4452                                  dev_info.port_hw_config[port].aeu_int_mask);
4453
4454         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4455
4456         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4457                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4458         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4459                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4460 }
4461
4462
4463 static void bnx2x_set_master_ln(struct link_params *params,
4464                                 struct bnx2x_phy *phy)
4465 {
4466         struct bnx2x *bp = params->bp;
4467         u16 new_master_ln, ser_lane;
4468         ser_lane = ((params->lane_config &
4469                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4470                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4471
4472         /* set the master_ln for AN */
4473         CL22_RD_OVER_CL45(bp, phy,
4474                           MDIO_REG_BANK_XGXS_BLOCK2,
4475                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4476                           &new_master_ln);
4477
4478         CL22_WR_OVER_CL45(bp, phy,
4479                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4480                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4481                           (new_master_ln | ser_lane));
4482 }
4483
4484 static int bnx2x_reset_unicore(struct link_params *params,
4485                                struct bnx2x_phy *phy,
4486                                u8 set_serdes)
4487 {
4488         struct bnx2x *bp = params->bp;
4489         u16 mii_control;
4490         u16 i;
4491         CL22_RD_OVER_CL45(bp, phy,
4492                           MDIO_REG_BANK_COMBO_IEEE0,
4493                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4494
4495         /* reset the unicore */
4496         CL22_WR_OVER_CL45(bp, phy,
4497                           MDIO_REG_BANK_COMBO_IEEE0,
4498                           MDIO_COMBO_IEEE0_MII_CONTROL,
4499                           (mii_control |
4500                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4501         if (set_serdes)
4502                 bnx2x_set_serdes_access(bp, params->port);
4503
4504         /* wait for the reset to self clear */
4505         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4506                 udelay(5);
4507
4508                 /* the reset erased the previous bank value */
4509                 CL22_RD_OVER_CL45(bp, phy,
4510                                   MDIO_REG_BANK_COMBO_IEEE0,
4511                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4512                                   &mii_control);
4513
4514                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4515                         udelay(5);
4516                         return 0;
4517                 }
4518         }
4519
4520         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4521                               " Port %d\n",
4522                          params->port);
4523         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4524         return -EINVAL;
4525
4526 }
4527
4528 static void bnx2x_set_swap_lanes(struct link_params *params,
4529                                  struct bnx2x_phy *phy)
4530 {
4531         struct bnx2x *bp = params->bp;
4532         /*
4533          *  Each two bits represents a lane number:
4534          *  No swap is 0123 => 0x1b no need to enable the swap
4535          */
4536         u16 ser_lane, rx_lane_swap, tx_lane_swap;
4537
4538         ser_lane = ((params->lane_config &
4539                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4540                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4541         rx_lane_swap = ((params->lane_config &
4542                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4543                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4544         tx_lane_swap = ((params->lane_config &
4545                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4546                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4547
4548         if (rx_lane_swap != 0x1b) {
4549                 CL22_WR_OVER_CL45(bp, phy,
4550                                   MDIO_REG_BANK_XGXS_BLOCK2,
4551                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4552                                   (rx_lane_swap |
4553                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4554                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4555         } else {
4556                 CL22_WR_OVER_CL45(bp, phy,
4557                                   MDIO_REG_BANK_XGXS_BLOCK2,
4558                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4559         }
4560
4561         if (tx_lane_swap != 0x1b) {
4562                 CL22_WR_OVER_CL45(bp, phy,
4563                                   MDIO_REG_BANK_XGXS_BLOCK2,
4564                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4565                                   (tx_lane_swap |
4566                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4567         } else {
4568                 CL22_WR_OVER_CL45(bp, phy,
4569                                   MDIO_REG_BANK_XGXS_BLOCK2,
4570                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4571         }
4572 }
4573
4574 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4575                                          struct link_params *params)
4576 {
4577         struct bnx2x *bp = params->bp;
4578         u16 control2;
4579         CL22_RD_OVER_CL45(bp, phy,
4580                           MDIO_REG_BANK_SERDES_DIGITAL,
4581                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4582                           &control2);
4583         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4584                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4585         else
4586                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4587         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4588                 phy->speed_cap_mask, control2);
4589         CL22_WR_OVER_CL45(bp, phy,
4590                           MDIO_REG_BANK_SERDES_DIGITAL,
4591                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4592                           control2);
4593
4594         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4595              (phy->speed_cap_mask &
4596                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4597                 DP(NETIF_MSG_LINK, "XGXS\n");
4598
4599                 CL22_WR_OVER_CL45(bp, phy,
4600                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4601                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4602                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4603
4604                 CL22_RD_OVER_CL45(bp, phy,
4605                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4606                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4607                                   &control2);
4608
4609
4610                 control2 |=
4611                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4612
4613                 CL22_WR_OVER_CL45(bp, phy,
4614                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4615                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4616                                   control2);
4617
4618                 /* Disable parallel detection of HiG */
4619                 CL22_WR_OVER_CL45(bp, phy,
4620                                   MDIO_REG_BANK_XGXS_BLOCK2,
4621                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4622                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4623                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4624         }
4625 }
4626
4627 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4628                               struct link_params *params,
4629                               struct link_vars *vars,
4630                               u8 enable_cl73)
4631 {
4632         struct bnx2x *bp = params->bp;
4633         u16 reg_val;
4634
4635         /* CL37 Autoneg */
4636         CL22_RD_OVER_CL45(bp, phy,
4637                           MDIO_REG_BANK_COMBO_IEEE0,
4638                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4639
4640         /* CL37 Autoneg Enabled */
4641         if (vars->line_speed == SPEED_AUTO_NEG)
4642                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4643         else /* CL37 Autoneg Disabled */
4644                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4645                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4646
4647         CL22_WR_OVER_CL45(bp, phy,
4648                           MDIO_REG_BANK_COMBO_IEEE0,
4649                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4650
4651         /* Enable/Disable Autodetection */
4652
4653         CL22_RD_OVER_CL45(bp, phy,
4654                           MDIO_REG_BANK_SERDES_DIGITAL,
4655                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4656         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4657                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4658         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4659         if (vars->line_speed == SPEED_AUTO_NEG)
4660                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4661         else
4662                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4663
4664         CL22_WR_OVER_CL45(bp, phy,
4665                           MDIO_REG_BANK_SERDES_DIGITAL,
4666                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4667
4668         /* Enable TetonII and BAM autoneg */
4669         CL22_RD_OVER_CL45(bp, phy,
4670                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4671                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4672                           &reg_val);
4673         if (vars->line_speed == SPEED_AUTO_NEG) {
4674                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4675                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4676                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4677         } else {
4678                 /* TetonII and BAM Autoneg Disabled */
4679                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4680                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4681         }
4682         CL22_WR_OVER_CL45(bp, phy,
4683                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4684                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4685                           reg_val);
4686
4687         if (enable_cl73) {
4688                 /* Enable Cl73 FSM status bits */
4689                 CL22_WR_OVER_CL45(bp, phy,
4690                                   MDIO_REG_BANK_CL73_USERB0,
4691                                   MDIO_CL73_USERB0_CL73_UCTRL,
4692                                   0xe);
4693
4694                 /* Enable BAM Station Manager*/
4695                 CL22_WR_OVER_CL45(bp, phy,
4696                         MDIO_REG_BANK_CL73_USERB0,
4697                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4698                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4699                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4700                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4701
4702                 /* Advertise CL73 link speeds */
4703                 CL22_RD_OVER_CL45(bp, phy,
4704                                   MDIO_REG_BANK_CL73_IEEEB1,
4705                                   MDIO_CL73_IEEEB1_AN_ADV2,
4706                                   &reg_val);
4707                 if (phy->speed_cap_mask &
4708                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4709                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4710                 if (phy->speed_cap_mask &
4711                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4712                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4713
4714                 CL22_WR_OVER_CL45(bp, phy,
4715                                   MDIO_REG_BANK_CL73_IEEEB1,
4716                                   MDIO_CL73_IEEEB1_AN_ADV2,
4717                                   reg_val);
4718
4719                 /* CL73 Autoneg Enabled */
4720                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4721
4722         } else /* CL73 Autoneg Disabled */
4723                 reg_val = 0;
4724
4725         CL22_WR_OVER_CL45(bp, phy,
4726                           MDIO_REG_BANK_CL73_IEEEB0,
4727                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4728 }
4729
4730 /* program SerDes, forced speed */
4731 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4732                                  struct link_params *params,
4733                                  struct link_vars *vars)
4734 {
4735         struct bnx2x *bp = params->bp;
4736         u16 reg_val;
4737
4738         /* program duplex, disable autoneg and sgmii*/
4739         CL22_RD_OVER_CL45(bp, phy,
4740                           MDIO_REG_BANK_COMBO_IEEE0,
4741                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4742         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4743                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4744                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4745         if (phy->req_duplex == DUPLEX_FULL)
4746                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4747         CL22_WR_OVER_CL45(bp, phy,
4748                           MDIO_REG_BANK_COMBO_IEEE0,
4749                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4750
4751         /*
4752          * program speed
4753          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4754          */
4755         CL22_RD_OVER_CL45(bp, phy,
4756                           MDIO_REG_BANK_SERDES_DIGITAL,
4757                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4758         /* clearing the speed value before setting the right speed */
4759         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4760
4761         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4762                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4763
4764         if (!((vars->line_speed == SPEED_1000) ||
4765               (vars->line_speed == SPEED_100) ||
4766               (vars->line_speed == SPEED_10))) {
4767
4768                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4769                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4770                 if (vars->line_speed == SPEED_10000)
4771                         reg_val |=
4772                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4773         }
4774
4775         CL22_WR_OVER_CL45(bp, phy,
4776                           MDIO_REG_BANK_SERDES_DIGITAL,
4777                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4778
4779 }
4780
4781 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4782                                               struct link_params *params)
4783 {
4784         struct bnx2x *bp = params->bp;
4785         u16 val = 0;
4786
4787         /* configure the 48 bits for BAM AN */
4788
4789         /* set extended capabilities */
4790         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4791                 val |= MDIO_OVER_1G_UP1_2_5G;
4792         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4793                 val |= MDIO_OVER_1G_UP1_10G;
4794         CL22_WR_OVER_CL45(bp, phy,
4795                           MDIO_REG_BANK_OVER_1G,
4796                           MDIO_OVER_1G_UP1, val);
4797
4798         CL22_WR_OVER_CL45(bp, phy,
4799                           MDIO_REG_BANK_OVER_1G,
4800                           MDIO_OVER_1G_UP3, 0x400);
4801 }
4802
4803 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4804                                               struct link_params *params,
4805                                               u16 ieee_fc)
4806 {
4807         struct bnx2x *bp = params->bp;
4808         u16 val;
4809         /* for AN, we are always publishing full duplex */
4810
4811         CL22_WR_OVER_CL45(bp, phy,
4812                           MDIO_REG_BANK_COMBO_IEEE0,
4813                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4814         CL22_RD_OVER_CL45(bp, phy,
4815                           MDIO_REG_BANK_CL73_IEEEB1,
4816                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4817         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4818         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4819         CL22_WR_OVER_CL45(bp, phy,
4820                           MDIO_REG_BANK_CL73_IEEEB1,
4821                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4822 }
4823
4824 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4825                                   struct link_params *params,
4826                                   u8 enable_cl73)
4827 {
4828         struct bnx2x *bp = params->bp;
4829         u16 mii_control;
4830
4831         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4832         /* Enable and restart BAM/CL37 aneg */
4833
4834         if (enable_cl73) {
4835                 CL22_RD_OVER_CL45(bp, phy,
4836                                   MDIO_REG_BANK_CL73_IEEEB0,
4837                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4838                                   &mii_control);
4839
4840                 CL22_WR_OVER_CL45(bp, phy,
4841                                   MDIO_REG_BANK_CL73_IEEEB0,
4842                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4843                                   (mii_control |
4844                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4845                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4846         } else {
4847
4848                 CL22_RD_OVER_CL45(bp, phy,
4849                                   MDIO_REG_BANK_COMBO_IEEE0,
4850                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4851                                   &mii_control);
4852                 DP(NETIF_MSG_LINK,
4853                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4854                          mii_control);
4855                 CL22_WR_OVER_CL45(bp, phy,
4856                                   MDIO_REG_BANK_COMBO_IEEE0,
4857                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4858                                   (mii_control |
4859                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4860                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4861         }
4862 }
4863
4864 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4865                                            struct link_params *params,
4866                                            struct link_vars *vars)
4867 {
4868         struct bnx2x *bp = params->bp;
4869         u16 control1;
4870
4871         /* in SGMII mode, the unicore is always slave */
4872
4873         CL22_RD_OVER_CL45(bp, phy,
4874                           MDIO_REG_BANK_SERDES_DIGITAL,
4875                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4876                           &control1);
4877         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4878         /* set sgmii mode (and not fiber) */
4879         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4880                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4881                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4882         CL22_WR_OVER_CL45(bp, phy,
4883                           MDIO_REG_BANK_SERDES_DIGITAL,
4884                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4885                           control1);
4886
4887         /* if forced speed */
4888         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4889                 /* set speed, disable autoneg */
4890                 u16 mii_control;
4891
4892                 CL22_RD_OVER_CL45(bp, phy,
4893                                   MDIO_REG_BANK_COMBO_IEEE0,
4894                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4895                                   &mii_control);
4896                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4897                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4898                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4899
4900                 switch (vars->line_speed) {
4901                 case SPEED_100:
4902                         mii_control |=
4903                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4904                         break;
4905                 case SPEED_1000:
4906                         mii_control |=
4907                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4908                         break;
4909                 case SPEED_10:
4910                         /* there is nothing to set for 10M */
4911                         break;
4912                 default:
4913                         /* invalid speed for SGMII */
4914                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4915                                   vars->line_speed);
4916                         break;
4917                 }
4918
4919                 /* setting the full duplex */
4920                 if (phy->req_duplex == DUPLEX_FULL)
4921                         mii_control |=
4922                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4923                 CL22_WR_OVER_CL45(bp, phy,
4924                                   MDIO_REG_BANK_COMBO_IEEE0,
4925                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4926                                   mii_control);
4927
4928         } else { /* AN mode */
4929                 /* enable and restart AN */
4930                 bnx2x_restart_autoneg(phy, params, 0);
4931         }
4932 }
4933
4934
4935 /*
4936  * link management
4937  */
4938
4939 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4940                                              struct link_params *params)
4941 {
4942         struct bnx2x *bp = params->bp;
4943         u16 pd_10g, status2_1000x;
4944         if (phy->req_line_speed != SPEED_AUTO_NEG)
4945                 return 0;
4946         CL22_RD_OVER_CL45(bp, phy,
4947                           MDIO_REG_BANK_SERDES_DIGITAL,
4948                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4949                           &status2_1000x);
4950         CL22_RD_OVER_CL45(bp, phy,
4951                           MDIO_REG_BANK_SERDES_DIGITAL,
4952                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4953                           &status2_1000x);
4954         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4955                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
4956                          params->port);
4957                 return 1;
4958         }
4959
4960         CL22_RD_OVER_CL45(bp, phy,
4961                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
4962                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
4963                           &pd_10g);
4964
4965         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4966                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
4967                          params->port);
4968                 return 1;
4969         }
4970         return 0;
4971 }
4972
4973 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
4974                                     struct link_params *params,
4975                                     struct link_vars *vars,
4976                                     u32 gp_status)
4977 {
4978         struct bnx2x *bp = params->bp;
4979         u16 ld_pause;   /* local driver */
4980         u16 lp_pause;   /* link partner */
4981         u16 pause_result;
4982
4983         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4984
4985         /* resolve from gp_status in case of AN complete and not sgmii */
4986         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
4987                 vars->flow_ctrl = phy->req_flow_ctrl;
4988         else if (phy->req_line_speed != SPEED_AUTO_NEG)
4989                 vars->flow_ctrl = params->req_fc_auto_adv;
4990         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
4991                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
4992                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
4993                         vars->flow_ctrl = params->req_fc_auto_adv;
4994                         return;
4995                 }
4996                 if ((gp_status &
4997                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
4998                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
4999                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5000                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5001
5002                         CL22_RD_OVER_CL45(bp, phy,
5003                                           MDIO_REG_BANK_CL73_IEEEB1,
5004                                           MDIO_CL73_IEEEB1_AN_ADV1,
5005                                           &ld_pause);
5006                         CL22_RD_OVER_CL45(bp, phy,
5007                                           MDIO_REG_BANK_CL73_IEEEB1,
5008                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
5009                                           &lp_pause);
5010                         pause_result = (ld_pause &
5011                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5012                                         >> 8;
5013                         pause_result |= (lp_pause &
5014                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5015                                         >> 10;
5016                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5017                                  pause_result);
5018                 } else {
5019                         CL22_RD_OVER_CL45(bp, phy,
5020                                           MDIO_REG_BANK_COMBO_IEEE0,
5021                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5022                                           &ld_pause);
5023                         CL22_RD_OVER_CL45(bp, phy,
5024                                 MDIO_REG_BANK_COMBO_IEEE0,
5025                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5026                                 &lp_pause);
5027                         pause_result = (ld_pause &
5028                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5029                         pause_result |= (lp_pause &
5030                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5031                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5032                                  pause_result);
5033                 }
5034                 bnx2x_pause_resolve(vars, pause_result);
5035         }
5036         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5037 }
5038
5039 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5040                                          struct link_params *params)
5041 {
5042         struct bnx2x *bp = params->bp;
5043         u16 rx_status, ustat_val, cl37_fsm_received;
5044         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5045         /* Step 1: Make sure signal is detected */
5046         CL22_RD_OVER_CL45(bp, phy,
5047                           MDIO_REG_BANK_RX0,
5048                           MDIO_RX0_RX_STATUS,
5049                           &rx_status);
5050         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5051             (MDIO_RX0_RX_STATUS_SIGDET)) {
5052                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5053                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5054                 CL22_WR_OVER_CL45(bp, phy,
5055                                   MDIO_REG_BANK_CL73_IEEEB0,
5056                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5057                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5058                 return;
5059         }
5060         /* Step 2: Check CL73 state machine */
5061         CL22_RD_OVER_CL45(bp, phy,
5062                           MDIO_REG_BANK_CL73_USERB0,
5063                           MDIO_CL73_USERB0_CL73_USTAT1,
5064                           &ustat_val);
5065         if ((ustat_val &
5066              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5067               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5068             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5069               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5070                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5071                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5072                 return;
5073         }
5074         /*
5075          * Step 3: Check CL37 Message Pages received to indicate LP
5076          * supports only CL37
5077          */
5078         CL22_RD_OVER_CL45(bp, phy,
5079                           MDIO_REG_BANK_REMOTE_PHY,
5080                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5081                           &cl37_fsm_received);
5082         if ((cl37_fsm_received &
5083              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5084              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5085             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5086               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5087                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5088                              "misc_rx_status(0x8330) = 0x%x\n",
5089                          cl37_fsm_received);
5090                 return;
5091         }
5092         /*
5093          * The combined cl37/cl73 fsm state information indicating that
5094          * we are connected to a device which does not support cl73, but
5095          * does support cl37 BAM. In this case we disable cl73 and
5096          * restart cl37 auto-neg
5097          */
5098
5099         /* Disable CL73 */
5100         CL22_WR_OVER_CL45(bp, phy,
5101                           MDIO_REG_BANK_CL73_IEEEB0,
5102                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5103                           0);
5104         /* Restart CL37 autoneg */
5105         bnx2x_restart_autoneg(phy, params, 0);
5106         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5107 }
5108
5109 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5110                                   struct link_params *params,
5111                                   struct link_vars *vars,
5112                                   u32 gp_status)
5113 {
5114         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5115                 vars->link_status |=
5116                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5117
5118         if (bnx2x_direct_parallel_detect_used(phy, params))
5119                 vars->link_status |=
5120                         LINK_STATUS_PARALLEL_DETECTION_USED;
5121 }
5122 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5123                                      struct link_params *params,
5124                                       struct link_vars *vars,
5125                                       u16 is_link_up,
5126                                       u16 speed_mask,
5127                                       u16 is_duplex)
5128 {
5129         struct bnx2x *bp = params->bp;
5130         if (phy->req_line_speed == SPEED_AUTO_NEG)
5131                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5132         if (is_link_up) {
5133                 DP(NETIF_MSG_LINK, "phy link up\n");
5134
5135                 vars->phy_link_up = 1;
5136                 vars->link_status |= LINK_STATUS_LINK_UP;
5137
5138                 switch (speed_mask) {
5139                 case GP_STATUS_10M:
5140                         vars->line_speed = SPEED_10;
5141                         if (vars->duplex == DUPLEX_FULL)
5142                                 vars->link_status |= LINK_10TFD;
5143                         else
5144                                 vars->link_status |= LINK_10THD;
5145                         break;
5146
5147                 case GP_STATUS_100M:
5148                         vars->line_speed = SPEED_100;
5149                         if (vars->duplex == DUPLEX_FULL)
5150                                 vars->link_status |= LINK_100TXFD;
5151                         else
5152                                 vars->link_status |= LINK_100TXHD;
5153                         break;
5154
5155                 case GP_STATUS_1G:
5156                 case GP_STATUS_1G_KX:
5157                         vars->line_speed = SPEED_1000;
5158                         if (vars->duplex == DUPLEX_FULL)
5159                                 vars->link_status |= LINK_1000TFD;
5160                         else
5161                                 vars->link_status |= LINK_1000THD;
5162                         break;
5163
5164                 case GP_STATUS_2_5G:
5165                         vars->line_speed = SPEED_2500;
5166                         if (vars->duplex == DUPLEX_FULL)
5167                                 vars->link_status |= LINK_2500TFD;
5168                         else
5169                                 vars->link_status |= LINK_2500THD;
5170                         break;
5171
5172                 case GP_STATUS_5G:
5173                 case GP_STATUS_6G:
5174                         DP(NETIF_MSG_LINK,
5175                                  "link speed unsupported  gp_status 0x%x\n",
5176                                   speed_mask);
5177                         return -EINVAL;
5178
5179                 case GP_STATUS_10G_KX4:
5180                 case GP_STATUS_10G_HIG:
5181                 case GP_STATUS_10G_CX4:
5182                 case GP_STATUS_10G_KR:
5183                 case GP_STATUS_10G_SFI:
5184                 case GP_STATUS_10G_XFI:
5185                         vars->line_speed = SPEED_10000;
5186                         vars->link_status |= LINK_10GTFD;
5187                         break;
5188                 case GP_STATUS_20G_DXGXS:
5189                         vars->line_speed = SPEED_20000;
5190                         vars->link_status |= LINK_20GTFD;
5191                         break;
5192                 default:
5193                         DP(NETIF_MSG_LINK,
5194                                   "link speed unsupported gp_status 0x%x\n",
5195                                   speed_mask);
5196                         return -EINVAL;
5197                 }
5198         } else { /* link_down */
5199                 DP(NETIF_MSG_LINK, "phy link down\n");
5200
5201                 vars->phy_link_up = 0;
5202
5203                 vars->duplex = DUPLEX_FULL;
5204                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5205                 vars->mac_type = MAC_TYPE_NONE;
5206         }
5207         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5208                     vars->phy_link_up, vars->line_speed);
5209         return 0;
5210 }
5211
5212 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5213                                       struct link_params *params,
5214                                       struct link_vars *vars)
5215 {
5216
5217         struct bnx2x *bp = params->bp;
5218
5219         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5220         int rc = 0;
5221
5222         /* Read gp_status */
5223         CL22_RD_OVER_CL45(bp, phy,
5224                           MDIO_REG_BANK_GP_STATUS,
5225                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5226                           &gp_status);
5227         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5228                 duplex = DUPLEX_FULL;
5229         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5230                 link_up = 1;
5231         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5232         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5233                        gp_status, link_up, speed_mask);
5234         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5235                                          duplex);
5236         if (rc == -EINVAL)
5237                 return rc;
5238
5239         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5240                 if (SINGLE_MEDIA_DIRECT(params)) {
5241                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5242                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5243                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5244                                                       gp_status);
5245                 }
5246         } else { /* link_down */
5247                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5248                     SINGLE_MEDIA_DIRECT(params)) {
5249                         /* Check signal is detected */
5250                         bnx2x_check_fallback_to_cl37(phy, params);
5251                 }
5252         }
5253
5254         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5255                    vars->duplex, vars->flow_ctrl, vars->link_status);
5256         return rc;
5257 }
5258
5259 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5260                                      struct link_params *params,
5261                                      struct link_vars *vars)
5262 {
5263
5264         struct bnx2x *bp = params->bp;
5265
5266         u8 lane;
5267         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5268         int rc = 0;
5269         lane = bnx2x_get_warpcore_lane(phy, params);
5270         /* Read gp_status */
5271         if (phy->req_line_speed > SPEED_10000) {
5272                 u16 temp_link_up;
5273                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5274                                 1, &temp_link_up);
5275                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5276                                 1, &link_up);
5277                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5278                                temp_link_up, link_up);
5279                 link_up &= (1<<2);
5280                 if (link_up)
5281                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5282         } else {
5283                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5284                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5285                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5286                 /* Check for either KR or generic link up. */
5287                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5288                         ((gp_status1 >> 12) & 0xf);
5289                 link_up = gp_status1 & (1 << lane);
5290                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5291                         u16 pd, gp_status4;
5292                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5293                                 /* Check Autoneg complete */
5294                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5295                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5296                                                 &gp_status4);
5297                                 if (gp_status4 & ((1<<12)<<lane))
5298                                         vars->link_status |=
5299                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5300
5301                                 /* Check parallel detect used */
5302                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5303                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5304                                                 &pd);
5305                                 if (pd & (1<<15))
5306                                         vars->link_status |=
5307                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5308                         }
5309                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5310                 }
5311         }
5312
5313         if (lane < 2) {
5314                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5315                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5316         } else {
5317                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5318                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5319         }
5320         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5321
5322         if ((lane & 1) == 0)
5323                 gp_speed <<= 8;
5324         gp_speed &= 0x3f00;
5325
5326
5327         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5328                                          duplex);
5329
5330         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5331                    vars->duplex, vars->flow_ctrl, vars->link_status);
5332         return rc;
5333 }
5334 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5335 {
5336         struct bnx2x *bp = params->bp;
5337         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5338         u16 lp_up2;
5339         u16 tx_driver;
5340         u16 bank;
5341
5342         /* read precomp */
5343         CL22_RD_OVER_CL45(bp, phy,
5344                           MDIO_REG_BANK_OVER_1G,
5345                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5346
5347         /* bits [10:7] at lp_up2, positioned at [15:12] */
5348         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5349                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5350                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5351
5352         if (lp_up2 == 0)
5353                 return;
5354
5355         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5356               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5357                 CL22_RD_OVER_CL45(bp, phy,
5358                                   bank,
5359                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5360
5361                 /* replace tx_driver bits [15:12] */
5362                 if (lp_up2 !=
5363                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5364                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5365                         tx_driver |= lp_up2;
5366                         CL22_WR_OVER_CL45(bp, phy,
5367                                           bank,
5368                                           MDIO_TX0_TX_DRIVER, tx_driver);
5369                 }
5370         }
5371 }
5372
5373 static int bnx2x_emac_program(struct link_params *params,
5374                               struct link_vars *vars)
5375 {
5376         struct bnx2x *bp = params->bp;
5377         u8 port = params->port;
5378         u16 mode = 0;
5379
5380         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5381         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5382                        EMAC_REG_EMAC_MODE,
5383                        (EMAC_MODE_25G_MODE |
5384                         EMAC_MODE_PORT_MII_10M |
5385                         EMAC_MODE_HALF_DUPLEX));
5386         switch (vars->line_speed) {
5387         case SPEED_10:
5388                 mode |= EMAC_MODE_PORT_MII_10M;
5389                 break;
5390
5391         case SPEED_100:
5392                 mode |= EMAC_MODE_PORT_MII;
5393                 break;
5394
5395         case SPEED_1000:
5396                 mode |= EMAC_MODE_PORT_GMII;
5397                 break;
5398
5399         case SPEED_2500:
5400                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5401                 break;
5402
5403         default:
5404                 /* 10G not valid for EMAC */
5405                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5406                            vars->line_speed);
5407                 return -EINVAL;
5408         }
5409
5410         if (vars->duplex == DUPLEX_HALF)
5411                 mode |= EMAC_MODE_HALF_DUPLEX;
5412         bnx2x_bits_en(bp,
5413                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5414                       mode);
5415
5416         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5417         return 0;
5418 }
5419
5420 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5421                                   struct link_params *params)
5422 {
5423
5424         u16 bank, i = 0;
5425         struct bnx2x *bp = params->bp;
5426
5427         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5428               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5429                         CL22_WR_OVER_CL45(bp, phy,
5430                                           bank,
5431                                           MDIO_RX0_RX_EQ_BOOST,
5432                                           phy->rx_preemphasis[i]);
5433         }
5434
5435         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5436                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5437                         CL22_WR_OVER_CL45(bp, phy,
5438                                           bank,
5439                                           MDIO_TX0_TX_DRIVER,
5440                                           phy->tx_preemphasis[i]);
5441         }
5442 }
5443
5444 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5445                                    struct link_params *params,
5446                                    struct link_vars *vars)
5447 {
5448         struct bnx2x *bp = params->bp;
5449         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5450                           (params->loopback_mode == LOOPBACK_XGXS));
5451         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5452                 if (SINGLE_MEDIA_DIRECT(params) &&
5453                     (params->feature_config_flags &
5454                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5455                         bnx2x_set_preemphasis(phy, params);
5456
5457                 /* forced speed requested? */
5458                 if (vars->line_speed != SPEED_AUTO_NEG ||
5459                     (SINGLE_MEDIA_DIRECT(params) &&
5460                      params->loopback_mode == LOOPBACK_EXT)) {
5461                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5462
5463                         /* disable autoneg */
5464                         bnx2x_set_autoneg(phy, params, vars, 0);
5465
5466                         /* program speed and duplex */
5467                         bnx2x_program_serdes(phy, params, vars);
5468
5469                 } else { /* AN_mode */
5470                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5471
5472                         /* AN enabled */
5473                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5474
5475                         /* program duplex & pause advertisement (for aneg) */
5476                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5477                                                           vars->ieee_fc);
5478
5479                         /* enable autoneg */
5480                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5481
5482                         /* enable and restart AN */
5483                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5484                 }
5485
5486         } else { /* SGMII mode */
5487                 DP(NETIF_MSG_LINK, "SGMII\n");
5488
5489                 bnx2x_initialize_sgmii_process(phy, params, vars);
5490         }
5491 }
5492
5493 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5494                           struct link_params *params,
5495                           struct link_vars *vars)
5496 {
5497         int rc;
5498         vars->phy_flags |= PHY_XGXS_FLAG;
5499         if ((phy->req_line_speed &&
5500              ((phy->req_line_speed == SPEED_100) ||
5501               (phy->req_line_speed == SPEED_10))) ||
5502             (!phy->req_line_speed &&
5503              (phy->speed_cap_mask >=
5504               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5505              (phy->speed_cap_mask <
5506               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5507             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5508                 vars->phy_flags |= PHY_SGMII_FLAG;
5509         else
5510                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5511
5512         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5513         bnx2x_set_aer_mmd(params, phy);
5514         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5515                 bnx2x_set_master_ln(params, phy);
5516
5517         rc = bnx2x_reset_unicore(params, phy, 0);
5518         /* reset the SerDes and wait for reset bit return low */
5519         if (rc != 0)
5520                 return rc;
5521
5522         bnx2x_set_aer_mmd(params, phy);
5523         /* setting the masterLn_def again after the reset */
5524         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5525                 bnx2x_set_master_ln(params, phy);
5526                 bnx2x_set_swap_lanes(params, phy);
5527         }
5528
5529         return rc;
5530 }
5531
5532 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5533                                      struct bnx2x_phy *phy,
5534                                      struct link_params *params)
5535 {
5536         u16 cnt, ctrl;
5537         /* Wait for soft reset to get cleared up to 1 sec */
5538         for (cnt = 0; cnt < 1000; cnt++) {
5539                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616)
5540                         bnx2x_cl22_read(bp, phy,
5541                                 MDIO_PMA_REG_CTRL, &ctrl);
5542                 else
5543                         bnx2x_cl45_read(bp, phy,
5544                                 MDIO_PMA_DEVAD,
5545                                 MDIO_PMA_REG_CTRL, &ctrl);
5546                 if (!(ctrl & (1<<15)))
5547                         break;
5548                 msleep(1);
5549         }
5550
5551         if (cnt == 1000)
5552                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5553                                       " Port %d\n",
5554                          params->port);
5555         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5556         return cnt;
5557 }
5558
5559 static void bnx2x_link_int_enable(struct link_params *params)
5560 {
5561         u8 port = params->port;
5562         u32 mask;
5563         struct bnx2x *bp = params->bp;
5564
5565         /* Setting the status to report on link up for either XGXS or SerDes */
5566         if (CHIP_IS_E3(bp)) {
5567                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5568                 if (!(SINGLE_MEDIA_DIRECT(params)))
5569                         mask |= NIG_MASK_MI_INT;
5570         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5571                 mask = (NIG_MASK_XGXS0_LINK10G |
5572                         NIG_MASK_XGXS0_LINK_STATUS);
5573                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5574                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5575                         params->phy[INT_PHY].type !=
5576                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5577                         mask |= NIG_MASK_MI_INT;
5578                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5579                 }
5580
5581         } else { /* SerDes */
5582                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5583                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5584                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5585                         params->phy[INT_PHY].type !=
5586                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5587                         mask |= NIG_MASK_MI_INT;
5588                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5589                 }
5590         }
5591         bnx2x_bits_en(bp,
5592                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5593                       mask);
5594
5595         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5596                  (params->switch_cfg == SWITCH_CFG_10G),
5597                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5598         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5599                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5600                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5601                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5602         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5603            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5604            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5605 }
5606
5607 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5608                                      u8 exp_mi_int)
5609 {
5610         u32 latch_status = 0;
5611
5612         /*
5613          * Disable the MI INT ( external phy int ) by writing 1 to the
5614          * status register. Link down indication is high-active-signal,
5615          * so in this case we need to write the status to clear the XOR
5616          */
5617         /* Read Latched signals */
5618         latch_status = REG_RD(bp,
5619                                     NIG_REG_LATCH_STATUS_0 + port*8);
5620         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5621         /* Handle only those with latched-signal=up.*/
5622         if (exp_mi_int)
5623                 bnx2x_bits_en(bp,
5624                               NIG_REG_STATUS_INTERRUPT_PORT0
5625                               + port*4,
5626                               NIG_STATUS_EMAC0_MI_INT);
5627         else
5628                 bnx2x_bits_dis(bp,
5629                                NIG_REG_STATUS_INTERRUPT_PORT0
5630                                + port*4,
5631                                NIG_STATUS_EMAC0_MI_INT);
5632
5633         if (latch_status & 1) {
5634
5635                 /* For all latched-signal=up : Re-Arm Latch signals */
5636                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5637                        (latch_status & 0xfffe) | (latch_status & 1));
5638         }
5639         /* For all latched-signal=up,Write original_signal to status */
5640 }
5641
5642 static void bnx2x_link_int_ack(struct link_params *params,
5643                                struct link_vars *vars, u8 is_10g_plus)
5644 {
5645         struct bnx2x *bp = params->bp;
5646         u8 port = params->port;
5647         u32 mask;
5648         /*
5649          * First reset all status we assume only one line will be
5650          * change at a time
5651          */
5652         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5653                        (NIG_STATUS_XGXS0_LINK10G |
5654                         NIG_STATUS_XGXS0_LINK_STATUS |
5655                         NIG_STATUS_SERDES0_LINK_STATUS));
5656         if (vars->phy_link_up) {
5657                 if (USES_WARPCORE(bp))
5658                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5659                 else {
5660                         if (is_10g_plus)
5661                                 mask = NIG_STATUS_XGXS0_LINK10G;
5662                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5663                                 /*
5664                                  * Disable the link interrupt by writing 1 to
5665                                  * the relevant lane in the status register
5666                                  */
5667                                 u32 ser_lane =
5668                                         ((params->lane_config &
5669                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5670                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5671                                 mask = ((1 << ser_lane) <<
5672                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5673                         } else
5674                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5675                 }
5676                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5677                                mask);
5678                 bnx2x_bits_en(bp,
5679                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5680                               mask);
5681         }
5682 }
5683
5684 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5685 {
5686         u8 *str_ptr = str;
5687         u32 mask = 0xf0000000;
5688         u8 shift = 8*4;
5689         u8 digit;
5690         u8 remove_leading_zeros = 1;
5691         if (*len < 10) {
5692                 /* Need more than 10chars for this format */
5693                 *str_ptr = '\0';
5694                 (*len)--;
5695                 return -EINVAL;
5696         }
5697         while (shift > 0) {
5698
5699                 shift -= 4;
5700                 digit = ((num & mask) >> shift);
5701                 if (digit == 0 && remove_leading_zeros) {
5702                         mask = mask >> 4;
5703                         continue;
5704                 } else if (digit < 0xa)
5705                         *str_ptr = digit + '0';
5706                 else
5707                         *str_ptr = digit - 0xa + 'a';
5708                 remove_leading_zeros = 0;
5709                 str_ptr++;
5710                 (*len)--;
5711                 mask = mask >> 4;
5712                 if (shift == 4*4) {
5713                         *str_ptr = '.';
5714                         str_ptr++;
5715                         (*len)--;
5716                         remove_leading_zeros = 1;
5717                 }
5718         }
5719         return 0;
5720 }
5721
5722
5723 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5724 {
5725         str[0] = '\0';
5726         (*len)--;
5727         return 0;
5728 }
5729
5730 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5731                                  u8 *version, u16 len)
5732 {
5733         struct bnx2x *bp;
5734         u32 spirom_ver = 0;
5735         int status = 0;
5736         u8 *ver_p = version;
5737         u16 remain_len = len;
5738         if (version == NULL || params == NULL)
5739                 return -EINVAL;
5740         bp = params->bp;
5741
5742         /* Extract first external phy*/
5743         version[0] = '\0';
5744         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5745
5746         if (params->phy[EXT_PHY1].format_fw_ver) {
5747                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5748                                                               ver_p,
5749                                                               &remain_len);
5750                 ver_p += (len - remain_len);
5751         }
5752         if ((params->num_phys == MAX_PHYS) &&
5753             (params->phy[EXT_PHY2].ver_addr != 0)) {
5754                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5755                 if (params->phy[EXT_PHY2].format_fw_ver) {
5756                         *ver_p = '/';
5757                         ver_p++;
5758                         remain_len--;
5759                         status |= params->phy[EXT_PHY2].format_fw_ver(
5760                                 spirom_ver,
5761                                 ver_p,
5762                                 &remain_len);
5763                         ver_p = version + (len - remain_len);
5764                 }
5765         }
5766         *ver_p = '\0';
5767         return status;
5768 }
5769
5770 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5771                                     struct link_params *params)
5772 {
5773         u8 port = params->port;
5774         struct bnx2x *bp = params->bp;
5775
5776         if (phy->req_line_speed != SPEED_1000) {
5777                 u32 md_devad = 0;
5778
5779                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5780
5781                 if (!CHIP_IS_E3(bp)) {
5782                         /* change the uni_phy_addr in the nig */
5783                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5784                                                port*0x18));
5785
5786                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5787                                0x5);
5788                 }
5789
5790                 bnx2x_cl45_write(bp, phy,
5791                                  5,
5792                                  (MDIO_REG_BANK_AER_BLOCK +
5793                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
5794                                  0x2800);
5795
5796                 bnx2x_cl45_write(bp, phy,
5797                                  5,
5798                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5799                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5800                                  0x6041);
5801                 msleep(200);
5802                 /* set aer mmd back */
5803                 bnx2x_set_aer_mmd(params, phy);
5804
5805                 if (!CHIP_IS_E3(bp)) {
5806                         /* and md_devad */
5807                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5808                                md_devad);
5809                 }
5810         } else {
5811                 u16 mii_ctrl;
5812                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5813                 bnx2x_cl45_read(bp, phy, 5,
5814                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5815                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5816                                 &mii_ctrl);
5817                 bnx2x_cl45_write(bp, phy, 5,
5818                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5819                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5820                                  mii_ctrl |
5821                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5822         }
5823 }
5824
5825 int bnx2x_set_led(struct link_params *params,
5826                   struct link_vars *vars, u8 mode, u32 speed)
5827 {
5828         u8 port = params->port;
5829         u16 hw_led_mode = params->hw_led_mode;
5830         int rc = 0;
5831         u8 phy_idx;
5832         u32 tmp;
5833         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5834         struct bnx2x *bp = params->bp;
5835         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5836         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5837                  speed, hw_led_mode);
5838         /* In case */
5839         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5840                 if (params->phy[phy_idx].set_link_led) {
5841                         params->phy[phy_idx].set_link_led(
5842                                 &params->phy[phy_idx], params, mode);
5843                 }
5844         }
5845
5846         switch (mode) {
5847         case LED_MODE_FRONT_PANEL_OFF:
5848         case LED_MODE_OFF:
5849                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5850                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5851                        SHARED_HW_CFG_LED_MAC1);
5852
5853                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5854                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5855                 break;
5856
5857         case LED_MODE_OPER:
5858                 /*
5859                  * For all other phys, OPER mode is same as ON, so in case
5860                  * link is down, do nothing
5861                  */
5862                 if (!vars->link_up)
5863                         break;
5864         case LED_MODE_ON:
5865                 if (((params->phy[EXT_PHY1].type ==
5866                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5867                          (params->phy[EXT_PHY1].type ==
5868                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5869                     CHIP_IS_E2(bp) && params->num_phys == 2) {
5870                         /*
5871                          * This is a work-around for E2+8727 Configurations
5872                          */
5873                         if (mode == LED_MODE_ON ||
5874                                 speed == SPEED_10000){
5875                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5876                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5877
5878                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5879                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5880                                         (tmp | EMAC_LED_OVERRIDE));
5881                                 return rc;
5882                         }
5883                 } else if (SINGLE_MEDIA_DIRECT(params) &&
5884                            (CHIP_IS_E1x(bp) ||
5885                             CHIP_IS_E2(bp))) {
5886                         /*
5887                          * This is a work-around for HW issue found when link
5888                          * is up in CL73
5889                          */
5890                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5891                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5892                 } else {
5893                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5894                 }
5895
5896                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5897                 /* Set blinking rate to ~15.9Hz */
5898                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5899                        LED_BLINK_RATE_VAL);
5900                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5901                        port*4, 1);
5902                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5903                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5904
5905                 if (CHIP_IS_E1(bp) &&
5906                     ((speed == SPEED_2500) ||
5907                      (speed == SPEED_1000) ||
5908                      (speed == SPEED_100) ||
5909                      (speed == SPEED_10))) {
5910                         /*
5911                          * On Everest 1 Ax chip versions for speeds less than
5912                          * 10G LED scheme is different
5913                          */
5914                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5915                                + port*4, 1);
5916                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5917                                port*4, 0);
5918                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5919                                port*4, 1);
5920                 }
5921                 break;
5922
5923         default:
5924                 rc = -EINVAL;
5925                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5926                          mode);
5927                 break;
5928         }
5929         return rc;
5930
5931 }
5932
5933 /*
5934  * This function comes to reflect the actual link state read DIRECTLY from the
5935  * HW
5936  */
5937 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5938                     u8 is_serdes)
5939 {
5940         struct bnx2x *bp = params->bp;
5941         u16 gp_status = 0, phy_index = 0;
5942         u8 ext_phy_link_up = 0, serdes_phy_type;
5943         struct link_vars temp_vars;
5944         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
5945
5946         if (CHIP_IS_E3(bp)) {
5947                 u16 link_up;
5948                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
5949                     > SPEED_10000) {
5950                         /* Check 20G link */
5951                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5952                                         1, &link_up);
5953                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5954                                         1, &link_up);
5955                         link_up &= (1<<2);
5956                 } else {
5957                         /* Check 10G link and below*/
5958                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
5959                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5960                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
5961                                         &gp_status);
5962                         gp_status = ((gp_status >> 8) & 0xf) |
5963                                 ((gp_status >> 12) & 0xf);
5964                         link_up = gp_status & (1 << lane);
5965                 }
5966                 if (!link_up)
5967                         return -ESRCH;
5968         } else {
5969                 CL22_RD_OVER_CL45(bp, int_phy,
5970                           MDIO_REG_BANK_GP_STATUS,
5971                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5972                           &gp_status);
5973         /* link is up only if both local phy and external phy are up */
5974         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
5975                 return -ESRCH;
5976         }
5977         /* In XGXS loopback mode, do not check external PHY */
5978         if (params->loopback_mode == LOOPBACK_XGXS)
5979                 return 0;
5980
5981         switch (params->num_phys) {
5982         case 1:
5983                 /* No external PHY */
5984                 return 0;
5985         case 2:
5986                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
5987                         &params->phy[EXT_PHY1],
5988                         params, &temp_vars);
5989                 break;
5990         case 3: /* Dual Media */
5991                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
5992                       phy_index++) {
5993                         serdes_phy_type = ((params->phy[phy_index].media_type ==
5994                                             ETH_PHY_SFP_FIBER) ||
5995                                            (params->phy[phy_index].media_type ==
5996                                             ETH_PHY_XFP_FIBER) ||
5997                                            (params->phy[phy_index].media_type ==
5998                                             ETH_PHY_DA_TWINAX));
5999
6000                         if (is_serdes != serdes_phy_type)
6001                                 continue;
6002                         if (params->phy[phy_index].read_status) {
6003                                 ext_phy_link_up |=
6004                                         params->phy[phy_index].read_status(
6005                                                 &params->phy[phy_index],
6006                                                 params, &temp_vars);
6007                         }
6008                 }
6009                 break;
6010         }
6011         if (ext_phy_link_up)
6012                 return 0;
6013         return -ESRCH;
6014 }
6015
6016 static int bnx2x_link_initialize(struct link_params *params,
6017                                  struct link_vars *vars)
6018 {
6019         int rc = 0;
6020         u8 phy_index, non_ext_phy;
6021         struct bnx2x *bp = params->bp;
6022         /*
6023          * In case of external phy existence, the line speed would be the
6024          * line speed linked up by the external phy. In case it is direct
6025          * only, then the line_speed during initialization will be
6026          * equal to the req_line_speed
6027          */
6028         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6029
6030         /*
6031          * Initialize the internal phy in case this is a direct board
6032          * (no external phys), or this board has external phy which requires
6033          * to first.
6034          */
6035         if (!USES_WARPCORE(bp))
6036                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6037         /* init ext phy and enable link state int */
6038         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6039                        (params->loopback_mode == LOOPBACK_XGXS));
6040
6041         if (non_ext_phy ||
6042             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6043             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6044                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6045                 if (vars->line_speed == SPEED_AUTO_NEG &&
6046                     (CHIP_IS_E1x(bp) ||
6047                      CHIP_IS_E2(bp)))
6048                         bnx2x_set_parallel_detection(phy, params);
6049                         if (params->phy[INT_PHY].config_init)
6050                                 params->phy[INT_PHY].config_init(phy,
6051                                                                  params,
6052                                                                  vars);
6053         }
6054
6055         /* Init external phy*/
6056         if (non_ext_phy) {
6057                 if (params->phy[INT_PHY].supported &
6058                     SUPPORTED_FIBRE)
6059                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6060         } else {
6061                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6062                       phy_index++) {
6063                         /*
6064                          * No need to initialize second phy in case of first
6065                          * phy only selection. In case of second phy, we do
6066                          * need to initialize the first phy, since they are
6067                          * connected.
6068                          */
6069                         if (params->phy[phy_index].supported &
6070                             SUPPORTED_FIBRE)
6071                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6072
6073                         if (phy_index == EXT_PHY2 &&
6074                             (bnx2x_phy_selection(params) ==
6075                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6076                                 DP(NETIF_MSG_LINK, "Not initializing"
6077                                                 " second phy\n");
6078                                 continue;
6079                         }
6080                         params->phy[phy_index].config_init(
6081                                 &params->phy[phy_index],
6082                                 params, vars);
6083                 }
6084         }
6085         /* Reset the interrupt indication after phy was initialized */
6086         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6087                        params->port*4,
6088                        (NIG_STATUS_XGXS0_LINK10G |
6089                         NIG_STATUS_XGXS0_LINK_STATUS |
6090                         NIG_STATUS_SERDES0_LINK_STATUS |
6091                         NIG_MASK_MI_INT));
6092         bnx2x_update_mng(params, vars->link_status);
6093         return rc;
6094 }
6095
6096 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6097                                  struct link_params *params)
6098 {
6099         /* reset the SerDes/XGXS */
6100         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6101                (0x1ff << (params->port*16)));
6102 }
6103
6104 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6105                                         struct link_params *params)
6106 {
6107         struct bnx2x *bp = params->bp;
6108         u8 gpio_port;
6109         /* HW reset */
6110         if (CHIP_IS_E2(bp))
6111                 gpio_port = BP_PATH(bp);
6112         else
6113                 gpio_port = params->port;
6114         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6115                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6116                        gpio_port);
6117         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6118                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6119                        gpio_port);
6120         DP(NETIF_MSG_LINK, "reset external PHY\n");
6121 }
6122
6123 static int bnx2x_update_link_down(struct link_params *params,
6124                                   struct link_vars *vars)
6125 {
6126         struct bnx2x *bp = params->bp;
6127         u8 port = params->port;
6128
6129         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6130         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6131         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6132         /* indicate no mac active */
6133         vars->mac_type = MAC_TYPE_NONE;
6134
6135         /* update shared memory */
6136         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6137                                LINK_STATUS_LINK_UP |
6138                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6139                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6140                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6141                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6142         vars->line_speed = 0;
6143         bnx2x_update_mng(params, vars->link_status);
6144
6145         /* activate nig drain */
6146         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6147
6148         /* disable emac */
6149         if (!CHIP_IS_E3(bp))
6150                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6151
6152         msleep(10);
6153         /* reset BigMac/Xmac */
6154         if (CHIP_IS_E1x(bp) ||
6155             CHIP_IS_E2(bp)) {
6156                 bnx2x_bmac_rx_disable(bp, params->port);
6157                 REG_WR(bp, GRCBASE_MISC +
6158                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6159                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6160         }
6161         if (CHIP_IS_E3(bp))
6162                 bnx2x_xmac_disable(params);
6163
6164         return 0;
6165 }
6166
6167 static int bnx2x_update_link_up(struct link_params *params,
6168                                 struct link_vars *vars,
6169                                 u8 link_10g)
6170 {
6171         struct bnx2x *bp = params->bp;
6172         u8 port = params->port;
6173         int rc = 0;
6174
6175         vars->link_status |= LINK_STATUS_LINK_UP;
6176         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6177
6178         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6179                 vars->link_status |=
6180                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6181
6182         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6183                 vars->link_status |=
6184                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6185         if (USES_WARPCORE(bp)) {
6186                 if (link_10g) {
6187                         if (bnx2x_xmac_enable(params, vars, 0) ==
6188                             -ESRCH) {
6189                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6190                                 vars->link_up = 0;
6191                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6192                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6193                         }
6194                 } else
6195                         bnx2x_umac_enable(params, vars, 0);
6196                 bnx2x_set_led(params, vars,
6197                               LED_MODE_OPER, vars->line_speed);
6198         }
6199         if ((CHIP_IS_E1x(bp) ||
6200              CHIP_IS_E2(bp))) {
6201                 if (link_10g) {
6202                         if (bnx2x_bmac_enable(params, vars, 0) ==
6203                             -ESRCH) {
6204                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6205                                 vars->link_up = 0;
6206                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6207                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6208                         }
6209
6210                         bnx2x_set_led(params, vars,
6211                                       LED_MODE_OPER, SPEED_10000);
6212                 } else {
6213                         rc = bnx2x_emac_program(params, vars);
6214                         bnx2x_emac_enable(params, vars, 0);
6215
6216                         /* AN complete? */
6217                         if ((vars->link_status &
6218                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6219                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6220                             SINGLE_MEDIA_DIRECT(params))
6221                                 bnx2x_set_gmii_tx_driver(params);
6222                 }
6223         }
6224
6225         /* PBF - link up */
6226         if (CHIP_IS_E1x(bp))
6227                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6228                                        vars->line_speed);
6229
6230         /* disable drain */
6231         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6232
6233         /* update shared memory */
6234         bnx2x_update_mng(params, vars->link_status);
6235         msleep(20);
6236         return rc;
6237 }
6238 /*
6239  * The bnx2x_link_update function should be called upon link
6240  * interrupt.
6241  * Link is considered up as follows:
6242  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6243  *   to be up
6244  * - SINGLE_MEDIA - The link between the 577xx and the external
6245  *   phy (XGXS) need to up as well as the external link of the
6246  *   phy (PHY_EXT1)
6247  * - DUAL_MEDIA - The link between the 577xx and the first
6248  *   external phy needs to be up, and at least one of the 2
6249  *   external phy link must be up.
6250  */
6251 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6252 {
6253         struct bnx2x *bp = params->bp;
6254         struct link_vars phy_vars[MAX_PHYS];
6255         u8 port = params->port;
6256         u8 link_10g_plus, phy_index;
6257         u8 ext_phy_link_up = 0, cur_link_up;
6258         int rc = 0;
6259         u8 is_mi_int = 0;
6260         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6261         u8 active_external_phy = INT_PHY;
6262         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6263         for (phy_index = INT_PHY; phy_index < params->num_phys;
6264               phy_index++) {
6265                 phy_vars[phy_index].flow_ctrl = 0;
6266                 phy_vars[phy_index].link_status = 0;
6267                 phy_vars[phy_index].line_speed = 0;
6268                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6269                 phy_vars[phy_index].phy_link_up = 0;
6270                 phy_vars[phy_index].link_up = 0;
6271                 phy_vars[phy_index].fault_detected = 0;
6272         }
6273
6274         if (USES_WARPCORE(bp))
6275                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6276
6277         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6278                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6279                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6280
6281         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6282                                 port*0x18) > 0);
6283         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6284                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6285                  is_mi_int,
6286                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6287
6288         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6289           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6290           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6291
6292         /* disable emac */
6293         if (!CHIP_IS_E3(bp))
6294                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6295
6296         /*
6297          * Step 1:
6298          * Check external link change only for external phys, and apply
6299          * priority selection between them in case the link on both phys
6300          * is up. Note that instead of the common vars, a temporary
6301          * vars argument is used since each phy may have different link/
6302          * speed/duplex result
6303          */
6304         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6305               phy_index++) {
6306                 struct bnx2x_phy *phy = &params->phy[phy_index];
6307                 if (!phy->read_status)
6308                         continue;
6309                 /* Read link status and params of this ext phy */
6310                 cur_link_up = phy->read_status(phy, params,
6311                                                &phy_vars[phy_index]);
6312                 if (cur_link_up) {
6313                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6314                                    phy_index);
6315                 } else {
6316                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6317                                    phy_index);
6318                         continue;
6319                 }
6320
6321                 if (!ext_phy_link_up) {
6322                         ext_phy_link_up = 1;
6323                         active_external_phy = phy_index;
6324                 } else {
6325                         switch (bnx2x_phy_selection(params)) {
6326                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6327                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6328                         /*
6329                          * In this option, the first PHY makes sure to pass the
6330                          * traffic through itself only.
6331                          * Its not clear how to reset the link on the second phy
6332                          */
6333                                 active_external_phy = EXT_PHY1;
6334                                 break;
6335                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6336                         /*
6337                          * In this option, the first PHY makes sure to pass the
6338                          * traffic through the second PHY.
6339                          */
6340                                 active_external_phy = EXT_PHY2;
6341                                 break;
6342                         default:
6343                         /*
6344                          * Link indication on both PHYs with the following cases
6345                          * is invalid:
6346                          * - FIRST_PHY means that second phy wasn't initialized,
6347                          * hence its link is expected to be down
6348                          * - SECOND_PHY means that first phy should not be able
6349                          * to link up by itself (using configuration)
6350                          * - DEFAULT should be overriden during initialiazation
6351                          */
6352                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6353                                            "mpc=0x%x. DISABLING LINK !!!\n",
6354                                            params->multi_phy_config);
6355                                 ext_phy_link_up = 0;
6356                                 break;
6357                         }
6358                 }
6359         }
6360         prev_line_speed = vars->line_speed;
6361         /*
6362          * Step 2:
6363          * Read the status of the internal phy. In case of
6364          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6365          * otherwise this is the link between the 577xx and the first
6366          * external phy
6367          */
6368         if (params->phy[INT_PHY].read_status)
6369                 params->phy[INT_PHY].read_status(
6370                         &params->phy[INT_PHY],
6371                         params, vars);
6372         /*
6373          * The INT_PHY flow control reside in the vars. This include the
6374          * case where the speed or flow control are not set to AUTO.
6375          * Otherwise, the active external phy flow control result is set
6376          * to the vars. The ext_phy_line_speed is needed to check if the
6377          * speed is different between the internal phy and external phy.
6378          * This case may be result of intermediate link speed change.
6379          */
6380         if (active_external_phy > INT_PHY) {
6381                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6382                 /*
6383                  * Link speed is taken from the XGXS. AN and FC result from
6384                  * the external phy.
6385                  */
6386                 vars->link_status |= phy_vars[active_external_phy].link_status;
6387
6388                 /*
6389                  * if active_external_phy is first PHY and link is up - disable
6390                  * disable TX on second external PHY
6391                  */
6392                 if (active_external_phy == EXT_PHY1) {
6393                         if (params->phy[EXT_PHY2].phy_specific_func) {
6394                                 DP(NETIF_MSG_LINK, "Disabling TX on"
6395                                                    " EXT_PHY2\n");
6396                                 params->phy[EXT_PHY2].phy_specific_func(
6397                                         &params->phy[EXT_PHY2],
6398                                         params, DISABLE_TX);
6399                         }
6400                 }
6401
6402                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6403                 vars->duplex = phy_vars[active_external_phy].duplex;
6404                 if (params->phy[active_external_phy].supported &
6405                     SUPPORTED_FIBRE)
6406                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6407                 else
6408                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6409                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6410                            active_external_phy);
6411         }
6412
6413         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6414               phy_index++) {
6415                 if (params->phy[phy_index].flags &
6416                     FLAGS_REARM_LATCH_SIGNAL) {
6417                         bnx2x_rearm_latch_signal(bp, port,
6418                                                  phy_index ==
6419                                                  active_external_phy);
6420                         break;
6421                 }
6422         }
6423         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6424                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6425                    vars->link_status, ext_phy_line_speed);
6426         /*
6427          * Upon link speed change set the NIG into drain mode. Comes to
6428          * deals with possible FIFO glitch due to clk change when speed
6429          * is decreased without link down indicator
6430          */
6431
6432         if (vars->phy_link_up) {
6433                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6434                     (ext_phy_line_speed != vars->line_speed)) {
6435                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6436                                    " different than the external"
6437                                    " link speed %d\n", vars->line_speed,
6438                                    ext_phy_line_speed);
6439                         vars->phy_link_up = 0;
6440                 } else if (prev_line_speed != vars->line_speed) {
6441                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6442                                0);
6443                         msleep(1);
6444                 }
6445         }
6446
6447         /* anything 10 and over uses the bmac */
6448         link_10g_plus = (vars->line_speed >= SPEED_10000);
6449
6450         bnx2x_link_int_ack(params, vars, link_10g_plus);
6451
6452         /*
6453          * In case external phy link is up, and internal link is down
6454          * (not initialized yet probably after link initialization, it
6455          * needs to be initialized.
6456          * Note that after link down-up as result of cable plug, the xgxs
6457          * link would probably become up again without the need
6458          * initialize it
6459          */
6460         if (!(SINGLE_MEDIA_DIRECT(params))) {
6461                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6462                            " init_preceding = %d\n", ext_phy_link_up,
6463                            vars->phy_link_up,
6464                            params->phy[EXT_PHY1].flags &
6465                            FLAGS_INIT_XGXS_FIRST);
6466                 if (!(params->phy[EXT_PHY1].flags &
6467                       FLAGS_INIT_XGXS_FIRST)
6468                     && ext_phy_link_up && !vars->phy_link_up) {
6469                         vars->line_speed = ext_phy_line_speed;
6470                         if (vars->line_speed < SPEED_1000)
6471                                 vars->phy_flags |= PHY_SGMII_FLAG;
6472                         else
6473                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6474
6475                         if (params->phy[INT_PHY].config_init)
6476                                 params->phy[INT_PHY].config_init(
6477                                         &params->phy[INT_PHY], params,
6478                                                 vars);
6479                 }
6480         }
6481         /*
6482          * Link is up only if both local phy and external phy (in case of
6483          * non-direct board) are up and no fault detected on active PHY.
6484          */
6485         vars->link_up = (vars->phy_link_up &&
6486                          (ext_phy_link_up ||
6487                           SINGLE_MEDIA_DIRECT(params)) &&
6488                          (phy_vars[active_external_phy].fault_detected == 0));
6489
6490         if (vars->link_up)
6491                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6492         else
6493                 rc = bnx2x_update_link_down(params, vars);
6494
6495         return rc;
6496 }
6497
6498
6499 /*****************************************************************************/
6500 /*                          External Phy section                             */
6501 /*****************************************************************************/
6502 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6503 {
6504         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6505                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6506         msleep(1);
6507         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6508                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6509 }
6510
6511 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6512                                       u32 spirom_ver, u32 ver_addr)
6513 {
6514         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6515                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6516
6517         if (ver_addr)
6518                 REG_WR(bp, ver_addr, spirom_ver);
6519 }
6520
6521 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6522                                       struct bnx2x_phy *phy,
6523                                       u8 port)
6524 {
6525         u16 fw_ver1, fw_ver2;
6526
6527         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6528                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6529         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6530                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6531         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6532                                   phy->ver_addr);
6533 }
6534
6535 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6536                                        struct bnx2x_phy *phy,
6537                                        struct link_vars *vars)
6538 {
6539         u16 val;
6540         bnx2x_cl45_read(bp, phy,
6541                         MDIO_AN_DEVAD,
6542                         MDIO_AN_REG_STATUS, &val);
6543         bnx2x_cl45_read(bp, phy,
6544                         MDIO_AN_DEVAD,
6545                         MDIO_AN_REG_STATUS, &val);
6546         if (val & (1<<5))
6547                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6548         if ((val & (1<<0)) == 0)
6549                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6550 }
6551
6552 /******************************************************************/
6553 /*              common BCM8073/BCM8727 PHY SECTION                */
6554 /******************************************************************/
6555 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6556                                   struct link_params *params,
6557                                   struct link_vars *vars)
6558 {
6559         struct bnx2x *bp = params->bp;
6560         if (phy->req_line_speed == SPEED_10 ||
6561             phy->req_line_speed == SPEED_100) {
6562                 vars->flow_ctrl = phy->req_flow_ctrl;
6563                 return;
6564         }
6565
6566         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6567             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6568                 u16 pause_result;
6569                 u16 ld_pause;           /* local */
6570                 u16 lp_pause;           /* link partner */
6571                 bnx2x_cl45_read(bp, phy,
6572                                 MDIO_AN_DEVAD,
6573                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6574
6575                 bnx2x_cl45_read(bp, phy,
6576                                 MDIO_AN_DEVAD,
6577                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6578                 pause_result = (ld_pause &
6579                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6580                 pause_result |= (lp_pause &
6581                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6582
6583                 bnx2x_pause_resolve(vars, pause_result);
6584                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6585                            pause_result);
6586         }
6587 }
6588 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6589                                              struct bnx2x_phy *phy,
6590                                              u8 port)
6591 {
6592         u32 count = 0;
6593         u16 fw_ver1, fw_msgout;
6594         int rc = 0;
6595
6596         /* Boot port from external ROM  */
6597         /* EDC grst */
6598         bnx2x_cl45_write(bp, phy,
6599                          MDIO_PMA_DEVAD,
6600                          MDIO_PMA_REG_GEN_CTRL,
6601                          0x0001);
6602
6603         /* ucode reboot and rst */
6604         bnx2x_cl45_write(bp, phy,
6605                          MDIO_PMA_DEVAD,
6606                          MDIO_PMA_REG_GEN_CTRL,
6607                          0x008c);
6608
6609         bnx2x_cl45_write(bp, phy,
6610                          MDIO_PMA_DEVAD,
6611                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6612
6613         /* Reset internal microprocessor */
6614         bnx2x_cl45_write(bp, phy,
6615                          MDIO_PMA_DEVAD,
6616                          MDIO_PMA_REG_GEN_CTRL,
6617                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6618
6619         /* Release srst bit */
6620         bnx2x_cl45_write(bp, phy,
6621                          MDIO_PMA_DEVAD,
6622                          MDIO_PMA_REG_GEN_CTRL,
6623                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6624
6625         /* Delay 100ms per the PHY specifications */
6626         msleep(100);
6627
6628         /* 8073 sometimes taking longer to download */
6629         do {
6630                 count++;
6631                 if (count > 300) {
6632                         DP(NETIF_MSG_LINK,
6633                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6634                                  "Download failed. fw version = 0x%x\n",
6635                                  port, fw_ver1);
6636                         rc = -EINVAL;
6637                         break;
6638                 }
6639
6640                 bnx2x_cl45_read(bp, phy,
6641                                 MDIO_PMA_DEVAD,
6642                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6643                 bnx2x_cl45_read(bp, phy,
6644                                 MDIO_PMA_DEVAD,
6645                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6646
6647                 msleep(1);
6648         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6649                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6650                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6651
6652         /* Clear ser_boot_ctl bit */
6653         bnx2x_cl45_write(bp, phy,
6654                          MDIO_PMA_DEVAD,
6655                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6656         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6657
6658         DP(NETIF_MSG_LINK,
6659                  "bnx2x_8073_8727_external_rom_boot port %x:"
6660                  "Download complete. fw version = 0x%x\n",
6661                  port, fw_ver1);
6662
6663         return rc;
6664 }
6665
6666 /******************************************************************/
6667 /*                      BCM8073 PHY SECTION                       */
6668 /******************************************************************/
6669 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6670 {
6671         /* This is only required for 8073A1, version 102 only */
6672         u16 val;
6673
6674         /* Read 8073 HW revision*/
6675         bnx2x_cl45_read(bp, phy,
6676                         MDIO_PMA_DEVAD,
6677                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6678
6679         if (val != 1) {
6680                 /* No need to workaround in 8073 A1 */
6681                 return 0;
6682         }
6683
6684         bnx2x_cl45_read(bp, phy,
6685                         MDIO_PMA_DEVAD,
6686                         MDIO_PMA_REG_ROM_VER2, &val);
6687
6688         /* SNR should be applied only for version 0x102 */
6689         if (val != 0x102)
6690                 return 0;
6691
6692         return 1;
6693 }
6694
6695 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6696 {
6697         u16 val, cnt, cnt1 ;
6698
6699         bnx2x_cl45_read(bp, phy,
6700                         MDIO_PMA_DEVAD,
6701                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6702
6703         if (val > 0) {
6704                 /* No need to workaround in 8073 A1 */
6705                 return 0;
6706         }
6707         /* XAUI workaround in 8073 A0: */
6708
6709         /*
6710          * After loading the boot ROM and restarting Autoneg, poll
6711          * Dev1, Reg $C820:
6712          */
6713
6714         for (cnt = 0; cnt < 1000; cnt++) {
6715                 bnx2x_cl45_read(bp, phy,
6716                                 MDIO_PMA_DEVAD,
6717                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6718                                 &val);
6719                   /*
6720                    * If bit [14] = 0 or bit [13] = 0, continue on with
6721                    * system initialization (XAUI work-around not required, as
6722                    * these bits indicate 2.5G or 1G link up).
6723                    */
6724                 if (!(val & (1<<14)) || !(val & (1<<13))) {
6725                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6726                         return 0;
6727                 } else if (!(val & (1<<15))) {
6728                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
6729                         /*
6730                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6731                          * MSB (bit15) goes to 1 (indicating that the XAUI
6732                          * workaround has completed), then continue on with
6733                          * system initialization.
6734                          */
6735                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6736                                 bnx2x_cl45_read(bp, phy,
6737                                         MDIO_PMA_DEVAD,
6738                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
6739                                 if (val & (1<<15)) {
6740                                         DP(NETIF_MSG_LINK,
6741                                           "XAUI workaround has completed\n");
6742                                         return 0;
6743                                  }
6744                                  msleep(3);
6745                         }
6746                         break;
6747                 }
6748                 msleep(3);
6749         }
6750         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6751         return -EINVAL;
6752 }
6753
6754 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6755 {
6756         /* Force KR or KX */
6757         bnx2x_cl45_write(bp, phy,
6758                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6759         bnx2x_cl45_write(bp, phy,
6760                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6761         bnx2x_cl45_write(bp, phy,
6762                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6763         bnx2x_cl45_write(bp, phy,
6764                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6765 }
6766
6767 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6768                                       struct bnx2x_phy *phy,
6769                                       struct link_vars *vars)
6770 {
6771         u16 cl37_val;
6772         struct bnx2x *bp = params->bp;
6773         bnx2x_cl45_read(bp, phy,
6774                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6775
6776         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6777         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6778         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6779         if ((vars->ieee_fc &
6780             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6781             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6782                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6783         }
6784         if ((vars->ieee_fc &
6785             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6786             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6787                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6788         }
6789         if ((vars->ieee_fc &
6790             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6791             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6792                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6793         }
6794         DP(NETIF_MSG_LINK,
6795                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6796
6797         bnx2x_cl45_write(bp, phy,
6798                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6799         msleep(500);
6800 }
6801
6802 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6803                                   struct link_params *params,
6804                                   struct link_vars *vars)
6805 {
6806         struct bnx2x *bp = params->bp;
6807         u16 val = 0, tmp1;
6808         u8 gpio_port;
6809         DP(NETIF_MSG_LINK, "Init 8073\n");
6810
6811         if (CHIP_IS_E2(bp))
6812                 gpio_port = BP_PATH(bp);
6813         else
6814                 gpio_port = params->port;
6815         /* Restore normal power mode*/
6816         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6817                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6818
6819         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6820                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6821
6822         /* enable LASI */
6823         bnx2x_cl45_write(bp, phy,
6824                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6825         bnx2x_cl45_write(bp, phy,
6826                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6827
6828         bnx2x_8073_set_pause_cl37(params, phy, vars);
6829
6830         bnx2x_cl45_read(bp, phy,
6831                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6832
6833         bnx2x_cl45_read(bp, phy,
6834                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6835
6836         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6837
6838         /* Swap polarity if required - Must be done only in non-1G mode */
6839         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6840                 /* Configure the 8073 to swap _P and _N of the KR lines */
6841                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6842                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6843                 bnx2x_cl45_read(bp, phy,
6844                                 MDIO_PMA_DEVAD,
6845                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6846                 bnx2x_cl45_write(bp, phy,
6847                                  MDIO_PMA_DEVAD,
6848                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6849                                  (val | (3<<9)));
6850         }
6851
6852
6853         /* Enable CL37 BAM */
6854         if (REG_RD(bp, params->shmem_base +
6855                          offsetof(struct shmem_region, dev_info.
6856                                   port_hw_config[params->port].default_cfg)) &
6857             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6858
6859                 bnx2x_cl45_read(bp, phy,
6860                                 MDIO_AN_DEVAD,
6861                                 MDIO_AN_REG_8073_BAM, &val);
6862                 bnx2x_cl45_write(bp, phy,
6863                                  MDIO_AN_DEVAD,
6864                                  MDIO_AN_REG_8073_BAM, val | 1);
6865                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6866         }
6867         if (params->loopback_mode == LOOPBACK_EXT) {
6868                 bnx2x_807x_force_10G(bp, phy);
6869                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6870                 return 0;
6871         } else {
6872                 bnx2x_cl45_write(bp, phy,
6873                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6874         }
6875         if (phy->req_line_speed != SPEED_AUTO_NEG) {
6876                 if (phy->req_line_speed == SPEED_10000) {
6877                         val = (1<<7);
6878                 } else if (phy->req_line_speed ==  SPEED_2500) {
6879                         val = (1<<5);
6880                         /*
6881                          * Note that 2.5G works only when used with 1G
6882                          * advertisement
6883                          */
6884                 } else
6885                         val = (1<<5);
6886         } else {
6887                 val = 0;
6888                 if (phy->speed_cap_mask &
6889                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6890                         val |= (1<<7);
6891
6892                 /* Note that 2.5G works only when used with 1G advertisement */
6893                 if (phy->speed_cap_mask &
6894                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6895                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6896                         val |= (1<<5);
6897                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6898         }
6899
6900         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6901         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6902
6903         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6904              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6905             (phy->req_line_speed == SPEED_2500)) {
6906                 u16 phy_ver;
6907                 /* Allow 2.5G for A1 and above */
6908                 bnx2x_cl45_read(bp, phy,
6909                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6910                                 &phy_ver);
6911                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6912                 if (phy_ver > 0)
6913                         tmp1 |= 1;
6914                 else
6915                         tmp1 &= 0xfffe;
6916         } else {
6917                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6918                 tmp1 &= 0xfffe;
6919         }
6920
6921         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6922         /* Add support for CL37 (passive mode) II */
6923
6924         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6925         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6926                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6927                                   0x20 : 0x40)));
6928
6929         /* Add support for CL37 (passive mode) III */
6930         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6931
6932         /*
6933          * The SNR will improve about 2db by changing BW and FEE main
6934          * tap. Rest commands are executed after link is up
6935          * Change FFE main cursor to 5 in EDC register
6936          */
6937         if (bnx2x_8073_is_snr_needed(bp, phy))
6938                 bnx2x_cl45_write(bp, phy,
6939                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6940                                  0xFB0C);
6941
6942         /* Enable FEC (Forware Error Correction) Request in the AN */
6943         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6944         tmp1 |= (1<<15);
6945         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6946
6947         bnx2x_ext_phy_set_pause(params, phy, vars);
6948
6949         /* Restart autoneg */
6950         msleep(500);
6951         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6952         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
6953                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
6954         return 0;
6955 }
6956
6957 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
6958                                  struct link_params *params,
6959                                  struct link_vars *vars)
6960 {
6961         struct bnx2x *bp = params->bp;
6962         u8 link_up = 0;
6963         u16 val1, val2;
6964         u16 link_status = 0;
6965         u16 an1000_status = 0;
6966
6967         bnx2x_cl45_read(bp, phy,
6968                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6969
6970         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
6971
6972         /* clear the interrupt LASI status register */
6973         bnx2x_cl45_read(bp, phy,
6974                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6975         bnx2x_cl45_read(bp, phy,
6976                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
6977         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
6978         /* Clear MSG-OUT */
6979         bnx2x_cl45_read(bp, phy,
6980                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
6981
6982         /* Check the LASI */
6983         bnx2x_cl45_read(bp, phy,
6984                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
6985
6986         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
6987
6988         /* Check the link status */
6989         bnx2x_cl45_read(bp, phy,
6990                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
6991         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
6992
6993         bnx2x_cl45_read(bp, phy,
6994                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6995         bnx2x_cl45_read(bp, phy,
6996                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6997         link_up = ((val1 & 4) == 4);
6998         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
6999
7000         if (link_up &&
7001              ((phy->req_line_speed != SPEED_10000))) {
7002                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7003                         return 0;
7004         }
7005         bnx2x_cl45_read(bp, phy,
7006                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7007         bnx2x_cl45_read(bp, phy,
7008                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7009
7010         /* Check the link status on 1.1.2 */
7011         bnx2x_cl45_read(bp, phy,
7012                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7013         bnx2x_cl45_read(bp, phy,
7014                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7015         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7016                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7017
7018         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7019         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7020                 /*
7021                  * The SNR will improve about 2dbby changing the BW and FEE main
7022                  * tap. The 1st write to change FFE main tap is set before
7023                  * restart AN. Change PLL Bandwidth in EDC register
7024                  */
7025                 bnx2x_cl45_write(bp, phy,
7026                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7027                                  0x26BC);
7028
7029                 /* Change CDR Bandwidth in EDC register */
7030                 bnx2x_cl45_write(bp, phy,
7031                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7032                                  0x0333);
7033         }
7034         bnx2x_cl45_read(bp, phy,
7035                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7036                         &link_status);
7037
7038         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7039         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7040                 link_up = 1;
7041                 vars->line_speed = SPEED_10000;
7042                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7043                            params->port);
7044         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7045                 link_up = 1;
7046                 vars->line_speed = SPEED_2500;
7047                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7048                            params->port);
7049         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7050                 link_up = 1;
7051                 vars->line_speed = SPEED_1000;
7052                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7053                            params->port);
7054         } else {
7055                 link_up = 0;
7056                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7057                            params->port);
7058         }
7059
7060         if (link_up) {
7061                 /* Swap polarity if required */
7062                 if (params->lane_config &
7063                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7064                         /* Configure the 8073 to swap P and N of the KR lines */
7065                         bnx2x_cl45_read(bp, phy,
7066                                         MDIO_XS_DEVAD,
7067                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7068                         /*
7069                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7070                          * when it`s in 10G mode.
7071                          */
7072                         if (vars->line_speed == SPEED_1000) {
7073                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7074                                               "the 8073\n");
7075                                 val1 |= (1<<3);
7076                         } else
7077                                 val1 &= ~(1<<3);
7078
7079                         bnx2x_cl45_write(bp, phy,
7080                                          MDIO_XS_DEVAD,
7081                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7082                                          val1);
7083                 }
7084                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7085                 bnx2x_8073_resolve_fc(phy, params, vars);
7086                 vars->duplex = DUPLEX_FULL;
7087         }
7088         return link_up;
7089 }
7090
7091 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7092                                   struct link_params *params)
7093 {
7094         struct bnx2x *bp = params->bp;
7095         u8 gpio_port;
7096         if (CHIP_IS_E2(bp))
7097                 gpio_port = BP_PATH(bp);
7098         else
7099                 gpio_port = params->port;
7100         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7101            gpio_port);
7102         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7103                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7104                        gpio_port);
7105 }
7106
7107 /******************************************************************/
7108 /*                      BCM8705 PHY SECTION                       */
7109 /******************************************************************/
7110 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7111                                   struct link_params *params,
7112                                   struct link_vars *vars)
7113 {
7114         struct bnx2x *bp = params->bp;
7115         DP(NETIF_MSG_LINK, "init 8705\n");
7116         /* Restore normal power mode*/
7117         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7118                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7119         /* HW reset */
7120         bnx2x_ext_phy_hw_reset(bp, params->port);
7121         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7122         bnx2x_wait_reset_complete(bp, phy, params);
7123
7124         bnx2x_cl45_write(bp, phy,
7125                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7126         bnx2x_cl45_write(bp, phy,
7127                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7128         bnx2x_cl45_write(bp, phy,
7129                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7130         bnx2x_cl45_write(bp, phy,
7131                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7132         /* BCM8705 doesn't have microcode, hence the 0 */
7133         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7134         return 0;
7135 }
7136
7137 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7138                                  struct link_params *params,
7139                                  struct link_vars *vars)
7140 {
7141         u8 link_up = 0;
7142         u16 val1, rx_sd;
7143         struct bnx2x *bp = params->bp;
7144         DP(NETIF_MSG_LINK, "read status 8705\n");
7145         bnx2x_cl45_read(bp, phy,
7146                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7147         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7148
7149         bnx2x_cl45_read(bp, phy,
7150                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7151         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7152
7153         bnx2x_cl45_read(bp, phy,
7154                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7155
7156         bnx2x_cl45_read(bp, phy,
7157                       MDIO_PMA_DEVAD, 0xc809, &val1);
7158         bnx2x_cl45_read(bp, phy,
7159                       MDIO_PMA_DEVAD, 0xc809, &val1);
7160
7161         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7162         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7163         if (link_up) {
7164                 vars->line_speed = SPEED_10000;
7165                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7166         }
7167         return link_up;
7168 }
7169
7170 /******************************************************************/
7171 /*                      SFP+ module Section                       */
7172 /******************************************************************/
7173 static u8 bnx2x_get_gpio_port(struct link_params *params)
7174 {
7175         u8 gpio_port;
7176         u32 swap_val, swap_override;
7177         struct bnx2x *bp = params->bp;
7178         if (CHIP_IS_E2(bp))
7179                 gpio_port = BP_PATH(bp);
7180         else
7181                 gpio_port = params->port;
7182         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7183         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7184         return gpio_port ^ (swap_val && swap_override);
7185 }
7186
7187 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7188                                            struct bnx2x_phy *phy,
7189                                            u8 tx_en)
7190 {
7191         u16 val;
7192         u8 port = params->port;
7193         struct bnx2x *bp = params->bp;
7194         u32 tx_en_mode;
7195
7196         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7197         tx_en_mode = REG_RD(bp, params->shmem_base +
7198                             offsetof(struct shmem_region,
7199                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7200                 PORT_HW_CFG_TX_LASER_MASK;
7201         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7202                            "mode = %x\n", tx_en, port, tx_en_mode);
7203         switch (tx_en_mode) {
7204         case PORT_HW_CFG_TX_LASER_MDIO:
7205
7206                 bnx2x_cl45_read(bp, phy,
7207                                 MDIO_PMA_DEVAD,
7208                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7209                                 &val);
7210
7211                 if (tx_en)
7212                         val &= ~(1<<15);
7213                 else
7214                         val |= (1<<15);
7215
7216                 bnx2x_cl45_write(bp, phy,
7217                                  MDIO_PMA_DEVAD,
7218                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7219                                  val);
7220         break;
7221         case PORT_HW_CFG_TX_LASER_GPIO0:
7222         case PORT_HW_CFG_TX_LASER_GPIO1:
7223         case PORT_HW_CFG_TX_LASER_GPIO2:
7224         case PORT_HW_CFG_TX_LASER_GPIO3:
7225         {
7226                 u16 gpio_pin;
7227                 u8 gpio_port, gpio_mode;
7228                 if (tx_en)
7229                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7230                 else
7231                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7232
7233                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7234                 gpio_port = bnx2x_get_gpio_port(params);
7235                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7236                 break;
7237         }
7238         default:
7239                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7240                 break;
7241         }
7242 }
7243
7244 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7245                                       struct bnx2x_phy *phy,
7246                                       u8 tx_en)
7247 {
7248         struct bnx2x *bp = params->bp;
7249         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7250         if (CHIP_IS_E3(bp))
7251                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7252         else
7253                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7254 }
7255
7256 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7257                                              struct link_params *params,
7258                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7259 {
7260         struct bnx2x *bp = params->bp;
7261         u16 val = 0;
7262         u16 i;
7263         if (byte_cnt > 16) {
7264                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7265                             " is limited to 0xf\n");
7266                 return -EINVAL;
7267         }
7268         /* Set the read command byte count */
7269         bnx2x_cl45_write(bp, phy,
7270                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7271                          (byte_cnt | 0xa000));
7272
7273         /* Set the read command address */
7274         bnx2x_cl45_write(bp, phy,
7275                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7276                          addr);
7277
7278         /* Activate read command */
7279         bnx2x_cl45_write(bp, phy,
7280                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7281                          0x2c0f);
7282
7283         /* Wait up to 500us for command complete status */
7284         for (i = 0; i < 100; i++) {
7285                 bnx2x_cl45_read(bp, phy,
7286                                 MDIO_PMA_DEVAD,
7287                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7288                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7289                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7290                         break;
7291                 udelay(5);
7292         }
7293
7294         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7295                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7296                 DP(NETIF_MSG_LINK,
7297                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7298                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7299                 return -EINVAL;
7300         }
7301
7302         /* Read the buffer */
7303         for (i = 0; i < byte_cnt; i++) {
7304                 bnx2x_cl45_read(bp, phy,
7305                                 MDIO_PMA_DEVAD,
7306                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7307                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7308         }
7309
7310         for (i = 0; i < 100; i++) {
7311                 bnx2x_cl45_read(bp, phy,
7312                                 MDIO_PMA_DEVAD,
7313                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7314                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7315                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7316                         return 0;
7317                 msleep(1);
7318         }
7319         return -EINVAL;
7320 }
7321
7322 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7323                                                  struct link_params *params,
7324                                                  u16 addr, u8 byte_cnt,
7325                                                  u8 *o_buf)
7326 {
7327         int rc = 0;
7328         u8 i, j = 0, cnt = 0;
7329         u32 data_array[4];
7330         u16 addr32;
7331         struct bnx2x *bp = params->bp;
7332         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7333                                         " addr %d, cnt %d\n",
7334                                         addr, byte_cnt);*/
7335         if (byte_cnt > 16) {
7336                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7337                             " is limited to 16 bytes\n");
7338                 return -EINVAL;
7339         }
7340
7341         /* 4 byte aligned address */
7342         addr32 = addr & (~0x3);
7343         do {
7344                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7345                                     data_array);
7346         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7347
7348         if (rc == 0) {
7349                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7350                         o_buf[j] = *((u8 *)data_array + i);
7351                         j++;
7352                 }
7353         }
7354
7355         return rc;
7356 }
7357
7358 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7359                                              struct link_params *params,
7360                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7361 {
7362         struct bnx2x *bp = params->bp;
7363         u16 val, i;
7364
7365         if (byte_cnt > 16) {
7366                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7367                             " is limited to 0xf\n");
7368                 return -EINVAL;
7369         }
7370
7371         /* Need to read from 1.8000 to clear it */
7372         bnx2x_cl45_read(bp, phy,
7373                         MDIO_PMA_DEVAD,
7374                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7375                         &val);
7376
7377         /* Set the read command byte count */
7378         bnx2x_cl45_write(bp, phy,
7379                          MDIO_PMA_DEVAD,
7380                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7381                          ((byte_cnt < 2) ? 2 : byte_cnt));
7382
7383         /* Set the read command address */
7384         bnx2x_cl45_write(bp, phy,
7385                          MDIO_PMA_DEVAD,
7386                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7387                          addr);
7388         /* Set the destination address */
7389         bnx2x_cl45_write(bp, phy,
7390                          MDIO_PMA_DEVAD,
7391                          0x8004,
7392                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7393
7394         /* Activate read command */
7395         bnx2x_cl45_write(bp, phy,
7396                          MDIO_PMA_DEVAD,
7397                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7398                          0x8002);
7399         /*
7400          * Wait appropriate time for two-wire command to finish before
7401          * polling the status register
7402          */
7403         msleep(1);
7404
7405         /* Wait up to 500us for command complete status */
7406         for (i = 0; i < 100; i++) {
7407                 bnx2x_cl45_read(bp, phy,
7408                                 MDIO_PMA_DEVAD,
7409                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7410                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7411                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7412                         break;
7413                 udelay(5);
7414         }
7415
7416         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7417                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7418                 DP(NETIF_MSG_LINK,
7419                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7420                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7421                 return -EFAULT;
7422         }
7423
7424         /* Read the buffer */
7425         for (i = 0; i < byte_cnt; i++) {
7426                 bnx2x_cl45_read(bp, phy,
7427                                 MDIO_PMA_DEVAD,
7428                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7429                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7430         }
7431
7432         for (i = 0; i < 100; i++) {
7433                 bnx2x_cl45_read(bp, phy,
7434                                 MDIO_PMA_DEVAD,
7435                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7436                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7437                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7438                         return 0;
7439                 msleep(1);
7440         }
7441
7442         return -EINVAL;
7443 }
7444
7445 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7446                                  struct link_params *params, u16 addr,
7447                                  u8 byte_cnt, u8 *o_buf)
7448 {
7449         int rc = -EINVAL;
7450         switch (phy->type) {
7451         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7452                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7453                                                        byte_cnt, o_buf);
7454         break;
7455         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7456         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7457                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7458                                                        byte_cnt, o_buf);
7459         break;
7460         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7461                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7462                                                            byte_cnt, o_buf);
7463         break;
7464         }
7465         return rc;
7466 }
7467
7468 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7469                               struct link_params *params,
7470                               u16 *edc_mode)
7471 {
7472         struct bnx2x *bp = params->bp;
7473         u32 sync_offset = 0, phy_idx, media_types;
7474         u8 val, check_limiting_mode = 0;
7475         *edc_mode = EDC_MODE_LIMITING;
7476
7477         phy->media_type = ETH_PHY_UNSPECIFIED;
7478         /* First check for copper cable */
7479         if (bnx2x_read_sfp_module_eeprom(phy,
7480                                          params,
7481                                          SFP_EEPROM_CON_TYPE_ADDR,
7482                                          1,
7483                                          &val) != 0) {
7484                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7485                 return -EINVAL;
7486         }
7487
7488         switch (val) {
7489         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7490         {
7491                 u8 copper_module_type;
7492                 phy->media_type = ETH_PHY_DA_TWINAX;
7493                 /*
7494                  * Check if its active cable (includes SFP+ module)
7495                  * of passive cable
7496                  */
7497                 if (bnx2x_read_sfp_module_eeprom(phy,
7498                                                params,
7499                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7500                                                1,
7501                                                &copper_module_type) != 0) {
7502                         DP(NETIF_MSG_LINK,
7503                                 "Failed to read copper-cable-type"
7504                                 " from SFP+ EEPROM\n");
7505                         return -EINVAL;
7506                 }
7507
7508                 if (copper_module_type &
7509                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7510                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7511                         check_limiting_mode = 1;
7512                 } else if (copper_module_type &
7513                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7514                                 DP(NETIF_MSG_LINK, "Passive Copper"
7515                                             " cable detected\n");
7516                                 *edc_mode =
7517                                       EDC_MODE_PASSIVE_DAC;
7518                 } else {
7519                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7520                                      "type 0x%x !!!\n", copper_module_type);
7521                         return -EINVAL;
7522                 }
7523                 break;
7524         }
7525         case SFP_EEPROM_CON_TYPE_VAL_LC:
7526                 phy->media_type = ETH_PHY_SFP_FIBER;
7527                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7528                 check_limiting_mode = 1;
7529                 break;
7530         default:
7531                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7532                          val);
7533                 return -EINVAL;
7534         }
7535         sync_offset = params->shmem_base +
7536                 offsetof(struct shmem_region,
7537                          dev_info.port_hw_config[params->port].media_type);
7538         media_types = REG_RD(bp, sync_offset);
7539         /* Update media type for non-PMF sync */
7540         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7541                 if (&(params->phy[phy_idx]) == phy) {
7542                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7543                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7544                         media_types |= ((phy->media_type &
7545                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7546                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7547                         break;
7548                 }
7549         }
7550         REG_WR(bp, sync_offset, media_types);
7551         if (check_limiting_mode) {
7552                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7553                 if (bnx2x_read_sfp_module_eeprom(phy,
7554                                                  params,
7555                                                  SFP_EEPROM_OPTIONS_ADDR,
7556                                                  SFP_EEPROM_OPTIONS_SIZE,
7557                                                  options) != 0) {
7558                         DP(NETIF_MSG_LINK, "Failed to read Option"
7559                                 " field from module EEPROM\n");
7560                         return -EINVAL;
7561                 }
7562                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7563                         *edc_mode = EDC_MODE_LINEAR;
7564                 else
7565                         *edc_mode = EDC_MODE_LIMITING;
7566         }
7567         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7568         return 0;
7569 }
7570 /*
7571  * This function read the relevant field from the module (SFP+), and verify it
7572  * is compliant with this board
7573  */
7574 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7575                                    struct link_params *params)
7576 {
7577         struct bnx2x *bp = params->bp;
7578         u32 val, cmd;
7579         u32 fw_resp, fw_cmd_param;
7580         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7581         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7582         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7583         val = REG_RD(bp, params->shmem_base +
7584                          offsetof(struct shmem_region, dev_info.
7585                                   port_feature_config[params->port].config));
7586         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7587             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7588                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7589                 return 0;
7590         }
7591
7592         if (params->feature_config_flags &
7593             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7594                 /* Use specific phy request */
7595                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7596         } else if (params->feature_config_flags &
7597                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7598                 /* Use first phy request only in case of non-dual media*/
7599                 if (DUAL_MEDIA(params)) {
7600                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7601                            "verification\n");
7602                         return -EINVAL;
7603                 }
7604                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7605         } else {
7606                 /* No support in OPT MDL detection */
7607                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7608                           "verification\n");
7609                 return -EINVAL;
7610         }
7611
7612         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7613         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7614         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7615                 DP(NETIF_MSG_LINK, "Approved module\n");
7616                 return 0;
7617         }
7618
7619         /* format the warning message */
7620         if (bnx2x_read_sfp_module_eeprom(phy,
7621                                          params,
7622                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7623                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7624                                          (u8 *)vendor_name))
7625                 vendor_name[0] = '\0';
7626         else
7627                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7628         if (bnx2x_read_sfp_module_eeprom(phy,
7629                                          params,
7630                                          SFP_EEPROM_PART_NO_ADDR,
7631                                          SFP_EEPROM_PART_NO_SIZE,
7632                                          (u8 *)vendor_pn))
7633                 vendor_pn[0] = '\0';
7634         else
7635                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7636
7637         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7638                               " Port %d from %s part number %s\n",
7639                          params->port, vendor_name, vendor_pn);
7640         phy->flags |= FLAGS_SFP_NOT_APPROVED;
7641         return -EINVAL;
7642 }
7643
7644 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7645                                                  struct link_params *params)
7646
7647 {
7648         u8 val;
7649         struct bnx2x *bp = params->bp;
7650         u16 timeout;
7651         /*
7652          * Initialization time after hot-plug may take up to 300ms for
7653          * some phys type ( e.g. JDSU )
7654          */
7655
7656         for (timeout = 0; timeout < 60; timeout++) {
7657                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7658                     == 0) {
7659                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
7660                                      "took %d ms\n", timeout * 5);
7661                         return 0;
7662                 }
7663                 msleep(5);
7664         }
7665         return -EINVAL;
7666 }
7667
7668 static void bnx2x_8727_power_module(struct bnx2x *bp,
7669                                     struct bnx2x_phy *phy,
7670                                     u8 is_power_up) {
7671         /* Make sure GPIOs are not using for LED mode */
7672         u16 val;
7673         /*
7674          * In the GPIO register, bit 4 is use to determine if the GPIOs are
7675          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7676          * output
7677          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7678          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7679          * where the 1st bit is the over-current(only input), and 2nd bit is
7680          * for power( only output )
7681          *
7682          * In case of NOC feature is disabled and power is up, set GPIO control
7683          *  as input to enable listening of over-current indication
7684          */
7685         if (phy->flags & FLAGS_NOC)
7686                 return;
7687         if (is_power_up)
7688                 val = (1<<4);
7689         else
7690                 /*
7691                  * Set GPIO control to OUTPUT, and set the power bit
7692                  * to according to the is_power_up
7693                  */
7694                 val = (1<<1);
7695
7696         bnx2x_cl45_write(bp, phy,
7697                          MDIO_PMA_DEVAD,
7698                          MDIO_PMA_REG_8727_GPIO_CTRL,
7699                          val);
7700 }
7701
7702 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7703                                         struct bnx2x_phy *phy,
7704                                         u16 edc_mode)
7705 {
7706         u16 cur_limiting_mode;
7707
7708         bnx2x_cl45_read(bp, phy,
7709                         MDIO_PMA_DEVAD,
7710                         MDIO_PMA_REG_ROM_VER2,
7711                         &cur_limiting_mode);
7712         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7713                  cur_limiting_mode);
7714
7715         if (edc_mode == EDC_MODE_LIMITING) {
7716                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7717                 bnx2x_cl45_write(bp, phy,
7718                                  MDIO_PMA_DEVAD,
7719                                  MDIO_PMA_REG_ROM_VER2,
7720                                  EDC_MODE_LIMITING);
7721         } else { /* LRM mode ( default )*/
7722
7723                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7724
7725                 /*
7726                  * Changing to LRM mode takes quite few seconds. So do it only
7727                  * if current mode is limiting (default is LRM)
7728                  */
7729                 if (cur_limiting_mode != EDC_MODE_LIMITING)
7730                         return 0;
7731
7732                 bnx2x_cl45_write(bp, phy,
7733                                  MDIO_PMA_DEVAD,
7734                                  MDIO_PMA_REG_LRM_MODE,
7735                                  0);
7736                 bnx2x_cl45_write(bp, phy,
7737                                  MDIO_PMA_DEVAD,
7738                                  MDIO_PMA_REG_ROM_VER2,
7739                                  0x128);
7740                 bnx2x_cl45_write(bp, phy,
7741                                  MDIO_PMA_DEVAD,
7742                                  MDIO_PMA_REG_MISC_CTRL0,
7743                                  0x4008);
7744                 bnx2x_cl45_write(bp, phy,
7745                                  MDIO_PMA_DEVAD,
7746                                  MDIO_PMA_REG_LRM_MODE,
7747                                  0xaaaa);
7748         }
7749         return 0;
7750 }
7751
7752 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7753                                         struct bnx2x_phy *phy,
7754                                         u16 edc_mode)
7755 {
7756         u16 phy_identifier;
7757         u16 rom_ver2_val;
7758         bnx2x_cl45_read(bp, phy,
7759                         MDIO_PMA_DEVAD,
7760                         MDIO_PMA_REG_PHY_IDENTIFIER,
7761                         &phy_identifier);
7762
7763         bnx2x_cl45_write(bp, phy,
7764                          MDIO_PMA_DEVAD,
7765                          MDIO_PMA_REG_PHY_IDENTIFIER,
7766                          (phy_identifier & ~(1<<9)));
7767
7768         bnx2x_cl45_read(bp, phy,
7769                         MDIO_PMA_DEVAD,
7770                         MDIO_PMA_REG_ROM_VER2,
7771                         &rom_ver2_val);
7772         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7773         bnx2x_cl45_write(bp, phy,
7774                          MDIO_PMA_DEVAD,
7775                          MDIO_PMA_REG_ROM_VER2,
7776                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7777
7778         bnx2x_cl45_write(bp, phy,
7779                          MDIO_PMA_DEVAD,
7780                          MDIO_PMA_REG_PHY_IDENTIFIER,
7781                          (phy_identifier | (1<<9)));
7782
7783         return 0;
7784 }
7785
7786 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7787                                      struct link_params *params,
7788                                      u32 action)
7789 {
7790         struct bnx2x *bp = params->bp;
7791
7792         switch (action) {
7793         case DISABLE_TX:
7794                 bnx2x_sfp_set_transmitter(params, phy, 0);
7795                 break;
7796         case ENABLE_TX:
7797                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7798                         bnx2x_sfp_set_transmitter(params, phy, 1);
7799                 break;
7800         default:
7801                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7802                    action);
7803                 return;
7804         }
7805 }
7806
7807 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7808                                            u8 gpio_mode)
7809 {
7810         struct bnx2x *bp = params->bp;
7811
7812         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7813                             offsetof(struct shmem_region,
7814                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
7815                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7816         switch (fault_led_gpio) {
7817         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7818                 return;
7819         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7820         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7821         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7822         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7823         {
7824                 u8 gpio_port = bnx2x_get_gpio_port(params);
7825                 u16 gpio_pin = fault_led_gpio -
7826                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7827                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7828                                    "pin %x port %x mode %x\n",
7829                                gpio_pin, gpio_port, gpio_mode);
7830                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7831         }
7832         break;
7833         default:
7834                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7835                                fault_led_gpio);
7836         }
7837 }
7838
7839 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7840                                           u8 gpio_mode)
7841 {
7842         u32 pin_cfg;
7843         u8 port = params->port;
7844         struct bnx2x *bp = params->bp;
7845         pin_cfg = (REG_RD(bp, params->shmem_base +
7846                          offsetof(struct shmem_region,
7847                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7848                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7849                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7850         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7851                        gpio_mode, pin_cfg);
7852         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7853 }
7854
7855 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7856                                            u8 gpio_mode)
7857 {
7858         struct bnx2x *bp = params->bp;
7859         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7860         if (CHIP_IS_E3(bp)) {
7861                 /*
7862                  * Low ==> if SFP+ module is supported otherwise
7863                  * High ==> if SFP+ module is not on the approved vendor list
7864                  */
7865                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7866         } else
7867                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7868 }
7869
7870 static void bnx2x_warpcore_power_module(struct link_params *params,
7871                                         struct bnx2x_phy *phy,
7872                                         u8 power)
7873 {
7874         u32 pin_cfg;
7875         struct bnx2x *bp = params->bp;
7876
7877         pin_cfg = (REG_RD(bp, params->shmem_base +
7878                           offsetof(struct shmem_region,
7879                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7880                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7881                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7882         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7883                        power, pin_cfg);
7884         /*
7885          * Low ==> corresponding SFP+ module is powered
7886          * high ==> the SFP+ module is powered down
7887          */
7888         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7889 }
7890
7891 static void bnx2x_power_sfp_module(struct link_params *params,
7892                                    struct bnx2x_phy *phy,
7893                                    u8 power)
7894 {
7895         struct bnx2x *bp = params->bp;
7896         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7897
7898         switch (phy->type) {
7899         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7900         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7901                 bnx2x_8727_power_module(params->bp, phy, power);
7902                 break;
7903         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7904                 bnx2x_warpcore_power_module(params, phy, power);
7905                 break;
7906         default:
7907                 break;
7908         }
7909 }
7910 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
7911                                              struct bnx2x_phy *phy,
7912                                              u16 edc_mode)
7913 {
7914         u16 val = 0;
7915         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7916         struct bnx2x *bp = params->bp;
7917
7918         u8 lane = bnx2x_get_warpcore_lane(phy, params);
7919         /* This is a global register which controls all lanes */
7920         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7921                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7922         val &= ~(0xf << (lane << 2));
7923
7924         switch (edc_mode) {
7925         case EDC_MODE_LINEAR:
7926         case EDC_MODE_LIMITING:
7927                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7928                 break;
7929         case EDC_MODE_PASSIVE_DAC:
7930                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
7931                 break;
7932         default:
7933                 break;
7934         }
7935
7936         val |= (mode << (lane << 2));
7937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
7938                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
7939         /* A must read */
7940         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7941                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7942
7943
7944 }
7945
7946 static void bnx2x_set_limiting_mode(struct link_params *params,
7947                                     struct bnx2x_phy *phy,
7948                                     u16 edc_mode)
7949 {
7950         switch (phy->type) {
7951         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7952                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
7953                 break;
7954         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7955         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7956                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
7957                 break;
7958         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7959                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
7960                 break;
7961         }
7962 }
7963
7964 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
7965                                struct link_params *params)
7966 {
7967         struct bnx2x *bp = params->bp;
7968         u16 edc_mode;
7969         int rc = 0;
7970
7971         u32 val = REG_RD(bp, params->shmem_base +
7972                              offsetof(struct shmem_region, dev_info.
7973                                      port_feature_config[params->port].config));
7974
7975         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
7976                  params->port);
7977         /* Power up module */
7978         bnx2x_power_sfp_module(params, phy, 1);
7979         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
7980                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
7981                 return -EINVAL;
7982         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
7983                 /* check SFP+ module compatibility */
7984                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
7985                 rc = -EINVAL;
7986                 /* Turn on fault module-detected led */
7987                 bnx2x_set_sfp_module_fault_led(params,
7988                                                MISC_REGISTERS_GPIO_HIGH);
7989
7990                 /* Check if need to power down the SFP+ module */
7991                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7992                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
7993                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
7994                         bnx2x_power_sfp_module(params, phy, 0);
7995                         return rc;
7996                 }
7997         } else {
7998                 /* Turn off fault module-detected led */
7999                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8000         }
8001
8002         /*
8003          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8004          * is done automatically
8005          */
8006         bnx2x_set_limiting_mode(params, phy, edc_mode);
8007
8008         /*
8009          * Enable transmit for this module if the module is approved, or
8010          * if unapproved modules should also enable the Tx laser
8011          */
8012         if (rc == 0 ||
8013             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8014             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8015                 bnx2x_sfp_set_transmitter(params, phy, 1);
8016         else
8017                 bnx2x_sfp_set_transmitter(params, phy, 0);
8018
8019         return rc;
8020 }
8021
8022 void bnx2x_handle_module_detect_int(struct link_params *params)
8023 {
8024         struct bnx2x *bp = params->bp;
8025         struct bnx2x_phy *phy;
8026         u32 gpio_val;
8027         u8 gpio_num, gpio_port;
8028         if (CHIP_IS_E3(bp))
8029                 phy = &params->phy[INT_PHY];
8030         else
8031                 phy = &params->phy[EXT_PHY1];
8032
8033         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8034                                       params->port, &gpio_num, &gpio_port) ==
8035             -EINVAL) {
8036                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8037                 return;
8038         }
8039
8040         /* Set valid module led off */
8041         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8042
8043         /* Get current gpio val reflecting module plugged in / out*/
8044         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8045
8046         /* Call the handling function in case module is detected */
8047         if (gpio_val == 0) {
8048                 bnx2x_power_sfp_module(params, phy, 1);
8049                 bnx2x_set_gpio_int(bp, gpio_num,
8050                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8051                                    gpio_port);
8052                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8053                         bnx2x_sfp_module_detection(phy, params);
8054                 else
8055                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8056         } else {
8057                 u32 val = REG_RD(bp, params->shmem_base +
8058                                  offsetof(struct shmem_region, dev_info.
8059                                           port_feature_config[params->port].
8060                                           config));
8061
8062                 bnx2x_set_gpio_int(bp, gpio_num,
8063                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8064                                    gpio_port);
8065                 /*
8066                  * Module was plugged out.
8067                  * Disable transmit for this module
8068                  */
8069                 phy->media_type = ETH_PHY_NOT_PRESENT;
8070                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8071                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8072                         bnx2x_sfp_set_transmitter(params, phy, 0);
8073         }
8074 }
8075
8076 /******************************************************************/
8077 /*              Used by 8706 and 8727                             */
8078 /******************************************************************/
8079 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8080                                  struct bnx2x_phy *phy,
8081                                  u16 alarm_status_offset,
8082                                  u16 alarm_ctrl_offset)
8083 {
8084         u16 alarm_status, val;
8085         bnx2x_cl45_read(bp, phy,
8086                         MDIO_PMA_DEVAD, alarm_status_offset,
8087                         &alarm_status);
8088         bnx2x_cl45_read(bp, phy,
8089                         MDIO_PMA_DEVAD, alarm_status_offset,
8090                         &alarm_status);
8091         /* Mask or enable the fault event. */
8092         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8093         if (alarm_status & (1<<0))
8094                 val &= ~(1<<0);
8095         else
8096                 val |= (1<<0);
8097         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8098 }
8099 /******************************************************************/
8100 /*              common BCM8706/BCM8726 PHY SECTION                */
8101 /******************************************************************/
8102 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8103                                       struct link_params *params,
8104                                       struct link_vars *vars)
8105 {
8106         u8 link_up = 0;
8107         u16 val1, val2, rx_sd, pcs_status;
8108         struct bnx2x *bp = params->bp;
8109         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8110         /* Clear RX Alarm*/
8111         bnx2x_cl45_read(bp, phy,
8112                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8113
8114         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8115                              MDIO_PMA_LASI_TXCTRL);
8116
8117         /* clear LASI indication*/
8118         bnx2x_cl45_read(bp, phy,
8119                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8120         bnx2x_cl45_read(bp, phy,
8121                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8122         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8123
8124         bnx2x_cl45_read(bp, phy,
8125                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8126         bnx2x_cl45_read(bp, phy,
8127                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8128         bnx2x_cl45_read(bp, phy,
8129                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8130         bnx2x_cl45_read(bp, phy,
8131                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8132
8133         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8134                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8135         /*
8136          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8137          * are set, or if the autoneg bit 1 is set
8138          */
8139         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8140         if (link_up) {
8141                 if (val2 & (1<<1))
8142                         vars->line_speed = SPEED_1000;
8143                 else
8144                         vars->line_speed = SPEED_10000;
8145                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8146                 vars->duplex = DUPLEX_FULL;
8147         }
8148
8149         /* Capture 10G link fault. Read twice to clear stale value. */
8150         if (vars->line_speed == SPEED_10000) {
8151                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8152                             MDIO_PMA_LASI_TXSTAT, &val1);
8153                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8154                             MDIO_PMA_LASI_TXSTAT, &val1);
8155                 if (val1 & (1<<0))
8156                         vars->fault_detected = 1;
8157         }
8158
8159         return link_up;
8160 }
8161
8162 /******************************************************************/
8163 /*                      BCM8706 PHY SECTION                       */
8164 /******************************************************************/
8165 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8166                                  struct link_params *params,
8167                                  struct link_vars *vars)
8168 {
8169         u32 tx_en_mode;
8170         u16 cnt, val, tmp1;
8171         struct bnx2x *bp = params->bp;
8172
8173         /* SPF+ PHY: Set flag to check for Tx error */
8174         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8175
8176         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8177                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8178         /* HW reset */
8179         bnx2x_ext_phy_hw_reset(bp, params->port);
8180         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8181         bnx2x_wait_reset_complete(bp, phy, params);
8182
8183         /* Wait until fw is loaded */
8184         for (cnt = 0; cnt < 100; cnt++) {
8185                 bnx2x_cl45_read(bp, phy,
8186                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8187                 if (val)
8188                         break;
8189                 msleep(10);
8190         }
8191         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8192         if ((params->feature_config_flags &
8193              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8194                 u8 i;
8195                 u16 reg;
8196                 for (i = 0; i < 4; i++) {
8197                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8198                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8199                                    MDIO_XS_8706_REG_BANK_RX0);
8200                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8201                         /* Clear first 3 bits of the control */
8202                         val &= ~0x7;
8203                         /* Set control bits according to configuration */
8204                         val |= (phy->rx_preemphasis[i] & 0x7);
8205                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8206                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8207                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8208                 }
8209         }
8210         /* Force speed */
8211         if (phy->req_line_speed == SPEED_10000) {
8212                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8213
8214                 bnx2x_cl45_write(bp, phy,
8215                                  MDIO_PMA_DEVAD,
8216                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8217                 bnx2x_cl45_write(bp, phy,
8218                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8219                                  0);
8220                 /* Arm LASI for link and Tx fault. */
8221                 bnx2x_cl45_write(bp, phy,
8222                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8223         } else {
8224                 /* Force 1Gbps using autoneg with 1G advertisement */
8225
8226                 /* Allow CL37 through CL73 */
8227                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8228                 bnx2x_cl45_write(bp, phy,
8229                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8230
8231                 /* Enable Full-Duplex advertisement on CL37 */
8232                 bnx2x_cl45_write(bp, phy,
8233                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8234                 /* Enable CL37 AN */
8235                 bnx2x_cl45_write(bp, phy,
8236                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8237                 /* 1G support */
8238                 bnx2x_cl45_write(bp, phy,
8239                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8240
8241                 /* Enable clause 73 AN */
8242                 bnx2x_cl45_write(bp, phy,
8243                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8244                 bnx2x_cl45_write(bp, phy,
8245                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8246                                  0x0400);
8247                 bnx2x_cl45_write(bp, phy,
8248                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8249                                  0x0004);
8250         }
8251         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8252
8253         /*
8254          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8255          * power mode, if TX Laser is disabled
8256          */
8257
8258         tx_en_mode = REG_RD(bp, params->shmem_base +
8259                             offsetof(struct shmem_region,
8260                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8261                         & PORT_HW_CFG_TX_LASER_MASK;
8262
8263         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8264                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8265                 bnx2x_cl45_read(bp, phy,
8266                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8267                 tmp1 |= 0x1;
8268                 bnx2x_cl45_write(bp, phy,
8269                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8270         }
8271
8272         return 0;
8273 }
8274
8275 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8276                                   struct link_params *params,
8277                                   struct link_vars *vars)
8278 {
8279         return bnx2x_8706_8726_read_status(phy, params, vars);
8280 }
8281
8282 /******************************************************************/
8283 /*                      BCM8726 PHY SECTION                       */
8284 /******************************************************************/
8285 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8286                                        struct link_params *params)
8287 {
8288         struct bnx2x *bp = params->bp;
8289         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8290         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8291 }
8292
8293 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8294                                          struct link_params *params)
8295 {
8296         struct bnx2x *bp = params->bp;
8297         /* Need to wait 100ms after reset */
8298         msleep(100);
8299
8300         /* Micro controller re-boot */
8301         bnx2x_cl45_write(bp, phy,
8302                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8303
8304         /* Set soft reset */
8305         bnx2x_cl45_write(bp, phy,
8306                          MDIO_PMA_DEVAD,
8307                          MDIO_PMA_REG_GEN_CTRL,
8308                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8309
8310         bnx2x_cl45_write(bp, phy,
8311                          MDIO_PMA_DEVAD,
8312                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8313
8314         bnx2x_cl45_write(bp, phy,
8315                          MDIO_PMA_DEVAD,
8316                          MDIO_PMA_REG_GEN_CTRL,
8317                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8318
8319         /* wait for 150ms for microcode load */
8320         msleep(150);
8321
8322         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8323         bnx2x_cl45_write(bp, phy,
8324                          MDIO_PMA_DEVAD,
8325                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8326
8327         msleep(200);
8328         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8329 }
8330
8331 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8332                                  struct link_params *params,
8333                                  struct link_vars *vars)
8334 {
8335         struct bnx2x *bp = params->bp;
8336         u16 val1;
8337         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8338         if (link_up) {
8339                 bnx2x_cl45_read(bp, phy,
8340                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8341                                 &val1);
8342                 if (val1 & (1<<15)) {
8343                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8344                         link_up = 0;
8345                         vars->line_speed = 0;
8346                 }
8347         }
8348         return link_up;
8349 }
8350
8351
8352 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8353                                   struct link_params *params,
8354                                   struct link_vars *vars)
8355 {
8356         struct bnx2x *bp = params->bp;
8357         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8358
8359         /* SPF+ PHY: Set flag to check for Tx error */
8360         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8361
8362         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8363         bnx2x_wait_reset_complete(bp, phy, params);
8364
8365         bnx2x_8726_external_rom_boot(phy, params);
8366
8367         /*
8368          * Need to call module detected on initialization since the module
8369          * detection triggered by actual module insertion might occur before
8370          * driver is loaded, and when driver is loaded, it reset all
8371          * registers, including the transmitter
8372          */
8373         bnx2x_sfp_module_detection(phy, params);
8374
8375         if (phy->req_line_speed == SPEED_1000) {
8376                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8377                 bnx2x_cl45_write(bp, phy,
8378                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8379                 bnx2x_cl45_write(bp, phy,
8380                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8381                 bnx2x_cl45_write(bp, phy,
8382                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8383                 bnx2x_cl45_write(bp, phy,
8384                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8385                                  0x400);
8386         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8387                    (phy->speed_cap_mask &
8388                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8389                    ((phy->speed_cap_mask &
8390                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8391                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8392                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8393                 /* Set Flow control */
8394                 bnx2x_ext_phy_set_pause(params, phy, vars);
8395                 bnx2x_cl45_write(bp, phy,
8396                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8397                 bnx2x_cl45_write(bp, phy,
8398                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8399                 bnx2x_cl45_write(bp, phy,
8400                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8401                 bnx2x_cl45_write(bp, phy,
8402                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8403                 bnx2x_cl45_write(bp, phy,
8404                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8405                 /*
8406                  * Enable RX-ALARM control to receive interrupt for 1G speed
8407                  * change
8408                  */
8409                 bnx2x_cl45_write(bp, phy,
8410                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8411                 bnx2x_cl45_write(bp, phy,
8412                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8413                                  0x400);
8414
8415         } else { /* Default 10G. Set only LASI control */
8416                 bnx2x_cl45_write(bp, phy,
8417                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8418         }
8419
8420         /* Set TX PreEmphasis if needed */
8421         if ((params->feature_config_flags &
8422              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8423                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8424                          "TX_CTRL2 0x%x\n",
8425                          phy->tx_preemphasis[0],
8426                          phy->tx_preemphasis[1]);
8427                 bnx2x_cl45_write(bp, phy,
8428                                  MDIO_PMA_DEVAD,
8429                                  MDIO_PMA_REG_8726_TX_CTRL1,
8430                                  phy->tx_preemphasis[0]);
8431
8432                 bnx2x_cl45_write(bp, phy,
8433                                  MDIO_PMA_DEVAD,
8434                                  MDIO_PMA_REG_8726_TX_CTRL2,
8435                                  phy->tx_preemphasis[1]);
8436         }
8437
8438         return 0;
8439
8440 }
8441
8442 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8443                                   struct link_params *params)
8444 {
8445         struct bnx2x *bp = params->bp;
8446         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8447         /* Set serial boot control for external load */
8448         bnx2x_cl45_write(bp, phy,
8449                          MDIO_PMA_DEVAD,
8450                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8451 }
8452
8453 /******************************************************************/
8454 /*                      BCM8727 PHY SECTION                       */
8455 /******************************************************************/
8456
8457 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8458                                     struct link_params *params, u8 mode)
8459 {
8460         struct bnx2x *bp = params->bp;
8461         u16 led_mode_bitmask = 0;
8462         u16 gpio_pins_bitmask = 0;
8463         u16 val;
8464         /* Only NOC flavor requires to set the LED specifically */
8465         if (!(phy->flags & FLAGS_NOC))
8466                 return;
8467         switch (mode) {
8468         case LED_MODE_FRONT_PANEL_OFF:
8469         case LED_MODE_OFF:
8470                 led_mode_bitmask = 0;
8471                 gpio_pins_bitmask = 0x03;
8472                 break;
8473         case LED_MODE_ON:
8474                 led_mode_bitmask = 0;
8475                 gpio_pins_bitmask = 0x02;
8476                 break;
8477         case LED_MODE_OPER:
8478                 led_mode_bitmask = 0x60;
8479                 gpio_pins_bitmask = 0x11;
8480                 break;
8481         }
8482         bnx2x_cl45_read(bp, phy,
8483                         MDIO_PMA_DEVAD,
8484                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8485                         &val);
8486         val &= 0xff8f;
8487         val |= led_mode_bitmask;
8488         bnx2x_cl45_write(bp, phy,
8489                          MDIO_PMA_DEVAD,
8490                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8491                          val);
8492         bnx2x_cl45_read(bp, phy,
8493                         MDIO_PMA_DEVAD,
8494                         MDIO_PMA_REG_8727_GPIO_CTRL,
8495                         &val);
8496         val &= 0xffe0;
8497         val |= gpio_pins_bitmask;
8498         bnx2x_cl45_write(bp, phy,
8499                          MDIO_PMA_DEVAD,
8500                          MDIO_PMA_REG_8727_GPIO_CTRL,
8501                          val);
8502 }
8503 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8504                                 struct link_params *params) {
8505         u32 swap_val, swap_override;
8506         u8 port;
8507         /*
8508          * The PHY reset is controlled by GPIO 1. Fake the port number
8509          * to cancel the swap done in set_gpio()
8510          */
8511         struct bnx2x *bp = params->bp;
8512         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8513         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8514         port = (swap_val && swap_override) ^ 1;
8515         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8516                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8517 }
8518
8519 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8520                                   struct link_params *params,
8521                                   struct link_vars *vars)
8522 {
8523         u32 tx_en_mode;
8524         u16 tmp1, val, mod_abs, tmp2;
8525         u16 rx_alarm_ctrl_val;
8526         u16 lasi_ctrl_val;
8527         struct bnx2x *bp = params->bp;
8528         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8529
8530         /* SPF+ PHY: Set flag to check for Tx error */
8531         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8532
8533         bnx2x_wait_reset_complete(bp, phy, params);
8534         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8535         /* Should be 0x6 to enable XS on Tx side. */
8536         lasi_ctrl_val = 0x0006;
8537
8538         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8539         /* enable LASI */
8540         bnx2x_cl45_write(bp, phy,
8541                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8542                          rx_alarm_ctrl_val);
8543         bnx2x_cl45_write(bp, phy,
8544                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8545                          0);
8546         bnx2x_cl45_write(bp, phy,
8547                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8548
8549         /*
8550          * Initially configure MOD_ABS to interrupt when module is
8551          * presence( bit 8)
8552          */
8553         bnx2x_cl45_read(bp, phy,
8554                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8555         /*
8556          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8557          * When the EDC is off it locks onto a reference clock and avoids
8558          * becoming 'lost'
8559          */
8560         mod_abs &= ~(1<<8);
8561         if (!(phy->flags & FLAGS_NOC))
8562                 mod_abs &= ~(1<<9);
8563         bnx2x_cl45_write(bp, phy,
8564                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8565
8566
8567         /* Make MOD_ABS give interrupt on change */
8568         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8569                         &val);
8570         val |= (1<<12);
8571         if (phy->flags & FLAGS_NOC)
8572                 val |= (3<<5);
8573
8574         /*
8575          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8576          * status which reflect SFP+ module over-current
8577          */
8578         if (!(phy->flags & FLAGS_NOC))
8579                 val &= 0xff8f; /* Reset bits 4-6 */
8580         bnx2x_cl45_write(bp, phy,
8581                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8582
8583         bnx2x_8727_power_module(bp, phy, 1);
8584
8585         bnx2x_cl45_read(bp, phy,
8586                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8587
8588         bnx2x_cl45_read(bp, phy,
8589                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8590
8591         /* Set option 1G speed */
8592         if (phy->req_line_speed == SPEED_1000) {
8593                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8594                 bnx2x_cl45_write(bp, phy,
8595                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8596                 bnx2x_cl45_write(bp, phy,
8597                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8598                 bnx2x_cl45_read(bp, phy,
8599                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8600                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8601                 /*
8602                  * Power down the XAUI until link is up in case of dual-media
8603                  * and 1G
8604                  */
8605                 if (DUAL_MEDIA(params)) {
8606                         bnx2x_cl45_read(bp, phy,
8607                                         MDIO_PMA_DEVAD,
8608                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8609                         val |= (3<<10);
8610                         bnx2x_cl45_write(bp, phy,
8611                                          MDIO_PMA_DEVAD,
8612                                          MDIO_PMA_REG_8727_PCS_GP, val);
8613                 }
8614         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8615                    ((phy->speed_cap_mask &
8616                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8617                    ((phy->speed_cap_mask &
8618                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8619                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8620
8621                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8622                 bnx2x_cl45_write(bp, phy,
8623                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8624                 bnx2x_cl45_write(bp, phy,
8625                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8626         } else {
8627                 /*
8628                  * Since the 8727 has only single reset pin, need to set the 10G
8629                  * registers although it is default
8630                  */
8631                 bnx2x_cl45_write(bp, phy,
8632                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8633                                  0x0020);
8634                 bnx2x_cl45_write(bp, phy,
8635                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8636                 bnx2x_cl45_write(bp, phy,
8637                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8638                 bnx2x_cl45_write(bp, phy,
8639                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8640                                  0x0008);
8641         }
8642
8643         /*
8644          * Set 2-wire transfer rate of SFP+ module EEPROM
8645          * to 100Khz since some DACs(direct attached cables) do
8646          * not work at 400Khz.
8647          */
8648         bnx2x_cl45_write(bp, phy,
8649                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8650                          0xa001);
8651
8652         /* Set TX PreEmphasis if needed */
8653         if ((params->feature_config_flags &
8654              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8655                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8656                            phy->tx_preemphasis[0],
8657                            phy->tx_preemphasis[1]);
8658                 bnx2x_cl45_write(bp, phy,
8659                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8660                                  phy->tx_preemphasis[0]);
8661
8662                 bnx2x_cl45_write(bp, phy,
8663                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8664                                  phy->tx_preemphasis[1]);
8665         }
8666
8667         /*
8668          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8669          * power mode, if TX Laser is disabled
8670          */
8671         tx_en_mode = REG_RD(bp, params->shmem_base +
8672                             offsetof(struct shmem_region,
8673                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8674                         & PORT_HW_CFG_TX_LASER_MASK;
8675
8676         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8677
8678                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8679                 bnx2x_cl45_read(bp, phy,
8680                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8681                 tmp2 |= 0x1000;
8682                 tmp2 &= 0xFFEF;
8683                 bnx2x_cl45_write(bp, phy,
8684                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8685         }
8686
8687         return 0;
8688 }
8689
8690 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8691                                       struct link_params *params)
8692 {
8693         struct bnx2x *bp = params->bp;
8694         u16 mod_abs, rx_alarm_status;
8695         u32 val = REG_RD(bp, params->shmem_base +
8696                              offsetof(struct shmem_region, dev_info.
8697                                       port_feature_config[params->port].
8698                                       config));
8699         bnx2x_cl45_read(bp, phy,
8700                         MDIO_PMA_DEVAD,
8701                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8702         if (mod_abs & (1<<8)) {
8703
8704                 /* Module is absent */
8705                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8706                             "show module is absent\n");
8707                 phy->media_type = ETH_PHY_NOT_PRESENT;
8708                 /*
8709                  * 1. Set mod_abs to detect next module
8710                  *    presence event
8711                  * 2. Set EDC off by setting OPTXLOS signal input to low
8712                  *    (bit 9).
8713                  *    When the EDC is off it locks onto a reference clock and
8714                  *    avoids becoming 'lost'.
8715                  */
8716                 mod_abs &= ~(1<<8);
8717                 if (!(phy->flags & FLAGS_NOC))
8718                         mod_abs &= ~(1<<9);
8719                 bnx2x_cl45_write(bp, phy,
8720                                  MDIO_PMA_DEVAD,
8721                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8722
8723                 /*
8724                  * Clear RX alarm since it stays up as long as
8725                  * the mod_abs wasn't changed
8726                  */
8727                 bnx2x_cl45_read(bp, phy,
8728                                 MDIO_PMA_DEVAD,
8729                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8730
8731         } else {
8732                 /* Module is present */
8733                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8734                             "show module is present\n");
8735                 /*
8736                  * First disable transmitter, and if the module is ok, the
8737                  * module_detection will enable it
8738                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8739                  * 2. Restore the default polarity of the OPRXLOS signal and
8740                  * this signal will then correctly indicate the presence or
8741                  * absence of the Rx signal. (bit 9)
8742                  */
8743                 mod_abs |= (1<<8);
8744                 if (!(phy->flags & FLAGS_NOC))
8745                         mod_abs |= (1<<9);
8746                 bnx2x_cl45_write(bp, phy,
8747                                  MDIO_PMA_DEVAD,
8748                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8749
8750                 /*
8751                  * Clear RX alarm since it stays up as long as the mod_abs
8752                  * wasn't changed. This is need to be done before calling the
8753                  * module detection, otherwise it will clear* the link update
8754                  * alarm
8755                  */
8756                 bnx2x_cl45_read(bp, phy,
8757                                 MDIO_PMA_DEVAD,
8758                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8759
8760
8761                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8762                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8763                         bnx2x_sfp_set_transmitter(params, phy, 0);
8764
8765                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8766                         bnx2x_sfp_module_detection(phy, params);
8767                 else
8768                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8769         }
8770
8771         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8772                    rx_alarm_status);
8773         /* No need to check link status in case of module plugged in/out */
8774 }
8775
8776 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8777                                  struct link_params *params,
8778                                  struct link_vars *vars)
8779
8780 {
8781         struct bnx2x *bp = params->bp;
8782         u8 link_up = 0, oc_port = params->port;
8783         u16 link_status = 0;
8784         u16 rx_alarm_status, lasi_ctrl, val1;
8785
8786         /* If PHY is not initialized, do not check link status */
8787         bnx2x_cl45_read(bp, phy,
8788                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8789                         &lasi_ctrl);
8790         if (!lasi_ctrl)
8791                 return 0;
8792
8793         /* Check the LASI on Rx */
8794         bnx2x_cl45_read(bp, phy,
8795                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8796                         &rx_alarm_status);
8797         vars->line_speed = 0;
8798         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
8799
8800         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8801                              MDIO_PMA_LASI_TXCTRL);
8802
8803         bnx2x_cl45_read(bp, phy,
8804                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8805
8806         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8807
8808         /* Clear MSG-OUT */
8809         bnx2x_cl45_read(bp, phy,
8810                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8811
8812         /*
8813          * If a module is present and there is need to check
8814          * for over current
8815          */
8816         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8817                 /* Check over-current using 8727 GPIO0 input*/
8818                 bnx2x_cl45_read(bp, phy,
8819                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8820                                 &val1);
8821
8822                 if ((val1 & (1<<8)) == 0) {
8823                         if (!CHIP_IS_E1x(bp))
8824                                 oc_port = BP_PATH(bp) + (params->port << 1);
8825                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8826                                        " on port %d\n", oc_port);
8827                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
8828                                             " been detected and the power to "
8829                                             "that SFP+ module has been removed"
8830                                             " to prevent failure of the card."
8831                                             " Please remove the SFP+ module and"
8832                                             " restart the system to clear this"
8833                                             " error.\n",
8834                          oc_port);
8835                         /* Disable all RX_ALARMs except for mod_abs */
8836                         bnx2x_cl45_write(bp, phy,
8837                                          MDIO_PMA_DEVAD,
8838                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
8839
8840                         bnx2x_cl45_read(bp, phy,
8841                                         MDIO_PMA_DEVAD,
8842                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8843                         /* Wait for module_absent_event */
8844                         val1 |= (1<<8);
8845                         bnx2x_cl45_write(bp, phy,
8846                                          MDIO_PMA_DEVAD,
8847                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8848                         /* Clear RX alarm */
8849                         bnx2x_cl45_read(bp, phy,
8850                                 MDIO_PMA_DEVAD,
8851                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8852                         return 0;
8853                 }
8854         } /* Over current check */
8855
8856         /* When module absent bit is set, check module */
8857         if (rx_alarm_status & (1<<5)) {
8858                 bnx2x_8727_handle_mod_abs(phy, params);
8859                 /* Enable all mod_abs and link detection bits */
8860                 bnx2x_cl45_write(bp, phy,
8861                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8862                                  ((1<<5) | (1<<2)));
8863         }
8864         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8865         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8866         /* If transmitter is disabled, ignore false link up indication */
8867         bnx2x_cl45_read(bp, phy,
8868                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8869         if (val1 & (1<<15)) {
8870                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8871                 return 0;
8872         }
8873
8874         bnx2x_cl45_read(bp, phy,
8875                         MDIO_PMA_DEVAD,
8876                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8877
8878         /*
8879          * Bits 0..2 --> speed detected,
8880          * Bits 13..15--> link is down
8881          */
8882         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8883                 link_up = 1;
8884                 vars->line_speed = SPEED_10000;
8885                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8886                            params->port);
8887         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8888                 link_up = 1;
8889                 vars->line_speed = SPEED_1000;
8890                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8891                            params->port);
8892         } else {
8893                 link_up = 0;
8894                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8895                            params->port);
8896         }
8897
8898         /* Capture 10G link fault. */
8899         if (vars->line_speed == SPEED_10000) {
8900                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8901                             MDIO_PMA_LASI_TXSTAT, &val1);
8902
8903                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8904                             MDIO_PMA_LASI_TXSTAT, &val1);
8905
8906                 if (val1 & (1<<0)) {
8907                         vars->fault_detected = 1;
8908                 }
8909         }
8910
8911         if (link_up) {
8912                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8913                 vars->duplex = DUPLEX_FULL;
8914                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
8915         }
8916
8917         if ((DUAL_MEDIA(params)) &&
8918             (phy->req_line_speed == SPEED_1000)) {
8919                 bnx2x_cl45_read(bp, phy,
8920                                 MDIO_PMA_DEVAD,
8921                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
8922                 /*
8923                  * In case of dual-media board and 1G, power up the XAUI side,
8924                  * otherwise power it down. For 10G it is done automatically
8925                  */
8926                 if (link_up)
8927                         val1 &= ~(3<<10);
8928                 else
8929                         val1 |= (3<<10);
8930                 bnx2x_cl45_write(bp, phy,
8931                                  MDIO_PMA_DEVAD,
8932                                  MDIO_PMA_REG_8727_PCS_GP, val1);
8933         }
8934         return link_up;
8935 }
8936
8937 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
8938                                   struct link_params *params)
8939 {
8940         struct bnx2x *bp = params->bp;
8941         /* Disable Transmitter */
8942         bnx2x_sfp_set_transmitter(params, phy, 0);
8943         /* Clear LASI */
8944         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
8945
8946 }
8947
8948 /******************************************************************/
8949 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
8950 /******************************************************************/
8951 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
8952                                            struct link_params *params)
8953 {
8954         u16 val, fw_ver1, fw_ver2, cnt;
8955         u8 port;
8956         struct bnx2x *bp = params->bp;
8957
8958         port = params->port;
8959
8960         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
8961         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
8962         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
8963         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
8964         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
8965         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
8966         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
8967
8968         for (cnt = 0; cnt < 100; cnt++) {
8969                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
8970                 if (val & 1)
8971                         break;
8972                 udelay(5);
8973         }
8974         if (cnt == 100) {
8975                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
8976                 bnx2x_save_spirom_version(bp, port, 0,
8977                                           phy->ver_addr);
8978                 return;
8979         }
8980
8981
8982         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
8983         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
8984         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
8985         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
8986         for (cnt = 0; cnt < 100; cnt++) {
8987                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
8988                 if (val & 1)
8989                         break;
8990                 udelay(5);
8991         }
8992         if (cnt == 100) {
8993                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
8994                 bnx2x_save_spirom_version(bp, port, 0,
8995                                           phy->ver_addr);
8996                 return;
8997         }
8998
8999         /* lower 16 bits of the register SPI_FW_STATUS */
9000         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9001         /* upper 16 bits of register SPI_FW_STATUS */
9002         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9003
9004         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9005                                   phy->ver_addr);
9006 }
9007
9008 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9009                                 struct bnx2x_phy *phy)
9010 {
9011         u16 val;
9012
9013         /* PHYC_CTL_LED_CTL */
9014         bnx2x_cl45_read(bp, phy,
9015                         MDIO_PMA_DEVAD,
9016                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9017         val &= 0xFE00;
9018         val |= 0x0092;
9019
9020         bnx2x_cl45_write(bp, phy,
9021                          MDIO_PMA_DEVAD,
9022                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9023
9024         bnx2x_cl45_write(bp, phy,
9025                          MDIO_PMA_DEVAD,
9026                          MDIO_PMA_REG_8481_LED1_MASK,
9027                          0x80);
9028
9029         bnx2x_cl45_write(bp, phy,
9030                          MDIO_PMA_DEVAD,
9031                          MDIO_PMA_REG_8481_LED2_MASK,
9032                          0x18);
9033
9034         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9035         bnx2x_cl45_write(bp, phy,
9036                          MDIO_PMA_DEVAD,
9037                          MDIO_PMA_REG_8481_LED3_MASK,
9038                          0x0006);
9039
9040         /* Select the closest activity blink rate to that in 10/100/1000 */
9041         bnx2x_cl45_write(bp, phy,
9042                         MDIO_PMA_DEVAD,
9043                         MDIO_PMA_REG_8481_LED3_BLINK,
9044                         0);
9045
9046         bnx2x_cl45_read(bp, phy,
9047                         MDIO_PMA_DEVAD,
9048                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9049         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9050
9051         bnx2x_cl45_write(bp, phy,
9052                          MDIO_PMA_DEVAD,
9053                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9054
9055         /* 'Interrupt Mask' */
9056         bnx2x_cl45_write(bp, phy,
9057                          MDIO_AN_DEVAD,
9058                          0xFFFB, 0xFFFD);
9059 }
9060
9061 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9062                                        struct link_params *params,
9063                                        struct link_vars *vars)
9064 {
9065         struct bnx2x *bp = params->bp;
9066         u16 autoneg_val, an_1000_val, an_10_100_val;
9067         u16 tmp_req_line_speed;
9068
9069         tmp_req_line_speed = phy->req_line_speed;
9070         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9071                 if (phy->req_line_speed == SPEED_10000)
9072                         phy->req_line_speed = SPEED_AUTO_NEG;
9073
9074         /*
9075          * This phy uses the NIG latch mechanism since link indication
9076          * arrives through its LED4 and not via its LASI signal, so we
9077          * get steady signal instead of clear on read
9078          */
9079         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9080                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9081
9082         bnx2x_cl45_write(bp, phy,
9083                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9084
9085         bnx2x_848xx_set_led(bp, phy);
9086
9087         /* set 1000 speed advertisement */
9088         bnx2x_cl45_read(bp, phy,
9089                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9090                         &an_1000_val);
9091
9092         bnx2x_ext_phy_set_pause(params, phy, vars);
9093         bnx2x_cl45_read(bp, phy,
9094                         MDIO_AN_DEVAD,
9095                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9096                         &an_10_100_val);
9097         bnx2x_cl45_read(bp, phy,
9098                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9099                         &autoneg_val);
9100         /* Disable forced speed */
9101         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9102         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9103
9104         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9105              (phy->speed_cap_mask &
9106              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9107             (phy->req_line_speed == SPEED_1000)) {
9108                 an_1000_val |= (1<<8);
9109                 autoneg_val |= (1<<9 | 1<<12);
9110                 if (phy->req_duplex == DUPLEX_FULL)
9111                         an_1000_val |= (1<<9);
9112                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9113         } else
9114                 an_1000_val &= ~((1<<8) | (1<<9));
9115
9116         bnx2x_cl45_write(bp, phy,
9117                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9118                          an_1000_val);
9119
9120         /* set 10 speed advertisement */
9121         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9122              (phy->speed_cap_mask &
9123              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9124               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
9125                 an_10_100_val |= (1<<7);
9126                 /* Enable autoneg and restart autoneg for legacy speeds */
9127                 autoneg_val |= (1<<9 | 1<<12);
9128
9129                 if (phy->req_duplex == DUPLEX_FULL)
9130                         an_10_100_val |= (1<<8);
9131                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9132         }
9133         /* set 10 speed advertisement */
9134         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9135             (phy->speed_cap_mask &
9136           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9137            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
9138                 an_10_100_val |= (1<<5);
9139                 autoneg_val |= (1<<9 | 1<<12);
9140                 if (phy->req_duplex == DUPLEX_FULL)
9141                         an_10_100_val |= (1<<6);
9142                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9143         }
9144
9145         /* Only 10/100 are allowed to work in FORCE mode */
9146         if (phy->req_line_speed == SPEED_100) {
9147                 autoneg_val |= (1<<13);
9148                 /* Enabled AUTO-MDIX when autoneg is disabled */
9149                 bnx2x_cl45_write(bp, phy,
9150                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9151                                  (1<<15 | 1<<9 | 7<<0));
9152                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9153         }
9154         if (phy->req_line_speed == SPEED_10) {
9155                 /* Enabled AUTO-MDIX when autoneg is disabled */
9156                 bnx2x_cl45_write(bp, phy,
9157                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9158                                  (1<<15 | 1<<9 | 7<<0));
9159                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9160         }
9161
9162         bnx2x_cl45_write(bp, phy,
9163                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9164                          an_10_100_val);
9165
9166         if (phy->req_duplex == DUPLEX_FULL)
9167                 autoneg_val |= (1<<8);
9168
9169         bnx2x_cl45_write(bp, phy,
9170                          MDIO_AN_DEVAD,
9171                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9172
9173         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9174             (phy->speed_cap_mask &
9175              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9176                 (phy->req_line_speed == SPEED_10000)) {
9177                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9178                         /* Restart autoneg for 10G*/
9179
9180                         bnx2x_cl45_write(bp, phy,
9181                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9182                                  0x3200);
9183         } else if (phy->req_line_speed != SPEED_10 &&
9184                    phy->req_line_speed != SPEED_100) {
9185                 bnx2x_cl45_write(bp, phy,
9186                                  MDIO_AN_DEVAD,
9187                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9188                                  1);
9189         }
9190         /* Save spirom version */
9191         bnx2x_save_848xx_spirom_version(phy, params);
9192
9193         phy->req_line_speed = tmp_req_line_speed;
9194
9195         return 0;
9196 }
9197
9198 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9199                                   struct link_params *params,
9200                                   struct link_vars *vars)
9201 {
9202         struct bnx2x *bp = params->bp;
9203         /* Restore normal power mode*/
9204         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9205                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9206
9207         /* HW reset */
9208         bnx2x_ext_phy_hw_reset(bp, params->port);
9209         bnx2x_wait_reset_complete(bp, phy, params);
9210
9211         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9212         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9213 }
9214
9215
9216 #define PHY84833_HDSHK_WAIT 300
9217 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9218                                    struct link_params *params,
9219                                    struct link_vars *vars)
9220 {
9221         u32 idx;
9222         u16 val;
9223         u16 data = 0x01b1;
9224         struct bnx2x *bp = params->bp;
9225         /* Do pair swap */
9226
9227
9228         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9229         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9230                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9231                         PHY84833_CMD_OPEN_OVERRIDE);
9232         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9233                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9234                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9235                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9236                         break;
9237                 msleep(1);
9238         }
9239         if (idx >= PHY84833_HDSHK_WAIT) {
9240                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9241                 return -EINVAL;
9242         }
9243
9244         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9245                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
9246                         data);
9247         /* Issue pair swap command */
9248         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9249                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
9250                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9251         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9252                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9253                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9254                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9255                         (val == PHY84833_CMD_COMPLETE_ERROR))
9256                         break;
9257                 msleep(1);
9258         }
9259         if ((idx >= PHY84833_HDSHK_WAIT) ||
9260                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9261                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9262                 return -EINVAL;
9263         }
9264         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9265                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9266                         PHY84833_CMD_CLEAR_COMPLETE);
9267         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9268         return 0;
9269 }
9270
9271
9272 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9273                                                 u32 shmem_base_path[],
9274                                                 u32 chip_id)
9275 {
9276         u32 reset_pin[2];
9277         u32 idx;
9278         u8 reset_gpios;
9279         if (CHIP_IS_E3(bp)) {
9280                 /* Assume that these will be GPIOs, not EPIOs. */
9281                 for (idx = 0; idx < 2; idx++) {
9282                         /* Map config param to register bit. */
9283                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9284                                 offsetof(struct shmem_region,
9285                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9286                         reset_pin[idx] = (reset_pin[idx] &
9287                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9288                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9289                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9290                         reset_pin[idx] = (1 << reset_pin[idx]);
9291                 }
9292                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9293         } else {
9294                 /* E2, look from diff place of shmem. */
9295                 for (idx = 0; idx < 2; idx++) {
9296                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9297                                 offsetof(struct shmem_region,
9298                                 dev_info.port_hw_config[0].default_cfg));
9299                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9300                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9301                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9302                         reset_pin[idx] = (1 << reset_pin[idx]);
9303                 }
9304                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9305         }
9306
9307         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9308         udelay(10);
9309         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9310         msleep(800);
9311         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9312                 reset_gpios);
9313
9314         return 0;
9315 }
9316
9317 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9318                                    struct link_params *params,
9319                                    struct link_vars *vars)
9320 {
9321         struct bnx2x *bp = params->bp;
9322         u8 port, initialize = 1;
9323         u16 val;
9324         u16 temp;
9325         u32 actual_phy_selection, cms_enable;
9326         int rc = 0;
9327
9328         msleep(1);
9329
9330         if (!(CHIP_IS_E1(bp)))
9331                 port = BP_PATH(bp);
9332         else
9333                 port = params->port;
9334
9335         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9336                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9337                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9338                                port);
9339         } else {
9340                 bnx2x_cl45_write(bp, phy,
9341                                 MDIO_PMA_DEVAD,
9342                                 MDIO_PMA_REG_CTRL, 0x8000);
9343         }
9344
9345         bnx2x_wait_reset_complete(bp, phy, params);
9346         /* Wait for GPHY to come out of reset */
9347         msleep(50);
9348
9349         /* Bring PHY out of super isolate mode */
9350         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9351                 bnx2x_cl45_read(bp, phy,
9352                                 MDIO_CTL_DEVAD,
9353                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9354                 val &= ~MDIO_84833_SUPER_ISOLATE;
9355                 bnx2x_cl45_write(bp, phy,
9356                                 MDIO_CTL_DEVAD,
9357                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9358                 bnx2x_wait_reset_complete(bp, phy, params);
9359         }
9360
9361         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9362                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9363
9364         /*
9365          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9366          */
9367         temp = vars->line_speed;
9368         vars->line_speed = SPEED_10000;
9369         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9370         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9371         vars->line_speed = temp;
9372
9373         /* Set dual-media configuration according to configuration */
9374
9375         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9376                         MDIO_CTL_REG_84823_MEDIA, &val);
9377         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9378                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9379                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9380                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9381                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9382
9383         if (CHIP_IS_E3(bp)) {
9384                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9385                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9386         } else {
9387                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9388                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9389         }
9390
9391         actual_phy_selection = bnx2x_phy_selection(params);
9392
9393         switch (actual_phy_selection) {
9394         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9395                 /* Do nothing. Essentially this is like the priority copper */
9396                 break;
9397         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9398                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9399                 break;
9400         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9401                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9402                 break;
9403         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9404                 /* Do nothing here. The first PHY won't be initialized at all */
9405                 break;
9406         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9407                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9408                 initialize = 0;
9409                 break;
9410         }
9411         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9412                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9413
9414         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9415                          MDIO_CTL_REG_84823_MEDIA, val);
9416         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9417                    params->multi_phy_config, val);
9418
9419         if (initialize)
9420                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9421         else
9422                 bnx2x_save_848xx_spirom_version(phy, params);
9423         cms_enable = REG_RD(bp, params->shmem_base +
9424                         offsetof(struct shmem_region,
9425                         dev_info.port_hw_config[params->port].default_cfg)) &
9426                         PORT_HW_CFG_ENABLE_CMS_MASK;
9427
9428         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9429                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9430         if (cms_enable)
9431                 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9432         else
9433                 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9434         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9435                 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9436
9437
9438         return rc;
9439 }
9440
9441 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9442                                   struct link_params *params,
9443                                   struct link_vars *vars)
9444 {
9445         struct bnx2x *bp = params->bp;
9446         u16 val, val1, val2;
9447         u8 link_up = 0;
9448
9449
9450         /* Check 10G-BaseT link status */
9451         /* Check PMD signal ok */
9452         bnx2x_cl45_read(bp, phy,
9453                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9454         bnx2x_cl45_read(bp, phy,
9455                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9456                         &val2);
9457         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9458
9459         /* Check link 10G */
9460         if (val2 & (1<<11)) {
9461                 vars->line_speed = SPEED_10000;
9462                 vars->duplex = DUPLEX_FULL;
9463                 link_up = 1;
9464                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9465         } else { /* Check Legacy speed link */
9466                 u16 legacy_status, legacy_speed;
9467
9468                 /* Enable expansion register 0x42 (Operation mode status) */
9469                 bnx2x_cl45_write(bp, phy,
9470                                  MDIO_AN_DEVAD,
9471                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9472
9473                 /* Get legacy speed operation status */
9474                 bnx2x_cl45_read(bp, phy,
9475                                 MDIO_AN_DEVAD,
9476                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9477                                 &legacy_status);
9478
9479                 DP(NETIF_MSG_LINK, "Legacy speed status"
9480                              " = 0x%x\n", legacy_status);
9481                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9482                 if (link_up) {
9483                         legacy_speed = (legacy_status & (3<<9));
9484                         if (legacy_speed == (0<<9))
9485                                 vars->line_speed = SPEED_10;
9486                         else if (legacy_speed == (1<<9))
9487                                 vars->line_speed = SPEED_100;
9488                         else if (legacy_speed == (2<<9))
9489                                 vars->line_speed = SPEED_1000;
9490                         else /* Should not happen */
9491                                 vars->line_speed = 0;
9492
9493                         if (legacy_status & (1<<8))
9494                                 vars->duplex = DUPLEX_FULL;
9495                         else
9496                                 vars->duplex = DUPLEX_HALF;
9497
9498                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9499                                    " is_duplex_full= %d\n", vars->line_speed,
9500                                    (vars->duplex == DUPLEX_FULL));
9501                         /* Check legacy speed AN resolution */
9502                         bnx2x_cl45_read(bp, phy,
9503                                         MDIO_AN_DEVAD,
9504                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9505                                         &val);
9506                         if (val & (1<<5))
9507                                 vars->link_status |=
9508                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9509                         bnx2x_cl45_read(bp, phy,
9510                                         MDIO_AN_DEVAD,
9511                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9512                                         &val);
9513                         if ((val & (1<<0)) == 0)
9514                                 vars->link_status |=
9515                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9516                 }
9517         }
9518         if (link_up) {
9519                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9520                            vars->line_speed);
9521                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9522         }
9523
9524         return link_up;
9525 }
9526
9527
9528 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9529 {
9530         int status = 0;
9531         u32 spirom_ver;
9532         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9533         status = bnx2x_format_ver(spirom_ver, str, len);
9534         return status;
9535 }
9536
9537 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9538                                 struct link_params *params)
9539 {
9540         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9541                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9542         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9543                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9544 }
9545
9546 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9547                                         struct link_params *params)
9548 {
9549         bnx2x_cl45_write(params->bp, phy,
9550                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9551         bnx2x_cl45_write(params->bp, phy,
9552                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9553 }
9554
9555 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9556                                    struct link_params *params)
9557 {
9558         struct bnx2x *bp = params->bp;
9559         u8 port;
9560         u16 val16;
9561
9562         if (!(CHIP_IS_E1(bp)))
9563                 port = BP_PATH(bp);
9564         else
9565                 port = params->port;
9566
9567         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9568                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9569                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
9570                                port);
9571         } else {
9572                 bnx2x_cl45_read(bp, phy,
9573                                 MDIO_CTL_DEVAD,
9574                                 0x400f, &val16);
9575                 /* Put to low power mode on newer FW */
9576                 if ((val16 & 0x303f) > 0x1009)
9577                         bnx2x_cl45_write(bp, phy,
9578                                         MDIO_PMA_DEVAD,
9579                                         MDIO_PMA_REG_CTRL, 0x800);
9580         }
9581 }
9582
9583 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9584                                      struct link_params *params, u8 mode)
9585 {
9586         struct bnx2x *bp = params->bp;
9587         u16 val;
9588         u8 port;
9589
9590         if (!(CHIP_IS_E1(bp)))
9591                 port = BP_PATH(bp);
9592         else
9593                 port = params->port;
9594
9595         switch (mode) {
9596         case LED_MODE_OFF:
9597
9598                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9599
9600                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9601                     SHARED_HW_CFG_LED_EXTPHY1) {
9602
9603                         /* Set LED masks */
9604                         bnx2x_cl45_write(bp, phy,
9605                                         MDIO_PMA_DEVAD,
9606                                         MDIO_PMA_REG_8481_LED1_MASK,
9607                                         0x0);
9608
9609                         bnx2x_cl45_write(bp, phy,
9610                                         MDIO_PMA_DEVAD,
9611                                         MDIO_PMA_REG_8481_LED2_MASK,
9612                                         0x0);
9613
9614                         bnx2x_cl45_write(bp, phy,
9615                                         MDIO_PMA_DEVAD,
9616                                         MDIO_PMA_REG_8481_LED3_MASK,
9617                                         0x0);
9618
9619                         bnx2x_cl45_write(bp, phy,
9620                                         MDIO_PMA_DEVAD,
9621                                         MDIO_PMA_REG_8481_LED5_MASK,
9622                                         0x0);
9623
9624                 } else {
9625                         bnx2x_cl45_write(bp, phy,
9626                                          MDIO_PMA_DEVAD,
9627                                          MDIO_PMA_REG_8481_LED1_MASK,
9628                                          0x0);
9629                 }
9630                 break;
9631         case LED_MODE_FRONT_PANEL_OFF:
9632
9633                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9634                    port);
9635
9636                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9637                     SHARED_HW_CFG_LED_EXTPHY1) {
9638
9639                         /* Set LED masks */
9640                         bnx2x_cl45_write(bp, phy,
9641                                          MDIO_PMA_DEVAD,
9642                                          MDIO_PMA_REG_8481_LED1_MASK,
9643                                          0x0);
9644
9645                         bnx2x_cl45_write(bp, phy,
9646                                          MDIO_PMA_DEVAD,
9647                                          MDIO_PMA_REG_8481_LED2_MASK,
9648                                          0x0);
9649
9650                         bnx2x_cl45_write(bp, phy,
9651                                          MDIO_PMA_DEVAD,
9652                                          MDIO_PMA_REG_8481_LED3_MASK,
9653                                          0x0);
9654
9655                         bnx2x_cl45_write(bp, phy,
9656                                          MDIO_PMA_DEVAD,
9657                                          MDIO_PMA_REG_8481_LED5_MASK,
9658                                          0x20);
9659
9660                 } else {
9661                         bnx2x_cl45_write(bp, phy,
9662                                          MDIO_PMA_DEVAD,
9663                                          MDIO_PMA_REG_8481_LED1_MASK,
9664                                          0x0);
9665                 }
9666                 break;
9667         case LED_MODE_ON:
9668
9669                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9670
9671                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9672                     SHARED_HW_CFG_LED_EXTPHY1) {
9673                         /* Set control reg */
9674                         bnx2x_cl45_read(bp, phy,
9675                                         MDIO_PMA_DEVAD,
9676                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9677                                         &val);
9678                         val &= 0x8000;
9679                         val |= 0x2492;
9680
9681                         bnx2x_cl45_write(bp, phy,
9682                                          MDIO_PMA_DEVAD,
9683                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9684                                          val);
9685
9686                         /* Set LED masks */
9687                         bnx2x_cl45_write(bp, phy,
9688                                          MDIO_PMA_DEVAD,
9689                                          MDIO_PMA_REG_8481_LED1_MASK,
9690                                          0x0);
9691
9692                         bnx2x_cl45_write(bp, phy,
9693                                          MDIO_PMA_DEVAD,
9694                                          MDIO_PMA_REG_8481_LED2_MASK,
9695                                          0x20);
9696
9697                         bnx2x_cl45_write(bp, phy,
9698                                          MDIO_PMA_DEVAD,
9699                                          MDIO_PMA_REG_8481_LED3_MASK,
9700                                          0x20);
9701
9702                         bnx2x_cl45_write(bp, phy,
9703                                          MDIO_PMA_DEVAD,
9704                                          MDIO_PMA_REG_8481_LED5_MASK,
9705                                          0x0);
9706                 } else {
9707                         bnx2x_cl45_write(bp, phy,
9708                                          MDIO_PMA_DEVAD,
9709                                          MDIO_PMA_REG_8481_LED1_MASK,
9710                                          0x20);
9711                 }
9712                 break;
9713
9714         case LED_MODE_OPER:
9715
9716                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9717
9718                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9719                     SHARED_HW_CFG_LED_EXTPHY1) {
9720
9721                         /* Set control reg */
9722                         bnx2x_cl45_read(bp, phy,
9723                                         MDIO_PMA_DEVAD,
9724                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9725                                         &val);
9726
9727                         if (!((val &
9728                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9729                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9730                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9731                                 bnx2x_cl45_write(bp, phy,
9732                                                  MDIO_PMA_DEVAD,
9733                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
9734                                                  0xa492);
9735                         }
9736
9737                         /* Set LED masks */
9738                         bnx2x_cl45_write(bp, phy,
9739                                          MDIO_PMA_DEVAD,
9740                                          MDIO_PMA_REG_8481_LED1_MASK,
9741                                          0x10);
9742
9743                         bnx2x_cl45_write(bp, phy,
9744                                          MDIO_PMA_DEVAD,
9745                                          MDIO_PMA_REG_8481_LED2_MASK,
9746                                          0x80);
9747
9748                         bnx2x_cl45_write(bp, phy,
9749                                          MDIO_PMA_DEVAD,
9750                                          MDIO_PMA_REG_8481_LED3_MASK,
9751                                          0x98);
9752
9753                         bnx2x_cl45_write(bp, phy,
9754                                          MDIO_PMA_DEVAD,
9755                                          MDIO_PMA_REG_8481_LED5_MASK,
9756                                          0x40);
9757
9758                 } else {
9759                         bnx2x_cl45_write(bp, phy,
9760                                          MDIO_PMA_DEVAD,
9761                                          MDIO_PMA_REG_8481_LED1_MASK,
9762                                          0x80);
9763
9764                         /* Tell LED3 to blink on source */
9765                         bnx2x_cl45_read(bp, phy,
9766                                         MDIO_PMA_DEVAD,
9767                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9768                                         &val);
9769                         val &= ~(7<<6);
9770                         val |= (1<<6); /* A83B[8:6]= 1 */
9771                         bnx2x_cl45_write(bp, phy,
9772                                          MDIO_PMA_DEVAD,
9773                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9774                                          val);
9775                 }
9776                 break;
9777         }
9778
9779         /*
9780          * This is a workaround for E3+84833 until autoneg
9781          * restart is fixed in f/w
9782          */
9783         if (CHIP_IS_E3(bp)) {
9784                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9785                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9786         }
9787 }
9788
9789 /******************************************************************/
9790 /*                      54616S PHY SECTION                        */
9791 /******************************************************************/
9792 static int bnx2x_54616s_config_init(struct bnx2x_phy *phy,
9793                                                struct link_params *params,
9794                                                struct link_vars *vars)
9795 {
9796         struct bnx2x *bp = params->bp;
9797         u8 port;
9798         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
9799         u32 cfg_pin;
9800
9801         DP(NETIF_MSG_LINK, "54616S cfg init\n");
9802         usleep_range(1000, 1000);
9803
9804         /* This works with E3 only, no need to check the chip
9805            before determining the port. */
9806         port = params->port;
9807
9808         cfg_pin = (REG_RD(bp, params->shmem_base +
9809                         offsetof(struct shmem_region,
9810                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
9811                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9812                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9813
9814         /* Drive pin high to bring the GPHY out of reset. */
9815         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
9816
9817         /* wait for GPHY to reset */
9818         msleep(50);
9819
9820         /* reset phy */
9821         bnx2x_cl22_write(bp, phy,
9822                          MDIO_PMA_REG_CTRL, 0x8000);
9823         bnx2x_wait_reset_complete(bp, phy, params);
9824
9825         /*wait for GPHY to reset */
9826         msleep(50);
9827
9828         /* Configure LED4: set to INTR (0x6). */
9829         /* Accessing shadow register 0xe. */
9830         bnx2x_cl22_write(bp, phy,
9831                         MDIO_REG_GPHY_SHADOW,
9832                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
9833         bnx2x_cl22_read(bp, phy,
9834                         MDIO_REG_GPHY_SHADOW,
9835                         &temp);
9836         temp &= ~(0xf << 4);
9837         temp |= (0x6 << 4);
9838         bnx2x_cl22_write(bp, phy,
9839                         MDIO_REG_GPHY_SHADOW,
9840                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
9841         /* Configure INTR based on link status change. */
9842         bnx2x_cl22_write(bp, phy,
9843                         MDIO_REG_INTR_MASK,
9844                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
9845
9846         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
9847         bnx2x_cl22_write(bp, phy,
9848                         MDIO_REG_GPHY_SHADOW,
9849                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
9850         bnx2x_cl22_read(bp, phy,
9851                         MDIO_REG_GPHY_SHADOW,
9852                         &temp);
9853         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
9854         bnx2x_cl22_write(bp, phy,
9855                         MDIO_REG_GPHY_SHADOW,
9856                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
9857
9858         /* Set up fc */
9859         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
9860         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
9861         fc_val = 0;
9862         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
9863                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
9864                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
9865
9866         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
9867                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
9868                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
9869
9870         /* read all advertisement */
9871         bnx2x_cl22_read(bp, phy,
9872                         0x09,
9873                         &an_1000_val);
9874
9875         bnx2x_cl22_read(bp, phy,
9876                         0x04,
9877                         &an_10_100_val);
9878
9879         bnx2x_cl22_read(bp, phy,
9880                         MDIO_PMA_REG_CTRL,
9881                         &autoneg_val);
9882
9883         /* Disable forced speed */
9884         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9885         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
9886                            (1<<11));
9887
9888         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9889                         (phy->speed_cap_mask &
9890                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9891                         (phy->req_line_speed == SPEED_1000)) {
9892                 an_1000_val |= (1<<8);
9893                 autoneg_val |= (1<<9 | 1<<12);
9894                 if (phy->req_duplex == DUPLEX_FULL)
9895                         an_1000_val |= (1<<9);
9896                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9897         } else
9898                 an_1000_val &= ~((1<<8) | (1<<9));
9899
9900         bnx2x_cl22_write(bp, phy,
9901                         0x09,
9902                         an_1000_val);
9903         bnx2x_cl22_read(bp, phy,
9904                         0x09,
9905                         &an_1000_val);
9906
9907         /* set 100 speed advertisement */
9908         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9909                         (phy->speed_cap_mask &
9910                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9911                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
9912                 an_10_100_val |= (1<<7);
9913                 /* Enable autoneg and restart autoneg for legacy speeds */
9914                 autoneg_val |= (1<<9 | 1<<12);
9915
9916                 if (phy->req_duplex == DUPLEX_FULL)
9917                         an_10_100_val |= (1<<8);
9918                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9919         }
9920
9921         /* set 10 speed advertisement */
9922         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9923                         (phy->speed_cap_mask &
9924                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9925                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
9926                 an_10_100_val |= (1<<5);
9927                 autoneg_val |= (1<<9 | 1<<12);
9928                 if (phy->req_duplex == DUPLEX_FULL)
9929                         an_10_100_val |= (1<<6);
9930                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9931         }
9932
9933         /* Only 10/100 are allowed to work in FORCE mode */
9934         if (phy->req_line_speed == SPEED_100) {
9935                 autoneg_val |= (1<<13);
9936                 /* Enabled AUTO-MDIX when autoneg is disabled */
9937                 bnx2x_cl22_write(bp, phy,
9938                                 0x18,
9939                                 (1<<15 | 1<<9 | 7<<0));
9940                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9941         }
9942         if (phy->req_line_speed == SPEED_10) {
9943                 /* Enabled AUTO-MDIX when autoneg is disabled */
9944                 bnx2x_cl22_write(bp, phy,
9945                                 0x18,
9946                                 (1<<15 | 1<<9 | 7<<0));
9947                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9948         }
9949
9950         bnx2x_cl22_write(bp, phy,
9951                         0x04,
9952                         an_10_100_val | fc_val);
9953
9954         if (phy->req_duplex == DUPLEX_FULL)
9955                 autoneg_val |= (1<<8);
9956
9957         bnx2x_cl22_write(bp, phy,
9958                         MDIO_PMA_REG_CTRL, autoneg_val);
9959
9960         return 0;
9961 }
9962
9963 static void bnx2x_54616s_set_link_led(struct bnx2x_phy *phy,
9964                                       struct link_params *params, u8 mode)
9965 {
9966         struct bnx2x *bp = params->bp;
9967         DP(NETIF_MSG_LINK, "54616S set link led (mode=%x)\n", mode);
9968         switch (mode) {
9969         case LED_MODE_FRONT_PANEL_OFF:
9970         case LED_MODE_OFF:
9971         case LED_MODE_OPER:
9972         case LED_MODE_ON:
9973         default:
9974                 break;
9975         }
9976         return;
9977 }
9978
9979 static void bnx2x_54616s_link_reset(struct bnx2x_phy *phy,
9980                                     struct link_params *params)
9981 {
9982         struct bnx2x *bp = params->bp;
9983         u32 cfg_pin;
9984         u8 port;
9985
9986         /* This works with E3 only, no need to check the chip
9987            before determining the port. */
9988         port = params->port;
9989         cfg_pin = (REG_RD(bp, params->shmem_base +
9990                         offsetof(struct shmem_region,
9991                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
9992                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9993                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9994
9995         /* Drive pin low to put GPHY in reset. */
9996         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
9997 }
9998
9999 static u8 bnx2x_54616s_read_status(struct bnx2x_phy *phy,
10000                                    struct link_params *params,
10001                                    struct link_vars *vars)
10002 {
10003         struct bnx2x *bp = params->bp;
10004         u16 val;
10005         u8 link_up = 0;
10006         u16 legacy_status, legacy_speed;
10007
10008         /* Get speed operation status */
10009         bnx2x_cl22_read(bp, phy,
10010                         0x19,
10011                         &legacy_status);
10012         DP(NETIF_MSG_LINK, "54616S read_status: 0x%x\n", legacy_status);
10013
10014         /* Read status to clear the PHY interrupt. */
10015         bnx2x_cl22_read(bp, phy,
10016                         MDIO_REG_INTR_STATUS,
10017                         &val);
10018
10019         link_up = ((legacy_status & (1<<2)) == (1<<2));
10020
10021         if (link_up) {
10022                 legacy_speed = (legacy_status & (7<<8));
10023                 if (legacy_speed == (7<<8)) {
10024                         vars->line_speed = SPEED_1000;
10025                         vars->duplex = DUPLEX_FULL;
10026                 } else if (legacy_speed == (6<<8)) {
10027                         vars->line_speed = SPEED_1000;
10028                         vars->duplex = DUPLEX_HALF;
10029                 } else if (legacy_speed == (5<<8)) {
10030                         vars->line_speed = SPEED_100;
10031                         vars->duplex = DUPLEX_FULL;
10032                 }
10033                 /* Omitting 100Base-T4 for now */
10034                 else if (legacy_speed == (3<<8)) {
10035                         vars->line_speed = SPEED_100;
10036                         vars->duplex = DUPLEX_HALF;
10037                 } else if (legacy_speed == (2<<8)) {
10038                         vars->line_speed = SPEED_10;
10039                         vars->duplex = DUPLEX_FULL;
10040                 } else if (legacy_speed == (1<<8)) {
10041                         vars->line_speed = SPEED_10;
10042                         vars->duplex = DUPLEX_HALF;
10043                 } else /* Should not happen */
10044                         vars->line_speed = 0;
10045
10046                 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10047                            " is_duplex_full= %d\n", vars->line_speed,
10048                            (vars->duplex == DUPLEX_FULL));
10049
10050                 /* Check legacy speed AN resolution */
10051                 bnx2x_cl22_read(bp, phy,
10052                                 0x01,
10053                                 &val);
10054                 if (val & (1<<5))
10055                         vars->link_status |=
10056                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10057                 bnx2x_cl22_read(bp, phy,
10058                                 0x06,
10059                                 &val);
10060                 if ((val & (1<<0)) == 0)
10061                         vars->link_status |=
10062                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10063
10064                 DP(NETIF_MSG_LINK, "BCM54616S: link speed is %d\n",
10065                            vars->line_speed);
10066                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10067         }
10068         return link_up;
10069 }
10070
10071 static void bnx2x_54616s_config_loopback(struct bnx2x_phy *phy,
10072                                        struct link_params *params)
10073 {
10074         struct bnx2x *bp = params->bp;
10075         u16 val;
10076         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10077
10078         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54616s\n");
10079
10080         /* Enable master/slave manual mmode and set to master */
10081         /* mii write 9 [bits set 11 12] */
10082         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10083
10084         /* forced 1G and disable autoneg */
10085         /* set val [mii read 0] */
10086         /* set val [expr $val & [bits clear 6 12 13]] */
10087         /* set val [expr $val | [bits set 6 8]] */
10088         /* mii write 0 $val */
10089         bnx2x_cl22_read(bp, phy, 0x00, &val);
10090         val &= ~((1<<6) | (1<<12) | (1<<13));
10091         val |= (1<<6) | (1<<8);
10092         bnx2x_cl22_write(bp, phy, 0x00, val);
10093
10094         /* Set external loopback and Tx using 6dB coding */
10095         /* mii write 0x18 7 */
10096         /* set val [mii read 0x18] */
10097         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10098         bnx2x_cl22_write(bp, phy, 0x18, 7);
10099         bnx2x_cl22_read(bp, phy, 0x18, &val);
10100         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10101
10102         /* This register opens the gate for the UMAC despite its name */
10103         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10104
10105         /*
10106          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10107          * length used by the MAC receive logic to check frames.
10108          */
10109         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10110 }
10111
10112 /******************************************************************/
10113 /*                      SFX7101 PHY SECTION                       */
10114 /******************************************************************/
10115 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10116                                        struct link_params *params)
10117 {
10118         struct bnx2x *bp = params->bp;
10119         /* SFX7101_XGXS_TEST1 */
10120         bnx2x_cl45_write(bp, phy,
10121                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10122 }
10123
10124 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10125                                   struct link_params *params,
10126                                   struct link_vars *vars)
10127 {
10128         u16 fw_ver1, fw_ver2, val;
10129         struct bnx2x *bp = params->bp;
10130         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10131
10132         /* Restore normal power mode*/
10133         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10134                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10135         /* HW reset */
10136         bnx2x_ext_phy_hw_reset(bp, params->port);
10137         bnx2x_wait_reset_complete(bp, phy, params);
10138
10139         bnx2x_cl45_write(bp, phy,
10140                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10141         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10142         bnx2x_cl45_write(bp, phy,
10143                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10144
10145         bnx2x_ext_phy_set_pause(params, phy, vars);
10146         /* Restart autoneg */
10147         bnx2x_cl45_read(bp, phy,
10148                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10149         val |= 0x200;
10150         bnx2x_cl45_write(bp, phy,
10151                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10152
10153         /* Save spirom version */
10154         bnx2x_cl45_read(bp, phy,
10155                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10156
10157         bnx2x_cl45_read(bp, phy,
10158                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10159         bnx2x_save_spirom_version(bp, params->port,
10160                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10161         return 0;
10162 }
10163
10164 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10165                                  struct link_params *params,
10166                                  struct link_vars *vars)
10167 {
10168         struct bnx2x *bp = params->bp;
10169         u8 link_up;
10170         u16 val1, val2;
10171         bnx2x_cl45_read(bp, phy,
10172                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10173         bnx2x_cl45_read(bp, phy,
10174                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10175         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10176                    val2, val1);
10177         bnx2x_cl45_read(bp, phy,
10178                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10179         bnx2x_cl45_read(bp, phy,
10180                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10181         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10182                    val2, val1);
10183         link_up = ((val1 & 4) == 4);
10184         /* if link is up print the AN outcome of the SFX7101 PHY */
10185         if (link_up) {
10186                 bnx2x_cl45_read(bp, phy,
10187                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10188                                 &val2);
10189                 vars->line_speed = SPEED_10000;
10190                 vars->duplex = DUPLEX_FULL;
10191                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10192                            val2, (val2 & (1<<14)));
10193                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10194                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10195         }
10196         return link_up;
10197 }
10198
10199 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10200 {
10201         if (*len < 5)
10202                 return -EINVAL;
10203         str[0] = (spirom_ver & 0xFF);
10204         str[1] = (spirom_ver & 0xFF00) >> 8;
10205         str[2] = (spirom_ver & 0xFF0000) >> 16;
10206         str[3] = (spirom_ver & 0xFF000000) >> 24;
10207         str[4] = '\0';
10208         *len -= 5;
10209         return 0;
10210 }
10211
10212 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10213 {
10214         u16 val, cnt;
10215
10216         bnx2x_cl45_read(bp, phy,
10217                         MDIO_PMA_DEVAD,
10218                         MDIO_PMA_REG_7101_RESET, &val);
10219
10220         for (cnt = 0; cnt < 10; cnt++) {
10221                 msleep(50);
10222                 /* Writes a self-clearing reset */
10223                 bnx2x_cl45_write(bp, phy,
10224                                  MDIO_PMA_DEVAD,
10225                                  MDIO_PMA_REG_7101_RESET,
10226                                  (val | (1<<15)));
10227                 /* Wait for clear */
10228                 bnx2x_cl45_read(bp, phy,
10229                                 MDIO_PMA_DEVAD,
10230                                 MDIO_PMA_REG_7101_RESET, &val);
10231
10232                 if ((val & (1<<15)) == 0)
10233                         break;
10234         }
10235 }
10236
10237 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10238                                 struct link_params *params) {
10239         /* Low power mode is controlled by GPIO 2 */
10240         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10241                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10242         /* The PHY reset is controlled by GPIO 1 */
10243         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10244                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10245 }
10246
10247 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10248                                     struct link_params *params, u8 mode)
10249 {
10250         u16 val = 0;
10251         struct bnx2x *bp = params->bp;
10252         switch (mode) {
10253         case LED_MODE_FRONT_PANEL_OFF:
10254         case LED_MODE_OFF:
10255                 val = 2;
10256                 break;
10257         case LED_MODE_ON:
10258                 val = 1;
10259                 break;
10260         case LED_MODE_OPER:
10261                 val = 0;
10262                 break;
10263         }
10264         bnx2x_cl45_write(bp, phy,
10265                          MDIO_PMA_DEVAD,
10266                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10267                          val);
10268 }
10269
10270 /******************************************************************/
10271 /*                      STATIC PHY DECLARATION                    */
10272 /******************************************************************/
10273
10274 static struct bnx2x_phy phy_null = {
10275         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10276         .addr           = 0,
10277         .def_md_devad   = 0,
10278         .flags          = FLAGS_INIT_XGXS_FIRST,
10279         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10280         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10281         .mdio_ctrl      = 0,
10282         .supported      = 0,
10283         .media_type     = ETH_PHY_NOT_PRESENT,
10284         .ver_addr       = 0,
10285         .req_flow_ctrl  = 0,
10286         .req_line_speed = 0,
10287         .speed_cap_mask = 0,
10288         .req_duplex     = 0,
10289         .rsrv           = 0,
10290         .config_init    = (config_init_t)NULL,
10291         .read_status    = (read_status_t)NULL,
10292         .link_reset     = (link_reset_t)NULL,
10293         .config_loopback = (config_loopback_t)NULL,
10294         .format_fw_ver  = (format_fw_ver_t)NULL,
10295         .hw_reset       = (hw_reset_t)NULL,
10296         .set_link_led   = (set_link_led_t)NULL,
10297         .phy_specific_func = (phy_specific_func_t)NULL
10298 };
10299
10300 static struct bnx2x_phy phy_serdes = {
10301         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10302         .addr           = 0xff,
10303         .def_md_devad   = 0,
10304         .flags          = 0,
10305         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10306         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10307         .mdio_ctrl      = 0,
10308         .supported      = (SUPPORTED_10baseT_Half |
10309                            SUPPORTED_10baseT_Full |
10310                            SUPPORTED_100baseT_Half |
10311                            SUPPORTED_100baseT_Full |
10312                            SUPPORTED_1000baseT_Full |
10313                            SUPPORTED_2500baseX_Full |
10314                            SUPPORTED_TP |
10315                            SUPPORTED_Autoneg |
10316                            SUPPORTED_Pause |
10317                            SUPPORTED_Asym_Pause),
10318         .media_type     = ETH_PHY_BASE_T,
10319         .ver_addr       = 0,
10320         .req_flow_ctrl  = 0,
10321         .req_line_speed = 0,
10322         .speed_cap_mask = 0,
10323         .req_duplex     = 0,
10324         .rsrv           = 0,
10325         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10326         .read_status    = (read_status_t)bnx2x_link_settings_status,
10327         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10328         .config_loopback = (config_loopback_t)NULL,
10329         .format_fw_ver  = (format_fw_ver_t)NULL,
10330         .hw_reset       = (hw_reset_t)NULL,
10331         .set_link_led   = (set_link_led_t)NULL,
10332         .phy_specific_func = (phy_specific_func_t)NULL
10333 };
10334
10335 static struct bnx2x_phy phy_xgxs = {
10336         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10337         .addr           = 0xff,
10338         .def_md_devad   = 0,
10339         .flags          = 0,
10340         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10341         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10342         .mdio_ctrl      = 0,
10343         .supported      = (SUPPORTED_10baseT_Half |
10344                            SUPPORTED_10baseT_Full |
10345                            SUPPORTED_100baseT_Half |
10346                            SUPPORTED_100baseT_Full |
10347                            SUPPORTED_1000baseT_Full |
10348                            SUPPORTED_2500baseX_Full |
10349                            SUPPORTED_10000baseT_Full |
10350                            SUPPORTED_FIBRE |
10351                            SUPPORTED_Autoneg |
10352                            SUPPORTED_Pause |
10353                            SUPPORTED_Asym_Pause),
10354         .media_type     = ETH_PHY_CX4,
10355         .ver_addr       = 0,
10356         .req_flow_ctrl  = 0,
10357         .req_line_speed = 0,
10358         .speed_cap_mask = 0,
10359         .req_duplex     = 0,
10360         .rsrv           = 0,
10361         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10362         .read_status    = (read_status_t)bnx2x_link_settings_status,
10363         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10364         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10365         .format_fw_ver  = (format_fw_ver_t)NULL,
10366         .hw_reset       = (hw_reset_t)NULL,
10367         .set_link_led   = (set_link_led_t)NULL,
10368         .phy_specific_func = (phy_specific_func_t)NULL
10369 };
10370 static struct bnx2x_phy phy_warpcore = {
10371         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10372         .addr           = 0xff,
10373         .def_md_devad   = 0,
10374         .flags          = FLAGS_HW_LOCK_REQUIRED,
10375         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10376         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10377         .mdio_ctrl      = 0,
10378         .supported      = (SUPPORTED_10baseT_Half |
10379                              SUPPORTED_10baseT_Full |
10380                              SUPPORTED_100baseT_Half |
10381                              SUPPORTED_100baseT_Full |
10382                              SUPPORTED_1000baseT_Full |
10383                              SUPPORTED_10000baseT_Full |
10384                              SUPPORTED_20000baseKR2_Full |
10385                              SUPPORTED_20000baseMLD2_Full |
10386                              SUPPORTED_FIBRE |
10387                              SUPPORTED_Autoneg |
10388                              SUPPORTED_Pause |
10389                              SUPPORTED_Asym_Pause),
10390         .media_type     = ETH_PHY_UNSPECIFIED,
10391         .ver_addr       = 0,
10392         .req_flow_ctrl  = 0,
10393         .req_line_speed = 0,
10394         .speed_cap_mask = 0,
10395         /* req_duplex = */0,
10396         /* rsrv = */0,
10397         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10398         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10399         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10400         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10401         .format_fw_ver  = (format_fw_ver_t)NULL,
10402         .hw_reset       = (hw_reset_t)NULL,
10403         .set_link_led   = (set_link_led_t)NULL,
10404         .phy_specific_func = (phy_specific_func_t)NULL
10405 };
10406
10407
10408 static struct bnx2x_phy phy_7101 = {
10409         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10410         .addr           = 0xff,
10411         .def_md_devad   = 0,
10412         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10413         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10414         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10415         .mdio_ctrl      = 0,
10416         .supported      = (SUPPORTED_10000baseT_Full |
10417                            SUPPORTED_TP |
10418                            SUPPORTED_Autoneg |
10419                            SUPPORTED_Pause |
10420                            SUPPORTED_Asym_Pause),
10421         .media_type     = ETH_PHY_BASE_T,
10422         .ver_addr       = 0,
10423         .req_flow_ctrl  = 0,
10424         .req_line_speed = 0,
10425         .speed_cap_mask = 0,
10426         .req_duplex     = 0,
10427         .rsrv           = 0,
10428         .config_init    = (config_init_t)bnx2x_7101_config_init,
10429         .read_status    = (read_status_t)bnx2x_7101_read_status,
10430         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10431         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10432         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
10433         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
10434         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
10435         .phy_specific_func = (phy_specific_func_t)NULL
10436 };
10437 static struct bnx2x_phy phy_8073 = {
10438         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10439         .addr           = 0xff,
10440         .def_md_devad   = 0,
10441         .flags          = FLAGS_HW_LOCK_REQUIRED,
10442         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10443         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10444         .mdio_ctrl      = 0,
10445         .supported      = (SUPPORTED_10000baseT_Full |
10446                            SUPPORTED_2500baseX_Full |
10447                            SUPPORTED_1000baseT_Full |
10448                            SUPPORTED_FIBRE |
10449                            SUPPORTED_Autoneg |
10450                            SUPPORTED_Pause |
10451                            SUPPORTED_Asym_Pause),
10452         .media_type     = ETH_PHY_KR,
10453         .ver_addr       = 0,
10454         .req_flow_ctrl  = 0,
10455         .req_line_speed = 0,
10456         .speed_cap_mask = 0,
10457         .req_duplex     = 0,
10458         .rsrv           = 0,
10459         .config_init    = (config_init_t)bnx2x_8073_config_init,
10460         .read_status    = (read_status_t)bnx2x_8073_read_status,
10461         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
10462         .config_loopback = (config_loopback_t)NULL,
10463         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10464         .hw_reset       = (hw_reset_t)NULL,
10465         .set_link_led   = (set_link_led_t)NULL,
10466         .phy_specific_func = (phy_specific_func_t)NULL
10467 };
10468 static struct bnx2x_phy phy_8705 = {
10469         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10470         .addr           = 0xff,
10471         .def_md_devad   = 0,
10472         .flags          = FLAGS_INIT_XGXS_FIRST,
10473         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10474         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10475         .mdio_ctrl      = 0,
10476         .supported      = (SUPPORTED_10000baseT_Full |
10477                            SUPPORTED_FIBRE |
10478                            SUPPORTED_Pause |
10479                            SUPPORTED_Asym_Pause),
10480         .media_type     = ETH_PHY_XFP_FIBER,
10481         .ver_addr       = 0,
10482         .req_flow_ctrl  = 0,
10483         .req_line_speed = 0,
10484         .speed_cap_mask = 0,
10485         .req_duplex     = 0,
10486         .rsrv           = 0,
10487         .config_init    = (config_init_t)bnx2x_8705_config_init,
10488         .read_status    = (read_status_t)bnx2x_8705_read_status,
10489         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10490         .config_loopback = (config_loopback_t)NULL,
10491         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
10492         .hw_reset       = (hw_reset_t)NULL,
10493         .set_link_led   = (set_link_led_t)NULL,
10494         .phy_specific_func = (phy_specific_func_t)NULL
10495 };
10496 static struct bnx2x_phy phy_8706 = {
10497         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10498         .addr           = 0xff,
10499         .def_md_devad   = 0,
10500         .flags          = FLAGS_INIT_XGXS_FIRST,
10501         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10502         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10503         .mdio_ctrl      = 0,
10504         .supported      = (SUPPORTED_10000baseT_Full |
10505                            SUPPORTED_1000baseT_Full |
10506                            SUPPORTED_FIBRE |
10507                            SUPPORTED_Pause |
10508                            SUPPORTED_Asym_Pause),
10509         .media_type     = ETH_PHY_SFP_FIBER,
10510         .ver_addr       = 0,
10511         .req_flow_ctrl  = 0,
10512         .req_line_speed = 0,
10513         .speed_cap_mask = 0,
10514         .req_duplex     = 0,
10515         .rsrv           = 0,
10516         .config_init    = (config_init_t)bnx2x_8706_config_init,
10517         .read_status    = (read_status_t)bnx2x_8706_read_status,
10518         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10519         .config_loopback = (config_loopback_t)NULL,
10520         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10521         .hw_reset       = (hw_reset_t)NULL,
10522         .set_link_led   = (set_link_led_t)NULL,
10523         .phy_specific_func = (phy_specific_func_t)NULL
10524 };
10525
10526 static struct bnx2x_phy phy_8726 = {
10527         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10528         .addr           = 0xff,
10529         .def_md_devad   = 0,
10530         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10531                            FLAGS_INIT_XGXS_FIRST),
10532         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10533         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10534         .mdio_ctrl      = 0,
10535         .supported      = (SUPPORTED_10000baseT_Full |
10536                            SUPPORTED_1000baseT_Full |
10537                            SUPPORTED_Autoneg |
10538                            SUPPORTED_FIBRE |
10539                            SUPPORTED_Pause |
10540                            SUPPORTED_Asym_Pause),
10541         .media_type     = ETH_PHY_NOT_PRESENT,
10542         .ver_addr       = 0,
10543         .req_flow_ctrl  = 0,
10544         .req_line_speed = 0,
10545         .speed_cap_mask = 0,
10546         .req_duplex     = 0,
10547         .rsrv           = 0,
10548         .config_init    = (config_init_t)bnx2x_8726_config_init,
10549         .read_status    = (read_status_t)bnx2x_8726_read_status,
10550         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
10551         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10552         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10553         .hw_reset       = (hw_reset_t)NULL,
10554         .set_link_led   = (set_link_led_t)NULL,
10555         .phy_specific_func = (phy_specific_func_t)NULL
10556 };
10557
10558 static struct bnx2x_phy phy_8727 = {
10559         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10560         .addr           = 0xff,
10561         .def_md_devad   = 0,
10562         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10563         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10564         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10565         .mdio_ctrl      = 0,
10566         .supported      = (SUPPORTED_10000baseT_Full |
10567                            SUPPORTED_1000baseT_Full |
10568                            SUPPORTED_FIBRE |
10569                            SUPPORTED_Pause |
10570                            SUPPORTED_Asym_Pause),
10571         .media_type     = ETH_PHY_NOT_PRESENT,
10572         .ver_addr       = 0,
10573         .req_flow_ctrl  = 0,
10574         .req_line_speed = 0,
10575         .speed_cap_mask = 0,
10576         .req_duplex     = 0,
10577         .rsrv           = 0,
10578         .config_init    = (config_init_t)bnx2x_8727_config_init,
10579         .read_status    = (read_status_t)bnx2x_8727_read_status,
10580         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
10581         .config_loopback = (config_loopback_t)NULL,
10582         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10583         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
10584         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
10585         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10586 };
10587 static struct bnx2x_phy phy_8481 = {
10588         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10589         .addr           = 0xff,
10590         .def_md_devad   = 0,
10591         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10592                           FLAGS_REARM_LATCH_SIGNAL,
10593         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10594         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10595         .mdio_ctrl      = 0,
10596         .supported      = (SUPPORTED_10baseT_Half |
10597                            SUPPORTED_10baseT_Full |
10598                            SUPPORTED_100baseT_Half |
10599                            SUPPORTED_100baseT_Full |
10600                            SUPPORTED_1000baseT_Full |
10601                            SUPPORTED_10000baseT_Full |
10602                            SUPPORTED_TP |
10603                            SUPPORTED_Autoneg |
10604                            SUPPORTED_Pause |
10605                            SUPPORTED_Asym_Pause),
10606         .media_type     = ETH_PHY_BASE_T,
10607         .ver_addr       = 0,
10608         .req_flow_ctrl  = 0,
10609         .req_line_speed = 0,
10610         .speed_cap_mask = 0,
10611         .req_duplex     = 0,
10612         .rsrv           = 0,
10613         .config_init    = (config_init_t)bnx2x_8481_config_init,
10614         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10615         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
10616         .config_loopback = (config_loopback_t)NULL,
10617         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10618         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
10619         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10620         .phy_specific_func = (phy_specific_func_t)NULL
10621 };
10622
10623 static struct bnx2x_phy phy_84823 = {
10624         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10625         .addr           = 0xff,
10626         .def_md_devad   = 0,
10627         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10628                           FLAGS_REARM_LATCH_SIGNAL,
10629         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10630         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10631         .mdio_ctrl      = 0,
10632         .supported      = (SUPPORTED_10baseT_Half |
10633                            SUPPORTED_10baseT_Full |
10634                            SUPPORTED_100baseT_Half |
10635                            SUPPORTED_100baseT_Full |
10636                            SUPPORTED_1000baseT_Full |
10637                            SUPPORTED_10000baseT_Full |
10638                            SUPPORTED_TP |
10639                            SUPPORTED_Autoneg |
10640                            SUPPORTED_Pause |
10641                            SUPPORTED_Asym_Pause),
10642         .media_type     = ETH_PHY_BASE_T,
10643         .ver_addr       = 0,
10644         .req_flow_ctrl  = 0,
10645         .req_line_speed = 0,
10646         .speed_cap_mask = 0,
10647         .req_duplex     = 0,
10648         .rsrv           = 0,
10649         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10650         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10651         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10652         .config_loopback = (config_loopback_t)NULL,
10653         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10654         .hw_reset       = (hw_reset_t)NULL,
10655         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10656         .phy_specific_func = (phy_specific_func_t)NULL
10657 };
10658
10659 static struct bnx2x_phy phy_84833 = {
10660         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10661         .addr           = 0xff,
10662         .def_md_devad   = 0,
10663         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10664                             FLAGS_REARM_LATCH_SIGNAL,
10665         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10666         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10667         .mdio_ctrl      = 0,
10668         .supported      = (SUPPORTED_10baseT_Half |
10669                            SUPPORTED_10baseT_Full |
10670                            SUPPORTED_100baseT_Half |
10671                            SUPPORTED_100baseT_Full |
10672                            SUPPORTED_1000baseT_Full |
10673                            SUPPORTED_10000baseT_Full |
10674                            SUPPORTED_TP |
10675                            SUPPORTED_Autoneg |
10676                            SUPPORTED_Pause |
10677                            SUPPORTED_Asym_Pause),
10678         .media_type     = ETH_PHY_BASE_T,
10679         .ver_addr       = 0,
10680         .req_flow_ctrl  = 0,
10681         .req_line_speed = 0,
10682         .speed_cap_mask = 0,
10683         .req_duplex     = 0,
10684         .rsrv           = 0,
10685         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10686         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10687         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10688         .config_loopback = (config_loopback_t)NULL,
10689         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10690         .hw_reset       = (hw_reset_t)NULL,
10691         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10692         .phy_specific_func = (phy_specific_func_t)NULL
10693 };
10694
10695 static struct bnx2x_phy phy_54616s = {
10696         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616,
10697         .addr           = 0xff,
10698         .def_md_devad   = 0,
10699         .flags          = FLAGS_INIT_XGXS_FIRST,
10700         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10701         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10702         .mdio_ctrl      = 0,
10703         .supported      = (SUPPORTED_10baseT_Half |
10704                            SUPPORTED_10baseT_Full |
10705                            SUPPORTED_100baseT_Half |
10706                            SUPPORTED_100baseT_Full |
10707                            SUPPORTED_1000baseT_Full |
10708                            SUPPORTED_TP |
10709                            SUPPORTED_Autoneg |
10710                            SUPPORTED_Pause |
10711                            SUPPORTED_Asym_Pause),
10712         .media_type     = ETH_PHY_BASE_T,
10713         .ver_addr       = 0,
10714         .req_flow_ctrl  = 0,
10715         .req_line_speed = 0,
10716         .speed_cap_mask = 0,
10717         /* req_duplex = */0,
10718         /* rsrv = */0,
10719         .config_init    = (config_init_t)bnx2x_54616s_config_init,
10720         .read_status    = (read_status_t)bnx2x_54616s_read_status,
10721         .link_reset     = (link_reset_t)bnx2x_54616s_link_reset,
10722         .config_loopback = (config_loopback_t)bnx2x_54616s_config_loopback,
10723         .format_fw_ver  = (format_fw_ver_t)NULL,
10724         .hw_reset       = (hw_reset_t)NULL,
10725         .set_link_led   = (set_link_led_t)bnx2x_54616s_set_link_led,
10726         .phy_specific_func = (phy_specific_func_t)NULL
10727 };
10728 /*****************************************************************/
10729 /*                                                               */
10730 /* Populate the phy according. Main function: bnx2x_populate_phy   */
10731 /*                                                               */
10732 /*****************************************************************/
10733
10734 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
10735                                      struct bnx2x_phy *phy, u8 port,
10736                                      u8 phy_index)
10737 {
10738         /* Get the 4 lanes xgxs config rx and tx */
10739         u32 rx = 0, tx = 0, i;
10740         for (i = 0; i < 2; i++) {
10741                 /*
10742                  * INT_PHY and EXT_PHY1 share the same value location in the
10743                  * shmem. When num_phys is greater than 1, than this value
10744                  * applies only to EXT_PHY1
10745                  */
10746                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
10747                         rx = REG_RD(bp, shmem_base +
10748                                     offsetof(struct shmem_region,
10749                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
10750
10751                         tx = REG_RD(bp, shmem_base +
10752                                     offsetof(struct shmem_region,
10753                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
10754                 } else {
10755                         rx = REG_RD(bp, shmem_base +
10756                                     offsetof(struct shmem_region,
10757                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10758
10759                         tx = REG_RD(bp, shmem_base +
10760                                     offsetof(struct shmem_region,
10761                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10762                 }
10763
10764                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
10765                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
10766
10767                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
10768                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
10769         }
10770 }
10771
10772 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
10773                                     u8 phy_index, u8 port)
10774 {
10775         u32 ext_phy_config = 0;
10776         switch (phy_index) {
10777         case EXT_PHY1:
10778                 ext_phy_config = REG_RD(bp, shmem_base +
10779                                               offsetof(struct shmem_region,
10780                         dev_info.port_hw_config[port].external_phy_config));
10781                 break;
10782         case EXT_PHY2:
10783                 ext_phy_config = REG_RD(bp, shmem_base +
10784                                               offsetof(struct shmem_region,
10785                         dev_info.port_hw_config[port].external_phy_config2));
10786                 break;
10787         default:
10788                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
10789                 return -EINVAL;
10790         }
10791
10792         return ext_phy_config;
10793 }
10794 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
10795                                   struct bnx2x_phy *phy)
10796 {
10797         u32 phy_addr;
10798         u32 chip_id;
10799         u32 switch_cfg = (REG_RD(bp, shmem_base +
10800                                        offsetof(struct shmem_region,
10801                         dev_info.port_feature_config[port].link_config)) &
10802                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
10803         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
10804         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
10805         if (USES_WARPCORE(bp)) {
10806                 u32 serdes_net_if;
10807                 phy_addr = REG_RD(bp,
10808                                   MISC_REG_WC0_CTRL_PHY_ADDR);
10809                 *phy = phy_warpcore;
10810                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
10811                         phy->flags |= FLAGS_4_PORT_MODE;
10812                 else
10813                         phy->flags &= ~FLAGS_4_PORT_MODE;
10814                         /* Check Dual mode */
10815                 serdes_net_if = (REG_RD(bp, shmem_base +
10816                                         offsetof(struct shmem_region, dev_info.
10817                                         port_hw_config[port].default_cfg)) &
10818                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
10819                 /*
10820                  * Set the appropriate supported and flags indications per
10821                  * interface type of the chip
10822                  */
10823                 switch (serdes_net_if) {
10824                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
10825                         phy->supported &= (SUPPORTED_10baseT_Half |
10826                                            SUPPORTED_10baseT_Full |
10827                                            SUPPORTED_100baseT_Half |
10828                                            SUPPORTED_100baseT_Full |
10829                                            SUPPORTED_1000baseT_Full |
10830                                            SUPPORTED_FIBRE |
10831                                            SUPPORTED_Autoneg |
10832                                            SUPPORTED_Pause |
10833                                            SUPPORTED_Asym_Pause);
10834                         phy->media_type = ETH_PHY_BASE_T;
10835                         break;
10836                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
10837                         phy->media_type = ETH_PHY_XFP_FIBER;
10838                         break;
10839                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
10840                         phy->supported &= (SUPPORTED_1000baseT_Full |
10841                                            SUPPORTED_10000baseT_Full |
10842                                            SUPPORTED_FIBRE |
10843                                            SUPPORTED_Pause |
10844                                            SUPPORTED_Asym_Pause);
10845                         phy->media_type = ETH_PHY_SFP_FIBER;
10846                         break;
10847                 case PORT_HW_CFG_NET_SERDES_IF_KR:
10848                         phy->media_type = ETH_PHY_KR;
10849                         phy->supported &= (SUPPORTED_1000baseT_Full |
10850                                            SUPPORTED_10000baseT_Full |
10851                                            SUPPORTED_FIBRE |
10852                                            SUPPORTED_Autoneg |
10853                                            SUPPORTED_Pause |
10854                                            SUPPORTED_Asym_Pause);
10855                         break;
10856                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
10857                         phy->media_type = ETH_PHY_KR;
10858                         phy->flags |= FLAGS_WC_DUAL_MODE;
10859                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
10860                                            SUPPORTED_FIBRE |
10861                                            SUPPORTED_Pause |
10862                                            SUPPORTED_Asym_Pause);
10863                         break;
10864                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
10865                         phy->media_type = ETH_PHY_KR;
10866                         phy->flags |= FLAGS_WC_DUAL_MODE;
10867                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
10868                                            SUPPORTED_FIBRE |
10869                                            SUPPORTED_Pause |
10870                                            SUPPORTED_Asym_Pause);
10871                         break;
10872                 default:
10873                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
10874                                        serdes_net_if);
10875                         break;
10876                 }
10877
10878                 /*
10879                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
10880                  * was not set as expected. For B0, ECO will be enabled so there
10881                  * won't be an issue there
10882                  */
10883                 if (CHIP_REV(bp) == CHIP_REV_Ax)
10884                         phy->flags |= FLAGS_MDC_MDIO_WA;
10885         } else {
10886                 switch (switch_cfg) {
10887                 case SWITCH_CFG_1G:
10888                         phy_addr = REG_RD(bp,
10889                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
10890                                           port * 0x10);
10891                         *phy = phy_serdes;
10892                         break;
10893                 case SWITCH_CFG_10G:
10894                         phy_addr = REG_RD(bp,
10895                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
10896                                           port * 0x18);
10897                         *phy = phy_xgxs;
10898                         break;
10899                 default:
10900                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
10901                         return -EINVAL;
10902                 }
10903         }
10904         phy->addr = (u8)phy_addr;
10905         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
10906                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
10907                                             port);
10908         if (CHIP_IS_E2(bp))
10909                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
10910         else
10911                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
10912
10913         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
10914                    port, phy->addr, phy->mdio_ctrl);
10915
10916         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
10917         return 0;
10918 }
10919
10920 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
10921                                   u8 phy_index,
10922                                   u32 shmem_base,
10923                                   u32 shmem2_base,
10924                                   u8 port,
10925                                   struct bnx2x_phy *phy)
10926 {
10927         u32 ext_phy_config, phy_type, config2;
10928         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
10929         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
10930                                                   phy_index, port);
10931         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10932         /* Select the phy type */
10933         switch (phy_type) {
10934         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
10935                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
10936                 *phy = phy_8073;
10937                 break;
10938         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
10939                 *phy = phy_8705;
10940                 break;
10941         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
10942                 *phy = phy_8706;
10943                 break;
10944         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
10945                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
10946                 *phy = phy_8726;
10947                 break;
10948         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
10949                 /* BCM8727_NOC => BCM8727 no over current */
10950                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
10951                 *phy = phy_8727;
10952                 phy->flags |= FLAGS_NOC;
10953                 break;
10954         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
10955         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
10956                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
10957                 *phy = phy_8727;
10958                 break;
10959         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
10960                 *phy = phy_8481;
10961                 break;
10962         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
10963                 *phy = phy_84823;
10964                 break;
10965         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
10966                 *phy = phy_84833;
10967                 break;
10968         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
10969                 *phy = phy_54616s;
10970                 break;
10971         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
10972                 *phy = phy_7101;
10973                 break;
10974         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
10975                 *phy = phy_null;
10976                 return -EINVAL;
10977         default:
10978                 *phy = phy_null;
10979                 return 0;
10980         }
10981
10982         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
10983         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
10984
10985         /*
10986          * The shmem address of the phy version is located on different
10987          * structures. In case this structure is too old, do not set
10988          * the address
10989          */
10990         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
10991                                         dev_info.shared_hw_config.config2));
10992         if (phy_index == EXT_PHY1) {
10993                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
10994                                 port_mb[port].ext_phy_fw_version);
10995
10996                 /* Check specific mdc mdio settings */
10997                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
10998                         mdc_mdio_access = config2 &
10999                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11000         } else {
11001                 u32 size = REG_RD(bp, shmem2_base);
11002
11003                 if (size >
11004                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11005                         phy->ver_addr = shmem2_base +
11006                             offsetof(struct shmem2_region,
11007                                      ext_phy_fw_version2[port]);
11008                 }
11009                 /* Check specific mdc mdio settings */
11010                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11011                         mdc_mdio_access = (config2 &
11012                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11013                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11014                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11015         }
11016         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11017
11018         /*
11019          * In case mdc/mdio_access of the external phy is different than the
11020          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11021          * to prevent one port interfere with another port's CL45 operations.
11022          */
11023         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11024                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11025         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11026                    phy_type, port, phy_index);
11027         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11028                    phy->addr, phy->mdio_ctrl);
11029         return 0;
11030 }
11031
11032 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11033                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11034 {
11035         int status = 0;
11036         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11037         if (phy_index == INT_PHY)
11038                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11039         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11040                                         port, phy);
11041         return status;
11042 }
11043
11044 static void bnx2x_phy_def_cfg(struct link_params *params,
11045                               struct bnx2x_phy *phy,
11046                               u8 phy_index)
11047 {
11048         struct bnx2x *bp = params->bp;
11049         u32 link_config;
11050         /* Populate the default phy configuration for MF mode */
11051         if (phy_index == EXT_PHY2) {
11052                 link_config = REG_RD(bp, params->shmem_base +
11053                                      offsetof(struct shmem_region, dev_info.
11054                         port_feature_config[params->port].link_config2));
11055                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11056                                              offsetof(struct shmem_region,
11057                                                       dev_info.
11058                         port_hw_config[params->port].speed_capability_mask2));
11059         } else {
11060                 link_config = REG_RD(bp, params->shmem_base +
11061                                      offsetof(struct shmem_region, dev_info.
11062                                 port_feature_config[params->port].link_config));
11063                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11064                                              offsetof(struct shmem_region,
11065                                                       dev_info.
11066                         port_hw_config[params->port].speed_capability_mask));
11067         }
11068         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11069                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11070
11071         phy->req_duplex = DUPLEX_FULL;
11072         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11073         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11074                 phy->req_duplex = DUPLEX_HALF;
11075         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11076                 phy->req_line_speed = SPEED_10;
11077                 break;
11078         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11079                 phy->req_duplex = DUPLEX_HALF;
11080         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11081                 phy->req_line_speed = SPEED_100;
11082                 break;
11083         case PORT_FEATURE_LINK_SPEED_1G:
11084                 phy->req_line_speed = SPEED_1000;
11085                 break;
11086         case PORT_FEATURE_LINK_SPEED_2_5G:
11087                 phy->req_line_speed = SPEED_2500;
11088                 break;
11089         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11090                 phy->req_line_speed = SPEED_10000;
11091                 break;
11092         default:
11093                 phy->req_line_speed = SPEED_AUTO_NEG;
11094                 break;
11095         }
11096
11097         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11098         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11099                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11100                 break;
11101         case PORT_FEATURE_FLOW_CONTROL_TX:
11102                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11103                 break;
11104         case PORT_FEATURE_FLOW_CONTROL_RX:
11105                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11106                 break;
11107         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11108                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11109                 break;
11110         default:
11111                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11112                 break;
11113         }
11114 }
11115
11116 u32 bnx2x_phy_selection(struct link_params *params)
11117 {
11118         u32 phy_config_swapped, prio_cfg;
11119         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11120
11121         phy_config_swapped = params->multi_phy_config &
11122                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11123
11124         prio_cfg = params->multi_phy_config &
11125                         PORT_HW_CFG_PHY_SELECTION_MASK;
11126
11127         if (phy_config_swapped) {
11128                 switch (prio_cfg) {
11129                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11130                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11131                      break;
11132                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11133                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11134                      break;
11135                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11136                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11137                      break;
11138                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11139                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11140                      break;
11141                 }
11142         } else
11143                 return_cfg = prio_cfg;
11144
11145         return return_cfg;
11146 }
11147
11148
11149 int bnx2x_phy_probe(struct link_params *params)
11150 {
11151         u8 phy_index, actual_phy_idx, link_cfg_idx;
11152         u32 phy_config_swapped, sync_offset, media_types;
11153         struct bnx2x *bp = params->bp;
11154         struct bnx2x_phy *phy;
11155         params->num_phys = 0;
11156         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11157         phy_config_swapped = params->multi_phy_config &
11158                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11159
11160         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11161               phy_index++) {
11162                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11163                 actual_phy_idx = phy_index;
11164                 if (phy_config_swapped) {
11165                         if (phy_index == EXT_PHY1)
11166                                 actual_phy_idx = EXT_PHY2;
11167                         else if (phy_index == EXT_PHY2)
11168                                 actual_phy_idx = EXT_PHY1;
11169                 }
11170                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11171                                " actual_phy_idx %x\n", phy_config_swapped,
11172                            phy_index, actual_phy_idx);
11173                 phy = &params->phy[actual_phy_idx];
11174                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11175                                        params->shmem2_base, params->port,
11176                                        phy) != 0) {
11177                         params->num_phys = 0;
11178                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11179                                    phy_index);
11180                         for (phy_index = INT_PHY;
11181                               phy_index < MAX_PHYS;
11182                               phy_index++)
11183                                 *phy = phy_null;
11184                         return -EINVAL;
11185                 }
11186                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11187                         break;
11188
11189                 sync_offset = params->shmem_base +
11190                         offsetof(struct shmem_region,
11191                         dev_info.port_hw_config[params->port].media_type);
11192                 media_types = REG_RD(bp, sync_offset);
11193
11194                 /*
11195                  * Update media type for non-PMF sync only for the first time
11196                  * In case the media type changes afterwards, it will be updated
11197                  * using the update_status function
11198                  */
11199                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11200                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11201                                      actual_phy_idx))) == 0) {
11202                         media_types |= ((phy->media_type &
11203                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11204                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11205                                  actual_phy_idx));
11206                 }
11207                 REG_WR(bp, sync_offset, media_types);
11208
11209                 bnx2x_phy_def_cfg(params, phy, phy_index);
11210                 params->num_phys++;
11211         }
11212
11213         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11214         return 0;
11215 }
11216
11217 void bnx2x_init_bmac_loopback(struct link_params *params,
11218                               struct link_vars *vars)
11219 {
11220         struct bnx2x *bp = params->bp;
11221                 vars->link_up = 1;
11222                 vars->line_speed = SPEED_10000;
11223                 vars->duplex = DUPLEX_FULL;
11224                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11225                 vars->mac_type = MAC_TYPE_BMAC;
11226
11227                 vars->phy_flags = PHY_XGXS_FLAG;
11228
11229                 bnx2x_xgxs_deassert(params);
11230
11231                 /* set bmac loopback */
11232                 bnx2x_bmac_enable(params, vars, 1);
11233
11234                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11235 }
11236
11237 void bnx2x_init_emac_loopback(struct link_params *params,
11238                               struct link_vars *vars)
11239 {
11240         struct bnx2x *bp = params->bp;
11241                 vars->link_up = 1;
11242                 vars->line_speed = SPEED_1000;
11243                 vars->duplex = DUPLEX_FULL;
11244                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11245                 vars->mac_type = MAC_TYPE_EMAC;
11246
11247                 vars->phy_flags = PHY_XGXS_FLAG;
11248
11249                 bnx2x_xgxs_deassert(params);
11250                 /* set bmac loopback */
11251                 bnx2x_emac_enable(params, vars, 1);
11252                 bnx2x_emac_program(params, vars);
11253                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11254 }
11255
11256 void bnx2x_init_xmac_loopback(struct link_params *params,
11257                               struct link_vars *vars)
11258 {
11259         struct bnx2x *bp = params->bp;
11260         vars->link_up = 1;
11261         if (!params->req_line_speed[0])
11262                 vars->line_speed = SPEED_10000;
11263         else
11264                 vars->line_speed = params->req_line_speed[0];
11265         vars->duplex = DUPLEX_FULL;
11266         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11267         vars->mac_type = MAC_TYPE_XMAC;
11268         vars->phy_flags = PHY_XGXS_FLAG;
11269         /*
11270          * Set WC to loopback mode since link is required to provide clock
11271          * to the XMAC in 20G mode
11272          */
11273         if (vars->line_speed == SPEED_20000) {
11274                 bnx2x_set_aer_mmd(params, &params->phy[0]);
11275                 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11276                 params->phy[INT_PHY].config_loopback(
11277                         &params->phy[INT_PHY],
11278                         params);
11279         }
11280         bnx2x_xmac_enable(params, vars, 1);
11281         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11282 }
11283
11284 void bnx2x_init_umac_loopback(struct link_params *params,
11285                               struct link_vars *vars)
11286 {
11287         struct bnx2x *bp = params->bp;
11288         vars->link_up = 1;
11289         vars->line_speed = SPEED_1000;
11290         vars->duplex = DUPLEX_FULL;
11291         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11292         vars->mac_type = MAC_TYPE_UMAC;
11293         vars->phy_flags = PHY_XGXS_FLAG;
11294         bnx2x_umac_enable(params, vars, 1);
11295
11296         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11297 }
11298
11299 void bnx2x_init_xgxs_loopback(struct link_params *params,
11300                               struct link_vars *vars)
11301 {
11302         struct bnx2x *bp = params->bp;
11303                 vars->link_up = 1;
11304                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11305                 vars->duplex = DUPLEX_FULL;
11306         if (params->req_line_speed[0] == SPEED_1000)
11307                         vars->line_speed = SPEED_1000;
11308         else
11309                         vars->line_speed = SPEED_10000;
11310
11311         if (!USES_WARPCORE(bp))
11312                 bnx2x_xgxs_deassert(params);
11313         bnx2x_link_initialize(params, vars);
11314
11315         if (params->req_line_speed[0] == SPEED_1000) {
11316                 if (USES_WARPCORE(bp))
11317                         bnx2x_umac_enable(params, vars, 0);
11318                 else {
11319                         bnx2x_emac_program(params, vars);
11320                         bnx2x_emac_enable(params, vars, 0);
11321                 }
11322         } else {
11323                 if (USES_WARPCORE(bp))
11324                         bnx2x_xmac_enable(params, vars, 0);
11325                 else
11326                         bnx2x_bmac_enable(params, vars, 0);
11327         }
11328
11329                 if (params->loopback_mode == LOOPBACK_XGXS) {
11330                         /* set 10G XGXS loopback */
11331                         params->phy[INT_PHY].config_loopback(
11332                                 &params->phy[INT_PHY],
11333                                 params);
11334
11335                 } else {
11336                         /* set external phy loopback */
11337                         u8 phy_index;
11338                         for (phy_index = EXT_PHY1;
11339                               phy_index < params->num_phys; phy_index++) {
11340                                 if (params->phy[phy_index].config_loopback)
11341                                         params->phy[phy_index].config_loopback(
11342                                                 &params->phy[phy_index],
11343                                                 params);
11344                         }
11345                 }
11346                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11347
11348         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11349 }
11350
11351 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11352 {
11353         struct bnx2x *bp = params->bp;
11354         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11355         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11356                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11357         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11358                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11359         vars->link_status = 0;
11360         vars->phy_link_up = 0;
11361         vars->link_up = 0;
11362         vars->line_speed = 0;
11363         vars->duplex = DUPLEX_FULL;
11364         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11365         vars->mac_type = MAC_TYPE_NONE;
11366         vars->phy_flags = 0;
11367
11368         /* disable attentions */
11369         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11370                        (NIG_MASK_XGXS0_LINK_STATUS |
11371                         NIG_MASK_XGXS0_LINK10G |
11372                         NIG_MASK_SERDES0_LINK_STATUS |
11373                         NIG_MASK_MI_INT));
11374
11375         bnx2x_emac_init(params, vars);
11376
11377         if (params->num_phys == 0) {
11378                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11379                 return -EINVAL;
11380         }
11381         set_phy_vars(params, vars);
11382
11383         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11384         switch (params->loopback_mode) {
11385         case LOOPBACK_BMAC:
11386                 bnx2x_init_bmac_loopback(params, vars);
11387                 break;
11388         case LOOPBACK_EMAC:
11389                 bnx2x_init_emac_loopback(params, vars);
11390                 break;
11391         case LOOPBACK_XMAC:
11392                 bnx2x_init_xmac_loopback(params, vars);
11393                 break;
11394         case LOOPBACK_UMAC:
11395                 bnx2x_init_umac_loopback(params, vars);
11396                 break;
11397         case LOOPBACK_XGXS:
11398         case LOOPBACK_EXT_PHY:
11399                 bnx2x_init_xgxs_loopback(params, vars);
11400                 break;
11401         default:
11402                 if (!CHIP_IS_E3(bp)) {
11403                         if (params->switch_cfg == SWITCH_CFG_10G)
11404                                 bnx2x_xgxs_deassert(params);
11405                         else
11406                                 bnx2x_serdes_deassert(bp, params->port);
11407                 }
11408                 bnx2x_link_initialize(params, vars);
11409                 msleep(30);
11410                 bnx2x_link_int_enable(params);
11411                 break;
11412         }
11413         return 0;
11414 }
11415
11416 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11417                      u8 reset_ext_phy)
11418 {
11419         struct bnx2x *bp = params->bp;
11420         u8 phy_index, port = params->port, clear_latch_ind = 0;
11421         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11422         /* disable attentions */
11423         vars->link_status = 0;
11424         bnx2x_update_mng(params, vars->link_status);
11425         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11426                        (NIG_MASK_XGXS0_LINK_STATUS |
11427                         NIG_MASK_XGXS0_LINK10G |
11428                         NIG_MASK_SERDES0_LINK_STATUS |
11429                         NIG_MASK_MI_INT));
11430
11431         /* activate nig drain */
11432         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11433
11434         /* disable nig egress interface */
11435         if (!CHIP_IS_E3(bp)) {
11436                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11437                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11438         }
11439
11440         /* Stop BigMac rx */
11441         if (!CHIP_IS_E3(bp))
11442                 bnx2x_bmac_rx_disable(bp, port);
11443         else
11444                 bnx2x_xmac_disable(params);
11445         /* disable emac */
11446         if (!CHIP_IS_E3(bp))
11447                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11448
11449         msleep(10);
11450         /* The PHY reset is controlled by GPIO 1
11451          * Hold it as vars low
11452          */
11453          /* clear link led */
11454         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11455
11456         if (reset_ext_phy) {
11457                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11458                       phy_index++) {
11459                         if (params->phy[phy_index].link_reset)
11460                                 params->phy[phy_index].link_reset(
11461                                         &params->phy[phy_index],
11462                                         params);
11463                         if (params->phy[phy_index].flags &
11464                             FLAGS_REARM_LATCH_SIGNAL)
11465                                 clear_latch_ind = 1;
11466                 }
11467         }
11468
11469         if (clear_latch_ind) {
11470                 /* Clear latching indication */
11471                 bnx2x_rearm_latch_signal(bp, port, 0);
11472                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11473                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
11474         }
11475         if (params->phy[INT_PHY].link_reset)
11476                 params->phy[INT_PHY].link_reset(
11477                         &params->phy[INT_PHY], params);
11478         /* reset BigMac */
11479         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11480                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11481
11482         /* disable nig ingress interface */
11483         if (!CHIP_IS_E3(bp)) {
11484                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11485                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11486         }
11487         vars->link_up = 0;
11488         vars->phy_flags = 0;
11489         return 0;
11490 }
11491
11492 /****************************************************************************/
11493 /*                              Common function                             */
11494 /****************************************************************************/
11495 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11496                                       u32 shmem_base_path[],
11497                                       u32 shmem2_base_path[], u8 phy_index,
11498                                       u32 chip_id)
11499 {
11500         struct bnx2x_phy phy[PORT_MAX];
11501         struct bnx2x_phy *phy_blk[PORT_MAX];
11502         u16 val;
11503         s8 port = 0;
11504         s8 port_of_path = 0;
11505         u32 swap_val, swap_override;
11506         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
11507         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
11508         port ^= (swap_val && swap_override);
11509         bnx2x_ext_phy_hw_reset(bp, port);
11510         /* PART1 - Reset both phys */
11511         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11512                 u32 shmem_base, shmem2_base;
11513                 /* In E2, same phy is using for port0 of the two paths */
11514                 if (CHIP_IS_E1x(bp)) {
11515                         shmem_base = shmem_base_path[0];
11516                         shmem2_base = shmem2_base_path[0];
11517                         port_of_path = port;
11518                 } else {
11519                         shmem_base = shmem_base_path[port];
11520                         shmem2_base = shmem2_base_path[port];
11521                         port_of_path = 0;
11522                 }
11523
11524                 /* Extract the ext phy address for the port */
11525                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11526                                        port_of_path, &phy[port]) !=
11527                     0) {
11528                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
11529                         return -EINVAL;
11530                 }
11531                 /* disable attentions */
11532                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11533                                port_of_path*4,
11534                                (NIG_MASK_XGXS0_LINK_STATUS |
11535                                 NIG_MASK_XGXS0_LINK10G |
11536                                 NIG_MASK_SERDES0_LINK_STATUS |
11537                                 NIG_MASK_MI_INT));
11538
11539                 /* Need to take the phy out of low power mode in order
11540                         to write to access its registers */
11541                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11542                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11543                                port);
11544
11545                 /* Reset the phy */
11546                 bnx2x_cl45_write(bp, &phy[port],
11547                                  MDIO_PMA_DEVAD,
11548                                  MDIO_PMA_REG_CTRL,
11549                                  1<<15);
11550         }
11551
11552         /* Add delay of 150ms after reset */
11553         msleep(150);
11554
11555         if (phy[PORT_0].addr & 0x1) {
11556                 phy_blk[PORT_0] = &(phy[PORT_1]);
11557                 phy_blk[PORT_1] = &(phy[PORT_0]);
11558         } else {
11559                 phy_blk[PORT_0] = &(phy[PORT_0]);
11560                 phy_blk[PORT_1] = &(phy[PORT_1]);
11561         }
11562
11563         /* PART2 - Download firmware to both phys */
11564         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11565                 if (CHIP_IS_E1x(bp))
11566                         port_of_path = port;
11567                 else
11568                         port_of_path = 0;
11569
11570                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11571                            phy_blk[port]->addr);
11572                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11573                                                       port_of_path))
11574                         return -EINVAL;
11575
11576                 /* Only set bit 10 = 1 (Tx power down) */
11577                 bnx2x_cl45_read(bp, phy_blk[port],
11578                                 MDIO_PMA_DEVAD,
11579                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11580
11581                 /* Phase1 of TX_POWER_DOWN reset */
11582                 bnx2x_cl45_write(bp, phy_blk[port],
11583                                  MDIO_PMA_DEVAD,
11584                                  MDIO_PMA_REG_TX_POWER_DOWN,
11585                                  (val | 1<<10));
11586         }
11587
11588         /*
11589          * Toggle Transmitter: Power down and then up with 600ms delay
11590          * between
11591          */
11592         msleep(600);
11593
11594         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11595         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11596                 /* Phase2 of POWER_DOWN_RESET */
11597                 /* Release bit 10 (Release Tx power down) */
11598                 bnx2x_cl45_read(bp, phy_blk[port],
11599                                 MDIO_PMA_DEVAD,
11600                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11601
11602                 bnx2x_cl45_write(bp, phy_blk[port],
11603                                 MDIO_PMA_DEVAD,
11604                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11605                 msleep(15);
11606
11607                 /* Read modify write the SPI-ROM version select register */
11608                 bnx2x_cl45_read(bp, phy_blk[port],
11609                                 MDIO_PMA_DEVAD,
11610                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11611                 bnx2x_cl45_write(bp, phy_blk[port],
11612                                  MDIO_PMA_DEVAD,
11613                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11614
11615                 /* set GPIO2 back to LOW */
11616                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11617                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11618         }
11619         return 0;
11620 }
11621 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11622                                       u32 shmem_base_path[],
11623                                       u32 shmem2_base_path[], u8 phy_index,
11624                                       u32 chip_id)
11625 {
11626         u32 val;
11627         s8 port;
11628         struct bnx2x_phy phy;
11629         /* Use port1 because of the static port-swap */
11630         /* Enable the module detection interrupt */
11631         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11632         val |= ((1<<MISC_REGISTERS_GPIO_3)|
11633                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11634         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11635
11636         bnx2x_ext_phy_hw_reset(bp, 0);
11637         msleep(5);
11638         for (port = 0; port < PORT_MAX; port++) {
11639                 u32 shmem_base, shmem2_base;
11640
11641                 /* In E2, same phy is using for port0 of the two paths */
11642                 if (CHIP_IS_E1x(bp)) {
11643                         shmem_base = shmem_base_path[0];
11644                         shmem2_base = shmem2_base_path[0];
11645                 } else {
11646                         shmem_base = shmem_base_path[port];
11647                         shmem2_base = shmem2_base_path[port];
11648                 }
11649                 /* Extract the ext phy address for the port */
11650                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11651                                        port, &phy) !=
11652                     0) {
11653                         DP(NETIF_MSG_LINK, "populate phy failed\n");
11654                         return -EINVAL;
11655                 }
11656
11657                 /* Reset phy*/
11658                 bnx2x_cl45_write(bp, &phy,
11659                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11660
11661
11662                 /* Set fault module detected LED on */
11663                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11664                                MISC_REGISTERS_GPIO_HIGH,
11665                                port);
11666         }
11667
11668         return 0;
11669 }
11670 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11671                                          u8 *io_gpio, u8 *io_port)
11672 {
11673
11674         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11675                                           offsetof(struct shmem_region,
11676                                 dev_info.port_hw_config[PORT_0].default_cfg));
11677         switch (phy_gpio_reset) {
11678         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11679                 *io_gpio = 0;
11680                 *io_port = 0;
11681                 break;
11682         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11683                 *io_gpio = 1;
11684                 *io_port = 0;
11685                 break;
11686         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11687                 *io_gpio = 2;
11688                 *io_port = 0;
11689                 break;
11690         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11691                 *io_gpio = 3;
11692                 *io_port = 0;
11693                 break;
11694         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11695                 *io_gpio = 0;
11696                 *io_port = 1;
11697                 break;
11698         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11699                 *io_gpio = 1;
11700                 *io_port = 1;
11701                 break;
11702         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11703                 *io_gpio = 2;
11704                 *io_port = 1;
11705                 break;
11706         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11707                 *io_gpio = 3;
11708                 *io_port = 1;
11709                 break;
11710         default:
11711                 /* Don't override the io_gpio and io_port */
11712                 break;
11713         }
11714 }
11715
11716 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11717                                       u32 shmem_base_path[],
11718                                       u32 shmem2_base_path[], u8 phy_index,
11719                                       u32 chip_id)
11720 {
11721         s8 port, reset_gpio;
11722         u32 swap_val, swap_override;
11723         struct bnx2x_phy phy[PORT_MAX];
11724         struct bnx2x_phy *phy_blk[PORT_MAX];
11725         s8 port_of_path;
11726         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11727         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11728
11729         reset_gpio = MISC_REGISTERS_GPIO_1;
11730         port = 1;
11731
11732         /*
11733          * Retrieve the reset gpio/port which control the reset.
11734          * Default is GPIO1, PORT1
11735          */
11736         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
11737                                      (u8 *)&reset_gpio, (u8 *)&port);
11738
11739         /* Calculate the port based on port swap */
11740         port ^= (swap_val && swap_override);
11741
11742         /* Initiate PHY reset*/
11743         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
11744                        port);
11745         msleep(1);
11746         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11747                        port);
11748
11749         msleep(5);
11750
11751         /* PART1 - Reset both phys */
11752         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11753                 u32 shmem_base, shmem2_base;
11754
11755                 /* In E2, same phy is using for port0 of the two paths */
11756                 if (CHIP_IS_E1x(bp)) {
11757                         shmem_base = shmem_base_path[0];
11758                         shmem2_base = shmem2_base_path[0];
11759                         port_of_path = port;
11760                 } else {
11761                         shmem_base = shmem_base_path[port];
11762                         shmem2_base = shmem2_base_path[port];
11763                         port_of_path = 0;
11764                 }
11765
11766                 /* Extract the ext phy address for the port */
11767                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11768                                        port_of_path, &phy[port]) !=
11769                                        0) {
11770                         DP(NETIF_MSG_LINK, "populate phy failed\n");
11771                         return -EINVAL;
11772                 }
11773                 /* disable attentions */
11774                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11775                                port_of_path*4,
11776                                (NIG_MASK_XGXS0_LINK_STATUS |
11777                                 NIG_MASK_XGXS0_LINK10G |
11778                                 NIG_MASK_SERDES0_LINK_STATUS |
11779                                 NIG_MASK_MI_INT));
11780
11781
11782                 /* Reset the phy */
11783                 bnx2x_cl45_write(bp, &phy[port],
11784                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
11785         }
11786
11787         /* Add delay of 150ms after reset */
11788         msleep(150);
11789         if (phy[PORT_0].addr & 0x1) {
11790                 phy_blk[PORT_0] = &(phy[PORT_1]);
11791                 phy_blk[PORT_1] = &(phy[PORT_0]);
11792         } else {
11793                 phy_blk[PORT_0] = &(phy[PORT_0]);
11794                 phy_blk[PORT_1] = &(phy[PORT_1]);
11795         }
11796         /* PART2 - Download firmware to both phys */
11797         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11798                 if (CHIP_IS_E1x(bp))
11799                         port_of_path = port;
11800                 else
11801                         port_of_path = 0;
11802                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11803                            phy_blk[port]->addr);
11804                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11805                                                       port_of_path))
11806                         return -EINVAL;
11807
11808         }
11809         return 0;
11810 }
11811
11812 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
11813                                      u32 shmem2_base_path[], u8 phy_index,
11814                                      u32 ext_phy_type, u32 chip_id)
11815 {
11816         int rc = 0;
11817
11818         switch (ext_phy_type) {
11819         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11820                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
11821                                                 shmem2_base_path,
11822                                                 phy_index, chip_id);
11823                 break;
11824         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11825         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11826         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11827                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
11828                                                 shmem2_base_path,
11829                                                 phy_index, chip_id);
11830                 break;
11831
11832         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11833                 /*
11834                  * GPIO1 affects both ports, so there's need to pull
11835                  * it for single port alone
11836                  */
11837                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
11838                                                 shmem2_base_path,
11839                                                 phy_index, chip_id);
11840                 break;
11841         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11842                 /*
11843                  * GPIO3's are linked, and so both need to be toggled
11844                  * to obtain required 2us pulse.
11845                  */
11846                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
11847                 break;
11848         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11849                 rc = -EINVAL;
11850                 break;
11851         default:
11852                 DP(NETIF_MSG_LINK,
11853                            "ext_phy 0x%x common init not required\n",
11854                            ext_phy_type);
11855                 break;
11856         }
11857
11858         if (rc != 0)
11859                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
11860                                       " Port %d\n",
11861                          0);
11862         return rc;
11863 }
11864
11865 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
11866                           u32 shmem2_base_path[], u32 chip_id)
11867 {
11868         int rc = 0;
11869         u32 phy_ver, val;
11870         u8 phy_index = 0;
11871         u32 ext_phy_type, ext_phy_config;
11872         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
11873         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
11874         DP(NETIF_MSG_LINK, "Begin common phy init\n");
11875         if (CHIP_IS_E3(bp)) {
11876                 /* Enable EPIO */
11877                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
11878                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
11879         }
11880         /* Check if common init was already done */
11881         phy_ver = REG_RD(bp, shmem_base_path[0] +
11882                          offsetof(struct shmem_region,
11883                                   port_mb[PORT_0].ext_phy_fw_version));
11884         if (phy_ver) {
11885                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
11886                                phy_ver);
11887                 return 0;
11888         }
11889
11890         /* Read the ext_phy_type for arbitrary port(0) */
11891         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
11892               phy_index++) {
11893                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
11894                                                           shmem_base_path[0],
11895                                                           phy_index, 0);
11896                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11897                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
11898                                                 shmem2_base_path,
11899                                                 phy_index, ext_phy_type,
11900                                                 chip_id);
11901         }
11902         return rc;
11903 }
11904
11905 static void bnx2x_check_over_curr(struct link_params *params,
11906                                   struct link_vars *vars)
11907 {
11908         struct bnx2x *bp = params->bp;
11909         u32 cfg_pin;
11910         u8 port = params->port;
11911         u32 pin_val;
11912
11913         cfg_pin = (REG_RD(bp, params->shmem_base +
11914                           offsetof(struct shmem_region,
11915                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
11916                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
11917                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
11918
11919         /* Ignore check if no external input PIN available */
11920         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
11921                 return;
11922
11923         if (!pin_val) {
11924                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
11925                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
11926                                             " been detected and the power to "
11927                                             "that SFP+ module has been removed"
11928                                             " to prevent failure of the card."
11929                                             " Please remove the SFP+ module and"
11930                                             " restart the system to clear this"
11931                                             " error.\n",
11932                          params->port);
11933                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
11934                 }
11935         } else
11936                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
11937 }
11938
11939 static void bnx2x_analyze_link_error(struct link_params *params,
11940                                      struct link_vars *vars, u32 lss_status)
11941 {
11942         struct bnx2x *bp = params->bp;
11943         /* Compare new value with previous value */
11944         u8 led_mode;
11945         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
11946
11947         /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
11948                        vars->link_up,
11949                        half_open_conn, lss_status);*/
11950
11951         if ((lss_status ^ half_open_conn) == 0)
11952                 return;
11953
11954         /* If values differ */
11955         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
11956                        half_open_conn, lss_status);
11957
11958         /*
11959          * a. Update shmem->link_status accordingly
11960          * b. Update link_vars->link_up
11961          */
11962         if (lss_status) {
11963                 vars->link_status &= ~LINK_STATUS_LINK_UP;
11964                 vars->link_up = 0;
11965                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
11966                 /*
11967                  * Set LED mode to off since the PHY doesn't know about these
11968                  * errors
11969                  */
11970                 led_mode = LED_MODE_OFF;
11971         } else {
11972                 vars->link_status |= LINK_STATUS_LINK_UP;
11973                 vars->link_up = 1;
11974                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
11975                 led_mode = LED_MODE_OPER;
11976         }
11977         /* Update the LED according to the link state */
11978         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
11979
11980         /* Update link status in the shared memory */
11981         bnx2x_update_mng(params, vars->link_status);
11982
11983         /* C. Trigger General Attention */
11984         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
11985         bnx2x_notify_link_changed(bp);
11986 }
11987
11988 static void bnx2x_check_half_open_conn(struct link_params *params,
11989                                        struct link_vars *vars)
11990 {
11991         struct bnx2x *bp = params->bp;
11992         u32 lss_status = 0;
11993         u32 mac_base;
11994         /* In case link status is physically up @ 10G do */
11995         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
11996                 return;
11997
11998         if (!CHIP_IS_E3(bp) &&
11999             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12000                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
12001                 /* Check E1X / E2 BMAC */
12002                 u32 lss_status_reg;
12003                 u32 wb_data[2];
12004                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12005                         NIG_REG_INGRESS_BMAC0_MEM;
12006                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12007                 if (CHIP_IS_E2(bp))
12008                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12009                 else
12010                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12011
12012                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12013                 lss_status = (wb_data[0] > 0);
12014
12015                 bnx2x_analyze_link_error(params, vars, lss_status);
12016         }
12017 }
12018
12019 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12020 {
12021         struct bnx2x *bp = params->bp;
12022         if (!params) {
12023                 DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
12024                 return;
12025         }
12026         /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
12027          RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
12028           REG_RD(bp, MISC_REG_RESET_REG_2)); */
12029         bnx2x_check_half_open_conn(params, vars);
12030         if (CHIP_IS_E3(bp))
12031                 bnx2x_check_over_curr(params, vars);
12032 }
12033
12034 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12035 {
12036         u8 phy_index;
12037         struct bnx2x_phy phy;
12038         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12039               phy_index++) {
12040                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12041                                        0, &phy) != 0) {
12042                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12043                         return 0;
12044                 }
12045
12046                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12047                         return 1;
12048         }
12049         return 0;
12050 }
12051
12052 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12053                              u32 shmem_base,
12054                              u32 shmem2_base,
12055                              u8 port)
12056 {
12057         u8 phy_index, fan_failure_det_req = 0;
12058         struct bnx2x_phy phy;
12059         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12060               phy_index++) {
12061                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12062                                        port, &phy)
12063                     != 0) {
12064                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12065                         return 0;
12066                 }
12067                 fan_failure_det_req |= (phy.flags &
12068                                         FLAGS_FAN_FAILURE_DET_REQ);
12069         }
12070         return fan_failure_det_req;
12071 }
12072
12073 void bnx2x_hw_reset_phy(struct link_params *params)
12074 {
12075         u8 phy_index;
12076         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12077               phy_index++) {
12078                 if (params->phy[phy_index].hw_reset) {
12079                         params->phy[phy_index].hw_reset(
12080                                 &params->phy[phy_index],
12081                                 params);
12082                         params->phy[phy_index] = phy_null;
12083                 }
12084         }
12085 }
12086
12087 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12088                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12089                             u8 port)
12090 {
12091         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12092         u32 val;
12093         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12094         if (CHIP_IS_E3(bp)) {
12095                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12096                                               shmem_base,
12097                                               port,
12098                                               &gpio_num,
12099                                               &gpio_port) != 0)
12100                         return;
12101         } else {
12102                 struct bnx2x_phy phy;
12103                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12104                       phy_index++) {
12105                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12106                                                shmem2_base, port, &phy)
12107                             != 0) {
12108                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12109                                 return;
12110                         }
12111                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12112                                 gpio_num = MISC_REGISTERS_GPIO_3;
12113                                 gpio_port = port;
12114                                 break;
12115                         }
12116                 }
12117         }
12118
12119         if (gpio_num == 0xff)
12120                 return;
12121
12122         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12123         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12124
12125         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12126         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12127         gpio_port ^= (swap_val && swap_override);
12128
12129         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12130                 (gpio_num + (gpio_port << 2));
12131
12132         sync_offset = shmem_base +
12133                 offsetof(struct shmem_region,
12134                          dev_info.port_hw_config[port].aeu_int_mask);
12135         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12136
12137         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12138                        gpio_num, gpio_port, vars->aeu_int_mask);
12139
12140         if (port == 0)
12141                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12142         else
12143                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12144
12145         /* Open appropriate AEU for interrupts */
12146         aeu_mask = REG_RD(bp, offset);
12147         aeu_mask |= vars->aeu_int_mask;
12148         REG_WR(bp, offset, aeu_mask);
12149
12150         /* Enable the GPIO to trigger interrupt */
12151         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12152         val |= 1 << (gpio_num + (gpio_port << 2));
12153         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12154 }