drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
 220                               int reg, u16 *val)
 221 {
 222         int addr = phy; /* PHY devices addresses start at 0x0 */
 223
 224         if (!chip->phy_ops)
 225                 return -EOPNOTSUPP;
 226
 227         return chip->phy_ops->read(chip, addr, reg, val);
 228 }
 229
 230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
 231                                int reg, u16 val)
 232 {
 233         int addr = phy; /* PHY devices addresses start at 0x0 */
 234
 235         if (!chip->phy_ops)
 236                 return -EOPNOTSUPP;
 237
 238         return chip->phy_ops->write(chip, addr, reg, val);
 239 }
 240
 241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 242 {
 243         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
 244                 return -EOPNOTSUPP;
 245
 246         return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 247 }
 248
 249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
 250 {
 251         int err;
 252
 253         /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
 254         err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
 255         if (unlikely(err)) {
 256                 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
 257                         phy, err);
 258         }
 259 }
 260
 261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
 262                                    u8 page, int reg, u16 *val)
 263 {
 264         int err;
 265
 266         /* There is no paging for registers 22 */
 267         if (reg == PHY_PAGE)
 268                 return -EINVAL;
 269
 270         err = mv88e6xxx_phy_page_get(chip, phy, page);
 271         if (!err) {
 272                 err = mv88e6xxx_phy_read(chip, phy, reg, val);
 273                 mv88e6xxx_phy_page_put(chip, phy);
 274         }
 275
 276         return err;
 277 }
 278
 279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
 280                                     u8 page, int reg, u16 val)
 281 {
 282         int err;
 283
 284         /* There is no paging for registers 22 */
 285         if (reg == PHY_PAGE)
 286                 return -EINVAL;
 287
 288         err = mv88e6xxx_phy_page_get(chip, phy, page);
 289         if (!err) {
 290                 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 291                 mv88e6xxx_phy_page_put(chip, phy);
 292         }
 293
 294         return err;
 295 }
 296
 297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 298 {
 299         return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 300                                        reg, val);
 301 }
 302
 303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 304 {
 305         return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 306                                         reg, val);
 307 }
 308
 309 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
 310                           u16 mask)
 311 {
 312         int i;
 313
 314         for (i = 0; i < 16; i++) {
 315                 u16 val;
 316                 int err;
 317
 318                 err = mv88e6xxx_read(chip, addr, reg, &val);
 319                 if (err)
 320                         return err;
 321
 322                 if (!(val & mask))
 323                         return 0;
 324
 325                 usleep_range(1000, 2000);
 326         }
 327
 328         return -ETIMEDOUT;
 329 }
 330
 331 /* Indirect write to single pointer-data register with an Update bit */
 332 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 333                             u16 update)
 334 {
 335         u16 val;
 336         int err;
 337
 338         /* Wait until the previous operation is completed */
 339         err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
 340         if (err)
 341                 return err;
 342
 343         /* Set the Update bit to trigger a write operation */
 344         val = BIT(15) | update;
 345
 346         return mv88e6xxx_write(chip, addr, reg, val);
 347 }
 348
 349 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 350 {
 351         u16 val;
 352         int err;
 353
 354         err = mv88e6xxx_read(chip, addr, reg, &val);
 355         if (err)
 356                 return err;
 357
 358         return val;
 359 }
 360
 361 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 362                                 int reg, u16 val)
 363 {
 364         return mv88e6xxx_write(chip, addr, reg, val);
 365 }
 366
 367 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 368 {
 369         int ret;
 370         int i;
 371
 372         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 373         if (ret < 0)
 374                 return ret;
 375
 376         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 377                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 378         if (ret)
 379                 return ret;
 380
 381         for (i = 0; i < 16; i++) {
 382                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 383                 if (ret < 0)
 384                         return ret;
 385
 386                 usleep_range(1000, 2000);
 387                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 388                     GLOBAL_STATUS_PPU_POLLING)
 389                         return 0;
 390         }
 391
 392         return -ETIMEDOUT;
 393 }
 394
 395 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 396 {
 397         int ret, err, i;
 398
 399         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 400         if (ret < 0)
 401                 return ret;
 402
 403         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 404                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 405         if (err)
 406                 return err;
 407
 408         for (i = 0; i < 16; i++) {
 409                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 410                 if (ret < 0)
 411                         return ret;
 412
 413                 usleep_range(1000, 2000);
 414                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 415                     GLOBAL_STATUS_PPU_POLLING)
 416                         return 0;
 417         }
 418
 419         return -ETIMEDOUT;
 420 }
 421
 422 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 423 {
 424         struct mv88e6xxx_chip *chip;
 425
 426         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 427
 428         mutex_lock(&chip->reg_lock);
 429
 430         if (mutex_trylock(&chip->ppu_mutex)) {
 431                 if (mv88e6xxx_ppu_enable(chip) == 0)
 432                         chip->ppu_disabled = 0;
 433                 mutex_unlock(&chip->ppu_mutex);
 434         }
 435
 436         mutex_unlock(&chip->reg_lock);
 437 }
 438
 439 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 440 {
 441         struct mv88e6xxx_chip *chip = (void *)_ps;
 442
 443         schedule_work(&chip->ppu_work);
 444 }
 445
 446 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 447 {
 448         int ret;
 449
 450         mutex_lock(&chip->ppu_mutex);
 451
 452         /* If the PHY polling unit is enabled, disable it so that
 453          * we can access the PHY registers.  If it was already
 454          * disabled, cancel the timer that is going to re-enable
 455          * it.
 456          */
 457         if (!chip->ppu_disabled) {
 458                 ret = mv88e6xxx_ppu_disable(chip);
 459                 if (ret < 0) {
 460                         mutex_unlock(&chip->ppu_mutex);
 461                         return ret;
 462                 }
 463                 chip->ppu_disabled = 1;
 464         } else {
 465                 del_timer(&chip->ppu_timer);
 466                 ret = 0;
 467         }
 468
 469         return ret;
 470 }
 471
 472 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 473 {
 474         /* Schedule a timer to re-enable the PHY polling unit. */
 475         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 476         mutex_unlock(&chip->ppu_mutex);
 477 }
 478
 479 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 480 {
 481         mutex_init(&chip->ppu_mutex);
 482         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 483         init_timer(&chip->ppu_timer);
 484         chip->ppu_timer.data = (unsigned long)chip;
 485         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 486 }
 487
 488 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
 489                                   int reg, u16 *val)
 490 {
 491         int err;
 492
 493         err = mv88e6xxx_ppu_access_get(chip);
 494         if (!err) {
 495                 err = mv88e6xxx_read(chip, addr, reg, val);
 496                 mv88e6xxx_ppu_access_put(chip);
 497         }
 498
 499         return err;
 500 }
 501
 502 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
 503                                    int reg, u16 val)
 504 {
 505         int err;
 506
 507         err = mv88e6xxx_ppu_access_get(chip);
 508         if (!err) {
 509                 err = mv88e6xxx_write(chip, addr, reg, val);
 510                 mv88e6xxx_ppu_access_put(chip);
 511         }
 512
 513         return err;
 514 }
 515
 516 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
 517         .read = mv88e6xxx_phy_ppu_read,
 518         .write = mv88e6xxx_phy_ppu_write,
 519 };
 520
 521 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 522 {
 523         return chip->info->family == MV88E6XXX_FAMILY_6065;
 524 }
 525
 526 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 527 {
 528         return chip->info->family == MV88E6XXX_FAMILY_6095;
 529 }
 530
 531 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 532 {
 533         return chip->info->family == MV88E6XXX_FAMILY_6097;
 534 }
 535
 536 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 537 {
 538         return chip->info->family == MV88E6XXX_FAMILY_6165;
 539 }
 540
 541 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 542 {
 543         return chip->info->family == MV88E6XXX_FAMILY_6185;
 544 }
 545
 546 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 547 {
 548         return chip->info->family == MV88E6XXX_FAMILY_6320;
 549 }
 550
 551 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 552 {
 553         return chip->info->family == MV88E6XXX_FAMILY_6351;
 554 }
 555
 556 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 557 {
 558         return chip->info->family == MV88E6XXX_FAMILY_6352;
 559 }
 560
 561 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 562 {
 563         return chip->info->num_databases;
 564 }
 565
 566 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 567 {
 568         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 569         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 570             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 571                 return true;
 572
 573         return false;
 574 }
 575
 576 /* We expect the switch to perform auto negotiation if there is a real
 577  * phy. However, in the case of a fixed link phy, we force the port
 578  * settings from the fixed link settings.
 579  */
 580 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 581                                   struct phy_device *phydev)
 582 {
 583         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 584         u32 reg;
 585         int ret;
 586
 587         if (!phy_is_pseudo_fixed_link(phydev))
 588                 return;
 589
 590         mutex_lock(&chip->reg_lock);
 591
 592         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 593         if (ret < 0)
 594                 goto out;
 595
 596         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 597                       PORT_PCS_CTRL_FORCE_LINK |
 598                       PORT_PCS_CTRL_DUPLEX_FULL |
 599                       PORT_PCS_CTRL_FORCE_DUPLEX |
 600                       PORT_PCS_CTRL_UNFORCED);
 601
 602         reg |= PORT_PCS_CTRL_FORCE_LINK;
 603         if (phydev->link)
 604                 reg |= PORT_PCS_CTRL_LINK_UP;
 605
 606         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 607                 goto out;
 608
 609         switch (phydev->speed) {
 610         case SPEED_1000:
 611                 reg |= PORT_PCS_CTRL_1000;
 612                 break;
 613         case SPEED_100:
 614                 reg |= PORT_PCS_CTRL_100;
 615                 break;
 616         case SPEED_10:
 617                 reg |= PORT_PCS_CTRL_10;
 618                 break;
 619         default:
 620                 pr_info("Unknown speed");
 621                 goto out;
 622         }
 623
 624         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 625         if (phydev->duplex == DUPLEX_FULL)
 626                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 627
 628         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 629             (port >= chip->info->num_ports - 2)) {
 630                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 631                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 632                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 633                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 634                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 635                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 636                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 637         }
 638         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 639
 640 out:
 641         mutex_unlock(&chip->reg_lock);
 642 }
 643
 644 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 645 {
 646         int ret;
 647         int i;
 648
 649         for (i = 0; i < 10; i++) {
 650                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 651                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 652                         return 0;
 653         }
 654
 655         return -ETIMEDOUT;
 656 }
 657
 658 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 659 {
 660         int ret;
 661
 662         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 663                 port = (port + 1) << 5;
 664
 665         /* Snapshot the hardware statistics counters for this port. */
 666         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 667                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 668                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 669         if (ret < 0)
 670                 return ret;
 671
 672         /* Wait for the snapshotting to complete. */
 673         ret = _mv88e6xxx_stats_wait(chip);
 674         if (ret < 0)
 675                 return ret;
 676
 677         return 0;
 678 }
 679
 680 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 681                                   int stat, u32 *val)
 682 {
 683         u32 _val;
 684         int ret;
 685
 686         *val = 0;
 687
 688         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 689                                    GLOBAL_STATS_OP_READ_CAPTURED |
 690                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 691         if (ret < 0)
 692                 return;
 693
 694         ret = _mv88e6xxx_stats_wait(chip);
 695         if (ret < 0)
 696                 return;
 697
 698         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 699         if (ret < 0)
 700                 return;
 701
 702         _val = ret << 16;
 703
 704         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 705         if (ret < 0)
 706                 return;
 707
 708         *val = _val | ret;
 709 }
 710
 711 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 712         { "in_good_octets",     8, 0x00, BANK0, },
 713         { "in_bad_octets",      4, 0x02, BANK0, },
 714         { "in_unicast",         4, 0x04, BANK0, },
 715         { "in_broadcasts",      4, 0x06, BANK0, },
 716         { "in_multicasts",      4, 0x07, BANK0, },
 717         { "in_pause",           4, 0x16, BANK0, },
 718         { "in_undersize",       4, 0x18, BANK0, },
 719         { "in_fragments",       4, 0x19, BANK0, },
 720         { "in_oversize",        4, 0x1a, BANK0, },
 721         { "in_jabber",          4, 0x1b, BANK0, },
 722         { "in_rx_error",        4, 0x1c, BANK0, },
 723         { "in_fcs_error",       4, 0x1d, BANK0, },
 724         { "out_octets",         8, 0x0e, BANK0, },
 725         { "out_unicast",        4, 0x10, BANK0, },
 726         { "out_broadcasts",     4, 0x13, BANK0, },
 727         { "out_multicasts",     4, 0x12, BANK0, },
 728         { "out_pause",          4, 0x15, BANK0, },
 729         { "excessive",          4, 0x11, BANK0, },
 730         { "collisions",         4, 0x1e, BANK0, },
 731         { "deferred",           4, 0x05, BANK0, },
 732         { "single",             4, 0x14, BANK0, },
 733         { "multiple",           4, 0x17, BANK0, },
 734         { "out_fcs_error",      4, 0x03, BANK0, },
 735         { "late",               4, 0x1f, BANK0, },
 736         { "hist_64bytes",       4, 0x08, BANK0, },
 737         { "hist_65_127bytes",   4, 0x09, BANK0, },
 738         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 739         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 740         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 741         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 742         { "sw_in_discards",     4, 0x10, PORT, },
 743         { "sw_in_filtered",     2, 0x12, PORT, },
 744         { "sw_out_filtered",    2, 0x13, PORT, },
 745         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 746         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 747         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 748         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 749         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 750         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 751         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 752         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 753         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 754         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 755         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 756         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 757         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 758         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 759         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 760         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 761         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 762         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 763         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 764         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 765         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 766         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 767         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 768         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 769         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 770         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 771 };
 772
 773 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 774                                struct mv88e6xxx_hw_stat *stat)
 775 {
 776         switch (stat->type) {
 777         case BANK0:
 778                 return true;
 779         case BANK1:
 780                 return mv88e6xxx_6320_family(chip);
 781         case PORT:
 782                 return mv88e6xxx_6095_family(chip) ||
 783                         mv88e6xxx_6185_family(chip) ||
 784                         mv88e6xxx_6097_family(chip) ||
 785                         mv88e6xxx_6165_family(chip) ||
 786                         mv88e6xxx_6351_family(chip) ||
 787                         mv88e6xxx_6352_family(chip);
 788         }
 789         return false;
 790 }
 791
 792 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 793                                             struct mv88e6xxx_hw_stat *s,
 794                                             int port)
 795 {
 796         u32 low;
 797         u32 high = 0;
 798         int ret;
 799         u64 value;
 800
 801         switch (s->type) {
 802         case PORT:
 803                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 804                 if (ret < 0)
 805                         return UINT64_MAX;
 806
 807                 low = ret;
 808                 if (s->sizeof_stat == 4) {
 809                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 810                                                   s->reg + 1);
 811                         if (ret < 0)
 812                                 return UINT64_MAX;
 813                         high = ret;
 814                 }
 815                 break;
 816         case BANK0:
 817         case BANK1:
 818                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 819                 if (s->sizeof_stat == 8)
 820                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 821         }
 822         value = (((u64)high) << 16) | low;
 823         return value;
 824 }
 825
 826 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 827                                   uint8_t *data)
 828 {
 829         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 830         struct mv88e6xxx_hw_stat *stat;
 831         int i, j;
 832
 833         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 834                 stat = &mv88e6xxx_hw_stats[i];
 835                 if (mv88e6xxx_has_stat(chip, stat)) {
 836                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 837                                ETH_GSTRING_LEN);
 838                         j++;
 839                 }
 840         }
 841 }
 842
 843 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 844 {
 845         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 846         struct mv88e6xxx_hw_stat *stat;
 847         int i, j;
 848
 849         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 850                 stat = &mv88e6xxx_hw_stats[i];
 851                 if (mv88e6xxx_has_stat(chip, stat))
 852                         j++;
 853         }
 854         return j;
 855 }
 856
 857 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 858                                         uint64_t *data)
 859 {
 860         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 861         struct mv88e6xxx_hw_stat *stat;
 862         int ret;
 863         int i, j;
 864
 865         mutex_lock(&chip->reg_lock);
 866
 867         ret = _mv88e6xxx_stats_snapshot(chip, port);
 868         if (ret < 0) {
 869                 mutex_unlock(&chip->reg_lock);
 870                 return;
 871         }
 872         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 873                 stat = &mv88e6xxx_hw_stats[i];
 874                 if (mv88e6xxx_has_stat(chip, stat)) {
 875                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 876                         j++;
 877                 }
 878         }
 879
 880         mutex_unlock(&chip->reg_lock);
 881 }
 882
 883 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 884 {
 885         return 32 * sizeof(u16);
 886 }
 887
 888 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 889                                struct ethtool_regs *regs, void *_p)
 890 {
 891         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 892         u16 *p = _p;
 893         int i;
 894
 895         regs->version = 0;
 896
 897         memset(p, 0xff, 32 * sizeof(u16));
 898
 899         mutex_lock(&chip->reg_lock);
 900
 901         for (i = 0; i < 32; i++) {
 902                 int ret;
 903
 904                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 905                 if (ret >= 0)
 906                         p[i] = ret;
 907         }
 908
 909         mutex_unlock(&chip->reg_lock);
 910 }
 911
 912 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 913 {
 914         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 915                               GLOBAL_ATU_OP_BUSY);
 916 }
 917
 918 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 919                              struct ethtool_eee *e)
 920 {
 921         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 922         u16 reg;
 923         int err;
 924
 925         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 926                 return -EOPNOTSUPP;
 927
 928         mutex_lock(&chip->reg_lock);
 929
 930         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 931         if (err)
 932                 goto out;
 933
 934         e->eee_enabled = !!(reg & 0x0200);
 935         e->tx_lpi_enabled = !!(reg & 0x0100);
 936
 937         err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
 938         if (err)
 939                 goto out;
 940
 941         e->eee_active = !!(reg & PORT_STATUS_EEE);
 942 out:
 943         mutex_unlock(&chip->reg_lock);
 944
 945         return err;
 946 }
 947
 948 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 949                              struct phy_device *phydev, struct ethtool_eee *e)
 950 {
 951         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 952         u16 reg;
 953         int err;
 954
 955         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 956                 return -EOPNOTSUPP;
 957
 958         mutex_lock(&chip->reg_lock);
 959
 960         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 961         if (err)
 962                 goto out;
 963
 964         reg &= ~0x0300;
 965         if (e->eee_enabled)
 966                 reg |= 0x0200;
 967         if (e->tx_lpi_enabled)
 968                 reg |= 0x0100;
 969
 970         err = mv88e6xxx_phy_write(chip, port, 16, reg);
 971 out:
 972         mutex_unlock(&chip->reg_lock);
 973
 974         return err;
 975 }
 976
 977 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 978 {
 979         int ret;
 980
 981         if (mv88e6xxx_has_fid_reg(chip)) {
 982                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 983                                            fid);
 984                 if (ret < 0)
 985                         return ret;
 986         } else if (mv88e6xxx_num_databases(chip) == 256) {
 987                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 988                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
 989                 if (ret < 0)
 990                         return ret;
 991
 992                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
 993                                            (ret & 0xfff) |
 994                                            ((fid << 8) & 0xf000));
 995                 if (ret < 0)
 996                         return ret;
 997
 998                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
 999                 cmd |= fid & 0xf;
1000         }
1001
1002         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1003         if (ret < 0)
1004                 return ret;
1005
1006         return _mv88e6xxx_atu_wait(chip);
1007 }
1008
1009 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1010                                      struct mv88e6xxx_atu_entry *entry)
1011 {
1012         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1013
1014         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1015                 unsigned int mask, shift;
1016
1017                 if (entry->trunk) {
1018                         data |= GLOBAL_ATU_DATA_TRUNK;
1019                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1020                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1021                 } else {
1022                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1023                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1024                 }
1025
1026                 data |= (entry->portv_trunkid << shift) & mask;
1027         }
1028
1029         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1030 }
1031
1032 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1033                                      struct mv88e6xxx_atu_entry *entry,
1034                                      bool static_too)
1035 {
1036         int op;
1037         int err;
1038
1039         err = _mv88e6xxx_atu_wait(chip);
1040         if (err)
1041                 return err;
1042
1043         err = _mv88e6xxx_atu_data_write(chip, entry);
1044         if (err)
1045                 return err;
1046
1047         if (entry->fid) {
1048                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1049                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1050         } else {
1051                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1052                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1053         }
1054
1055         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1056 }
1057
1058 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1059                                 u16 fid, bool static_too)
1060 {
1061         struct mv88e6xxx_atu_entry entry = {
1062                 .fid = fid,
1063                 .state = 0, /* EntryState bits must be 0 */
1064         };
1065
1066         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1067 }
1068
1069 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1070                                int from_port, int to_port, bool static_too)
1071 {
1072         struct mv88e6xxx_atu_entry entry = {
1073                 .trunk = false,
1074                 .fid = fid,
1075         };
1076
1077         /* EntryState bits must be 0xF */
1078         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1079
1080         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1081         entry.portv_trunkid = (to_port & 0x0f) << 4;
1082         entry.portv_trunkid |= from_port & 0x0f;
1083
1084         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1085 }
1086
1087 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1088                                  int port, bool static_too)
1089 {
1090         /* Destination port 0xF means remove the entries */
1091         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1092 }
1093
1094 static const char * const mv88e6xxx_port_state_names[] = {
1095         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1096         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1097         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1098         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1099 };
1100
1101 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1102                                  u8 state)
1103 {
1104         struct dsa_switch *ds = chip->ds;
1105         int reg, ret = 0;
1106         u8 oldstate;
1107
1108         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1109         if (reg < 0)
1110                 return reg;
1111
1112         oldstate = reg & PORT_CONTROL_STATE_MASK;
1113
1114         if (oldstate != state) {
1115                 /* Flush forwarding database if we're moving a port
1116                  * from Learning or Forwarding state to Disabled or
1117                  * Blocking or Listening state.
1118                  */
1119                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1120                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1121                     (state == PORT_CONTROL_STATE_DISABLED ||
1122                      state == PORT_CONTROL_STATE_BLOCKING)) {
1123                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1124                         if (ret)
1125                                 return ret;
1126                 }
1127
1128                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1129                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1130                                            reg);
1131                 if (ret)
1132                         return ret;
1133
1134                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1135                            mv88e6xxx_port_state_names[state],
1136                            mv88e6xxx_port_state_names[oldstate]);
1137         }
1138
1139         return ret;
1140 }
1141
1142 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1143 {
1144         struct net_device *bridge = chip->ports[port].bridge_dev;
1145         const u16 mask = (1 << chip->info->num_ports) - 1;
1146         struct dsa_switch *ds = chip->ds;
1147         u16 output_ports = 0;
1148         int reg;
1149         int i;
1150
1151         /* allow CPU port or DSA link(s) to send frames to every port */
1152         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1153                 output_ports = mask;
1154         } else {
1155                 for (i = 0; i < chip->info->num_ports; ++i) {
1156                         /* allow sending frames to every group member */
1157                         if (bridge && chip->ports[i].bridge_dev == bridge)
1158                                 output_ports |= BIT(i);
1159
1160                         /* allow sending frames to CPU port and DSA link(s) */
1161                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1162                                 output_ports |= BIT(i);
1163                 }
1164         }
1165
1166         /* prevent frames from going back out of the port they came in on */
1167         output_ports &= ~BIT(port);
1168
1169         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1170         if (reg < 0)
1171                 return reg;
1172
1173         reg &= ~mask;
1174         reg |= output_ports & mask;
1175
1176         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1177 }
1178
1179 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1180                                          u8 state)
1181 {
1182         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1183         int stp_state;
1184         int err;
1185
1186         switch (state) {
1187         case BR_STATE_DISABLED:
1188                 stp_state = PORT_CONTROL_STATE_DISABLED;
1189                 break;
1190         case BR_STATE_BLOCKING:
1191         case BR_STATE_LISTENING:
1192                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1193                 break;
1194         case BR_STATE_LEARNING:
1195                 stp_state = PORT_CONTROL_STATE_LEARNING;
1196                 break;
1197         case BR_STATE_FORWARDING:
1198         default:
1199                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1200                 break;
1201         }
1202
1203         mutex_lock(&chip->reg_lock);
1204         err = _mv88e6xxx_port_state(chip, port, stp_state);
1205         mutex_unlock(&chip->reg_lock);
1206
1207         if (err)
1208                 netdev_err(ds->ports[port].netdev,
1209                            "failed to update state to %s\n",
1210                            mv88e6xxx_port_state_names[stp_state]);
1211 }
1212
1213 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1214                                 u16 *new, u16 *old)
1215 {
1216         struct dsa_switch *ds = chip->ds;
1217         u16 pvid;
1218         int ret;
1219
1220         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1221         if (ret < 0)
1222                 return ret;
1223
1224         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1225
1226         if (new) {
1227                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1228                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1229
1230                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1231                                            PORT_DEFAULT_VLAN, ret);
1232                 if (ret < 0)
1233                         return ret;
1234
1235                 netdev_dbg(ds->ports[port].netdev,
1236                            "DefaultVID %d (was %d)\n", *new, pvid);
1237         }
1238
1239         if (old)
1240                 *old = pvid;
1241
1242         return 0;
1243 }
1244
1245 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1246                                     int port, u16 *pvid)
1247 {
1248         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1249 }
1250
1251 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1252                                     int port, u16 pvid)
1253 {
1254         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1255 }
1256
1257 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1258 {
1259         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1260                               GLOBAL_VTU_OP_BUSY);
1261 }
1262
1263 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1264 {
1265         int ret;
1266
1267         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1268         if (ret < 0)
1269                 return ret;
1270
1271         return _mv88e6xxx_vtu_wait(chip);
1272 }
1273
1274 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1275 {
1276         int ret;
1277
1278         ret = _mv88e6xxx_vtu_wait(chip);
1279         if (ret < 0)
1280                 return ret;
1281
1282         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1283 }
1284
1285 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1286                                         struct mv88e6xxx_vtu_stu_entry *entry,
1287                                         unsigned int nibble_offset)
1288 {
1289         u16 regs[3];
1290         int i;
1291         int ret;
1292
1293         for (i = 0; i < 3; ++i) {
1294                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1295                                           GLOBAL_VTU_DATA_0_3 + i);
1296                 if (ret < 0)
1297                         return ret;
1298
1299                 regs[i] = ret;
1300         }
1301
1302         for (i = 0; i < chip->info->num_ports; ++i) {
1303                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1304                 u16 reg = regs[i / 4];
1305
1306                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1313                                    struct mv88e6xxx_vtu_stu_entry *entry)
1314 {
1315         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1316 }
1317
1318 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1319                                    struct mv88e6xxx_vtu_stu_entry *entry)
1320 {
1321         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1322 }
1323
1324 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1325                                          struct mv88e6xxx_vtu_stu_entry *entry,
1326                                          unsigned int nibble_offset)
1327 {
1328         u16 regs[3] = { 0 };
1329         int i;
1330         int ret;
1331
1332         for (i = 0; i < chip->info->num_ports; ++i) {
1333                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1334                 u8 data = entry->data[i];
1335
1336                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1337         }
1338
1339         for (i = 0; i < 3; ++i) {
1340                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1341                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1342                 if (ret < 0)
1343                         return ret;
1344         }
1345
1346         return 0;
1347 }
1348
1349 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1350                                     struct mv88e6xxx_vtu_stu_entry *entry)
1351 {
1352         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1353 }
1354
1355 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1356                                     struct mv88e6xxx_vtu_stu_entry *entry)
1357 {
1358         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1359 }
1360
1361 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1362 {
1363         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1364                                     vid & GLOBAL_VTU_VID_MASK);
1365 }
1366
1367 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1368                                   struct mv88e6xxx_vtu_stu_entry *entry)
1369 {
1370         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1371         int ret;
1372
1373         ret = _mv88e6xxx_vtu_wait(chip);
1374         if (ret < 0)
1375                 return ret;
1376
1377         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1378         if (ret < 0)
1379                 return ret;
1380
1381         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1382         if (ret < 0)
1383                 return ret;
1384
1385         next.vid = ret & GLOBAL_VTU_VID_MASK;
1386         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1387
1388         if (next.valid) {
1389                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1390                 if (ret < 0)
1391                         return ret;
1392
1393                 if (mv88e6xxx_has_fid_reg(chip)) {
1394                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1395                                                   GLOBAL_VTU_FID);
1396                         if (ret < 0)
1397                                 return ret;
1398
1399                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1400                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1401                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1402                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1403                          */
1404                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1405                                                   GLOBAL_VTU_OP);
1406                         if (ret < 0)
1407                                 return ret;
1408
1409                         next.fid = (ret & 0xf00) >> 4;
1410                         next.fid |= ret & 0xf;
1411                 }
1412
1413                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1414                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1415                                                   GLOBAL_VTU_SID);
1416                         if (ret < 0)
1417                                 return ret;
1418
1419                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1420                 }
1421         }
1422
1423         *entry = next;
1424         return 0;
1425 }
1426
1427 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1428                                     struct switchdev_obj_port_vlan *vlan,
1429                                     int (*cb)(struct switchdev_obj *obj))
1430 {
1431         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1432         struct mv88e6xxx_vtu_stu_entry next;
1433         u16 pvid;
1434         int err;
1435
1436         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1437                 return -EOPNOTSUPP;
1438
1439         mutex_lock(&chip->reg_lock);
1440
1441         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1442         if (err)
1443                 goto unlock;
1444
1445         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1446         if (err)
1447                 goto unlock;
1448
1449         do {
1450                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1451                 if (err)
1452                         break;
1453
1454                 if (!next.valid)
1455                         break;
1456
1457                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1458                         continue;
1459
1460                 /* reinit and dump this VLAN obj */
1461                 vlan->vid_begin = next.vid;
1462                 vlan->vid_end = next.vid;
1463                 vlan->flags = 0;
1464
1465                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1466                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1467
1468                 if (next.vid == pvid)
1469                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1470
1471                 err = cb(&vlan->obj);
1472                 if (err)
1473                         break;
1474         } while (next.vid < GLOBAL_VTU_VID_MASK);
1475
1476 unlock:
1477         mutex_unlock(&chip->reg_lock);
1478
1479         return err;
1480 }
1481
1482 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1483                                     struct mv88e6xxx_vtu_stu_entry *entry)
1484 {
1485         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1486         u16 reg = 0;
1487         int ret;
1488
1489         ret = _mv88e6xxx_vtu_wait(chip);
1490         if (ret < 0)
1491                 return ret;
1492
1493         if (!entry->valid)
1494                 goto loadpurge;
1495
1496         /* Write port member tags */
1497         ret = mv88e6xxx_vtu_data_write(chip, entry);
1498         if (ret < 0)
1499                 return ret;
1500
1501         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1502                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1503                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1504                                            reg);
1505                 if (ret < 0)
1506                         return ret;
1507         }
1508
1509         if (mv88e6xxx_has_fid_reg(chip)) {
1510                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1511                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1512                                            reg);
1513                 if (ret < 0)
1514                         return ret;
1515         } else if (mv88e6xxx_num_databases(chip) == 256) {
1516                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1517                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1518                  */
1519                 op |= (entry->fid & 0xf0) << 8;
1520                 op |= entry->fid & 0xf;
1521         }
1522
1523         reg = GLOBAL_VTU_VID_VALID;
1524 loadpurge:
1525         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1526         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1527         if (ret < 0)
1528                 return ret;
1529
1530         return _mv88e6xxx_vtu_cmd(chip, op);
1531 }
1532
1533 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1534                                   struct mv88e6xxx_vtu_stu_entry *entry)
1535 {
1536         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1537         int ret;
1538
1539         ret = _mv88e6xxx_vtu_wait(chip);
1540         if (ret < 0)
1541                 return ret;
1542
1543         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1544                                    sid & GLOBAL_VTU_SID_MASK);
1545         if (ret < 0)
1546                 return ret;
1547
1548         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1549         if (ret < 0)
1550                 return ret;
1551
1552         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1553         if (ret < 0)
1554                 return ret;
1555
1556         next.sid = ret & GLOBAL_VTU_SID_MASK;
1557
1558         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1559         if (ret < 0)
1560                 return ret;
1561
1562         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1563
1564         if (next.valid) {
1565                 ret = mv88e6xxx_stu_data_read(chip, &next);
1566                 if (ret < 0)
1567                         return ret;
1568         }
1569
1570         *entry = next;
1571         return 0;
1572 }
1573
1574 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1575                                     struct mv88e6xxx_vtu_stu_entry *entry)
1576 {
1577         u16 reg = 0;
1578         int ret;
1579
1580         ret = _mv88e6xxx_vtu_wait(chip);
1581         if (ret < 0)
1582                 return ret;
1583
1584         if (!entry->valid)
1585                 goto loadpurge;
1586
1587         /* Write port states */
1588         ret = mv88e6xxx_stu_data_write(chip, entry);
1589         if (ret < 0)
1590                 return ret;
1591
1592         reg = GLOBAL_VTU_VID_VALID;
1593 loadpurge:
1594         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1595         if (ret < 0)
1596                 return ret;
1597
1598         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1599         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1600         if (ret < 0)
1601                 return ret;
1602
1603         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1604 }
1605
1606 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1607                                u16 *new, u16 *old)
1608 {
1609         struct dsa_switch *ds = chip->ds;
1610         u16 upper_mask;
1611         u16 fid;
1612         int ret;
1613
1614         if (mv88e6xxx_num_databases(chip) == 4096)
1615                 upper_mask = 0xff;
1616         else if (mv88e6xxx_num_databases(chip) == 256)
1617                 upper_mask = 0xf;
1618         else
1619                 return -EOPNOTSUPP;
1620
1621         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1622         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1623         if (ret < 0)
1624                 return ret;
1625
1626         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1627
1628         if (new) {
1629                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1630                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1631
1632                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1633                                            ret);
1634                 if (ret < 0)
1635                         return ret;
1636         }
1637
1638         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1639         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1640         if (ret < 0)
1641                 return ret;
1642
1643         fid |= (ret & upper_mask) << 4;
1644
1645         if (new) {
1646                 ret &= ~upper_mask;
1647                 ret |= (*new >> 4) & upper_mask;
1648
1649                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1650                                            ret);
1651                 if (ret < 0)
1652                         return ret;
1653
1654                 netdev_dbg(ds->ports[port].netdev,
1655                            "FID %d (was %d)\n", *new, fid);
1656         }
1657
1658         if (old)
1659                 *old = fid;
1660
1661         return 0;
1662 }
1663
1664 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1665                                    int port, u16 *fid)
1666 {
1667         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1668 }
1669
1670 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1671                                    int port, u16 fid)
1672 {
1673         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1674 }
1675
1676 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1677 {
1678         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1679         struct mv88e6xxx_vtu_stu_entry vlan;
1680         int i, err;
1681
1682         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1683
1684         /* Set every FID bit used by the (un)bridged ports */
1685         for (i = 0; i < chip->info->num_ports; ++i) {
1686                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1687                 if (err)
1688                         return err;
1689
1690                 set_bit(*fid, fid_bitmap);
1691         }
1692
1693         /* Set every FID bit used by the VLAN entries */
1694         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1695         if (err)
1696                 return err;
1697
1698         do {
1699                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1700                 if (err)
1701                         return err;
1702
1703                 if (!vlan.valid)
1704                         break;
1705
1706                 set_bit(vlan.fid, fid_bitmap);
1707         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1708
1709         /* The reset value 0x000 is used to indicate that multiple address
1710          * databases are not needed. Return the next positive available.
1711          */
1712         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1713         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1714                 return -ENOSPC;
1715
1716         /* Clear the database */
1717         return _mv88e6xxx_atu_flush(chip, *fid, true);
1718 }
1719
1720 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1721                               struct mv88e6xxx_vtu_stu_entry *entry)
1722 {
1723         struct dsa_switch *ds = chip->ds;
1724         struct mv88e6xxx_vtu_stu_entry vlan = {
1725                 .valid = true,
1726                 .vid = vid,
1727         };
1728         int i, err;
1729
1730         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1731         if (err)
1732                 return err;
1733
1734         /* exclude all ports except the CPU and DSA ports */
1735         for (i = 0; i < chip->info->num_ports; ++i)
1736                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1737                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1738                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1739
1740         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1741             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1742                 struct mv88e6xxx_vtu_stu_entry vstp;
1743
1744                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1745                  * implemented, only one STU entry is needed to cover all VTU
1746                  * entries. Thus, validate the SID 0.
1747                  */
1748                 vlan.sid = 0;
1749                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1750                 if (err)
1751                         return err;
1752
1753                 if (vstp.sid != vlan.sid || !vstp.valid) {
1754                         memset(&vstp, 0, sizeof(vstp));
1755                         vstp.valid = true;
1756                         vstp.sid = vlan.sid;
1757
1758                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1759                         if (err)
1760                                 return err;
1761                 }
1762         }
1763
1764         *entry = vlan;
1765         return 0;
1766 }
1767
1768 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1769                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1770 {
1771         int err;
1772
1773         if (!vid)
1774                 return -EINVAL;
1775
1776         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1777         if (err)
1778                 return err;
1779
1780         err = _mv88e6xxx_vtu_getnext(chip, entry);
1781         if (err)
1782                 return err;
1783
1784         if (entry->vid != vid || !entry->valid) {
1785                 if (!creat)
1786                         return -EOPNOTSUPP;
1787                 /* -ENOENT would've been more appropriate, but switchdev expects
1788                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1789                  */
1790
1791                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1792         }
1793
1794         return err;
1795 }
1796
1797 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1798                                         u16 vid_begin, u16 vid_end)
1799 {
1800         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1801         struct mv88e6xxx_vtu_stu_entry vlan;
1802         int i, err;
1803
1804         if (!vid_begin)
1805                 return -EOPNOTSUPP;
1806
1807         mutex_lock(&chip->reg_lock);
1808
1809         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1810         if (err)
1811                 goto unlock;
1812
1813         do {
1814                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1815                 if (err)
1816                         goto unlock;
1817
1818                 if (!vlan.valid)
1819                         break;
1820
1821                 if (vlan.vid > vid_end)
1822                         break;
1823
1824                 for (i = 0; i < chip->info->num_ports; ++i) {
1825                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1826                                 continue;
1827
1828                         if (vlan.data[i] ==
1829                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1830                                 continue;
1831
1832                         if (chip->ports[i].bridge_dev ==
1833                             chip->ports[port].bridge_dev)
1834                                 break; /* same bridge, check next VLAN */
1835
1836                         netdev_warn(ds->ports[port].netdev,
1837                                     "hardware VLAN %d already used by %s\n",
1838                                     vlan.vid,
1839                                     netdev_name(chip->ports[i].bridge_dev));
1840                         err = -EOPNOTSUPP;
1841                         goto unlock;
1842                 }
1843         } while (vlan.vid < vid_end);
1844
1845 unlock:
1846         mutex_unlock(&chip->reg_lock);
1847
1848         return err;
1849 }
1850
1851 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1852         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1853         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1854         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1855         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1856 };
1857
1858 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1859                                          bool vlan_filtering)
1860 {
1861         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1862         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1863                 PORT_CONTROL_2_8021Q_DISABLED;
1864         int ret;
1865
1866         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1867                 return -EOPNOTSUPP;
1868
1869         mutex_lock(&chip->reg_lock);
1870
1871         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1872         if (ret < 0)
1873                 goto unlock;
1874
1875         old = ret & PORT_CONTROL_2_8021Q_MASK;
1876
1877         if (new != old) {
1878                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1879                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1880
1881                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1882                                            ret);
1883                 if (ret < 0)
1884                         goto unlock;
1885
1886                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1887                            mv88e6xxx_port_8021q_mode_names[new],
1888                            mv88e6xxx_port_8021q_mode_names[old]);
1889         }
1890
1891         ret = 0;
1892 unlock:
1893         mutex_unlock(&chip->reg_lock);
1894
1895         return ret;
1896 }
1897
1898 static int
1899 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1900                             const struct switchdev_obj_port_vlan *vlan,
1901                             struct switchdev_trans *trans)
1902 {
1903         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1904         int err;
1905
1906         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1907                 return -EOPNOTSUPP;
1908
1909         /* If the requested port doesn't belong to the same bridge as the VLAN
1910          * members, do not support it (yet) and fallback to software VLAN.
1911          */
1912         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1913                                            vlan->vid_end);
1914         if (err)
1915                 return err;
1916
1917         /* We don't need any dynamic resource from the kernel (yet),
1918          * so skip the prepare phase.
1919          */
1920         return 0;
1921 }
1922
1923 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1924                                     u16 vid, bool untagged)
1925 {
1926         struct mv88e6xxx_vtu_stu_entry vlan;
1927         int err;
1928
1929         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1930         if (err)
1931                 return err;
1932
1933         vlan.data[port] = untagged ?
1934                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1935                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1936
1937         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1938 }
1939
1940 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1941                                     const struct switchdev_obj_port_vlan *vlan,
1942                                     struct switchdev_trans *trans)
1943 {
1944         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1945         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1946         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1947         u16 vid;
1948
1949         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1950                 return;
1951
1952         mutex_lock(&chip->reg_lock);
1953
1954         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1955                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1956                         netdev_err(ds->ports[port].netdev,
1957                                    "failed to add VLAN %d%c\n",
1958                                    vid, untagged ? 'u' : 't');
1959
1960         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1961                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1962                            vlan->vid_end);
1963
1964         mutex_unlock(&chip->reg_lock);
1965 }
1966
1967 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1968                                     int port, u16 vid)
1969 {
1970         struct dsa_switch *ds = chip->ds;
1971         struct mv88e6xxx_vtu_stu_entry vlan;
1972         int i, err;
1973
1974         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1975         if (err)
1976                 return err;
1977
1978         /* Tell switchdev if this VLAN is handled in software */
1979         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1980                 return -EOPNOTSUPP;
1981
1982         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1983
1984         /* keep the VLAN unless all ports are excluded */
1985         vlan.valid = false;
1986         for (i = 0; i < chip->info->num_ports; ++i) {
1987                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1988                         continue;
1989
1990                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1991                         vlan.valid = true;
1992                         break;
1993                 }
1994         }
1995
1996         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1997         if (err)
1998                 return err;
1999
2000         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2001 }
2002
2003 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2004                                    const struct switchdev_obj_port_vlan *vlan)
2005 {
2006         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2007         u16 pvid, vid;
2008         int err = 0;
2009
2010         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2011                 return -EOPNOTSUPP;
2012
2013         mutex_lock(&chip->reg_lock);
2014
2015         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2016         if (err)
2017                 goto unlock;
2018
2019         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2020                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2021                 if (err)
2022                         goto unlock;
2023
2024                 if (vid == pvid) {
2025                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2026                         if (err)
2027                                 goto unlock;
2028                 }
2029         }
2030
2031 unlock:
2032         mutex_unlock(&chip->reg_lock);
2033
2034         return err;
2035 }
2036
2037 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2038                                     const unsigned char *addr)
2039 {
2040         int i, ret;
2041
2042         for (i = 0; i < 3; i++) {
2043                 ret = _mv88e6xxx_reg_write(
2044                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2045                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2046                 if (ret < 0)
2047                         return ret;
2048         }
2049
2050         return 0;
2051 }
2052
2053 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2054                                    unsigned char *addr)
2055 {
2056         int i, ret;
2057
2058         for (i = 0; i < 3; i++) {
2059                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2060                                           GLOBAL_ATU_MAC_01 + i);
2061                 if (ret < 0)
2062                         return ret;
2063                 addr[i * 2] = ret >> 8;
2064                 addr[i * 2 + 1] = ret & 0xff;
2065         }
2066
2067         return 0;
2068 }
2069
2070 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2071                                struct mv88e6xxx_atu_entry *entry)
2072 {
2073         int ret;
2074
2075         ret = _mv88e6xxx_atu_wait(chip);
2076         if (ret < 0)
2077                 return ret;
2078
2079         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2080         if (ret < 0)
2081                 return ret;
2082
2083         ret = _mv88e6xxx_atu_data_write(chip, entry);
2084         if (ret < 0)
2085                 return ret;
2086
2087         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2088 }
2089
2090 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2091                                     const unsigned char *addr, u16 vid,
2092                                     u8 state)
2093 {
2094         struct mv88e6xxx_atu_entry entry = { 0 };
2095         struct mv88e6xxx_vtu_stu_entry vlan;
2096         int err;
2097
2098         /* Null VLAN ID corresponds to the port private database */
2099         if (vid == 0)
2100                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2101         else
2102                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2103         if (err)
2104                 return err;
2105
2106         entry.fid = vlan.fid;
2107         entry.state = state;
2108         ether_addr_copy(entry.mac, addr);
2109         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2110                 entry.trunk = false;
2111                 entry.portv_trunkid = BIT(port);
2112         }
2113
2114         return _mv88e6xxx_atu_load(chip, &entry);
2115 }
2116
2117 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2118                                       const struct switchdev_obj_port_fdb *fdb,
2119                                       struct switchdev_trans *trans)
2120 {
2121         /* We don't need any dynamic resource from the kernel (yet),
2122          * so skip the prepare phase.
2123          */
2124         return 0;
2125 }
2126
2127 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2128                                    const struct switchdev_obj_port_fdb *fdb,
2129                                    struct switchdev_trans *trans)
2130 {
2131         int state = is_multicast_ether_addr(fdb->addr) ?
2132                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2133                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2134         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2135
2136         mutex_lock(&chip->reg_lock);
2137         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2138                 netdev_err(ds->ports[port].netdev,
2139                            "failed to load MAC address\n");
2140         mutex_unlock(&chip->reg_lock);
2141 }
2142
2143 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2144                                   const struct switchdev_obj_port_fdb *fdb)
2145 {
2146         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2147         int ret;
2148
2149         mutex_lock(&chip->reg_lock);
2150         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2151                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2152         mutex_unlock(&chip->reg_lock);
2153
2154         return ret;
2155 }
2156
2157 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2158                                   struct mv88e6xxx_atu_entry *entry)
2159 {
2160         struct mv88e6xxx_atu_entry next = { 0 };
2161         int ret;
2162
2163         next.fid = fid;
2164
2165         ret = _mv88e6xxx_atu_wait(chip);
2166         if (ret < 0)
2167                 return ret;
2168
2169         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2170         if (ret < 0)
2171                 return ret;
2172
2173         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2174         if (ret < 0)
2175                 return ret;
2176
2177         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2178         if (ret < 0)
2179                 return ret;
2180
2181         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2182         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2183                 unsigned int mask, shift;
2184
2185                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2186                         next.trunk = true;
2187                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2188                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2189                 } else {
2190                         next.trunk = false;
2191                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2192                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2193                 }
2194
2195                 next.portv_trunkid = (ret & mask) >> shift;
2196         }
2197
2198         *entry = next;
2199         return 0;
2200 }
2201
2202 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2203                                         u16 fid, u16 vid, int port,
2204                                         struct switchdev_obj_port_fdb *fdb,
2205                                         int (*cb)(struct switchdev_obj *obj))
2206 {
2207         struct mv88e6xxx_atu_entry addr = {
2208                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2209         };
2210         int err;
2211
2212         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2213         if (err)
2214                 return err;
2215
2216         do {
2217                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2218                 if (err)
2219                         break;
2220
2221                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2222                         break;
2223
2224                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2225                         bool is_static = addr.state ==
2226                                 (is_multicast_ether_addr(addr.mac) ?
2227                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2228                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2229
2230                         fdb->vid = vid;
2231                         ether_addr_copy(fdb->addr, addr.mac);
2232                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2233
2234                         err = cb(&fdb->obj);
2235                         if (err)
2236                                 break;
2237                 }
2238         } while (!is_broadcast_ether_addr(addr.mac));
2239
2240         return err;
2241 }
2242
2243 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2244                                    struct switchdev_obj_port_fdb *fdb,
2245                                    int (*cb)(struct switchdev_obj *obj))
2246 {
2247         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2248         struct mv88e6xxx_vtu_stu_entry vlan = {
2249                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2250         };
2251         u16 fid;
2252         int err;
2253
2254         mutex_lock(&chip->reg_lock);
2255
2256         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2257         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2258         if (err)
2259                 goto unlock;
2260
2261         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2262         if (err)
2263                 goto unlock;
2264
2265         /* Dump VLANs' Filtering Information Databases */
2266         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2267         if (err)
2268                 goto unlock;
2269
2270         do {
2271                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2272                 if (err)
2273                         break;
2274
2275                 if (!vlan.valid)
2276                         break;
2277
2278                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2279                                                    port, fdb, cb);
2280                 if (err)
2281                         break;
2282         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2283
2284 unlock:
2285         mutex_unlock(&chip->reg_lock);
2286
2287         return err;
2288 }
2289
2290 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2291                                       struct net_device *bridge)
2292 {
2293         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2294         int i, err = 0;
2295
2296         mutex_lock(&chip->reg_lock);
2297
2298         /* Assign the bridge and remap each port's VLANTable */
2299         chip->ports[port].bridge_dev = bridge;
2300
2301         for (i = 0; i < chip->info->num_ports; ++i) {
2302                 if (chip->ports[i].bridge_dev == bridge) {
2303                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2304                         if (err)
2305                                 break;
2306                 }
2307         }
2308
2309         mutex_unlock(&chip->reg_lock);
2310
2311         return err;
2312 }
2313
2314 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2315 {
2316         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2317         struct net_device *bridge = chip->ports[port].bridge_dev;
2318         int i;
2319
2320         mutex_lock(&chip->reg_lock);
2321
2322         /* Unassign the bridge and remap each port's VLANTable */
2323         chip->ports[port].bridge_dev = NULL;
2324
2325         for (i = 0; i < chip->info->num_ports; ++i)
2326                 if (i == port || chip->ports[i].bridge_dev == bridge)
2327                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2328                                 netdev_warn(ds->ports[i].netdev,
2329                                             "failed to remap\n");
2330
2331         mutex_unlock(&chip->reg_lock);
2332 }
2333
2334 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2335 {
2336         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2337         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2338         struct gpio_desc *gpiod = chip->reset;
2339         unsigned long timeout;
2340         int ret;
2341         int i;
2342
2343         /* Set all ports to the disabled state. */
2344         for (i = 0; i < chip->info->num_ports; i++) {
2345                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2346                 if (ret < 0)
2347                         return ret;
2348
2349                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2350                                            ret & 0xfffc);
2351                 if (ret)
2352                         return ret;
2353         }
2354
2355         /* Wait for transmit queues to drain. */
2356         usleep_range(2000, 4000);
2357
2358         /* If there is a gpio connected to the reset pin, toggle it */
2359         if (gpiod) {
2360                 gpiod_set_value_cansleep(gpiod, 1);
2361                 usleep_range(10000, 20000);
2362                 gpiod_set_value_cansleep(gpiod, 0);
2363                 usleep_range(10000, 20000);
2364         }
2365
2366         /* Reset the switch. Keep the PPU active if requested. The PPU
2367          * needs to be active to support indirect phy register access
2368          * through global registers 0x18 and 0x19.
2369          */
2370         if (ppu_active)
2371                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2372         else
2373                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2374         if (ret)
2375                 return ret;
2376
2377         /* Wait up to one second for reset to complete. */
2378         timeout = jiffies + 1 * HZ;
2379         while (time_before(jiffies, timeout)) {
2380                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2381                 if (ret < 0)
2382                         return ret;
2383
2384                 if ((ret & is_reset) == is_reset)
2385                         break;
2386                 usleep_range(1000, 2000);
2387         }
2388         if (time_after(jiffies, timeout))
2389                 ret = -ETIMEDOUT;
2390         else
2391                 ret = 0;
2392
2393         return ret;
2394 }
2395
2396 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2397 {
2398         u16 val;
2399         int err;
2400
2401         /* Clear Power Down bit */
2402         err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2403         if (err)
2404                 return err;
2405
2406         if (val & BMCR_PDOWN) {
2407                 val &= ~BMCR_PDOWN;
2408                 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2409         }
2410
2411         return err;
2412 }
2413
2414 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2415                                int reg, u16 *val)
2416 {
2417         int addr = chip->info->port_base_addr + port;
2418
2419         if (port >= chip->info->num_ports)
2420                 return -EINVAL;
2421
2422         return mv88e6xxx_read(chip, addr, reg, val);
2423 }
2424
2425 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2426 {
2427         struct dsa_switch *ds = chip->ds;
2428         int ret;
2429         u16 reg;
2430
2431         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2432             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2433             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2434             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2435                 /* MAC Forcing register: don't force link, speed,
2436                  * duplex or flow control state to any particular
2437                  * values on physical ports, but force the CPU port
2438                  * and all DSA ports to their maximum bandwidth and
2439                  * full duplex.
2440                  */
2441                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2442                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2443                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2444                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2445                                 PORT_PCS_CTRL_LINK_UP |
2446                                 PORT_PCS_CTRL_DUPLEX_FULL |
2447                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2448                         if (mv88e6xxx_6065_family(chip))
2449                                 reg |= PORT_PCS_CTRL_100;
2450                         else
2451                                 reg |= PORT_PCS_CTRL_1000;
2452                 } else {
2453                         reg |= PORT_PCS_CTRL_UNFORCED;
2454                 }
2455
2456                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2457                                            PORT_PCS_CTRL, reg);
2458                 if (ret)
2459                         return ret;
2460         }
2461
2462         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2463          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2464          * tunneling, determine priority by looking at 802.1p and IP
2465          * priority fields (IP prio has precedence), and set STP state
2466          * to Forwarding.
2467          *
2468          * If this is the CPU link, use DSA or EDSA tagging depending
2469          * on which tagging mode was configured.
2470          *
2471          * If this is a link to another switch, use DSA tagging mode.
2472          *
2473          * If this is the upstream port for this switch, enable
2474          * forwarding of unknown unicasts and multicasts.
2475          */
2476         reg = 0;
2477         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2478             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2479             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2480             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2481                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2482                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2483                 PORT_CONTROL_STATE_FORWARDING;
2484         if (dsa_is_cpu_port(ds, port)) {
2485                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2486                         reg |= PORT_CONTROL_DSA_TAG;
2487                 if (mv88e6xxx_6352_family(chip) ||
2488                     mv88e6xxx_6351_family(chip) ||
2489                     mv88e6xxx_6165_family(chip) ||
2490                     mv88e6xxx_6097_family(chip) ||
2491                     mv88e6xxx_6320_family(chip)) {
2492                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2493                                 PORT_CONTROL_FORWARD_UNKNOWN |
2494                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2495                 }
2496
2497                 if (mv88e6xxx_6352_family(chip) ||
2498                     mv88e6xxx_6351_family(chip) ||
2499                     mv88e6xxx_6165_family(chip) ||
2500                     mv88e6xxx_6097_family(chip) ||
2501                     mv88e6xxx_6095_family(chip) ||
2502                     mv88e6xxx_6065_family(chip) ||
2503                     mv88e6xxx_6185_family(chip) ||
2504                     mv88e6xxx_6320_family(chip)) {
2505                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2506                 }
2507         }
2508         if (dsa_is_dsa_port(ds, port)) {
2509                 if (mv88e6xxx_6095_family(chip) ||
2510                     mv88e6xxx_6185_family(chip))
2511                         reg |= PORT_CONTROL_DSA_TAG;
2512                 if (mv88e6xxx_6352_family(chip) ||
2513                     mv88e6xxx_6351_family(chip) ||
2514                     mv88e6xxx_6165_family(chip) ||
2515                     mv88e6xxx_6097_family(chip) ||
2516                     mv88e6xxx_6320_family(chip)) {
2517                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2518                 }
2519
2520                 if (port == dsa_upstream_port(ds))
2521                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2522                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2523         }
2524         if (reg) {
2525                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2526                                            PORT_CONTROL, reg);
2527                 if (ret)
2528                         return ret;
2529         }
2530
2531         /* If this port is connected to a SerDes, make sure the SerDes is not
2532          * powered down.
2533          */
2534         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2535                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2536                 if (ret < 0)
2537                         return ret;
2538                 ret &= PORT_STATUS_CMODE_MASK;
2539                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2540                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2541                     (ret == PORT_STATUS_CMODE_SGMII)) {
2542                         ret = mv88e6xxx_serdes_power_on(chip);
2543                         if (ret < 0)
2544                                 return ret;
2545                 }
2546         }
2547
2548         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2549          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2550          * untagged frames on this port, do a destination address lookup on all
2551          * received packets as usual, disable ARP mirroring and don't send a
2552          * copy of all transmitted/received frames on this port to the CPU.
2553          */
2554         reg = 0;
2555         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2556             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2557             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2558             mv88e6xxx_6185_family(chip))
2559                 reg = PORT_CONTROL_2_MAP_DA;
2560
2561         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2562             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2563                 reg |= PORT_CONTROL_2_JUMBO_10240;
2564
2565         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2566                 /* Set the upstream port this port should use */
2567                 reg |= dsa_upstream_port(ds);
2568                 /* enable forwarding of unknown multicast addresses to
2569                  * the upstream port
2570                  */
2571                 if (port == dsa_upstream_port(ds))
2572                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2573         }
2574
2575         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2576
2577         if (reg) {
2578                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2579                                            PORT_CONTROL_2, reg);
2580                 if (ret)
2581                         return ret;
2582         }
2583
2584         /* Port Association Vector: when learning source addresses
2585          * of packets, add the address to the address database using
2586          * a port bitmap that has only the bit for this port set and
2587          * the other bits clear.
2588          */
2589         reg = 1 << port;
2590         /* Disable learning for CPU port */
2591         if (dsa_is_cpu_port(ds, port))
2592                 reg = 0;
2593
2594         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2595                                    reg);
2596         if (ret)
2597                 return ret;
2598
2599         /* Egress rate control 2: disable egress rate control. */
2600         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2601                                    0x0000);
2602         if (ret)
2603                 return ret;
2604
2605         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2606             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2607             mv88e6xxx_6320_family(chip)) {
2608                 /* Do not limit the period of time that this port can
2609                  * be paused for by the remote end or the period of
2610                  * time that this port can pause the remote end.
2611                  */
2612                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2613                                            PORT_PAUSE_CTRL, 0x0000);
2614                 if (ret)
2615                         return ret;
2616
2617                 /* Port ATU control: disable limiting the number of
2618                  * address database entries that this port is allowed
2619                  * to use.
2620                  */
2621                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2622                                            PORT_ATU_CONTROL, 0x0000);
2623                 /* Priority Override: disable DA, SA and VTU priority
2624                  * override.
2625                  */
2626                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2627                                            PORT_PRI_OVERRIDE, 0x0000);
2628                 if (ret)
2629                         return ret;
2630
2631                 /* Port Ethertype: use the Ethertype DSA Ethertype
2632                  * value.
2633                  */
2634                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2635                                            PORT_ETH_TYPE, ETH_P_EDSA);
2636                 if (ret)
2637                         return ret;
2638                 /* Tag Remap: use an identity 802.1p prio -> switch
2639                  * prio mapping.
2640                  */
2641                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2642                                            PORT_TAG_REGMAP_0123, 0x3210);
2643                 if (ret)
2644                         return ret;
2645
2646                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2647                  * prio mapping.
2648                  */
2649                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2650                                            PORT_TAG_REGMAP_4567, 0x7654);
2651                 if (ret)
2652                         return ret;
2653         }
2654
2655         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2656             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2657             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2658             mv88e6xxx_6320_family(chip)) {
2659                 /* Rate Control: disable ingress rate limiting. */
2660                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2661                                            PORT_RATE_CONTROL, 0x0001);
2662                 if (ret)
2663                         return ret;
2664         }
2665
2666         /* Port Control 1: disable trunking, disable sending
2667          * learning messages to this port.
2668          */
2669         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2670                                    0x0000);
2671         if (ret)
2672                 return ret;
2673
2674         /* Port based VLAN map: give each port the same default address
2675          * database, and allow bidirectional communication between the
2676          * CPU and DSA port(s), and the other ports.
2677          */
2678         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2679         if (ret)
2680                 return ret;
2681
2682         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2683         if (ret)
2684                 return ret;
2685
2686         /* Default VLAN ID and priority: don't set a default VLAN
2687          * ID, and set the default packet priority to zero.
2688          */
2689         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2690                                    0x0000);
2691         if (ret)
2692                 return ret;
2693
2694         return 0;
2695 }
2696
2697 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2698 {
2699         int err;
2700
2701         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2702                               (addr[0] << 8) | addr[1]);
2703         if (err)
2704                 return err;
2705
2706         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2707                               (addr[2] << 8) | addr[3]);
2708         if (err)
2709                 return err;
2710
2711         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2712                                (addr[4] << 8) | addr[5]);
2713 }
2714
2715 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2716                                      unsigned int msecs)
2717 {
2718         const unsigned int coeff = chip->info->age_time_coeff;
2719         const unsigned int min = 0x01 * coeff;
2720         const unsigned int max = 0xff * coeff;
2721         u8 age_time;
2722         u16 val;
2723         int err;
2724
2725         if (msecs < min || msecs > max)
2726                 return -ERANGE;
2727
2728         /* Round to nearest multiple of coeff */
2729         age_time = (msecs + coeff / 2) / coeff;
2730
2731         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2732         if (err)
2733                 return err;
2734
2735         /* AgeTime is 11:4 bits */
2736         val &= ~0xff0;
2737         val |= age_time << 4;
2738
2739         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2740 }
2741
2742 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2743                                      unsigned int ageing_time)
2744 {
2745         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2746         int err;
2747
2748         mutex_lock(&chip->reg_lock);
2749         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2750         mutex_unlock(&chip->reg_lock);
2751
2752         return err;
2753 }
2754
2755 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2756 {
2757         struct dsa_switch *ds = chip->ds;
2758         u32 upstream_port = dsa_upstream_port(ds);
2759         u16 reg;
2760         int err;
2761
2762         /* Enable the PHY Polling Unit if present, don't discard any packets,
2763          * and mask all interrupt sources.
2764          */
2765         reg = 0;
2766         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2767             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2768                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2769
2770         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2771         if (err)
2772                 return err;
2773
2774         /* Configure the upstream port, and configure it as the port to which
2775          * ingress and egress and ARP monitor frames are to be sent.
2776          */
2777         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2778                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2779                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2780         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2781                                    reg);
2782         if (err)
2783                 return err;
2784
2785         /* Disable remote management, and set the switch's DSA device number. */
2786         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2787                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2788                                    (ds->index & 0x1f));
2789         if (err)
2790                 return err;
2791
2792         /* Clear all the VTU and STU entries */
2793         err = _mv88e6xxx_vtu_stu_flush(chip);
2794         if (err < 0)
2795                 return err;
2796
2797         /* Set the default address aging time to 5 minutes, and
2798          * enable address learn messages to be sent to all message
2799          * ports.
2800          */
2801         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2802                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2803         if (err)
2804                 return err;
2805
2806         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2807         if (err)
2808                 return err;
2809
2810         /* Clear all ATU entries */
2811         err = _mv88e6xxx_atu_flush(chip, 0, true);
2812         if (err)
2813                 return err;
2814
2815         /* Configure the IP ToS mapping registers. */
2816         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2817         if (err)
2818                 return err;
2819         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2820         if (err)
2821                 return err;
2822         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2823         if (err)
2824                 return err;
2825         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2826         if (err)
2827                 return err;
2828         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2829         if (err)
2830                 return err;
2831         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2832         if (err)
2833                 return err;
2834         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2835         if (err)
2836                 return err;
2837         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2838         if (err)
2839                 return err;
2840
2841         /* Configure the IEEE 802.1p priority mapping register. */
2842         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2843         if (err)
2844                 return err;
2845
2846         /* Clear the statistics counters for all ports */
2847         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2848                                    GLOBAL_STATS_OP_FLUSH_ALL);
2849         if (err)
2850                 return err;
2851
2852         /* Wait for the flush to complete. */
2853         err = _mv88e6xxx_stats_wait(chip);
2854         if (err)
2855                 return err;
2856
2857         return 0;
2858 }
2859
2860 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2861                                              int target, int port)
2862 {
2863         u16 val = (target << 8) | (port & 0xf);
2864
2865         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2866 }
2867
2868 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2869 {
2870         int target, port;
2871         int err;
2872
2873         /* Initialize the routing port to the 32 possible target devices */
2874         for (target = 0; target < 32; ++target) {
2875                 port = 0xf;
2876
2877                 if (target < DSA_MAX_SWITCHES) {
2878                         port = chip->ds->rtable[target];
2879                         if (port == DSA_RTABLE_NONE)
2880                                 port = 0xf;
2881                 }
2882
2883                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2884                 if (err)
2885                         break;
2886         }
2887
2888         return err;
2889 }
2890
2891 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2892                                          bool hask, u16 mask)
2893 {
2894         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2895         u16 val = (num << 12) | (mask & port_mask);
2896
2897         if (hask)
2898                 val |= GLOBAL2_TRUNK_MASK_HASK;
2899
2900         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2901 }
2902
2903 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2904                                             u16 map)
2905 {
2906         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2907         u16 val = (id << 11) | (map & port_mask);
2908
2909         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2910 }
2911
2912 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2913 {
2914         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2915         int i, err;
2916
2917         /* Clear all eight possible Trunk Mask vectors */
2918         for (i = 0; i < 8; ++i) {
2919                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2920                 if (err)
2921                         return err;
2922         }
2923
2924         /* Clear all sixteen possible Trunk ID routing vectors */
2925         for (i = 0; i < 16; ++i) {
2926                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2927                 if (err)
2928                         return err;
2929         }
2930
2931         return 0;
2932 }
2933
2934 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2935 {
2936         int port, err;
2937
2938         /* Init all Ingress Rate Limit resources of all ports */
2939         for (port = 0; port < chip->info->num_ports; ++port) {
2940                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2941                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2942                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2943                                       (port << 8));
2944                 if (err)
2945                         break;
2946
2947                 /* Wait for the operation to complete */
2948                 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2949                                      GLOBAL2_IRL_CMD_BUSY);
2950                 if (err)
2951                         break;
2952         }
2953
2954         return err;
2955 }
2956
2957 /* Indirect write to the Switch MAC/WoL/WoF register */
2958 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2959                                          unsigned int pointer, u8 data)
2960 {
2961         u16 val = (pointer << 8) | data;
2962
2963         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2964 }
2965
2966 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2967 {
2968         int i, err;
2969
2970         for (i = 0; i < 6; i++) {
2971                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2972                 if (err)
2973                         break;
2974         }
2975
2976         return err;
2977 }
2978
2979 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2980                                   u8 data)
2981 {
2982         u16 val = (pointer << 8) | (data & 0x7);
2983
2984         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2985 }
2986
2987 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2988 {
2989         int i, err;
2990
2991         /* Clear all sixteen possible Priority Override entries */
2992         for (i = 0; i < 16; i++) {
2993                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
2994                 if (err)
2995                         break;
2996         }
2997
2998         return err;
2999 }
3000
3001 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3002 {
3003         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3004                               GLOBAL2_EEPROM_CMD_BUSY |
3005                               GLOBAL2_EEPROM_CMD_RUNNING);
3006 }
3007
3008 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3009 {
3010         int err;
3011
3012         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3013         if (err)
3014                 return err;
3015
3016         return mv88e6xxx_g2_eeprom_wait(chip);
3017 }
3018
3019 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3020                                       u8 addr, u16 *data)
3021 {
3022         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3023         int err;
3024
3025         err = mv88e6xxx_g2_eeprom_wait(chip);
3026         if (err)
3027                 return err;
3028
3029         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3030         if (err)
3031                 return err;
3032
3033         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3034 }
3035
3036 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3037                                        u8 addr, u16 data)
3038 {
3039         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3040         int err;
3041
3042         err = mv88e6xxx_g2_eeprom_wait(chip);
3043         if (err)
3044                 return err;
3045
3046         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3047         if (err)
3048                 return err;
3049
3050         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3051 }
3052
3053 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3054 {
3055         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3056                               GLOBAL2_SMI_PHY_CMD_BUSY);
3057 }
3058
3059 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3060 {
3061         int err;
3062
3063         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3064         if (err)
3065                 return err;
3066
3067         return mv88e6xxx_g2_smi_phy_wait(chip);
3068 }
3069
3070 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3071                                      int reg, u16 *val)
3072 {
3073         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3074         int err;
3075
3076         err = mv88e6xxx_g2_smi_phy_wait(chip);
3077         if (err)
3078                 return err;
3079
3080         err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3081         if (err)
3082                 return err;
3083
3084         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3085 }
3086
3087 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3088                                       int reg, u16 val)
3089 {
3090         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3091         int err;
3092
3093         err = mv88e6xxx_g2_smi_phy_wait(chip);
3094         if (err)
3095                 return err;
3096
3097         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3098         if (err)
3099                 return err;
3100
3101         return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3102 }
3103
3104 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3105         .read = mv88e6xxx_g2_smi_phy_read,
3106         .write = mv88e6xxx_g2_smi_phy_write,
3107 };
3108
3109 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3110 {
3111         u16 reg;
3112         int err;
3113
3114         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3115                 /* Consider the frames with reserved multicast destination
3116                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3117                  */
3118                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3119                                       0xffff);
3120                 if (err)
3121                         return err;
3122         }
3123
3124         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3125                 /* Consider the frames with reserved multicast destination
3126                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3127                  */
3128                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3129                                       0xffff);
3130                 if (err)
3131                         return err;
3132         }
3133
3134         /* Ignore removed tag data on doubly tagged packets, disable
3135          * flow control messages, force flow control priority to the
3136          * highest, and send all special multicast frames to the CPU
3137          * port at the highest priority.
3138          */
3139         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3140         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3141             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3142                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3143         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3144         if (err)
3145                 return err;
3146
3147         /* Program the DSA routing table. */
3148         err = mv88e6xxx_g2_set_device_mapping(chip);
3149         if (err)
3150                 return err;
3151
3152         /* Clear all trunk masks and mapping. */
3153         err = mv88e6xxx_g2_clear_trunk(chip);
3154         if (err)
3155                 return err;
3156
3157         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3158                 /* Disable ingress rate limiting by resetting all per port
3159                  * ingress rate limit resources to their initial state.
3160                  */
3161                 err = mv88e6xxx_g2_clear_irl(chip);
3162                         if (err)
3163                                 return err;
3164         }
3165
3166         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3167                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3168                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3169                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3170                 if (err)
3171                         return err;
3172         }
3173
3174         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3175                 /* Clear the priority override table. */
3176                 err = mv88e6xxx_g2_clear_pot(chip);
3177                 if (err)
3178                         return err;
3179         }
3180
3181         return 0;
3182 }
3183
3184 static int mv88e6xxx_setup(struct dsa_switch *ds)
3185 {
3186         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3187         int err;
3188         int i;
3189
3190         chip->ds = ds;
3191         ds->slave_mii_bus = chip->mdio_bus;
3192
3193         mutex_lock(&chip->reg_lock);
3194
3195         err = mv88e6xxx_switch_reset(chip);
3196         if (err)
3197                 goto unlock;
3198
3199         /* Setup Switch Port Registers */
3200         for (i = 0; i < chip->info->num_ports; i++) {
3201                 err = mv88e6xxx_setup_port(chip, i);
3202                 if (err)
3203                         goto unlock;
3204         }
3205
3206         /* Setup Switch Global 1 Registers */
3207         err = mv88e6xxx_g1_setup(chip);
3208         if (err)
3209                 goto unlock;
3210
3211         /* Setup Switch Global 2 Registers */
3212         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3213                 err = mv88e6xxx_g2_setup(chip);
3214                 if (err)
3215                         goto unlock;
3216         }
3217
3218 unlock:
3219         mutex_unlock(&chip->reg_lock);
3220
3221         return err;
3222 }
3223
3224 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3225 {
3226         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3227         int err;
3228
3229         mutex_lock(&chip->reg_lock);
3230
3231         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3232         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3233                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3234         else
3235                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3236
3237         mutex_unlock(&chip->reg_lock);
3238
3239         return err;
3240 }
3241
3242 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3243 {
3244         struct mv88e6xxx_chip *chip = bus->priv;
3245         u16 val;
3246         int err;
3247
3248         if (phy >= chip->info->num_ports)
3249                 return 0xffff;
3250
3251         mutex_lock(&chip->reg_lock);
3252         err = mv88e6xxx_phy_read(chip, phy, reg, &val);
3253         mutex_unlock(&chip->reg_lock);
3254
3255         return err ? err : val;
3256 }
3257
3258 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3259 {
3260         struct mv88e6xxx_chip *chip = bus->priv;
3261         int err;
3262
3263         if (phy >= chip->info->num_ports)
3264                 return 0xffff;
3265
3266         mutex_lock(&chip->reg_lock);
3267         err = mv88e6xxx_phy_write(chip, phy, reg, val);
3268         mutex_unlock(&chip->reg_lock);
3269
3270         return err;
3271 }
3272
3273 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3274                                    struct device_node *np)
3275 {
3276         static int index;
3277         struct mii_bus *bus;
3278         int err;
3279
3280         if (np)
3281                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3282
3283         bus = devm_mdiobus_alloc(chip->dev);
3284         if (!bus)
3285                 return -ENOMEM;
3286
3287         bus->priv = (void *)chip;
3288         if (np) {
3289                 bus->name = np->full_name;
3290                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3291         } else {
3292                 bus->name = "mv88e6xxx SMI";
3293                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3294         }
3295
3296         bus->read = mv88e6xxx_mdio_read;
3297         bus->write = mv88e6xxx_mdio_write;
3298         bus->parent = chip->dev;
3299
3300         if (chip->mdio_np)
3301                 err = of_mdiobus_register(bus, chip->mdio_np);
3302         else
3303                 err = mdiobus_register(bus);
3304         if (err) {
3305                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3306                 goto out;
3307         }
3308         chip->mdio_bus = bus;
3309
3310         return 0;
3311
3312 out:
3313         if (chip->mdio_np)
3314                 of_node_put(chip->mdio_np);
3315
3316         return err;
3317 }
3318
3319 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3320
3321 {
3322         struct mii_bus *bus = chip->mdio_bus;
3323
3324         mdiobus_unregister(bus);
3325
3326         if (chip->mdio_np)
3327                 of_node_put(chip->mdio_np);
3328 }
3329
3330 #ifdef CONFIG_NET_DSA_HWMON
3331
3332 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3333 {
3334         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3335         u16 val;
3336         int ret;
3337
3338         *temp = 0;
3339
3340         mutex_lock(&chip->reg_lock);
3341
3342         ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3343         if (ret < 0)
3344                 goto error;
3345
3346         /* Enable temperature sensor */
3347         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3348         if (ret < 0)
3349                 goto error;
3350
3351         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3352         if (ret < 0)
3353                 goto error;
3354
3355         /* Wait for temperature to stabilize */
3356         usleep_range(10000, 12000);
3357
3358         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3359         if (ret < 0)
3360                 goto error;
3361
3362         /* Disable temperature sensor */
3363         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3364         if (ret < 0)
3365                 goto error;
3366
3367         *temp = ((val & 0x1f) - 5) * 5;
3368
3369 error:
3370         mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3371         mutex_unlock(&chip->reg_lock);
3372         return ret;
3373 }
3374
3375 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3376 {
3377         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3378         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3379         u16 val;
3380         int ret;
3381
3382         *temp = 0;
3383
3384         mutex_lock(&chip->reg_lock);
3385         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3386         mutex_unlock(&chip->reg_lock);
3387         if (ret < 0)
3388                 return ret;
3389
3390         *temp = (val & 0xff) - 25;
3391
3392         return 0;
3393 }
3394
3395 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3396 {
3397         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3398
3399         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3400                 return -EOPNOTSUPP;
3401
3402         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3403                 return mv88e63xx_get_temp(ds, temp);
3404
3405         return mv88e61xx_get_temp(ds, temp);
3406 }
3407
3408 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3409 {
3410         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3411         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3412         u16 val;
3413         int ret;
3414
3415         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3416                 return -EOPNOTSUPP;
3417
3418         *temp = 0;
3419
3420         mutex_lock(&chip->reg_lock);
3421         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3422         mutex_unlock(&chip->reg_lock);
3423         if (ret < 0)
3424                 return ret;
3425
3426         *temp = (((val >> 8) & 0x1f) * 5) - 25;
3427
3428         return 0;
3429 }
3430
3431 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3432 {
3433         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3434         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3435         u16 val;
3436         int err;
3437
3438         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3439                 return -EOPNOTSUPP;
3440
3441         mutex_lock(&chip->reg_lock);
3442         err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3443         if (err)
3444                 goto unlock;
3445         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3446         err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3447                                        (val & 0xe0ff) | (temp << 8));
3448 unlock:
3449         mutex_unlock(&chip->reg_lock);
3450
3451         return err;
3452 }
3453
3454 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3455 {
3456         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3457         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3458         u16 val;
3459         int ret;
3460
3461         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3462                 return -EOPNOTSUPP;
3463
3464         *alarm = false;
3465
3466         mutex_lock(&chip->reg_lock);
3467         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3468         mutex_unlock(&chip->reg_lock);
3469         if (ret < 0)
3470                 return ret;
3471
3472         *alarm = !!(val & 0x40);
3473
3474         return 0;
3475 }
3476 #endif /* CONFIG_NET_DSA_HWMON */
3477
3478 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3479 {
3480         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3481
3482         return chip->eeprom_len;
3483 }
3484
3485 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3486                                   struct ethtool_eeprom *eeprom, u8 *data)
3487 {
3488         unsigned int offset = eeprom->offset;
3489         unsigned int len = eeprom->len;
3490         u16 val;
3491         int err;
3492
3493         eeprom->len = 0;
3494
3495         if (offset & 1) {
3496                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3497                 if (err)
3498                         return err;
3499
3500                 *data++ = (val >> 8) & 0xff;
3501
3502                 offset++;
3503                 len--;
3504                 eeprom->len++;
3505         }
3506
3507         while (len >= 2) {
3508                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3509                 if (err)
3510                         return err;
3511
3512                 *data++ = val & 0xff;
3513                 *data++ = (val >> 8) & 0xff;
3514
3515                 offset += 2;
3516                 len -= 2;
3517                 eeprom->len += 2;
3518         }
3519
3520         if (len) {
3521                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3522                 if (err)
3523                         return err;
3524
3525                 *data++ = val & 0xff;
3526
3527                 offset++;
3528                 len--;
3529                 eeprom->len++;
3530         }
3531
3532         return 0;
3533 }
3534
3535 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3536                                 struct ethtool_eeprom *eeprom, u8 *data)
3537 {
3538         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3539         int err;
3540
3541         mutex_lock(&chip->reg_lock);
3542
3543         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3544                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3545         else
3546                 err = -EOPNOTSUPP;
3547
3548         mutex_unlock(&chip->reg_lock);
3549
3550         if (err)
3551                 return err;
3552
3553         eeprom->magic = 0xc3ec4951;
3554
3555         return 0;
3556 }
3557
3558 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3559                                   struct ethtool_eeprom *eeprom, u8 *data)
3560 {
3561         unsigned int offset = eeprom->offset;
3562         unsigned int len = eeprom->len;
3563         u16 val;
3564         int err;
3565
3566         /* Ensure the RO WriteEn bit is set */
3567         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3568         if (err)
3569                 return err;
3570
3571         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3572                 return -EROFS;
3573
3574         eeprom->len = 0;
3575
3576         if (offset & 1) {
3577                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3578                 if (err)
3579                         return err;
3580
3581                 val = (*data++ << 8) | (val & 0xff);
3582
3583                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3584                 if (err)
3585                         return err;
3586
3587                 offset++;
3588                 len--;
3589                 eeprom->len++;
3590         }
3591
3592         while (len >= 2) {
3593                 val = *data++;
3594                 val |= *data++ << 8;
3595
3596                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3597                 if (err)
3598                         return err;
3599
3600                 offset += 2;
3601                 len -= 2;
3602                 eeprom->len += 2;
3603         }
3604
3605         if (len) {
3606                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3607                 if (err)
3608                         return err;
3609
3610                 val = (val & 0xff00) | *data++;
3611
3612                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3613                 if (err)
3614                         return err;
3615
3616                 offset++;
3617                 len--;
3618                 eeprom->len++;
3619         }
3620
3621         return 0;
3622 }
3623
3624 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3625                                 struct ethtool_eeprom *eeprom, u8 *data)
3626 {
3627         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3628         int err;
3629
3630         if (eeprom->magic != 0xc3ec4951)
3631                 return -EINVAL;
3632
3633         mutex_lock(&chip->reg_lock);
3634
3635         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3636                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3637         else
3638                 err = -EOPNOTSUPP;
3639
3640         mutex_unlock(&chip->reg_lock);
3641
3642         return err;
3643 }
3644
3645 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3646         [MV88E6085] = {
3647                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3648                 .family = MV88E6XXX_FAMILY_6097,
3649                 .name = "Marvell 88E6085",
3650                 .num_databases = 4096,
3651                 .num_ports = 10,
3652                 .port_base_addr = 0x10,
3653                 .age_time_coeff = 15000,
3654                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3655         },
3656
3657         [MV88E6095] = {
3658                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3659                 .family = MV88E6XXX_FAMILY_6095,
3660                 .name = "Marvell 88E6095/88E6095F",
3661                 .num_databases = 256,
3662                 .num_ports = 11,
3663                 .port_base_addr = 0x10,
3664                 .age_time_coeff = 15000,
3665                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3666         },
3667
3668         [MV88E6123] = {
3669                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3670                 .family = MV88E6XXX_FAMILY_6165,
3671                 .name = "Marvell 88E6123",
3672                 .num_databases = 4096,
3673                 .num_ports = 3,
3674                 .port_base_addr = 0x10,
3675                 .age_time_coeff = 15000,
3676                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3677         },
3678
3679         [MV88E6131] = {
3680                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3681                 .family = MV88E6XXX_FAMILY_6185,
3682                 .name = "Marvell 88E6131",
3683                 .num_databases = 256,
3684                 .num_ports = 8,
3685                 .port_base_addr = 0x10,
3686                 .age_time_coeff = 15000,
3687                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3688         },
3689
3690         [MV88E6161] = {
3691                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3692                 .family = MV88E6XXX_FAMILY_6165,
3693                 .name = "Marvell 88E6161",
3694                 .num_databases = 4096,
3695                 .num_ports = 6,
3696                 .port_base_addr = 0x10,
3697                 .age_time_coeff = 15000,
3698                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3699         },
3700
3701         [MV88E6165] = {
3702                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3703                 .family = MV88E6XXX_FAMILY_6165,
3704                 .name = "Marvell 88E6165",
3705                 .num_databases = 4096,
3706                 .num_ports = 6,
3707                 .port_base_addr = 0x10,
3708                 .age_time_coeff = 15000,
3709                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3710         },
3711
3712         [MV88E6171] = {
3713                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3714                 .family = MV88E6XXX_FAMILY_6351,
3715                 .name = "Marvell 88E6171",
3716                 .num_databases = 4096,
3717                 .num_ports = 7,
3718                 .port_base_addr = 0x10,
3719                 .age_time_coeff = 15000,
3720                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3721         },
3722
3723         [MV88E6172] = {
3724                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3725                 .family = MV88E6XXX_FAMILY_6352,
3726                 .name = "Marvell 88E6172",
3727                 .num_databases = 4096,
3728                 .num_ports = 7,
3729                 .port_base_addr = 0x10,
3730                 .age_time_coeff = 15000,
3731                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3732         },
3733
3734         [MV88E6175] = {
3735                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3736                 .family = MV88E6XXX_FAMILY_6351,
3737                 .name = "Marvell 88E6175",
3738                 .num_databases = 4096,
3739                 .num_ports = 7,
3740                 .port_base_addr = 0x10,
3741                 .age_time_coeff = 15000,
3742                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3743         },
3744
3745         [MV88E6176] = {
3746                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3747                 .family = MV88E6XXX_FAMILY_6352,
3748                 .name = "Marvell 88E6176",
3749                 .num_databases = 4096,
3750                 .num_ports = 7,
3751                 .port_base_addr = 0x10,
3752                 .age_time_coeff = 15000,
3753                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3754         },
3755
3756         [MV88E6185] = {
3757                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3758                 .family = MV88E6XXX_FAMILY_6185,
3759                 .name = "Marvell 88E6185",
3760                 .num_databases = 256,
3761                 .num_ports = 10,
3762                 .port_base_addr = 0x10,
3763                 .age_time_coeff = 15000,
3764                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3765         },
3766
3767         [MV88E6240] = {
3768                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3769                 .family = MV88E6XXX_FAMILY_6352,
3770                 .name = "Marvell 88E6240",
3771                 .num_databases = 4096,
3772                 .num_ports = 7,
3773                 .port_base_addr = 0x10,
3774                 .age_time_coeff = 15000,
3775                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3776         },
3777
3778         [MV88E6320] = {
3779                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3780                 .family = MV88E6XXX_FAMILY_6320,
3781                 .name = "Marvell 88E6320",
3782                 .num_databases = 4096,
3783                 .num_ports = 7,
3784                 .port_base_addr = 0x10,
3785                 .age_time_coeff = 15000,
3786                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3787         },
3788
3789         [MV88E6321] = {
3790                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3791                 .family = MV88E6XXX_FAMILY_6320,
3792                 .name = "Marvell 88E6321",
3793                 .num_databases = 4096,
3794                 .num_ports = 7,
3795                 .port_base_addr = 0x10,
3796                 .age_time_coeff = 15000,
3797                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3798         },
3799
3800         [MV88E6350] = {
3801                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3802                 .family = MV88E6XXX_FAMILY_6351,
3803                 .name = "Marvell 88E6350",
3804                 .num_databases = 4096,
3805                 .num_ports = 7,
3806                 .port_base_addr = 0x10,
3807                 .age_time_coeff = 15000,
3808                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3809         },
3810
3811         [MV88E6351] = {
3812                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3813                 .family = MV88E6XXX_FAMILY_6351,
3814                 .name = "Marvell 88E6351",
3815                 .num_databases = 4096,
3816                 .num_ports = 7,
3817                 .port_base_addr = 0x10,
3818                 .age_time_coeff = 15000,
3819                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3820         },
3821
3822         [MV88E6352] = {
3823                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3824                 .family = MV88E6XXX_FAMILY_6352,
3825                 .name = "Marvell 88E6352",
3826                 .num_databases = 4096,
3827                 .num_ports = 7,
3828                 .port_base_addr = 0x10,
3829                 .age_time_coeff = 15000,
3830                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3831         },
3832 };
3833
3834 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3835 {
3836         int i;
3837
3838         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3839                 if (mv88e6xxx_table[i].prod_num == prod_num)
3840                         return &mv88e6xxx_table[i];
3841
3842         return NULL;
3843 }
3844
3845 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3846 {
3847         const struct mv88e6xxx_info *info;
3848         unsigned int prod_num, rev;
3849         u16 id;
3850         int err;
3851
3852         mutex_lock(&chip->reg_lock);
3853         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3854         mutex_unlock(&chip->reg_lock);
3855         if (err)
3856                 return err;
3857
3858         prod_num = (id & 0xfff0) >> 4;
3859         rev = id & 0x000f;
3860
3861         info = mv88e6xxx_lookup_info(prod_num);
3862         if (!info)
3863                 return -ENODEV;
3864
3865         /* Update the compatible info with the probed one */
3866         chip->info = info;
3867
3868         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3869                  chip->info->prod_num, chip->info->name, rev);
3870
3871         return 0;
3872 }
3873
3874 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3875 {
3876         struct mv88e6xxx_chip *chip;
3877
3878         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3879         if (!chip)
3880                 return NULL;
3881
3882         chip->dev = dev;
3883
3884         mutex_init(&chip->reg_lock);
3885
3886         return chip;
3887 }
3888
3889 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3890         .read = mv88e6xxx_read,
3891         .write = mv88e6xxx_write,
3892 };
3893
3894 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3895 {
3896         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3897                 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3898         } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3899                 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3900                 mv88e6xxx_ppu_state_init(chip);
3901         } else {
3902                 chip->phy_ops = &mv88e6xxx_phy_ops;
3903         }
3904 }
3905
3906 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3907                               struct mii_bus *bus, int sw_addr)
3908 {
3909         /* ADDR[0] pin is unavailable externally and considered zero */
3910         if (sw_addr & 0x1)
3911                 return -EINVAL;
3912
3913         if (sw_addr == 0)
3914                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3915         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3916                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3917         else
3918                 return -EINVAL;
3919
3920         chip->bus = bus;
3921         chip->sw_addr = sw_addr;
3922
3923         return 0;
3924 }
3925
3926 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3927                                        struct device *host_dev, int sw_addr,
3928                                        void **priv)
3929 {
3930         struct mv88e6xxx_chip *chip;
3931         struct mii_bus *bus;
3932         int err;
3933
3934         bus = dsa_host_dev_to_mii_bus(host_dev);
3935         if (!bus)
3936                 return NULL;
3937
3938         chip = mv88e6xxx_alloc_chip(dsa_dev);
3939         if (!chip)
3940                 return NULL;
3941
3942         /* Legacy SMI probing will only support chips similar to 88E6085 */
3943         chip->info = &mv88e6xxx_table[MV88E6085];
3944
3945         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3946         if (err)
3947                 goto free;
3948
3949         err = mv88e6xxx_detect(chip);
3950         if (err)
3951                 goto free;
3952
3953         mv88e6xxx_phy_init(chip);
3954
3955         err = mv88e6xxx_mdio_register(chip, NULL);
3956         if (err)
3957                 goto free;
3958
3959         *priv = chip;
3960
3961         return chip->info->name;
3962 free:
3963         devm_kfree(dsa_dev, chip);
3964
3965         return NULL;
3966 }
3967
3968 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3969         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3970         .probe                  = mv88e6xxx_drv_probe,
3971         .setup                  = mv88e6xxx_setup,
3972         .set_addr               = mv88e6xxx_set_addr,
3973         .adjust_link            = mv88e6xxx_adjust_link,
3974         .get_strings            = mv88e6xxx_get_strings,
3975         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3976         .get_sset_count         = mv88e6xxx_get_sset_count,
3977         .set_eee                = mv88e6xxx_set_eee,
3978         .get_eee                = mv88e6xxx_get_eee,
3979 #ifdef CONFIG_NET_DSA_HWMON
3980         .get_temp               = mv88e6xxx_get_temp,
3981         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3982         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3983         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3984 #endif
3985         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3986         .get_eeprom             = mv88e6xxx_get_eeprom,
3987         .set_eeprom             = mv88e6xxx_set_eeprom,
3988         .get_regs_len           = mv88e6xxx_get_regs_len,
3989         .get_regs               = mv88e6xxx_get_regs,
3990         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3991         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3992         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3993         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3994         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3995         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3996         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3997         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3998         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3999         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
4000         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4001         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4002         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4003 };
4004
4005 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4006                                      struct device_node *np)
4007 {
4008         struct device *dev = chip->dev;
4009         struct dsa_switch *ds;
4010
4011         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4012         if (!ds)
4013                 return -ENOMEM;
4014
4015         ds->dev = dev;
4016         ds->priv = chip;
4017         ds->drv = &mv88e6xxx_switch_driver;
4018
4019         dev_set_drvdata(dev, ds);
4020
4021         return dsa_register_switch(ds, np);
4022 }
4023
4024 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4025 {
4026         dsa_unregister_switch(chip->ds);
4027 }
4028
4029 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4030 {
4031         struct device *dev = &mdiodev->dev;
4032         struct device_node *np = dev->of_node;
4033         const struct mv88e6xxx_info *compat_info;
4034         struct mv88e6xxx_chip *chip;
4035         u32 eeprom_len;
4036         int err;
4037
4038         compat_info = of_device_get_match_data(dev);
4039         if (!compat_info)
4040                 return -EINVAL;
4041
4042         chip = mv88e6xxx_alloc_chip(dev);
4043         if (!chip)
4044                 return -ENOMEM;
4045
4046         chip->info = compat_info;
4047
4048         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4049         if (err)
4050                 return err;
4051
4052         err = mv88e6xxx_detect(chip);
4053         if (err)
4054                 return err;
4055
4056         mv88e6xxx_phy_init(chip);
4057
4058         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4059         if (IS_ERR(chip->reset))
4060                 return PTR_ERR(chip->reset);
4061
4062         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4063             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4064                 chip->eeprom_len = eeprom_len;
4065
4066         err = mv88e6xxx_mdio_register(chip, np);
4067         if (err)
4068                 return err;
4069
4070         err = mv88e6xxx_register_switch(chip, np);
4071         if (err) {
4072                 mv88e6xxx_mdio_unregister(chip);
4073                 return err;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4080 {
4081         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4082         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4083
4084         mv88e6xxx_unregister_switch(chip);
4085         mv88e6xxx_mdio_unregister(chip);
4086 }
4087
4088 static const struct of_device_id mv88e6xxx_of_match[] = {
4089         {
4090                 .compatible = "marvell,mv88e6085",
4091                 .data = &mv88e6xxx_table[MV88E6085],
4092         },
4093         { /* sentinel */ },
4094 };
4095
4096 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4097
4098 static struct mdio_driver mv88e6xxx_driver = {
4099         .probe  = mv88e6xxx_probe,
4100         .remove = mv88e6xxx_remove,
4101         .mdiodrv.driver = {
4102                 .name = "mv88e6085",
4103                 .of_match_table = mv88e6xxx_of_match,
4104         },
4105 };
4106
4107 static int __init mv88e6xxx_init(void)
4108 {
4109         register_switch_driver(&mv88e6xxx_switch_driver);
4110         return mdio_driver_register(&mv88e6xxx_driver);
4111 }
4112 module_init(mv88e6xxx_init);
4113
4114 static void __exit mv88e6xxx_cleanup(void)
4115 {
4116         mdio_driver_unregister(&mv88e6xxx_driver);
4117         unregister_switch_driver(&mv88e6xxx_switch_driver);
4118 }
4119 module_exit(mv88e6xxx_cleanup);
4120
4121 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4122 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4123 MODULE_LICENSE("GPL");